24 lines
448 B
Systemverilog
24 lines
448 B
Systemverilog
|
module sdmod (
|
||
|
input signed [7:0] val,
|
||
|
input clk,
|
||
|
input reset,
|
||
|
output daco
|
||
|
);
|
||
|
|
||
|
logic out;
|
||
|
logic signed [7:0] eps;
|
||
|
logic signed [8:0] un;
|
||
|
|
||
|
always_ff @(posedge clk, negedge reset) begin
|
||
|
if (~reset) begin
|
||
|
un <= 9'd0;
|
||
|
end else begin
|
||
|
un <= val - eps;
|
||
|
end
|
||
|
end
|
||
|
|
||
|
assign out = (un >= $signed(9'd0)) ? 1'd1 : 1'd0;
|
||
|
assign eps = (un >= $signed(9'd0)) ? $signed(9'd127) - un : $signed(-9'd128) - un;
|
||
|
assign daco = out;
|
||
|
endmodule
|