From 8fc12247b5d78e1cf66cb804a4c6e0da8f48971d Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Mon, 30 Jan 2023 13:12:47 +0300 Subject: [PATCH] fpga lab3 lab4 reports wip --- 03-fpga-lab-03-report.tex | 231 ++++ 03-fpga-lab-04-report.tex | 65 + pics/03-fpga-03-lab-indi-scheme.svg | 200 +++ pics/03-fpga-04-sigdel.pgf | 1822 +++++++++++++++++++++++++++ 4 files changed, 2318 insertions(+) create mode 100644 03-fpga-lab-03-report.tex create mode 100644 03-fpga-lab-04-report.tex create mode 100644 pics/03-fpga-03-lab-indi-scheme.svg create mode 100644 pics/03-fpga-04-sigdel.pgf diff --git a/03-fpga-lab-03-report.tex b/03-fpga-lab-03-report.tex new file mode 100644 index 0000000..3c2ce13 --- /dev/null +++ b/03-fpga-lab-03-report.tex @@ -0,0 +1,231 @@ +\documentclass[a4paper,fontsize=14bp]{article} + +\input{../common-preamble} +\input{../fancy-listings-preamble} +\input{../bmstu-preamble} +\setcounter{secnumdepth}{4} +\numerationTop + +\begin{document} +\thispagestyle{empty} +\makeBMSTUHeader + +\makeReportTitle{лабораторной}{№ 3}{Разработка и интеграция пользовательских инструкций в состав ядра Nios II}{Проектирование цифровых устройств на \\ программируемых логических интегральных схемах (ПЛИС)}{}{С.В. Фёдоров} + +\newpage +\pagestyle{fancy} +\section{Цель} +Освоить методику использования в составе системы на кристалле пользовательских периферийных модулей и пользовательских инструкций. Реализовать и отладить программное обеспечение системы на кристалле. + +\section{Задачи} +\begin{itemize} +\item Изучить методики расширения набора команд процессора пользовательскими инструкциями. +\item Реализовать программное обеспечение, использующее пользовательские инструкции на примере инструкции вычисления количества единиц в двоичном числе. +\item Сравнить быстродействие с программной реализацией на базовом наборе команд. +\item Выполнить индивидуальное задание. +\end{itemize} + +\section{Выполнение работы} +По шагам из методического материала был создан проект в САПР Quartus Prime (доступен по \href{https://git.iovchinnikov.ru/ivan-igorevich/fpga-lab-2/commits/branch/lab3}{ссылке}). + +Созданная пользовательская инструкция доступна для обращения из программного кода в прикладном проекте. + +\section{Индивидуальное задание} +В качестве индивидуального было дано следующее задание: описать пользовательскую инструкцию, принимающую на вход два 32-разрядных значения и возвращающая минимальное, максимальное, верхнее медианное и нижнее медианное значения. Схема получения данных на рис. \hrf{pic:indi-scheme}. Исходные данные представляют собой два 32-разрядных слова, каждое из которых необходимо разделить на четыре 8-разрядных слова, отсортировать все восемь 8-разрядных слов по возрастанию и взять их минимум (1), максимум (4) и медианы (2, 3). + +\begin{figure}[H] + \centering + \fontsize{12}{1}\selectfont + \includesvg[scale=1.01]{pics/03-fpga-03-lab-indi-scheme.svg} + \caption{Схема обработки данных} + \label{pic:indi-scheme} +\end{figure} + +Поскольку сложность самой быстрой сортировки $O(N*\lg_2(N))$, принято решение опираться на то, что значений в искомом множестве всегда фиксированное число. Сложность задания состоит в том, чтобы получить медианы не отсортированного множества за время меньшее, чем $O(N*\lg_2(N))$. Отсутствие необходимости разработки для множеств не фиксированной длины позволяет воспользоваться несколькими способами получения медианных значений. + +\subsection{Описание схемотехнического решения} +Дан исходный числовой ряд (восемь байт, полученных из двух 32-разрядных переменных), например + +\[ [31, 44, 216, 0, 132, 68, 18, 100]. \] + +Алгоритм выполняется в несколько шагов: +\begin{enumerate} +\item сравнение соседних значений в ряду парами; +\item меньшие значения сравнить с меньшими значениями пар, а большие с большими; +\item взять меньшую из больших полученных пар и б\'{о}льшую из меньших, также сравнить меньшие с меньшими и б\'{о}льшие с б\'{о}льшими; +\item выявить меньшее из меньшей пары, полученной в п. 2 и большее из большей. +\end{enumerate} +\begin{equation*} + \begin{gathered} + [31, 44, 216, 0, 132, 68, 18, 100] + \to + \begin{bmatrix} + 31, 44 \\ 0, 216 \\ 68, 132 \\ 18, 100 + \end{bmatrix} + \to + \begin{bmatrix} + 0, 31 \\ 18, 68 \\ 44, 216 \\ 100, 132 + \end{bmatrix} +\\ \to + \begin{bmatrix} + 44, 100 \\ 31, 68 + \end{bmatrix} +\\ \to [31, 44, 68, 100] \to 44, 68; +\\ \to [0, 18], [132, 216] \to 0, 216. + \end{gathered} +\end{equation*} + +Из приведённых вычислений очевидно, что исходное множество содержит: +\begin{itemize} +\item минимум = 0; +\item максимум = 216; +\item нижняя медиана = 44 +\item верхняя медиана = 68. +\end{itemize} + +Для реализации данного алгоритма был описан вспомогательный модуль на языке Verilog, возвращающий меньшее и большее из двух входящих чисел. + +\begin{lstlisting}[language=Verilog,style=VerilogStyle] +module lessmore ( + input [7:0] in1, + input [7:0] in2, + output logic [7:0] less, + output logic [7:0] more + ); + + always_comb begin + if (in1 < in2) begin + less = in1; + more = in2; + end else begin + less = in2; + more = in1; + end + end +endmodule +\end{lstlisting} + +Сам же алгоритм реализован в несколько «шагов», представляющих собой слои комбинационной логики +\begin{lstlisting}[language=Verilog,style=VerilogStyle] +module minmelhmax ( + input clk, + input reset, + input [31:0] in1, + input [31:0] in2, + output logic [31:0] result + ); + +logic [7:0] step1less [0:3]; +logic [7:0] step1more [0:3]; +logic [7:0] step2less [0:3]; +logic [7:0] step2more [0:3]; +logic [7:0] median [0:3]; +logic [7:0] temp [0:3]; + +// 1: compare pairs +lessmore s01 (in1[7:0], in1[15:8], step1less[0], step1more[0]); +lessmore s02 (in1[23:16], in1[31:24], step1less[1], step1more[1]); +lessmore s03 (in2[7:0], in2[15:8], step1less[2], step1more[2]); +lessmore s04 (in2[23:16], in2[31:24], step1less[3], step1more[3]); + +// 2: 1st step mins to mins, maxes to maxes +lessmore s11 (step1less[0], step1less[1], step2less[0], step2more[0]); +lessmore s12 (step1less[2], step1less[3], step2less[1], step2more[1]); +lessmore s13 (step1more[0], step1more[1], step2less[2], step2more[2]); +lessmore s14 (step1more[2], step1more[3], step2less[3], step2more[3]); + +// 3: 2nd step less-maxes, more-mins +lessmore s21 (step2less[2], step2less[3], median[0], median[1]); +lessmore s22 (step2more[0], step2more[1], median[2], median[3]); + +// 4: median of four +lessmore s31 (median[0], median[1], temp[1], result[1]); +lessmore s32 (median[2], median[3], result[2], temp[2]); + +// 5: max and min of input +lessmore s41 (step2less[0], step2less[1], result[0], temp[0]); +lessmore s42 (step2more[2], step2more[3], temp[3], result[3]); +endmodule +\end{lstlisting} + +Работа модуля была проверена на тестовом стенде + +\subsection{Описание программного решения} +Два входящих слова записываются во временный указатель и интерпретируются, как указатель на восемь 8-разрядных переменных \code{alt_u8}, далее цикл работает с ними как с массивом данных. На каждом шаге цикла ищется минимальный и максимальный элемент. Найденные элементы меняются местами с теми числами, которые находятся на месте действительно минимального и максимального элемента соответственно. Алгоритм являет собой совмещение \textit{сортировки выбором} и \textit{шейкерной сортировки}. Таким образом за четыре итерации получается сортированное множество, в котором необходимые значения берутся по индексу. + +\begin{equation*} + \begin{gathered} +[31, 44, 216, 0, 132, 68, 18, 100] \to \\ +[0, 44, 100, 31, 132, 68, 18, 216] \to \\ +[0, 18, 100, 31, 44, 68, 132, 216] \to \\ +[0, 18, 31, 68, 44, 100, 132, 216] \to \\ +[0, 18, 31, 44, 68, 100, 132, 216] + \end{gathered} +\end{equation*} + +Программная реализация алгоритма копирует исходные значения функцией \code{memset(dst, src, size)} и обрабатывает ситуацию, в которой найденный максимум равен найденному минимуму. +\begin{lstlisting}[language=C,style=CCodeStyle] +alt_u32 ones_sw ( + alt_u32* data_block_a, + alt_u32* data_block_b, + alt_u32 words) { + alt_u32 result; + int word; + for (word = 0; word < words; ++word) { + alt_u8 tmp[8]; + memset(tmp, data_block_a[word], 4); + memset((tmp + 4), data_block_b[word], 4); + + for (int k = 0; k < 4; ++k) { + int min = tmp[k]; + int max = min; + for (int i = k; i < 8 - k; ++i) { + if (min >= tmp[i]) { + min = tmp[i]; + tmp[i] = tmp[k]; + tmp[k] = min; + } + + if ((max <= tmp[i]) && (max != min)) { + max = tmp[i]; + tmp[i] = tmp[8 - k - 1]; + tmp[8 - k - 1] = max; + } + } + } + + result += tmp[0]; + result += (tmp[3] << 8); + result += (tmp[4] << 16); + result += (tmp[7] << 24); + } + return result; +} +\end{lstlisting} + +\section{Результат и выводы} +После запуска приложения были получены результаты, представленные на рис. \hrf{:}. + +\begin{figure}[H] + \centering +% \includegraphics[width=12cm]{.} + \caption{} + \label{pic:} +\end{figure} + + +Пользовательская инструкция для процессора Nios II -- это эффективный инструмент ускорения работы программы и выноса некоторых алгоритмов поточной обработки данных в аппаратную часть. + +\newpage +\appendix +\setcounter{secnumdepth}{4} +\section{Приложения} +\subsection{Исходные коды проекта} +\label{appendix:src} + +\lstinputlisting[language=C,style=CCodeStyle,caption={\code{sem.c}},label={lst:sem}]{src/sem.c} + +\end{document} + + + diff --git a/03-fpga-lab-04-report.tex b/03-fpga-lab-04-report.tex new file mode 100644 index 0000000..019c0ff --- /dev/null +++ b/03-fpga-lab-04-report.tex @@ -0,0 +1,65 @@ +\documentclass[a4paper,fontsize=14bp]{article} + +\input{../common-preamble} +\input{../fancy-listings-preamble} +\input{../bmstu-preamble} +\setcounter{secnumdepth}{4} +\numerationTop + +\begin{document} +\thispagestyle{empty} +\makeBMSTUHeader + +\makeReportTitle{лабораторной}{№ 4}{Проектирование цифрового синтезатора}{Проектирование цифровых устройств на \\ программируемых логических интегральных схемах (ПЛИС)}{}{С.В. Фёдоров} + +\newpage +\sloppy +\pagestyle{fancy} +\section{Цель} +Осуществить полный цикл проектирования цифрового устройства на ПЛИС на языке SystemVerilog. Реализовать генератор периодических функций на основе метода прямого цифрового синтеза на микросхеме семейства Cyclone IV E. + +\section{Задачи} +\begin{itemize} +\item Реализовать модули «Накопителя фазы», «Просмотровой таблицы», «Сигма-Дельта модулятора». +\item Реализовать синтезатор, используя разработанные модули. +\item Осуществить моделирование каждого этапа разработки. +\item В рамках самостоятельной подготовки провести расчёт значений $u_n$,$x_n$,$y'_n$ и $\varepsilon_n$ для 5 тактов работы дельта-сигма модулятора. Приведите значения для каждого такта и график выходного сигнала $y_n$. +\end{itemize} + +\section{Выполнение работы} +\subsection{Самостоятельная подготовка} +Вариант 9 для первой группы $x_n = 9 * 3 - 21 = 6$. + +\begin{figure}[H] + \centering + \resizebox{\textwidth}{!}{\input{pics/03-fpga-04-sigdel.pgf}} + \caption{1} + \label{pic:1} +\end{figure} + +\begin{enumerate} +\item $x_n = 6, \varepsilon_n = 127$, уровень квантования 127; +\item $u_{n + 1} = x_n - \varepsilon_n = 6 – 127 = -121$, при этом $\varepsilon_n = -128-(-121)=-7$, а уровень квантования -128; +\item $u_{n + 2} = x_n - \varepsilon_n = 6 – (–7) = 13$, при этом $\varepsilon_n = 127 - 13 = 104$, а уровень квантования 127; +\item $u_{n + 3} = x_n - \varepsilon_n = 6 – 104 = -98$, при этом $\varepsilon_n= -128-(-98) = -30$, а уровень квантования -128; +\item $u_{n + 4} = x_n - \varepsilon_n = 26 – (–30) = 106$, при этом ξn= 127-106 = 11, а уровень квантования 127 F: Un+1=XN-ξn=26 – 11 = 15, при этом ξn= 127-15 = 112, а уровень квантования 127 + G: Un+1=XN-ξn=26 – 112 = -86, при этом ξn= -128-(-86) = -42, а уровень квантования -128 H: Un+1=XN-varepsilonn=26 – (–42) = 88, при этом ξn= 127-88 = 39, а уровень квантования 127 +\end{enumerate} +\subsection{Разработка модулей} +По шагам из методического материала был создан проект в САПР Quartus Prime (доступен по \href{https://git.iovchinnikov.ru/ivan-igorevich/fpga-lab-2/commits/branch/lab4}{ссылке}). + +\section{Выводы} + +\newpage +\appendix +\setcounter{secnumdepth}{4} +\section{Приложения} +\subsection{Исходные коды проекта} +\label{appendix:src} + +\lstinputlisting[language=C,style=CCodeStyle,caption={\code{sem.c}},label={lst:sem}]{src/sem.c} + +\end{document} + + + diff --git a/pics/03-fpga-03-lab-indi-scheme.svg b/pics/03-fpga-03-lab-indi-scheme.svg new file mode 100644 index 0000000..a7cfa54 --- /dev/null +++ b/pics/03-fpga-03-lab-indi-scheme.svg @@ -0,0 +1,200 @@ + + + + + + + + + + Исходные данные + Искомые значения + + + + + + + + + + + + + + + + + + + + + \circled{1} + \circled{4} + \circled{3} + \circled{2} + + diff --git a/pics/03-fpga-04-sigdel.pgf b/pics/03-fpga-04-sigdel.pgf new file mode 100644 index 0000000..c375d55 --- /dev/null +++ b/pics/03-fpga-04-sigdel.pgf @@ -0,0 +1,1822 @@ +%% Creator: Matplotlib, PGF backend +%% +%% To include the figure in your LaTeX document, write +%% \input{.pgf} +%% +%% Make sure the required packages are loaded in your preamble +%% \usepackage{pgf} +%% +%% Also ensure that all the required font packages are loaded; for instance, +%% the lmodern package is sometimes necessary when using math font. +%% \usepackage{lmodern} +%% +%% Figures using additional raster images can only be included by \input if +%% they are in the same directory as the main LaTeX file. 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