97 lines
2.7 KiB
Systemverilog
97 lines
2.7 KiB
Systemverilog
module dec
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#(m = 32)
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(
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//clock and reset
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//control slave
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//memory slave
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//external ports
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);
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typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
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logic run;
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logic [1:0] divider;
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logic [1:0] state;
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logic [31:0] greenSaved;
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logic [31:0] greenCount;
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// we don't enable counters, if color is green
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always_comb begin
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enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
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end
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always_ff @ (posedge clk or negedge clrn) begin
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if (!clrn) begin
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colors <= 3'b001;
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state <= GREEN;
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greenCount <= 32'd0;
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end else begin
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if (~run) begin
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colors <= 3'b001;
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state <= GREEN;
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end
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if (train) begin
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colors <= 3'b100;
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state <= RED;
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greenSaved <= divisor;
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greenCount <= divisor;
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end else begin
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case (state)
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RED: begin
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colors <= 3'b100;
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if (enacnt) begin
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state <= state + 1'b1;
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greenSaved <= divisor;
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end
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end
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YELLOW: begin
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colors <= 3'b010;
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if (enacnt) begin
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state <= state + 1'b1;
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end
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end
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BLINK: begin
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if (enacnt) begin
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state <= state + 1'b1;
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end
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if (greenSaved[0] == 0) begin
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colors <= 3'b011;
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end else begin
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greenCount <= greenCount - 1'b1;
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if (greenCount == 32'd0) begin
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colors[1] <= ~colors[1];
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greenCount <= greenSaved;
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end
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end
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end
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GREEN: begin
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if (enacnt) begin
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state <= state + 1'b1;
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end
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colors <= 3'b001;
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end
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default: colors <= 3'b100;
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endcase
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end
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end
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end
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assign contr = state;
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assign red = colors[2];
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assign yellow = colors[1];
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assign green = colors[0];
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periodram b2v_inst3
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(
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.clock(clk),
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.data (ram_wrdata),
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.wraddress (ram_addr),
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.wren (ram_wr),
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.rdaddress({divider,contr}),
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.q(divisor)
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);
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endmodule
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