56 lines
2.4 KiB
Verilog
56 lines
2.4 KiB
Verilog
// niosII_tb.v
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module niosII_tb (
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);
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wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
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wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
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reg train;
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wire red, yellow, green;
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niosII niosii_inst (
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.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
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.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
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.sem_export_train (train), // sem_export.train
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.sem_export_red (red), // .red
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.sem_export_yellow (yellow), // .yellow
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.sem_export_green (green) // .green
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);
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altera_avalon_clock_source #(
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.CLOCK_RATE (50000000),
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.CLOCK_UNIT (1)
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) niosii_inst_clk_bfm (
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.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
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);
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altera_avalon_reset_source #(
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.ASSERT_HIGH_RESET (0),
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.INITIAL_RESET_CYCLES (50)
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) niosii_inst_reset_bfm (
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.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
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.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
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);
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initial begin
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train = 0;
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wait (niosii_inst_reset_bfm_reset_reset);
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forever begin
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wait ({red,yellow,green}==3'b001);
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repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
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repeat(8) begin
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train = 1;
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repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
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train = 0;
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wait ({red,yellow,green}==3'b001);
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repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
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end
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end
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end
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endmodule
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