# -*- mode: snippet -*-
# name: testbench
# key: tb
# --
`timescale 1 ns/1 ns
// `timescale 10 ps/10 ps

module $1_tb();

   logic clk, clr;

   // Instantiate UUT
   $1 UUT (.clk(clk), .reset(clr), 
       //add more custom signals here
   );
   
   // Clock definition
   initial begin
	  clk = 0;
	  forever #25 clk = ~clk; // 20MHz
   end

   // reset signal definition
   initial begin
	  clr = 0;
	  repeat(100)@(posedge clk); // wait 100 clock periods
	  clr = 1;
   end
   
   initial begin
	  repeat(120)@(posedge clk); // wait 120 clock periods (reset + a bit more)

      // do useful things here

	  repeat(10)@(posedge clk);
	  $stop;
   end   
endmodule