fpga-lab-2/Testbench/sigdel/db/sigdel_partition_pins.json

{
	"partitions" : [
		{
			"name" : "Top",
			"pins" : [
				{
					"name" : "phase[0]",
					"strict" : false
				},
				{
					"name" : "phase[1]",
					"strict" : false
				},
				{
					"name" : "phase[2]",
					"strict" : false
				},
				{
					"name" : "phase[3]",
					"strict" : false
				},
				{
					"name" : "phase[4]",
					"strict" : false
				},
				{
					"name" : "phase[5]",
					"strict" : false
				},
				{
					"name" : "phase[6]",
					"strict" : false
				},
				{
					"name" : "phase[7]",
					"strict" : false
				},
				{
					"name" : "clk",
					"strict" : false
				},
				{
					"name" : "clr_n",
					"strict" : false
				},
				{
					"name" : "phinc[6]",
					"strict" : false
				},
				{
					"name" : "phinc[7]",
					"strict" : false
				},
				{
					"name" : "phinc[5]",
					"strict" : false
				},
				{
					"name" : "phinc[4]",
					"strict" : false
				},
				{
					"name" : "phinc[3]",
					"strict" : false
				},
				{
					"name" : "phinc[2]",
					"strict" : false
				},
				{
					"name" : "phinc[1]",
					"strict" : false
				},
				{
					"name" : "phinc[0]",
					"strict" : false
				}
			]
		}
	]
}