fpga-lab-2/Top/niosII/niosII_bb.v

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module niosII (
clk_clk,
reset_reset_n,
sem_export_train,
sem_export_red,
sem_export_yellow,
sem_export_green);
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input clk_clk;
input reset_reset_n;
input sem_export_train;
output sem_export_red;
output sem_export_yellow;
output sem_export_green;
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endmodule