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# (C) 2001-2023 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
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# ACDS 18.1 625 linux 2023.01.17.19:01:36
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# ----------------------------------------
# Initialize variables
if ! [ info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME " "
} elseif { ! [ string match " " $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME " / $ S Y S T E M _ I N S T A N C E _ N A M E "
}
if ! [ info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME " n i o s I I _ t b "
}
if ! [ info exists QSYS_SIMDIR] {
set QSYS_SIMDIR " . / . . / "
}
if ! [ info exists QUARTUS_INSTALL_DIR] {
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set QUARTUS_INSTALL_DIR " / h o m e / o v c h i n n i k o v _ i i @ R I S D E . r u / i n t e l F P G A _ l i t e / 1 8 . 1 / q u a r t u s / "
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}
if ! [ info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS " "
}
if ! [ info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS " "
}
if ! [ info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS " "
}
if ! [ info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS " "
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS " "
set SIM_OPTIONS " "
if ! [ string match " * - 6 4 v s i m * " [ vsim - version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo " \[ e x e c \] f i l e _ c o p y "
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_ociram_default_contents.dat ./
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_a.dat ./
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file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_ociram_default_contents.mif ./
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file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_b.dat ./
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_b.hex ./
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_b.mif ./
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file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_ociram_default_contents.hex ./
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_a.mif ./
file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_cpu_cpu_rf_ram_a.hex ./
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file copy - force $QSYS_SIMDIR / niosII_tb/ simulation/ submodules/ niosII_mem.hex ./
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ! [ file isdirectory $lib ] { vlib $lib } }
ensure_lib ./ libraries/
ensure_lib ./ libraries/ work/
vmap work ./ libraries/ work/
vmap work_lib ./ libraries/ work/
if ! [ string match " * M o d e l S i m A L T E R A * " [ vsim - version ] ] {
ensure_lib ./ libraries/ altera_ver/
vmap altera_ver ./ libraries/ altera_ver/
ensure_lib ./ libraries/ lpm_ver/
vmap lpm_ver ./ libraries/ lpm_ver/
ensure_lib ./ libraries/ sgate_ver/
vmap sgate_ver ./ libraries/ sgate_ver/
ensure_lib ./ libraries/ altera_mf_ver/
vmap altera_mf_ver ./ libraries/ altera_mf_ver/
ensure_lib ./ libraries/ altera_lnsim_ver/
vmap altera_lnsim_ver ./ libraries/ altera_lnsim_ver/
ensure_lib ./ libraries/ cycloneive_ver/
vmap cycloneive_ver ./ libraries/ cycloneive_ver/
}
ensure_lib ./ libraries/ altera_common_sv_packages/
vmap altera_common_sv_packages ./ libraries/ altera_common_sv_packages/
ensure_lib ./ libraries/ error_adapter_0/
vmap error_adapter_0 ./ libraries/ error_adapter_0/
ensure_lib ./ libraries/ avalon_st_adapter/
vmap avalon_st_adapter ./ libraries/ avalon_st_adapter/
ensure_lib ./ libraries/ rsp_mux_001/
vmap rsp_mux_001 ./ libraries/ rsp_mux_001/
ensure_lib ./ libraries/ rsp_mux/
vmap rsp_mux ./ libraries/ rsp_mux/
ensure_lib ./ libraries/ rsp_demux/
vmap rsp_demux ./ libraries/ rsp_demux/
ensure_lib ./ libraries/ cmd_mux_002/
vmap cmd_mux_002 ./ libraries/ cmd_mux_002/
ensure_lib ./ libraries/ cmd_mux/
vmap cmd_mux ./ libraries/ cmd_mux/
ensure_lib ./ libraries/ cmd_demux_001/
vmap cmd_demux_001 ./ libraries/ cmd_demux_001/
ensure_lib ./ libraries/ cmd_demux/
vmap cmd_demux ./ libraries/ cmd_demux/
ensure_lib ./ libraries/ router_008/
vmap router_008 ./ libraries/ router_008/
ensure_lib ./ libraries/ router_004/
vmap router_004 ./ libraries/ router_004/
ensure_lib ./ libraries/ router_002/
vmap router_002 ./ libraries/ router_002/
ensure_lib ./ libraries/ router_001/
vmap router_001 ./ libraries/ router_001/
ensure_lib ./ libraries/ router/
vmap router ./ libraries/ router/
ensure_lib ./ libraries/ jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./ libraries/ jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
ensure_lib ./ libraries/ jtag_uart_avalon_jtag_slave_agent/
vmap jtag_uart_avalon_jtag_slave_agent ./ libraries/ jtag_uart_avalon_jtag_slave_agent/
ensure_lib ./ libraries/ cpu_data_master_agent/
vmap cpu_data_master_agent ./ libraries/ cpu_data_master_agent/
ensure_lib ./ libraries/ jtag_uart_avalon_jtag_slave_translator/
vmap jtag_uart_avalon_jtag_slave_translator ./ libraries/ jtag_uart_avalon_jtag_slave_translator/
ensure_lib ./ libraries/ cpu_data_master_translator/
vmap cpu_data_master_translator ./ libraries/ cpu_data_master_translator/
ensure_lib ./ libraries/ cpu/
vmap cpu ./ libraries/ cpu/
ensure_lib ./ libraries/ rst_controller/
vmap rst_controller ./ libraries/ rst_controller/
ensure_lib ./ libraries/ irq_mapper/
vmap irq_mapper ./ libraries/ irq_mapper/
ensure_lib ./ libraries/ mm_interconnect_0/
vmap mm_interconnect_0 ./ libraries/ mm_interconnect_0/
ensure_lib ./ libraries/ sys_clk_timer/
vmap sys_clk_timer ./ libraries/ sys_clk_timer/
ensure_lib ./ libraries/ sem/
vmap sem ./ libraries/ sem/
ensure_lib ./ libraries/ mem/
vmap mem ./ libraries/ mem/
ensure_lib ./ libraries/ jtag_uart/
vmap jtag_uart ./ libraries/ jtag_uart/
ensure_lib ./ libraries/ niosII_inst_reset_bfm/
vmap niosII_inst_reset_bfm ./ libraries/ niosII_inst_reset_bfm/
ensure_lib ./ libraries/ niosII_inst_clk_bfm/
vmap niosII_inst_clk_bfm ./ libraries/ niosII_inst_clk_bfm/
ensure_lib ./ libraries/ niosII_inst/
vmap niosII_inst ./ libraries/ niosII_inst/
# ----------------------------------------
# Compile device library files
alias dev_com {
echo " \[ e x e c \] d e v _ c o m "
if ! [ string match " * M o d e l S i m A L T E R A * " [ vsim - version ] ] {
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / a l t e r a _ p r i m i t i v e s . v " - work altera_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / 2 2 0 m o d e l . v " - work lpm_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / s g a t e . v " - work sgate_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / a l t e r a _ m f . v " - work altera_mf_ver
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / a l t e r a _ l n s i m . s v " - work altera_lnsim_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q U A R T U S _ I N S T A L L _ D I R / e d a / s i m _ l i b / c y c l o n e i v e _ a t o m s . v " - work cycloneive_ver
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo " \[ e x e c \] c o m "
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / v e r b o s i t y _ p k g . s v " - work altera_common_sv_packages
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ a v a l o n _ s t _ a d a p t e r _ e r r o r _ a d a p t e r _ 0 . s v " - L altera_common_sv_packages - work error_adapter_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ a v a l o n _ s t _ a d a p t e r . v " - work avalon_st_adapter
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r s p _ m u x _ 0 0 1 . s v " - L altera_common_sv_packages - work rsp_mux_001
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ a r b i t r a t o r . s v " - L altera_common_sv_packages - work rsp_mux_001
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r s p _ m u x . s v " - L altera_common_sv_packages - work rsp_mux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ a r b i t r a t o r . s v " - L altera_common_sv_packages - work rsp_mux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r s p _ d e m u x . s v " - L altera_common_sv_packages - work rsp_demux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ c m d _ m u x _ 0 0 2 . s v " - L altera_common_sv_packages - work cmd_mux_002
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ a r b i t r a t o r . s v " - L altera_common_sv_packages - work cmd_mux_002
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ c m d _ m u x . s v " - L altera_common_sv_packages - work cmd_mux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ a r b i t r a t o r . s v " - L altera_common_sv_packages - work cmd_mux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ c m d _ d e m u x _ 0 0 1 . s v " - L altera_common_sv_packages - work cmd_demux_001
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ c m d _ d e m u x . s v " - L altera_common_sv_packages - work cmd_demux
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r o u t e r _ 0 0 8 . s v " - L altera_common_sv_packages - work router_008
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r o u t e r _ 0 0 4 . s v " - L altera_common_sv_packages - work router_004
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r o u t e r _ 0 0 2 . s v " - L altera_common_sv_packages - work router_002
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r o u t e r _ 0 0 1 . s v " - L altera_common_sv_packages - work router_001
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 _ r o u t e r . s v " - L altera_common_sv_packages - work router
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ a v a l o n _ s c _ f i f o . v " - work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ s l a v e _ a g e n t . s v " - L altera_common_sv_packages - work jtag_uart_avalon_jtag_slave_agent
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ b u r s t _ u n c o m p r e s s o r . s v " - L altera_common_sv_packages - work jtag_uart_avalon_jtag_slave_agent
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ m a s t e r _ a g e n t . s v " - L altera_common_sv_packages - work cpu_data_master_agent
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ s l a v e _ t r a n s l a t o r . s v " - L altera_common_sv_packages - work jtag_uart_avalon_jtag_slave_translator
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ m e r l i n _ m a s t e r _ t r a n s l a t o r . s v " - L altera_common_sv_packages - work cpu_data_master_translator
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u _ c p u _ d e b u g _ s l a v e _ s y s c l k . v " - work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u _ c p u _ d e b u g _ s l a v e _ t c k . v " - work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u _ c p u . v " - work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u _ c p u _ d e b u g _ s l a v e _ w r a p p e r . v " - work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u _ c p u _ t e s t _ b e n c h . v " - work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ r e s e t _ c o n t r o l l e r . v " - work rst_controller
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ r e s e t _ s y n c h r o n i z e r . v " - work rst_controller
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ i r q _ m a p p e r . s v " - L altera_common_sv_packages - work irq_mapper
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m m _ i n t e r c o n n e c t _ 0 . v " - work mm_interconnect_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ s y s _ c l k _ t i m e r . v " - work sys_clk_timer
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / d e c . s v " - L altera_common_sv_packages - work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / p e r i o d r a m . v " - work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ m e m . v " - work mem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ j t a g _ u a r t . v " - work jtag_uart
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I _ c p u . v " - work cpu
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ a v a l o n _ r e s e t _ s o u r c e . s v " - L altera_common_sv_packages - work niosII_inst_reset_bfm
eval vlog - sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / a l t e r a _ a v a l o n _ c l o c k _ s o u r c e . s v " - L altera_common_sv_packages - work niosII_inst_clk_bfm
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / s u b m o d u l e s / n i o s I I . v " - work niosII_inst
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS " $ Q S Y S _ S I M D I R / n i o s I I _ t b / s i m u l a t i o n / n i o s I I _ t b . v "
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo " \[ e x e c \] e l a b "
eval vsim - t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS - L work - L work_lib - L altera_common_sv_packages - L error_adapter_0 - L avalon_st_adapter - L rsp_mux_001 - L rsp_mux - L rsp_demux - L cmd_mux_002 - L cmd_mux - L cmd_demux_001 - L cmd_demux - L router_008 - L router_004 - L router_002 - L router_001 - L router - L jtag_uart_avalon_jtag_slave_agent_rsp_fifo - L jtag_uart_avalon_jtag_slave_agent - L cpu_data_master_agent - L jtag_uart_avalon_jtag_slave_translator - L cpu_data_master_translator - L cpu - L rst_controller - L irq_mapper - L mm_interconnect_0 - L sys_clk_timer - L sem - L mem - L jtag_uart - L niosII_inst_reset_bfm - L niosII_inst_clk_bfm - L niosII_inst - L altera_ver - L lpm_ver - L sgate_ver - L altera_mf_ver - L altera_lnsim_ver - L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo " \[ e x e c \] e l a b _ d e b u g "
eval vsim - novopt - t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS - L work - L work_lib - L altera_common_sv_packages - L error_adapter_0 - L avalon_st_adapter - L rsp_mux_001 - L rsp_mux - L rsp_demux - L cmd_mux_002 - L cmd_mux - L cmd_demux_001 - L cmd_demux - L router_008 - L router_004 - L router_002 - L router_001 - L router - L jtag_uart_avalon_jtag_slave_agent_rsp_fifo - L jtag_uart_avalon_jtag_slave_agent - L cpu_data_master_agent - L jtag_uart_avalon_jtag_slave_translator - L cpu_data_master_translator - L cpu - L rst_controller - L irq_mapper - L mm_interconnect_0 - L sys_clk_timer - L sem - L mem - L jtag_uart - L niosII_inst_reset_bfm - L niosII_inst_clk_bfm - L niosII_inst - L altera_ver - L lpm_ver - L sgate_ver - L altera_mf_ver - L altera_lnsim_ver - L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo " L i s t O f C o m m a n d L i n e A l i a s e s "
echo
echo " f i l e _ c o p y - - C o p y R O M / R A M f i l e s t o s i m u l a t i o n d i r e c t o r y "
echo
echo " d e v _ c o m - - C o m p i l e d e v i c e l i b r a r y f i l e s "
echo
echo " c o m - - C o m p i l e t h e d e s i g n f i l e s i n c o r r e c t o r d e r "
echo
echo " e l a b - - E l a b o r a t e t o p l e v e l d e s i g n "
echo
echo " e l a b _ d e b u g - - E l a b o r a t e t h e t o p l e v e l d e s i g n w i t h n o v o p t o p t i o n "
echo
echo " l d - - C o m p i l e a l l t h e d e s i g n f i l e s a n d e l a b o r a t e t h e t o p l e v e l d e s i g n "
echo
echo " l d _ d e b u g - - C o m p i l e a l l t h e d e s i g n f i l e s a n d e l a b o r a t e t h e t o p l e v e l d e s i g n w i t h - n o v o p t "
echo
echo
echo
echo " L i s t O f V a r i a b l e s "
echo
echo " T O P _ L E V E L _ N A M E - - T o p l e v e l m o d u l e n a m e . "
echo " F o r m o s t d e s i g n s , t h i s s h o u l d b e o v e r r i d d e n "
echo " t o e n a b l e t h e e l a b / e l a b _ d e b u g a l i a s e s . "
echo
echo " S Y S T E M _ I N S T A N C E _ N A M E - - I n s t a n t i a t e d s y s t e m m o d u l e n a m e i n s i d e t o p l e v e l m o d u l e . "
echo
echo " Q S Y S _ S I M D I R - - P l a t f o r m D e s i g n e r b a s e s i m u l a t i o n d i r e c t o r y . "
echo
echo " Q U A R T U S _ I N S T A L L _ D I R - - Q u a r t u s i n s t a l l a t i o n d i r e c t o r y . "
echo
echo " U S E R _ D E F I N E D _ C O M P I L E _ O P T I O N S - - U s e r - d e f i n e d c o m p i l e o p t i o n s , a d d e d t o c o m / d e v _ c o m a l i a s e s . "
echo
echo " U S E R _ D E F I N E D _ E L A B _ O P T I O N S - - U s e r - d e f i n e d e l a b o r a t i o n o p t i o n s , a d d e d t o e l a b / e l a b _ d e b u g a l i a s e s . "
echo
echo " U S E R _ D E F I N E D _ V H D L _ C O M P I L E _ O P T I O N S - - U s e r - d e f i n e d v h d l c o m p i l e o p t i o n s , a d d e d t o c o m / d e v _ c o m a l i a s e s . "
echo
echo " U S E R _ D E F I N E D _ V E R I L O G _ C O M P I L E _ O P T I O N S - - U s e r - d e f i n e d v e r i l o g c o m p i l e o p t i o n s , a d d e d t o c o m / d e v _ c o m a l i a s e s . "
}
file_copy
h
