20 lines
503 B
Systemverilog
20 lines
503 B
Systemverilog
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module top
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(
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input logic clk,
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input logic train,
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output logic green,
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output logic red,
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output logic yellow
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);
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niosII u0 (
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.clk_clk (clk), // clk.clk
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.reset_reset_n (1'b1), // reset.reset_n
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.sem_export_train (~train), // sem_export.train
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.sem_export_red (red), // .red
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.sem_export_yellow (yellow), // .yellow
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.sem_export_green (green) // .green
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);
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endmodule
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