fpga-lab-2/Top/countones_ci_hw.tcl

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2022-12-24 22:37:46 +03:00
# TCL File Generated by Component Editor 18.1
# Sat Dec 24 22:54:47 MSK 2022
# DO NOT MODIFY
#
# countones_ci "countones_ci" v1.0
# 2022.12.24.22:54:47
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module countones_ci
#
set_module_property DESCRIPTION ""
set_module_property NAME countones_ci
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Custom Instruction Modules"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME countones_ci
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL countones
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file countones.v VERILOG PATH ../HDL/countones.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
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# connection point nios_custom_instruction_slave
#
add_interface nios_custom_instruction_slave nios_custom_instruction end
set_interface_property nios_custom_instruction_slave clockCycle 0
set_interface_property nios_custom_instruction_slave operands 1
set_interface_property nios_custom_instruction_slave ENABLED true
set_interface_property nios_custom_instruction_slave EXPORT_OF ""
set_interface_property nios_custom_instruction_slave PORT_NAME_MAP ""
set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES ""
set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP ""
add_interface_port nios_custom_instruction_slave din dataa Input 32
add_interface_port nios_custom_instruction_slave ones result Output 32