54 lines
2.1 KiB
Plaintext
54 lines
2.1 KiB
Plaintext
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
|
<system name="$${FILENAME}">
|
||
|
|
<component
|
||
|
|
name="$${FILENAME}"
|
||
|
|
displayName="$${FILENAME}"
|
||
|
|
version="1.0"
|
||
|
|
description=""
|
||
|
|
tags=""
|
||
|
|
categories="" />
|
||
|
|
<parameter name="bonusData"><![CDATA[bonusData
|
||
|
|
{
|
||
|
|
element clk
|
||
|
|
{
|
||
|
|
datum _sortIndex
|
||
|
|
{
|
||
|
|
value = "0";
|
||
|
|
type = "int";
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
]]></parameter>
|
||
|
|
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||
|
|
<parameter name="device" value="EP4CE115F29C7" />
|
||
|
|
<parameter name="deviceFamily" value="Cyclone IV E" />
|
||
|
|
<parameter name="deviceSpeedGrade" value="7" />
|
||
|
|
<parameter name="fabricMode" value="QSYS" />
|
||
|
|
<parameter name="generateLegacySim" value="false" />
|
||
|
|
<parameter name="generationId" value="0" />
|
||
|
|
<parameter name="globalResetBus" value="false" />
|
||
|
|
<parameter name="hdlLanguage" value="VERILOG" />
|
||
|
|
<parameter name="hideFromIPCatalog" value="false" />
|
||
|
|
<parameter name="lockedInterfaceDefinition" value="" />
|
||
|
|
<parameter name="maxAdditionalLatency" value="1" />
|
||
|
|
<parameter name="projectName" value="" />
|
||
|
|
<parameter name="sopcBorderPoints" value="false" />
|
||
|
|
<parameter name="systemHash" value="0" />
|
||
|
|
<parameter name="testBenchDutName" value="" />
|
||
|
|
<parameter name="timeStamp" value="0" />
|
||
|
|
<parameter name="useTestBenchNamingPattern" value="false" />
|
||
|
|
<instanceScript></instanceScript>
|
||
|
|
<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
|
||
|
|
<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
|
||
|
|
<module name="clk" kind="clock_source" version="18.1" enabled="1">
|
||
|
|
<parameter name="clockFrequency" value="50000000" />
|
||
|
|
<parameter name="clockFrequencyKnown" value="true" />
|
||
|
|
<parameter name="inputClockFrequency" value="0" />
|
||
|
|
<parameter name="resetSynchronousEdges" value="NONE" />
|
||
|
|
</module>
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||
|
|
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||
|
|
</system>
|