diff --git a/HDL/avalon_pwm.v b/HDL/avalon_pwm.v new file mode 100644 index 0000000..f17ce25 --- /dev/null +++ b/HDL/avalon_pwm.v @@ -0,0 +1,88 @@ +module avalon_pwm +( + clk, wr_data, cs, wr_n, addr, clr_n, rd_data, pwm_out +); + + input clk; + input [31:0] wr_data; + input cs; + input wr_n; + input addr; + input clr_n; + output [31:0] rd_data; + output [7:0] pwm_out; + + ///////////////////////////////////////////////////////////////////// + // Registers and wires + + reg [31:0] div; + reg [31:0] duty; + reg [31:0] counter; + reg off; + reg [31:0] rd_data; + wire div_en, duty_en; + + ///////////////////////////////////////////////////////////////////// + // Avalon slave interface + + //chip select and address decoder + assign div_en = cs & !wr_n & !addr ; + assign duty_en = cs & !wr_n & addr ; + + //register write + always @(posedge clk or negedge clr_n) + begin + if (clr_n == 0) + begin + div <= 0; + duty <= 0; + end + else + begin + if (div_en) div <= wr_data; + if (duty_en) duty <= wr_data; + end + end + + //register read + always @(*) + begin + if (addr == 0) + rd_data = div; + else + rd_data = duty; + end + + ///////////////////////////////////////////////////////////////////// + // PWM logic + + //PWM counter + always @(posedge clk or negedge clr_n) + begin + if (clr_n == 0) + counter <= 0; + else + if (counter >= div) + counter <= 0; + else + counter <= counter + 1; + end + + //PWM compare + always @(posedge clk or negedge clr_n) + begin + if (clr_n == 0) + off <= 0; + else + if (counter >= duty) + off <= 1; + else + if (counter == 0) + off <= 0; + else + off <= off; + end + + assign pwm_out = {8{!off}}; + +endmodule diff --git a/HDL/countones.v b/HDL/countones.v new file mode 100644 index 0000000..84b2ef2 --- /dev/null +++ b/HDL/countones.v @@ -0,0 +1,17 @@ +module countones(din,ones); + + input [31:0] din; + output reg [31:0] ones; + + integer i; + + always @(*) + begin + ones=0; + for (i = 0; i<32; i=i+1) + begin + if (din[i]) ones=ones+1; + end + end + +endmodule diff --git a/Top/countones_ci_hw.tcl b/Top/countones_ci_hw.tcl new file mode 100644 index 0000000..9fa2ced --- /dev/null +++ b/Top/countones_ci_hw.tcl @@ -0,0 +1,70 @@ +# TCL File Generated by Component Editor 18.1 +# Sat Dec 24 22:54:47 MSK 2022 +# DO NOT MODIFY + + +# +# countones_ci "countones_ci" v1.0 +# 2022.12.24.22:54:47 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module countones_ci +# +set_module_property DESCRIPTION "" +set_module_property NAME countones_ci +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP "Custom Instruction Modules" +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME countones_ci +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL countones +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file countones.v VERILOG PATH ../HDL/countones.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point nios_custom_instruction_slave +# +add_interface nios_custom_instruction_slave nios_custom_instruction end +set_interface_property nios_custom_instruction_slave clockCycle 0 +set_interface_property nios_custom_instruction_slave operands 1 +set_interface_property nios_custom_instruction_slave ENABLED true +set_interface_property nios_custom_instruction_slave EXPORT_OF "" +set_interface_property nios_custom_instruction_slave PORT_NAME_MAP "" +set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES "" +set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP "" + +add_interface_port nios_custom_instruction_slave din dataa Input 32 +add_interface_port nios_custom_instruction_slave ones result Output 32 + diff --git a/Top/niosII.qsys b/Top/niosII.qsys index c2c790b..1478d9d 100644 --- a/Top/niosII.qsys +++ b/Top/niosII.qsys @@ -17,6 +17,14 @@ type = "int"; } } + element countones + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } element cpu { datum _sortIndex @@ -37,7 +45,7 @@ { datum _sortIndex { - value = "3"; + value = "4"; type = "int"; } } @@ -45,7 +53,7 @@ { datum baseAddress { - value = "135272"; + value = "135336"; type = "String"; } } @@ -53,7 +61,7 @@ { datum _sortIndex { - value = "2"; + value = "3"; type = "int"; } } @@ -105,23 +113,15 @@ type = "String"; } } - element sem + element perf_counter { datum _sortIndex { - value = "5"; + value = "7"; type = "int"; } } - element sem.ctl_slave - { - datum baseAddress - { - value = "135264"; - type = "String"; - } - } - element sem.ram_slave + element perf_counter.control_slave { datum baseAddress { @@ -129,11 +129,35 @@ type = "String"; } } + element sem + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element sem.ctl_slave + { + datum baseAddress + { + value = "135328"; + type = "String"; + } + } + element sem.ram_slave + { + datum baseAddress + { + value = "135232"; + type = "String"; + } + } element sys_clk_timer { datum _sortIndex { - value = "4"; + value = "5"; type = "int"; } } @@ -141,7 +165,7 @@ { datum baseAddress { - value = "135232"; + value = "135296"; type = "String"; } } @@ -175,6 +199,7 @@ + @@ -188,14 +213,14 @@ - + ]]> - ]]> + ]]> @@ -404,6 +429,13 @@ + + + @@ -429,7 +461,16 @@ start="cpu.data_master" end="jtag_uart.avalon_jtag_slave"> - + + + + + + - + - + - + @@ -494,6 +535,7 @@ + + + + + + + + - + java.lang.Integer - 1671833790 + 1671909530 false true false @@ -348,6 +348,12 @@ parameters are a RESULT of the module parameters. --> clk sys_clk_timer.clk + + false + perf_counter + clk + perf_counter.clk + false mem @@ -423,6 +429,128 @@ parameters are a RESULT of the module parameters. --> + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.custominstruction.CustomInstruction$ClockCycleType + COMBINATORIAL + true + true + true + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + false + + din + Input + 32 + dataa + + + ones + Output + 32 + result + + + @@ -2034,7 +2162,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -2173,7 +2301,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -2705,15 +2833,23 @@ parameters are a RESULT of the module parameters. --> jtag_uart avalon_jtag_slave jtag_uart.avalon_jtag_slave - 135272 + 135336 8 + + false + perf_counter + control_slave + perf_counter.control_slave + 135168 + 64 + false sem ctl_slave sem.ctl_slave - 135264 + 135328 8 @@ -2729,7 +2865,7 @@ parameters are a RESULT of the module parameters. --> sem ram_slave sem.ram_slave - 135168 + 135232 64 @@ -2737,7 +2873,7 @@ parameters are a RESULT of the module parameters. --> sys_clk_timer s1 sys_clk_timer.s1 - 135232 + 135296 32 @@ -3598,7 +3734,7 @@ parameters are a RESULT of the module parameters. --> int 0 false - false + true true true @@ -3628,7 +3764,7 @@ parameters are a RESULT of the module parameters. --> boolean - false + true false true false @@ -3653,11 +3789,103 @@ parameters are a RESULT of the module parameters. --> nios_custom_instruction true - dummy_ci_port + E_ci_result + Input + 32 + result + + + D_ci_a + Output + 5 + a + + + D_ci_b + Output + 5 + b + + + D_ci_c + Output + 5 + c + + + D_ci_n + Output + 8 + n + + + D_ci_readra Output 1 readra + + D_ci_readrb + Output + 1 + readrb + + + D_ci_writerc + Output + 1 + writerc + + + E_ci_dataa + Output + 32 + dataa + + + E_ci_datab + Output + 32 + datab + + + E_ci_multi_clock + Output + 1 + clk + + + E_ci_multi_reset + Output + 1 + reset + + + E_ci_multi_reset_req + Output + 1 + reset_req + + + W_ci_estatus + Output + 1 + estatus + + + W_ci_ipending + Output + 32 + ipending + + + false + countones + nios_custom_instruction_slave + countones.nios_custom_instruction_slave + 0 + countones + + + + + embeddedsw.CMacro.HOW_MANY_SECTIONS + 3 + + + int + 3 + false + true + true + true + + + int + 4 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 4 + address + + + begintransfer + Input + 1 + begintransfer + + + readdata + Output + 32 + readdata + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + @@ -7349,7 +8076,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00021068 + 0x000210a8 false true true @@ -7384,6 +8111,57 @@ parameters are a RESULT of the module parameters. --> jtag_uart avalon_jtag_slave + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00021000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + perf_counter + control_slave + java.math.BigInteger - 0x00021060 + 0x000210a0 false true true @@ -7502,7 +8280,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00021000 + 0x00021040 false true true @@ -7553,7 +8331,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00021040 + 0x00021080 false true true @@ -7822,6 +8600,33 @@ parameters are a RESULT of the module parameters. --> sys_clk_timer clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + perf_counter + clk + jtag_uart irq + + + java.lang.String + countones + false + true + true + true + + + java.lang.String + + true + true + true + true + + + int + 1 + false + true + false + true + + + long + 0 + false + true + true + true + + + int + -1 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + custom_instruction_master + countones + nios_custom_instruction_slave + sys_clk_timer reset + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk_reset + perf_counter + reset + sys_clk_timer reset + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + debug_reset_request + perf_counter + reset + Reset Output 18.1 + + 1 + countones_ci + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + countones_ci + 1.0 + + + 1 + nios_custom_instruction_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Slave + 18.1 + 1 altera_nios2_gen2 @@ -8265,7 +9207,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 5 + 6 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -8273,7 +9215,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 5 + 6 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -8305,7 +9247,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 7 + 8 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -8344,6 +9286,14 @@ parameters are a RESULT of the module parameters. --> On-Chip Memory (RAM or ROM) Intel FPGA IP 18.1 + + 1 + altera_avalon_performance_counter + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Performance Counter Unit Intel FPGA IP + 18.1 + 1 sem @@ -8369,7 +9319,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 8 + 9 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -8377,7 +9327,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 5 + 6 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -8393,7 +9343,15 @@ parameters are a RESULT of the module parameters. --> 18.1 - 10 + 1 + nios_custom_instruction + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Nios II Custom Instruction Connection + 18.1 + + + 12 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html index b1d525b..fe305a4 100644 --- a/Top/niosII/niosII.html +++ b/Top/niosII/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.24.02:16:302022.12.24.23:18:51 Datasheet
@@ -100,6 +100,9 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord mem altera_avalon_onchip_memory2 18.1
   + perf_counter + altera_avalon_performance_counter 18.1 +
   sem sem 1.1
   @@ -144,7 +147,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord avalon_jtag_slave  - 0x00021068 + 0x000210a8 @@ -165,6 +168,19 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord 0x00000000 + +   + perf_counter + + + + + + + control_slave  + 0x00021000 + +   sem @@ -175,12 +191,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord ctl_slave  - 0x00021060 + 0x000210a0 ram_slave  - 0x00021000 + 0x00021040 @@ -193,7 +209,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord s1  - 0x00021040 + 0x00021080 @@ -244,6 +260,51 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + +
+
+

countones

countones_ci v1.0 +
+
+ + + + + + + + + +
+ cpu + custom_instruction_master  countones
  nios_custom_instruction_slave
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + +
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
@@ -256,7 +317,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord clk clk   - cpu + cpu   clk @@ -303,6 +364,32 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + data_master   + + perf_counter + + + + + +   control_slave + + + + + debug_reset_request   + + + + +   reset + + + + @@ -408,6 +495,22 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord   reset1 + + + + + + + custom_instruction_master   + + countones + + + + + +   nios_custom_instruction_slave +

@@ -1107,7 +1210,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord dataSlaveMapParam - <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> + <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='perf_counter.control_slave' start='0x21000' end='0x21040' type='altera_avalon_performance_counter.control_slave' /><slave name='sem.ram_slave' start='0x21040' end='0x21080' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21080' end='0x210A0' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x210A0' end='0x210A8' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x210A8' end='0x210B0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> tightlyCoupledDataMaster0MapParam @@ -1163,7 +1266,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord customInstSlavesSystemInfo - <info/> + <info><slave name="countones" baseAddress="0" addressSpan="1" clockCycleType="COMBINATORIAL" /></info> customInstSlavesSystemInfo_nios_a @@ -1763,6 +1866,90 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + +
+
+

perf_counter

altera_avalon_performance_counter v18.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ cpu + data_master  perf_counter
  control_slave
debug_reset_request  
  reset
+ clk + clk  
  clk
clk_reset  
  reset
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + +
numberOfSections3
control_slave_address_width4
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + +
HOW_MANY_SECTIONS3
+
+
@@ -2038,8 +2225,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- - + +
generation took 0,00 secondsrendering took 0,03 secondsgeneration took 0,02 secondsrendering took 0,09 seconds
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml index 73d6d07..0d613c3 100644 --- a/Top/niosII/niosII.xml +++ b/Top/niosII/niosII.xml @@ -1,6 +1,6 @@ - + @@ -92,6 +92,10 @@ type="VERILOG" /> + @@ -143,6 +147,10 @@ path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mem.v" type="VERILOG" attributes="" /> + + + + @@ -195,11 +215,11 @@ type="SYSTEM_VERILOG" attributes="" /> + + + + + Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 6 modules, 25 connections]]> + + + + + + + + + + 11 modules, 33 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform - 6 modules, 23 connections]]> + 7 modules, 27 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform @@ -373,7 +410,10 @@ - 15 modules, 59 connections]]> + + + + 17 modules, 67 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 @@ -447,14 +487,24 @@ + + + + + + + + + Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave + Transform merlin_domain_transform not run on matched interfaces perf_counter_control_slave_translator.avalon_anti_slave_0 and perf_counter.control_slave Transform merlin_domain_transform not run on matched interfaces sem_ctl_slave_translator.avalon_anti_slave_0 and sem.ctl_slave Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave Transform merlin_domain_transform not run on matched interfaces sem_ram_slave_translator.avalon_anti_slave_0 and sem.ram_slave Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1 Transform merlin_domain_transform not run on matched interfaces mem_s2_translator.avalon_anti_slave_0 and mem.s2 Transform merlin_domain_transform not run on matched interfaces mem_s1_translator.avalon_anti_slave_0 and mem.s1 - 32 modules, 174 connections]]> + 36 modules, 196 connections]]> Transform: RouterTransform @@ -483,7 +533,10 @@ - 41 modules, 210 connections]]> + + + + 46 modules, 236 connections]]> Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform @@ -542,7 +595,13 @@ - 58 modules, 253 connections]]> + + + + + + + 65 modules, 284 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform @@ -558,19 +617,19 @@ - 60 modules, 312 connections]]> + 67 modules, 350 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 7 modules, 29 connections]]> - 7 modules, 29 connections]]> + 12 modules, 37 connections]]> + 12 modules, 37 connections]]> Transform: InterruptMapperTransform - 8 modules, 33 connections]]> + 13 modules, 41 connections]]> Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform @@ -581,16 +640,26 @@ - 10 modules, 35 connections]]> + 15 modules, 43 connections]]> + "No matching role found for cpu:custom_instruction_master:E_ci_multi_clock (clk)" + "No matching role found for cpu:custom_instruction_master:E_ci_multi_reset_req (reset_req)" + "No matching role found for cpu:custom_instruction_master:E_ci_multi_reset (reset)" + niosII" reuses countones_ci "submodules/countones"]]> niosII" reuses altera_nios2_gen2 "submodules/niosII_cpu"]]> niosII" reuses altera_avalon_jtag_uart "submodules/niosII_jtag_uart"]]> niosII" reuses altera_avalon_onchip_memory2 "submodules/niosII_mem"]]> + niosII" reuses altera_avalon_performance_counter "submodules/niosII_perf_counter"]]> niosII" reuses sem "submodules/dec"]]> niosII" reuses altera_avalon_timer "submodules/niosII_sys_clk_timer"]]> + niosII" reuses altera_customins_master_translator "submodules/altera_customins_master_translator"]]> + niosII" reuses altera_customins_xconnect "submodules/niosII_cpu_custom_instruction_master_comb_xconnect"]]> + niosII" reuses altera_customins_slave_translator "submodules/altera_customins_slave_translator"]]> niosII" reuses altera_mm_interconnect "submodules/niosII_mm_interconnect_0"]]> niosII" reuses altera_irq_mapper "submodules/niosII_irq_mapper"]]> niosII" reuses altera_reset_controller "submodules/altera_reset_controller"]]> - queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu" + queue size: 12 starting:countones_ci "submodules/countones" + niosII" instantiated countones_ci "countones"]]> + queue size: 11 starting:altera_nios2_gen2 "submodules/niosII_cpu" @@ -605,47 +674,60 @@ Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"]]> niosII" instantiated altera_nios2_gen2 "cpu"]]> - queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" + queue size: 66 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.24 01:16:53 (*) Starting Nios II generation - # 2022.12.24 01:16:53 (*) Checking for plaintext license. - # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.24 01:16:54 (*) Plaintext license not found. - # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. - # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings - # 2022.12.24 01:16:54 (*) Creating all objects for CPU - # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects - # 2022.12.24 01:16:55 (*) Creating plain-text RTL - # 2022.12.24 01:16:56 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 22:19:19 (*) Starting Nios II generation + # 2022.12.24 22:19:19 (*) Checking for plaintext license. + # 2022.12.24 22:19:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 22:19:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 22:19:20 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 22:19:20 (*) Plaintext license not found. + # 2022.12.24 22:19:20 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 22:19:20 (*) Elaborating CPU configuration settings + # 2022.12.24 22:19:20 (*) Creating all objects for CPU + # 2022.12.24 22:19:22 (*) Generating RTL from CPU objects + # 2022.12.24 22:19:22 (*) Creating plain-text RTL + # 2022.12.24 22:19:22 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> - queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" + queue size: 11 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0005_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0005_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> - queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" + queue size: 10 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0006_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0006_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> - queue size: 5 starting:sem "submodules/dec" + queue size: 9 starting:altera_avalon_performance_counter "submodules/niosII_perf_counter" + Starting RTL generation for module 'niosII_perf_counter' + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_performance_counter -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_performance_counter/generate_rtl.pl --name=niosII_perf_counter --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0007_perf_counter_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0007_perf_counter_gen//niosII_perf_counter_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'niosII_perf_counter' + niosII" instantiated altera_avalon_performance_counter "perf_counter"]]> + queue size: 8 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> - queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" + queue size: 7 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0009_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0009_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> + queue size: 6 starting:altera_customins_master_translator "submodules/altera_customins_master_translator" + niosII" instantiated altera_customins_master_translator "cpu_custom_instruction_master_translator"]]> + queue size: 5 starting:altera_customins_xconnect "submodules/niosII_cpu_custom_instruction_master_comb_xconnect" + niosII" instantiated altera_customins_xconnect "cpu_custom_instruction_master_comb_xconnect"]]> + queue size: 4 starting:altera_customins_slave_translator "submodules/altera_customins_slave_translator" + niosII" instantiated altera_customins_slave_translator "cpu_custom_instruction_master_comb_slave_translator0"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> @@ -671,7 +753,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -696,7 +778,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -721,7 +803,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -746,7 +828,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -771,7 +853,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -796,7 +878,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -821,7 +903,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -846,7 +928,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -871,7 +953,32 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 60 modules, 199 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform @@ -880,61 +987,69 @@ Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.027s - Timing: COM:3/0.052s/0.076s + Timing: ELA:1/0.000s + Timing: ELA:2/0.008s/0.016s + Timing: ELA:1/0.000s + Timing: COM:3/0.076s/0.101s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.011s - Timing: COM:3/0.021s/0.022s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.018s + Timing: COM:3/0.039s/0.054s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.019s/0.025s + Timing: ELA:1/0.015s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.011s - Timing: COM:3/0.021s/0.024s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.015s + Timing: COM:3/0.028s/0.037s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.024s/0.032s + Timing: ELA:1/0.000s + Timing: ELA:2/0.007s/0.015s + Timing: ELA:1/0.000s + Timing: COM:3/0.026s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.008s - Timing: COM:3/0.019s/0.022s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.020s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.011s - Timing: COM:3/0.022s/0.028s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.020s/0.031s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.000s + Timing: COM:3/0.015s/0.016s 61 modules, 199 connections]]> + culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform">68 modules, 223 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> @@ -945,6 +1060,7 @@ mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> @@ -961,26 +1077,31 @@ mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> - mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_005"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> - mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_009"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> - mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_003"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> @@ -995,45 +1116,46 @@ mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> niosII" instantiated altera_mm_interconnect "mm_interconnect_0"]]> - queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + queue size: 65 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> - queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + queue size: 63 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> - queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + queue size: 55 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> - queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + queue size: 53 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> - queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + queue size: 52 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> - queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" + queue size: 37 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> - queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" + queue size: 36 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> - queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" + queue size: 35 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> - queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" - mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> - queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" - mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> - queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" + queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_005" + mm_interconnect_0" instantiated altera_merlin_router "router_005"]]> + queue size: 28 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_009" + mm_interconnect_0" instantiated altera_merlin_router "router_009"]]> + queue size: 27 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> - queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" + queue size: 26 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> - queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" + queue size: 25 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> - queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" - mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> + queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_003" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_003"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" + queue size: 17 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> - queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" + queue size: 9 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" + queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" + queue size: 7 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" @@ -1050,15 +1172,39 @@ mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> - queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper" + queue size: 68 starting:altera_irq_mapper "submodules/niosII_irq_mapper" niosII" instantiated altera_irq_mapper "irq_mapper"]]> - queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller" + queue size: 67 starting:altera_reset_controller "submodules/altera_reset_controller" niosII" instantiated altera_reset_controller "rst_controller"]]> + + + + + + + + + + + queue size: 12 starting:countones_ci "submodules/countones" + niosII" instantiated countones_ci "countones"]]> + + + + value="<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='perf_counter.control_slave' start='0x21000' end='0x21040' type='altera_avalon_performance_counter.control_slave' /><slave name='sem.ram_slave' start='0x21040' end='0x21080' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21080' end='0x210A0' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x210A0' end='0x210A8' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x210A8' end='0x210B0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>" /> @@ -1162,7 +1308,9 @@ - + @@ -1317,7 +1465,7 @@ - queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu" + queue size: 11 starting:altera_nios2_gen2 "submodules/niosII_cpu" @@ -1332,21 +1480,21 @@ Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"]]> niosII" instantiated altera_nios2_gen2 "cpu"]]> - queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" + queue size: 66 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.24 01:16:53 (*) Starting Nios II generation - # 2022.12.24 01:16:53 (*) Checking for plaintext license. - # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.24 01:16:54 (*) Plaintext license not found. - # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. - # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings - # 2022.12.24 01:16:54 (*) Creating all objects for CPU - # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects - # 2022.12.24 01:16:55 (*) Creating plain-text RTL - # 2022.12.24 01:16:56 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 22:19:19 (*) Starting Nios II generation + # 2022.12.24 22:19:19 (*) Checking for plaintext license. + # 2022.12.24 22:19:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 22:19:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 22:19:20 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 22:19:20 (*) Plaintext license not found. + # 2022.12.24 22:19:20 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 22:19:20 (*) Elaborating CPU configuration settings + # 2022.12.24 22:19:20 (*) Creating all objects for CPU + # 2022.12.24 22:19:22 (*) Generating RTL from CPU objects + # 2022.12.24 22:19:22 (*) Creating plain-text RTL + # 2022.12.24 22:19:22 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> @@ -1388,9 +1536,9 @@ - queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" + queue size: 11 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0005_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0005_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> @@ -1457,13 +1605,43 @@ - queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" + queue size: 10 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0006_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0006_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> + + + + + + + + + + + + + + queue size: 9 starting:altera_avalon_performance_counter "submodules/niosII_perf_counter" + Starting RTL generation for module 'niosII_perf_counter' + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_performance_counter -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_performance_counter/generate_rtl.pl --name=niosII_perf_counter --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0007_perf_counter_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0007_perf_counter_gen//niosII_perf_counter_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'niosII_perf_counter' + niosII" instantiated altera_avalon_performance_counter "perf_counter"]]> + + - queue size: 5 starting:sem "submodules/dec" + queue size: 8 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> @@ -1531,29 +1709,154 @@ - queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" + queue size: 7 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0009_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0009_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 6 starting:altera_customins_master_translator "submodules/altera_customins_master_translator" + niosII" instantiated altera_customins_master_translator "cpu_custom_instruction_master_translator"]]> + + + + + + + + + + + + + + + + + + queue size: 5 starting:altera_customins_xconnect "submodules/niosII_cpu_custom_instruction_master_comb_xconnect" + niosII" instantiated altera_customins_xconnect "cpu_custom_instruction_master_comb_xconnect"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 4 starting:altera_customins_slave_translator "submodules/altera_customins_slave_translator" + niosII" instantiated altera_customins_slave_translator "cpu_custom_instruction_master_comb_slave_translator0"]]> + + + +};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ID} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ECC_ENABLE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {perf_counter_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {perf_counter_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {perf_counter_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {perf_counter_control_slave_agent} {ID} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {ECC_ENABLE} {0};add_instance {perf_counter_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ctl_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ctl_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ctl_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ctl_slave_agent} {ID} {5};set_instance_parameter_value {sem_ctl_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ctl_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ram_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ram_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ram_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ram_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ram_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ram_slave_agent} {ID} {6};set_instance_parameter_value {sem_ram_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ram_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s2_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s2_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s2_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s2_agent} {ID} {3};set_instance_parameter_value {mem_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {ECC_ENABLE} {0};add_instance {mem_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s1_agent} {ID} {2};set_instance_parameter_value {mem_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {ECC_ENABLE} {0};add_instance {mem_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 0 4 6 7 5 1 };set_instance_parameter_value {router} {CHANNEL_ID} {1000000 0001000 0000010 0010000 0100000 0000100 0000001 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both write both both both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x20800 0x21000 0x21040 0x21080 0x210a0 0x210a8 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 0x21000 0x21040 0x21080 0x210a0 0x210a8 0x210b0 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {53};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router} {PKT_TRANS_READ} {57};set_instance_parameter_value {router} {ST_DATA_W} {94};set_instance_parameter_value {router} {ST_CHANNEL_W} {8};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {6};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {2 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {10 01 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x20800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 0x21000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {53};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_001} {ST_DATA_W} {94};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {2};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {53};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_002} {ST_DATA_W} {94};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {53};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {0 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {53};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_004} {ST_DATA_W} {94};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_005} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_005} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {53};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_005} {ST_DATA_W} {94};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_005} {DECODER_TYPE} {1};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {0 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {53};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_006} {ST_DATA_W} {94};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_006} {DECODER_TYPE} {1};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {0 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {53};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_007} {ST_DATA_W} {94};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_007} {DECODER_TYPE} {1};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 };set_instance_parameter_value {router_008} {CHANNEL_ID} {1 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {53};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_008} {ST_DATA_W} {94};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {1 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {53};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_009} {ST_DATA_W} {94};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {7};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {7};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {jtag_uart_avalon_jtag_slave_agent.m0} {jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.rf_source} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.out} {jtag_uart_avalon_jtag_slave_agent.rf_sink} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_src} {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {jtag_uart_avalon_jtag_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/jtag_uart_avalon_jtag_slave_agent.cp} {qsys_mm.command};add_connection {perf_counter_control_slave_agent.m0} {perf_counter_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {perf_counter_control_slave_agent.rf_source} {perf_counter_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {perf_counter_control_slave_agent_rsp_fifo.out} {perf_counter_control_slave_agent.rf_sink} {avalon_streaming};add_connection {perf_counter_control_slave_agent.rdata_fifo_src} {perf_counter_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {perf_counter_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/perf_counter_control_slave_agent.cp} {qsys_mm.command};add_connection {sem_ctl_slave_agent.m0} {sem_ctl_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ctl_slave_agent.rf_source} {sem_ctl_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ctl_slave_agent_rsp_fifo.out} {sem_ctl_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ctl_slave_agent.rdata_fifo_src} {sem_ctl_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_002.src} {sem_ctl_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/sem_ctl_slave_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {sem_ram_slave_agent.m0} {sem_ram_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ram_slave_agent.rf_source} {sem_ram_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ram_slave_agent_rsp_fifo.out} {sem_ram_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ram_slave_agent.rdata_fifo_src} {sem_ram_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sem_ram_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sem_ram_slave_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {mem_s2_agent.m0} {mem_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s2_agent.rf_source} {mem_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s2_agent_rsp_fifo.out} {mem_s2_agent.rf_sink} {avalon_streaming};add_connection {mem_s2_agent.rdata_fifo_src} {mem_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {mem_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/mem_s2_agent.cp} {qsys_mm.command};add_connection {mem_s1_agent.m0} {mem_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s1_agent.rf_source} {mem_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s1_agent_rsp_fifo.out} {mem_s1_agent.rf_sink} {avalon_streaming};add_connection {mem_s1_agent.rdata_fifo_src} {mem_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {mem_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/mem_s1_agent.cp} {qsys_mm.command};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {jtag_uart_avalon_jtag_slave_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {jtag_uart_avalon_jtag_slave_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {perf_counter_control_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {perf_counter_control_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {sem_ctl_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {sem_ctl_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_005.sink} {qsys_mm.response};add_connection {router_005.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sem_ram_slave_agent.rp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {sem_ram_slave_agent.rp/router_006.sink} {qsys_mm.response};add_connection {router_006.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_007.sink} {qsys_mm.response};add_connection {router_007.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {mem_s2_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {mem_s2_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {mem_s1_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {mem_s1_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux_003.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux_003.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_007.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_003.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_interface {clk_clk} {clock} {slave};set_interface_property {clk_clk} {EXPORT_OF} {clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {jtag_uart_avalon_jtag_slave} {avalon} {master};set_interface_property {jtag_uart_avalon_jtag_slave} {EXPORT_OF} {jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0};add_interface {mem_s1} {avalon} {master};set_interface_property {mem_s1} {EXPORT_OF} {mem_s1_translator.avalon_anti_slave_0};add_interface {mem_s2} {avalon} {master};set_interface_property {mem_s2} {EXPORT_OF} {mem_s2_translator.avalon_anti_slave_0};add_interface {perf_counter_control_slave} {avalon} {master};set_interface_property {perf_counter_control_slave} {EXPORT_OF} {perf_counter_control_slave_translator.avalon_anti_slave_0};add_interface {sem_ctl_slave} {avalon} {master};set_interface_property {sem_ctl_slave} {EXPORT_OF} {sem_ctl_slave_translator.avalon_anti_slave_0};add_interface {sem_ram_slave} {avalon} {master};set_interface_property {sem_ram_slave} {EXPORT_OF} {sem_ram_slave_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {0};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.jtag_uart.avalon_jtag_slave} {1};set_module_assignment {interconnect_id.mem.s1} {2};set_module_assignment {interconnect_id.mem.s2} {3};set_module_assignment {interconnect_id.perf_counter.control_slave} {4};set_module_assignment {interconnect_id.sem.ctl_slave} {5};set_module_assignment {interconnect_id.sem.ram_slave} {6};set_module_assignment {interconnect_id.sys_clk_timer.s1} {7};" /> Transform: CustomInstructionTransform No custom instruction connections, skipping transform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> @@ -1919,7 +2236,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -1944,7 +2261,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -1969,7 +2286,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -1994,7 +2311,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2019,7 +2336,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2044,7 +2361,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2069,7 +2386,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2094,7 +2411,7 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2119,7 +2436,32 @@ Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 54 modules, 178 connections]]> + 60 modules, 199 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 60 modules, 199 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform @@ -2128,61 +2470,69 @@ Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.027s - Timing: COM:3/0.052s/0.076s + Timing: ELA:1/0.000s + Timing: ELA:2/0.008s/0.016s + Timing: ELA:1/0.000s + Timing: COM:3/0.076s/0.101s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.011s - Timing: COM:3/0.021s/0.022s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.018s + Timing: COM:3/0.039s/0.054s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.019s/0.025s + Timing: ELA:1/0.015s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.011s - Timing: COM:3/0.021s/0.024s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.015s + Timing: COM:3/0.028s/0.037s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.024s/0.032s + Timing: ELA:1/0.000s + Timing: ELA:2/0.007s/0.015s + Timing: ELA:1/0.000s + Timing: COM:3/0.026s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.008s - Timing: COM:3/0.019s/0.022s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.020s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.011s - Timing: COM:3/0.022s/0.028s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.020s/0.031s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.000s + Timing: COM:3/0.015s/0.016s 61 modules, 199 connections]]> + culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform">68 modules, 223 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> @@ -2193,6 +2543,7 @@ mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> @@ -2209,26 +2560,31 @@ mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> - mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_005"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> - mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_009"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> - mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_003"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> @@ -2243,45 +2599,46 @@ mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> niosII" instantiated altera_mm_interconnect "mm_interconnect_0"]]> - queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + queue size: 65 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> - queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + queue size: 63 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> - queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + queue size: 55 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> - queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + queue size: 53 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> - queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + queue size: 52 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> - queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" + queue size: 37 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> - queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" + queue size: 36 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> - queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" + queue size: 35 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> - queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" - mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> - queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" - mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> - queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" + queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_005" + mm_interconnect_0" instantiated altera_merlin_router "router_005"]]> + queue size: 28 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_009" + mm_interconnect_0" instantiated altera_merlin_router "router_009"]]> + queue size: 27 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> - queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" + queue size: 26 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> - queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" + queue size: 25 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> - queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" - mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> + queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_003" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_003"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" + queue size: 17 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> - queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" + queue size: 9 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" + queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" + queue size: 7 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" @@ -2325,7 +2682,7 @@ - queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper" + queue size: 68 starting:altera_irq_mapper "submodules/niosII_irq_mapper" niosII" instantiated altera_irq_mapper "irq_mapper"]]> @@ -2358,13 +2715,13 @@ - queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller" + queue size: 67 starting:altera_reset_controller "submodules/altera_reset_controller" niosII" instantiated altera_reset_controller "rst_controller"]]> + value="<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='perf_counter.control_slave' start='0x21000' end='0x21040' type='altera_avalon_performance_counter.control_slave' /><slave name='sem.ram_slave' start='0x21040' end='0x21080' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21080' end='0x210A0' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x210A0' end='0x210A8' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x210A8' end='0x210B0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>" /> @@ -2548,7 +2905,9 @@ - + @@ -2603,21 +2962,21 @@ - queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" + queue size: 66 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.24 01:16:53 (*) Starting Nios II generation - # 2022.12.24 01:16:53 (*) Checking for plaintext license. - # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.24 01:16:54 (*) Plaintext license not found. - # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. - # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings - # 2022.12.24 01:16:54 (*) Creating all objects for CPU - # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects - # 2022.12.24 01:16:55 (*) Creating plain-text RTL - # 2022.12.24 01:16:56 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9350_6910880825044437279.dir/0015_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 22:19:19 (*) Starting Nios II generation + # 2022.12.24 22:19:19 (*) Checking for plaintext license. + # 2022.12.24 22:19:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 22:19:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 22:19:20 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 22:19:20 (*) Plaintext license not found. + # 2022.12.24 22:19:20 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 22:19:20 (*) Elaborating CPU configuration settings + # 2022.12.24 22:19:20 (*) Creating all objects for CPU + # 2022.12.24 22:19:22 (*) Generating RTL from CPU objects + # 2022.12.24 22:19:22 (*) Creating plain-text RTL + # 2022.12.24 22:19:22 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> @@ -2646,7 +3005,7 @@ instantiator="niosII_mm_interconnect_0" as="cpu_data_master_translator,cpu_instruction_master_translator" /> - queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + queue size: 65 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> @@ -2671,9 +3030,9 @@ + as="jtag_uart_avalon_jtag_slave_translator,perf_counter_control_slave_translator,sem_ctl_slave_translator,cpu_debug_mem_slave_translator,sem_ram_slave_translator,sys_clk_timer_s1_translator,mem_s2_translator,mem_s1_translator" /> - queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + queue size: 63 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> @@ -2684,15 +3043,22 @@ <slave id="1" name="jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0" - start="0x0000000000021068" - end="0x00000000000021070" + start="0x00000000000210a8" + end="0x000000000000210b0" responds="1" user_default="0" /> <slave id="4" + name="perf_counter_control_slave_translator.avalon_universal_slave_0" + start="0x0000000000021000" + end="0x00000000000021040" + responds="1" + user_default="0" /> + <slave + id="5" name="sem_ctl_slave_translator.avalon_universal_slave_0" - start="0x0000000000021060" - end="0x00000000000021068" + start="0x00000000000210a0" + end="0x000000000000210a8" responds="1" user_default="0" /> <slave @@ -2703,17 +3069,17 @@ responds="1" user_default="0" /> <slave - id="5" + id="6" name="sem_ram_slave_translator.avalon_universal_slave_0" - start="0x0000000000021000" - end="0x00000000000021040" + start="0x0000000000021040" + end="0x00000000000021080" responds="0" user_default="0" /> <slave - id="6" + id="7" name="sys_clk_timer_s1_translator.avalon_universal_slave_0" - start="0x0000000000021040" - end="0x00000000000021060" + start="0x0000000000021080" + end="0x000000000000210a0" responds="1" user_default="0" /> <slave @@ -2724,7 +3090,7 @@ responds="1" user_default="0" /> </address_map> -,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=7,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=71,PKT_ADDR_SIDEBAND_L=71,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BURST_TYPE_H=70,PKT_BURST_TYPE_L=69,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_CACHE_H=88,PKT_CACHE_L=85,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=72,PKT_DATA_SIDEBAND_L=72,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_QOS_H=74,PKT_QOS_L=74,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_THREAD_ID_H=81,PKT_THREAD_ID_L=81,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_EXCLUSIVE=59,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0" +,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=7,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=71,PKT_ADDR_SIDEBAND_L=71,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BURST_TYPE_H=70,PKT_BURST_TYPE_L=69,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_CACHE_H=88,PKT_CACHE_L=85,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=72,PKT_DATA_SIDEBAND_L=72,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_QOS_H=74,PKT_QOS_L=74,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_THREAD_ID_H=81,PKT_THREAD_ID_L=81,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_EXCLUSIVE=59,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=8,ST_DATA_W=94,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0" instancePathKey="niosII:.:mm_interconnect_0:.:cpu_data_master_agent" kind="altera_merlin_master_agent" version="18.1" @@ -2745,13 +3111,13 @@ instantiator="niosII_mm_interconnect_0" as="cpu_data_master_agent,cpu_instruction_master_agent" /> - queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + queue size: 55 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> + as="jtag_uart_avalon_jtag_slave_agent,perf_counter_control_slave_agent,sem_ctl_slave_agent,cpu_debug_mem_slave_agent,sem_ram_slave_agent,sys_clk_timer_s1_agent,mem_s2_agent,mem_s1_agent" /> - queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + queue size: 53 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> @@ -2805,30 +3171,30 @@ + as="jtag_uart_avalon_jtag_slave_agent_rsp_fifo,perf_counter_control_slave_agent_rsp_fifo,sem_ctl_slave_agent_rsp_fifo,cpu_debug_mem_slave_agent_rsp_fifo,sem_ram_slave_agent_rsp_fifo,sys_clk_timer_s1_agent_rsp_fifo,mem_s2_agent_rsp_fifo,mem_s1_agent_rsp_fifo" /> - queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + queue size: 52 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> - + - + value="0x0,0x20800,0x21000,0x21040,0x21080,0x210a0,0x210a8" /> + + value="3:1000000:0x0:0x20000:both:1:0:0:1,0:0001000:0x20800:0x21000:both:1:0:0:1,4:0000010:0x21000:0x21040:both:1:0:0:1,6:0010000:0x21040:0x21080:write:1:0:0:1,7:0100000:0x21080:0x210a0:both:1:0:0:1,5:0000100:0x210a0:0x210a8:both:1:0:0:1,1:0000001:0x210a8:0x210b0:both:1:0:0:1" /> @@ -2837,22 +3203,26 @@ - - - + + + - + + value="0x20000,0x21000,0x21040,0x21080,0x210a0,0x210a8,0x210b0" /> - - + + - queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" + queue size: 37 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> - + @@ -2923,18 +3293,18 @@ - queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" + queue size: 36 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> - + @@ -2977,20 +3347,20 @@ + as="router_002,router_003,router_004,router_006,router_007,router_008" /> - queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" + queue size: 35 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> - + name="niosII_mm_interconnect_0_router_005"> + @@ -3023,7 +3393,7 @@ @@ -3033,20 +3403,20 @@ path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> - + - queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" - mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> + queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_005" + mm_interconnect_0" instantiated altera_merlin_router "router_005"]]> - + name="niosII_mm_interconnect_0_router_009"> + @@ -3077,7 +3447,7 @@ @@ -3087,15 +3457,15 @@ path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> - + - queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" - mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> + queue size: 28 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_009" + mm_interconnect_0" instantiated altera_merlin_router "router_009"]]> - + - + - queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" + queue size: 27 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> - + @@ -3157,15 +3527,15 @@ + as="cmd_demux_001,rsp_demux_003" /> - queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" + queue size: 26 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> - + @@ -3199,23 +3569,23 @@ + as="cmd_mux,cmd_mux_001,cmd_mux_002,cmd_mux_004,cmd_mux_005,cmd_mux_006,cmd_mux_007" /> - queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" + queue size: 25 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> + name="niosII_mm_interconnect_0_cmd_mux_003"> - + @@ -3225,7 +3595,7 @@ - + - queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" - mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> + queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_003" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_003"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - + @@ -3276,15 +3646,15 @@ + as="rsp_demux,rsp_demux_001,rsp_demux_002,rsp_demux_004,rsp_demux_005,rsp_demux_006,rsp_demux_007" /> - queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" + queue size: 17 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> - - - + + + @@ -3318,14 +3688,14 @@ - queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" + queue size: 9 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> - + @@ -3359,7 +3729,7 @@ - queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" + queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> @@ -3417,9 +3787,9 @@ + as="avalon_st_adapter,avalon_st_adapter_001,avalon_st_adapter_002,avalon_st_adapter_003,avalon_st_adapter_004,avalon_st_adapter_005,avalon_st_adapter_006,avalon_st_adapter_007" /> - queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" + queue size: 7 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" diff --git a/Top/niosII/synthesis/niosII.debuginfo b/Top/niosII/synthesis/niosII.debuginfo index 0b4d440..ca55e08 100644 --- a/Top/niosII/synthesis/niosII.debuginfo +++ b/Top/niosII/synthesis/niosII.debuginfo @@ -1,7 +1,7 @@ - + com.altera.sopcmodel.ensemble.EClockAdapter @@ -53,7 +53,7 @@ int - 1671833790 + 1671909530 false true true @@ -400,6 +400,12 @@ parameters are a RESULT of the module parameters. --> clk sys_clk_timer.clk + + false + perf_counter + clk + perf_counter.clk + false mem @@ -499,6 +505,128 @@ parameters are a RESULT of the module parameters. --> + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.custominstruction.CustomInstruction$ClockCycleType + COMBINATORIAL + true + true + true + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + false + + din + Input + 32 + dataa + + + ones + Output + 32 + result + + + @@ -2110,7 +2238,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -2249,7 +2377,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -3649,7 +3777,7 @@ parameters are a RESULT of the module parameters. --> boolean - false + true false true false @@ -3674,11 +3802,103 @@ parameters are a RESULT of the module parameters. --> nios_custom_instruction true - dummy_ci_port + E_ci_result + Input + 32 + result + + + D_ci_a + Output + 5 + a + + + D_ci_b + Output + 5 + b + + + D_ci_c + Output + 5 + c + + + D_ci_n + Output + 8 + n + + + D_ci_readra Output 1 readra + + D_ci_readrb + Output + 1 + readrb + + + D_ci_writerc + Output + 1 + writerc + + + E_ci_dataa + Output + 32 + dataa + + + E_ci_datab + Output + 32 + datab + + + E_ci_multi_clock + Output + 1 + clk + + + E_ci_multi_reset + Output + 1 + reset + + + E_ci_multi_reset_req + Output + 1 + reset_req + + + W_ci_estatus + Output + 1 + estatus + + + W_ci_ipending + Output + 32 + ipending + + + false + cpu_custom_instruction_master_translator + ci_slave + cpu_custom_instruction_master_translator.ci_slave + 0 + + + + + + embeddedsw.CMacro.HOW_MANY_SECTIONS + 3 + + + int + 3 + false + true + true + true + + + int + 4 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + false + true + + + int + 8 + false + true + false + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 4 + address + + + begintransfer + Input + 1 + begintransfer + + + readdata + Output + 32 + readdata + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + @@ -7354,6 +8073,1274 @@ parameters are a RESULT of the module parameters. --> + + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.custominstruction.CustomInstruction$ClockCycleType + COMBINATORIAL + true + true + true + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + false + + ci_slave_dataa + Input + 32 + dataa + + + ci_slave_datab + Input + 32 + datab + + + ci_slave_result + Output + 32 + result + + + ci_slave_n + Input + 8 + n + + + ci_slave_readra + Input + 1 + readra + + + ci_slave_readrb + Input + 1 + readrb + + + ci_slave_writerc + Input + 1 + writerc + + + ci_slave_a + Input + 5 + a + + + ci_slave_b + Input + 5 + b + + + ci_slave_c + Input + 5 + c + + + ci_slave_ipending + Input + 32 + ipending + + + ci_slave_estatus + Input + 1 + estatus + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + comb_ci_master_dataa + Output + 32 + dataa + + + comb_ci_master_datab + Output + 32 + datab + + + comb_ci_master_result + Input + 32 + result + + + comb_ci_master_n + Output + 8 + n + + + comb_ci_master_readra + Output + 1 + readra + + + comb_ci_master_readrb + Output + 1 + readrb + + + comb_ci_master_writerc + Output + 1 + writerc + + + comb_ci_master_a + Output + 5 + a + + + comb_ci_master_b + Output + 5 + b + + + comb_ci_master_c + Output + 5 + c + + + comb_ci_master_ipending + Output + 32 + ipending + + + comb_ci_master_estatus + Output + 1 + estatus + + + false + cpu_custom_instruction_master_comb_xconnect + ci_slave + cpu_custom_instruction_master_comb_xconnect.ci_slave + 0 + + + + + + + + [Ljava.lang.Integer; + 0 + false + true + true + true + + + [Ljava.lang.Integer; + 0 + false + true + true + true + + + [Ljava.lang.Integer; + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.custominstruction.CustomInstruction$ClockCycleType + COMBINATORIAL + true + true + true + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + false + + ci_slave_dataa + Input + 32 + dataa + + + ci_slave_datab + Input + 32 + datab + + + ci_slave_result + Output + 32 + result + + + ci_slave_n + Input + 8 + n + + + ci_slave_readra + Input + 1 + readra + + + ci_slave_readrb + Input + 1 + readrb + + + ci_slave_writerc + Input + 1 + writerc + + + ci_slave_a + Input + 5 + a + + + ci_slave_b + Input + 5 + b + + + ci_slave_c + Input + 5 + c + + + ci_slave_ipending + Input + 32 + ipending + + + ci_slave_estatus + Input + 1 + estatus + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + ci_master0_dataa + Output + 32 + dataa + + + ci_master0_datab + Output + 32 + datab + + + ci_master0_result + Input + 32 + result + + + ci_master0_n + Output + 8 + n + + + ci_master0_readra + Output + 1 + readra + + + ci_master0_readrb + Output + 1 + readrb + + + ci_master0_writerc + Output + 1 + writerc + + + ci_master0_a + Output + 5 + a + + + ci_master0_b + Output + 5 + b + + + ci_master0_c + Output + 5 + c + + + ci_master0_ipending + Output + 32 + ipending + + + ci_master0_estatus + Output + 1 + estatus + + + false + cpu_custom_instruction_master_comb_slave_translator0 + ci_slave + cpu_custom_instruction_master_comb_slave_translator0.ci_slave + 0 + + + + + + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.custominstruction.CustomInstruction$ClockCycleType + COMBINATORIAL + true + true + true + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + false + + ci_slave_dataa + Input + 32 + dataa + + + ci_slave_datab + Input + 32 + datab + + + ci_slave_result + Output + 32 + result + + + ci_slave_n + Input + 8 + n + + + ci_slave_readra + Input + 1 + readra + + + ci_slave_readrb + Input + 1 + readrb + + + ci_slave_writerc + Input + 1 + writerc + + + ci_slave_a + Input + 5 + a + + + ci_slave_b + Input + 5 + b + + + ci_slave_c + Input + 5 + c + + + ci_slave_ipending + Input + 32 + ipending + + + ci_slave_estatus + Input + 1 + estatus + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + ci_master_dataa + Output + 32 + dataa + + + ci_master_result + Input + 32 + result + + + false + countones + nios_custom_instruction_slave + countones.nios_custom_instruction_slave + 0 + + + + 3 - interconnect_id.sem.ctl_slave + interconnect_id.perf_counter.control_slave 4 - interconnect_id.sem.ram_slave + interconnect_id.sem.ctl_slave 5 - interconnect_id.sys_clk_timer.s1 + interconnect_id.sem.ram_slave 6 + + interconnect_id.sys_clk_timer.s1 + 7 + java.lang.String - + + responds="1" user_default="0" /> responds="1" user_default="0" /> -};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {7};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {85};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {59};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} { +};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {7};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {85};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {59};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} { responds="1" user_default="0" /> -};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ID} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ECC_ENABLE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ctl_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {sem_ctl_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ctl_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ctl_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ctl_slave_agent} {ID} {4};set_instance_parameter_value {sem_ctl_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ctl_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ram_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {sem_ram_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ram_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ram_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ram_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ram_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ram_slave_agent} {ID} {5};set_instance_parameter_value {sem_ram_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ram_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {6};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s2_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {mem_s2_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s2_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s2_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s2_agent} {ID} {3};set_instance_parameter_value {mem_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {ECC_ENABLE} {0};add_instance {mem_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {mem_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s1_agent} {ID} {2};set_instance_parameter_value {mem_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {ECC_ENABLE} {0};add_instance {mem_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 0 5 6 4 1 };set_instance_parameter_value {router} {CHANNEL_ID} {100000 000100 001000 010000 000010 000001 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both write both both both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x20800 0x21000 0x21040 0x21060 0x21068 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 0x21000 0x21040 0x21060 0x21068 0x21070 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {53};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router} {PKT_TRANS_READ} {57};set_instance_parameter_value {router} {ST_DATA_W} {94};set_instance_parameter_value {router} {ST_CHANNEL_W} {7};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {5};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {2 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {10 01 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x20800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 0x21000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {53};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_001} {ST_DATA_W} {94};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {2};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {53};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_002} {ST_DATA_W} {94};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {53};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_004} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {53};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_004} {ST_DATA_W} {94};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {0 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {53};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_005} {ST_DATA_W} {94};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_005} {DECODER_TYPE} {1};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {0 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {53};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_006} {ST_DATA_W} {94};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_006} {DECODER_TYPE} {1};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {0 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {53};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_007} {ST_DATA_W} {94};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_007} {DECODER_TYPE} {1};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {1 };set_instance_parameter_value {router_008} {CHANNEL_ID} {1 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {53};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_008} {ST_DATA_W} {94};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {7};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {6};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {7};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {6};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {7};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {jtag_uart_avalon_jtag_slave_agent.m0} {jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.rf_source} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.out} {jtag_uart_avalon_jtag_slave_agent.rf_sink} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_src} {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {jtag_uart_avalon_jtag_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/jtag_uart_avalon_jtag_slave_agent.cp} {qsys_mm.command};add_connection {sem_ctl_slave_agent.m0} {sem_ctl_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ctl_slave_agent.rf_source} {sem_ctl_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ctl_slave_agent_rsp_fifo.out} {sem_ctl_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ctl_slave_agent.rdata_fifo_src} {sem_ctl_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {sem_ctl_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/sem_ctl_slave_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_002.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {sem_ram_slave_agent.m0} {sem_ram_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ram_slave_agent.rf_source} {sem_ram_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ram_slave_agent_rsp_fifo.out} {sem_ram_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ram_slave_agent.rdata_fifo_src} {sem_ram_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {sem_ram_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/sem_ram_slave_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {mem_s2_agent.m0} {mem_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s2_agent.rf_source} {mem_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s2_agent_rsp_fifo.out} {mem_s2_agent.rf_sink} {avalon_streaming};add_connection {mem_s2_agent.rdata_fifo_src} {mem_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {mem_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/mem_s2_agent.cp} {qsys_mm.command};add_connection {mem_s1_agent.m0} {mem_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s1_agent.rf_source} {mem_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s1_agent_rsp_fifo.out} {mem_s1_agent.rf_sink} {avalon_streaming};add_connection {mem_s1_agent.rdata_fifo_src} {mem_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {mem_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/mem_s1_agent.cp} {qsys_mm.command};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {jtag_uart_avalon_jtag_slave_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {jtag_uart_avalon_jtag_slave_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {sem_ctl_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {sem_ctl_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {sem_ram_slave_agent.rp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {sem_ram_slave_agent.rp/router_005.sink} {qsys_mm.response};add_connection {router_005.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_006.sink} {qsys_mm.response};add_connection {router_006.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {mem_s2_agent.rp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {mem_s2_agent.rp/router_007.sink} {qsys_mm.response};add_connection {router_007.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {mem_s1_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {mem_s1_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_006.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_interface {clk_clk} {clock} {slave};set_interface_property {clk_clk} {EXPORT_OF} {clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {jtag_uart_avalon_jtag_slave} {avalon} {master};set_interface_property {jtag_uart_avalon_jtag_slave} {EXPORT_OF} {jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0};add_interface {mem_s1} {avalon} {master};set_interface_property {mem_s1} {EXPORT_OF} {mem_s1_translator.avalon_anti_slave_0};add_interface {mem_s2} {avalon} {master};set_interface_property {mem_s2} {EXPORT_OF} {mem_s2_translator.avalon_anti_slave_0};add_interface {sem_ctl_slave} {avalon} {master};set_interface_property {sem_ctl_slave} {EXPORT_OF} {sem_ctl_slave_translator.avalon_anti_slave_0};add_interface {sem_ram_slave} {avalon} {master};set_interface_property {sem_ram_slave} {EXPORT_OF} {sem_ram_slave_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {0};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.jtag_uart.avalon_jtag_slave} {1};set_module_assignment {interconnect_id.mem.s1} {2};set_module_assignment {interconnect_id.mem.s2} {3};set_module_assignment {interconnect_id.sem.ctl_slave} {4};set_module_assignment {interconnect_id.sem.ram_slave} {5};set_module_assignment {interconnect_id.sys_clk_timer.s1} {6};]]> +};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ID} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ECC_ENABLE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {perf_counter_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {perf_counter_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {perf_counter_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {perf_counter_control_slave_agent} {ID} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {ECC_ENABLE} {0};add_instance {perf_counter_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ctl_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ctl_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ctl_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ctl_slave_agent} {ID} {5};set_instance_parameter_value {sem_ctl_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ctl_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ram_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ram_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ram_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ram_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ram_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ram_slave_agent} {ID} {6};set_instance_parameter_value {sem_ram_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ram_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s2_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s2_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s2_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s2_agent} {ID} {3};set_instance_parameter_value {mem_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {ECC_ENABLE} {0};add_instance {mem_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s1_agent} {ID} {2};set_instance_parameter_value {mem_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {ECC_ENABLE} {0};add_instance {mem_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 0 4 6 7 5 1 };set_instance_parameter_value {router} {CHANNEL_ID} {1000000 0001000 0000010 0010000 0100000 0000100 0000001 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both write both both both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x20800 0x21000 0x21040 0x21080 0x210a0 0x210a8 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 0x21000 0x21040 0x21080 0x210a0 0x210a8 0x210b0 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {53};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router} {PKT_TRANS_READ} {57};set_instance_parameter_value {router} {ST_DATA_W} {94};set_instance_parameter_value {router} {ST_CHANNEL_W} {8};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {6};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {2 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {10 01 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x20800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 0x21000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {53};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_001} {ST_DATA_W} {94};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {2};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {53};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_002} {ST_DATA_W} {94};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {53};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {0 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {53};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_004} {ST_DATA_W} {94};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_005} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_005} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {53};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_005} {ST_DATA_W} {94};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_005} {DECODER_TYPE} {1};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {0 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {53};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_006} {ST_DATA_W} {94};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_006} {DECODER_TYPE} {1};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {0 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {53};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_007} {ST_DATA_W} {94};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_007} {DECODER_TYPE} {1};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 };set_instance_parameter_value {router_008} {CHANNEL_ID} {1 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {53};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_008} {ST_DATA_W} {94};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {1 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {53};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_009} {ST_DATA_W} {94};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {7};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {7};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {jtag_uart_avalon_jtag_slave_agent.m0} {jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.rf_source} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.out} {jtag_uart_avalon_jtag_slave_agent.rf_sink} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_src} {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {jtag_uart_avalon_jtag_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/jtag_uart_avalon_jtag_slave_agent.cp} {qsys_mm.command};add_connection {perf_counter_control_slave_agent.m0} {perf_counter_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {perf_counter_control_slave_agent.rf_source} {perf_counter_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {perf_counter_control_slave_agent_rsp_fifo.out} {perf_counter_control_slave_agent.rf_sink} {avalon_streaming};add_connection {perf_counter_control_slave_agent.rdata_fifo_src} {perf_counter_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {perf_counter_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/perf_counter_control_slave_agent.cp} {qsys_mm.command};add_connection {sem_ctl_slave_agent.m0} {sem_ctl_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ctl_slave_agent.rf_source} {sem_ctl_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ctl_slave_agent_rsp_fifo.out} {sem_ctl_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ctl_slave_agent.rdata_fifo_src} {sem_ctl_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_002.src} {sem_ctl_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/sem_ctl_slave_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {sem_ram_slave_agent.m0} {sem_ram_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ram_slave_agent.rf_source} {sem_ram_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ram_slave_agent_rsp_fifo.out} {sem_ram_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ram_slave_agent.rdata_fifo_src} {sem_ram_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sem_ram_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sem_ram_slave_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {mem_s2_agent.m0} {mem_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s2_agent.rf_source} {mem_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s2_agent_rsp_fifo.out} {mem_s2_agent.rf_sink} {avalon_streaming};add_connection {mem_s2_agent.rdata_fifo_src} {mem_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {mem_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/mem_s2_agent.cp} {qsys_mm.command};add_connection {mem_s1_agent.m0} {mem_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s1_agent.rf_source} {mem_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s1_agent_rsp_fifo.out} {mem_s1_agent.rf_sink} {avalon_streaming};add_connection {mem_s1_agent.rdata_fifo_src} {mem_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {mem_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/mem_s1_agent.cp} {qsys_mm.command};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {jtag_uart_avalon_jtag_slave_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {jtag_uart_avalon_jtag_slave_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {perf_counter_control_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {perf_counter_control_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {sem_ctl_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {sem_ctl_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_005.sink} {qsys_mm.response};add_connection {router_005.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sem_ram_slave_agent.rp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {sem_ram_slave_agent.rp/router_006.sink} {qsys_mm.response};add_connection {router_006.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_007.sink} {qsys_mm.response};add_connection {router_007.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {mem_s2_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {mem_s2_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {mem_s1_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {mem_s1_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux_003.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux_003.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_007.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_003.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_interface {clk_clk} {clock} {slave};set_interface_property {clk_clk} {EXPORT_OF} {clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {jtag_uart_avalon_jtag_slave} {avalon} {master};set_interface_property {jtag_uart_avalon_jtag_slave} {EXPORT_OF} {jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0};add_interface {mem_s1} {avalon} {master};set_interface_property {mem_s1} {EXPORT_OF} {mem_s1_translator.avalon_anti_slave_0};add_interface {mem_s2} {avalon} {master};set_interface_property {mem_s2} {EXPORT_OF} {mem_s2_translator.avalon_anti_slave_0};add_interface {perf_counter_control_slave} {avalon} {master};set_interface_property {perf_counter_control_slave} {EXPORT_OF} {perf_counter_control_slave_translator.avalon_anti_slave_0};add_interface {sem_ctl_slave} {avalon} {master};set_interface_property {sem_ctl_slave} {EXPORT_OF} {sem_ctl_slave_translator.avalon_anti_slave_0};add_interface {sem_ram_slave} {avalon} {master};set_interface_property {sem_ram_slave} {EXPORT_OF} {sem_ram_slave_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {0};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.jtag_uart.avalon_jtag_slave} {1};set_module_assignment {interconnect_id.mem.s1} {2};set_module_assignment {interconnect_id.mem.s2} {3};set_module_assignment {interconnect_id.perf_counter.control_slave} {4};set_module_assignment {interconnect_id.sem.ctl_slave} {5};set_module_assignment {interconnect_id.sem.ram_slave} {6};set_module_assignment {interconnect_id.sys_clk_timer.s1} {7};]]> false true true @@ -9615,6 +11613,307 @@ parameters are a RESULT of the module parameters. --> 131072 + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_clk + false + true + true + true + + + java.lang.String + cpu_reset_reset_bridge_in_reset + false + true + true + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + perf_counter_control_slave_address + Output + 4 + address + + + perf_counter_control_slave_write + Output + 1 + write + + + perf_counter_control_slave_readdata + Input + 32 + readdata + + + perf_counter_control_slave_writedata + Output + 32 + writedata + + + perf_counter_control_slave_begintransfer + Output + 1 + begintransfer + + + false + perf_counter + control_slave + perf_counter.control_slave + 0 + 64 + + sys_clk_timer clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + perf_counter + clk + sem clock + + + java.lang.String + + false + true + true + true + + + java.lang.String + + true + true + true + true + + + int + 1 + false + true + false + true + + + long + 0 + false + true + true + true + + + int + -1 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + custom_instruction_master + cpu_custom_instruction_master_translator + ci_slave + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + true + true + true + true + + + int + 1 + false + true + false + true + + + long + 0 + false + true + true + true + + + int + -1 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_custom_instruction_master_translator + comb_ci_master + cpu_custom_instruction_master_comb_xconnect + ci_slave + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + true + true + true + true + + + int + 1 + false + true + false + true + + + long + 0 + false + true + true + true + + + int + -1 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_custom_instruction_master_comb_xconnect + ci_master0 + cpu_custom_instruction_master_comb_slave_translator0 + ci_slave + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + true + true + true + true + + + int + 1 + false + true + false + true + + + long + 0 + false + true + true + true + + + int + -1 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_custom_instruction_master_comb_slave_translator0 + ci_master + countones + nios_custom_instruction_slave + jtag_uart avalon_jtag_slave + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + mm_interconnect_0 + perf_counter_control_slave + perf_counter + control_slave + rst_translator in_reset + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + rst_translator + out_reset + perf_counter + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + rst_controller + reset_out + rst_translator + in_reset + Reset Output 18.1 + + 1 + countones_ci + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + countones_ci + 1.0 + + + 4 + nios_custom_instruction_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Slave + 18.1 + 1 altera_nios2_gen2 @@ -12749,7 +15464,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 9 + 10 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -12757,7 +15472,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 10 + 11 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -12765,7 +15480,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 9 + 10 avalon_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -12789,7 +15504,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 9 + 10 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -12797,7 +15512,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 1 + 4 nios_custom_instruction_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -12828,6 +15543,14 @@ parameters are a RESULT of the module parameters. --> On-Chip Memory (RAM or ROM) Intel FPGA IP 18.1 + + 1 + altera_avalon_performance_counter + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Performance Counter Unit Intel FPGA IP + 18.1 + 1 sem @@ -12852,6 +15575,30 @@ parameters are a RESULT of the module parameters. --> Interval Timer Intel FPGA IP 18.1 + + 1 + altera_customins_master_translator + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Custom Instruction Master Translator + 18.1 + + + 1 + altera_customins_xconnect + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Custom Instruction Interconnect + 18.1 + + + 1 + altera_customins_slave_translator + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Custom Instruction Slave Translator + 18.1 + 1 altera_mm_interconnect @@ -12885,7 +15632,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 5 + 6 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -12893,7 +15640,15 @@ parameters are a RESULT of the module parameters. --> 18.1 - 9 + 4 + nios_custom_instruction + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Nios II Custom Instruction Connection + 18.1 + + + 10 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -12917,7 +15672,7 @@ parameters are a RESULT of the module parameters. --> 18.1 - 14 + 16 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -12925,5 +15680,5 @@ parameters are a RESULT of the module parameters. --> 18.1 18.1 625 - 7A31C1D0889000000185410F37E7 + 7A31C1D08890000001854592F535 diff --git a/Top/niosII/synthesis/niosII.qip b/Top/niosII/synthesis/niosII.qip index 08a5253..16e7448 100644 --- a/Top/niosII/synthesis/niosII.qip +++ b/Top/niosII/synthesis/niosII.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] -set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790" +set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671909530" set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] @@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTkwOTUzMA==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" @@ -128,7 +128,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "n set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" @@ -144,13 +144,13 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosI set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Ng==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" +set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Nw==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NTg=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l" -set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwxLDE=::QXJiaXRyYXRpb24gc2hhcmVz" +set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwxLDEsMQ==::QXJiaXRyYXRpb24gc2hhcmVz" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JzcF9kZW11eA==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy" @@ -160,28 +160,28 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "nio set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX2NtZF9tdXhfMDAy" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg==" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NTg=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwx::QXJiaXRyYXRpb24gc2hhcmVz" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX2NtZF9tdXhfMDAz" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg==" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NTg=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwx::QXJiaXRyYXRpb24gc2hhcmVz" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX2NtZF9tdXg=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" @@ -190,7 +190,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosI set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u" @@ -206,7 +206,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Mg==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" @@ -220,78 +220,78 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "nio set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Ng==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Nw==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MQ==::RGVzdGluYXRpb24gSUQ=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::cmVhZA==::VHlwZSBvZiBUcmFuc2FjdGlvbg==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MToxOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDQ=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MCwx::RGVzdGluYXRpb24gSUQ=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDEsMTA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxyZWFk::VHlwZSBvZiBUcmFuc2FjdGlvbg==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgwLDB4MA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwx::Tm9uLXNlY3VyZWQgdGFncw==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCww::U2VjdXJlZCByYW5nZSBwYWlycw==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMToweDA6MHgwOmJvdGg6MTowOjA6MSwxOjEwOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDk=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MQ==::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::cmVhZA==::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MToxOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDU=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MCwx::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDEsMTA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxyZWFk::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgwLDB4MA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwx::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCww::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMToweDA6MHgwOmJvdGg6MTowOjA6MSwxOjEwOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg==" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ==" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDI=" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI=" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" @@ -316,7 +316,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "ni set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8=" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs" @@ -349,7 +349,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "ni set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MjoxMDoweDA6MHgyMDAwMDpib3RoOjE6MDowOjEsMDowMToweDIwODAwOjB4MjEwMDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8=" set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl" set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MQ==::RGVmYXVsdCBjaGFubmVs" @@ -365,14 +365,14 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDUsNiw0LDE=::RGVzdGluYXRpb24gSUQ=" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMDEwMDAsMDEwMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLHdyaXRlLGJvdGgsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg==" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDQwLDB4MjEwNjAsMHgyMTA2OA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwNDAsMHgyMTA2MCwweDIxMDY4LDB4MjEwNzA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw==" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDQsNiw3LDUsMQ==::RGVzdGluYXRpb24gSUQ=" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwMCwwMDAxMDAwLDAwMDAwMTAsMDAxMDAwMCwwMTAwMDAwLDAwMDAxMDAsMDAwMDAwMQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsd3JpdGUsYm90aCxib3RoLGJvdGg=::VHlwZSBvZiBUcmFuc2FjdGlvbg==" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDQwLDB4MjEwODAsMHgyMTBhMCwweDIxMGE4::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwNDAsMHgyMTA4MCwweDIxMGEwLDB4MjEwYTgsMHgyMTBiMA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDEsMQ==::Tm9uLXNlY3VyZWQgdGFncw==" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDAsMA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDAsMA==::U2VjdXJlZCByYW5nZSBwYWlycw==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA==" @@ -382,10 +382,10 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNTowMDEwMDA6MHgyMTAwMDoweDIxMDQwOndyaXRlOjE6MDowOjEsNjowMTAwMDA6MHgyMTA0MDoweDIxMDYwOmJvdGg6MTowOjA6MSw0OjAwMDAxMDoweDIxMDYwOjB4MjEwNjg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwNjg6MHgyMTA3MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8=" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDAwOjB4MDoweDIwMDAwOmJvdGg6MTowOjA6MSwwOjAwMDEwMDA6MHgyMDgwMDoweDIxMDAwOmJvdGg6MTowOjA6MSw0OjAwMDAwMTA6MHgyMTAwMDoweDIxMDQwOmJvdGg6MTowOjA6MSw2OjAwMTAwMDA6MHgyMTA0MDoweDIxMDgwOndyaXRlOjE6MDowOjEsNzowMTAwMDAwOjB4MjEwODA6MHgyMTBhMDpib3RoOjE6MDowOjEsNTowMDAwMTAwOjB4MjEwYTA6MHgyMTBhODpib3RoOjE6MDowOjEsMTowMDAwMDAxOjB4MjEwYTg6MHgyMTBiMDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl" -set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs" +set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::Ng==::RGVmYXVsdCBjaGFubmVs" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mw==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA==" @@ -447,7 +447,7 @@ set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -nam set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1NZTUJPTF9X::OA==::UGFja2V0IHN5bWJvbCB3aWR0aA==" -set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfU1lNQk9MUw==::MA==::YnVyc3Rjb3VudFN5bWJvbHM=" set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfVw==::Mw==::YnVyc3Rjb3VudCB3aWR0aA==" @@ -510,7 +510,7 @@ set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -na set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA==" set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93" set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" -set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" +set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::OA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::Mw==::QXZhbG9uLU1NIGJ1cnN0Y291bnQgd2lkdGg=" set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM=" set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MQ==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk=" @@ -639,6 +639,61 @@ set_global_assignment -entity "altera_merlin_master_translator" -library "niosII set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MQ==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM=" set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA==" set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "U1lOQ19SRVNFVA==::MA==::VXNlIHN5bmNocm9ub3VzIHJlc2V0cw==" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_NAME "YWx0ZXJhX2N1c3RvbWluc19zbGF2ZV90cmFuc2xhdG9y" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "Q3VzdG9tIEluc3RydWN0aW9uIFNsYXZlIFRyYW5zbGF0b3I=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEFB::MQ==::VVNFX0RBVEFB" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEFC::MA==::VVNFX0RBVEFC" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX04=::MA==::VVNFX04=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "Tl9XSURUSA==::OA==::Tl9XSURUSA==" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSQQ==::MA==::VVNFX1JFQURSQQ==" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSQg==::MA==::VVNFX1JFQURSQg==" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkM=::MA==::VVNFX1dSSVRFUkM=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0lQRU5ESU5H::MA==::VVNFX0lQRU5ESU5H" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VTVEFUVVM=::MA==::VVNFX0VTVEFUVVM=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1Q=::MA==::VVNFX1JFU0VUX1JFUVVFU1Q=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01VTFRJQ1lDTEU=::MA==::RU5BQkxFX01VTFRJQ1lDTEU=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1NUQVJU::MA==::VVNFX1NUQVJU" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RPTkU=::MA==::VVNFX0RPTkU=" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0ZJWEVEX0NZQ0xFUw==::MA==::TlVNX0ZJWEVEX0NZQ0xFUw==" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX2NwdV9jdXN0b21faW5zdHJ1Y3Rpb25fbWFzdGVyX2NvbWJfeGNvbm5lY3Q=" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "Q3VzdG9tIEluc3RydWN0aW9uIEludGVyY29ubmVjdA==" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_PARAMETER "TUFTVEVSX0lOREVY::MA==::TWFzdGVy" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_PARAMETER "T1BDT0RFX0w=::MA==::T3Bjb2RlIChsb3cp" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_PARAMETER "T1BDT0RFX0g=::MQ==::T3Bjb2RlIChoaWdoKQ==" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01VTFRJQ1lDTEU=::MA==::RW5hYmxlIG11bHRpY3ljbGUgbG9naWM=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_NAME "YWx0ZXJhX2N1c3RvbWluc19tYXN0ZXJfdHJhbnNsYXRvcg==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "Q3VzdG9tIEluc3RydWN0aW9uIE1hc3RlciBUcmFuc2xhdG9y" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEFB::MQ==::VVNFX0RBVEFB" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEFC::MQ==::VVNFX0RBVEFC" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX04=::MQ==::VVNFX04=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSQQ==::MQ==::VVNFX1JFQURSQQ==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSQg==::MQ==::VVNFX1JFQURSQg==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkM=::MQ==::VVNFX1dSSVRFUkM=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0lQRU5ESU5H::MQ==::VVNFX0lQRU5ESU5H" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VTVEFUVVM=::MQ==::VVNFX0VTVEFUVVM=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01VTFRJQ1lDTEU=::MA==::RU5BQkxFX01VTFRJQ1lDTEU=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX1NUQVJU::MA==::VVNFX1NUQVJU" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0RPTkU=::MA==::VVNFX0RPTkU=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX0RBVEFB::MA==::VVNFX01VTFRJX0RBVEFB" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX0RBVEFC::MA==::VVNFX01VTFRJX0RBVEFC" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX1JFU1VMVA==::MA==::VVNFX01VTFRJX1JFU1VMVA==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX04=::MA==::VVNFX01VTFRJX04=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX1JFQURSQQ==::MA==::VVNFX01VTFRJX1JFQURSQQ==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX1JFQURSQg==::MA==::VVNFX01VTFRJX1JFQURSQg==" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX01VTFRJX1dSSVRFUkM=::MA==::VVNFX01VTFRJX1dSSVRFUkM=" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_COMPONENT_PARAMETER "U0hBUkVEX0NPTUJfQU5EX01VTFRJ::MQ==::U0hBUkVEX0NPTUJfQU5EX01VTFRJ" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX3N5c19jbGtfdGltZXI=" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "SW50ZXJ2YWwgVGltZXIgSW50ZWwgRlBHQSBJUA==" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" @@ -668,6 +723,14 @@ set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_REPORT_ set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_VERSION "MS4x" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_PARAMETER "bQ==::MzI=::bQ==" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX3BlcmZfY291bnRlcg==" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "UGVyZm9ybWFuY2UgQ291bnRlciBVbml0IEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_PARAMETER "bnVtYmVyT2ZTZWN0aW9ucw==::Mw==::TnVtYmVyIG9mIHNpbXVsdGFuZW91c2x5LW1lYXN1cmVkIHNlY3Rpb25z" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_COMPONENT_PARAMETER "Y29udHJvbF9zbGF2ZV9hZGRyZXNzX3dpZHRo::NA==::Y29udHJvbCBzbGF2ZSBhZGRyZXNzIHdpZHRo" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ==" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" @@ -859,11 +922,11 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" -set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" +set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdwZXJmX2NvdW50ZXIuY29udHJvbF9zbGF2ZScgc3RhcnQ9JzB4MjEwMDAnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9wZXJmb3JtYW5jZV9jb3VudGVyLmNvbnRyb2xfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J3NlbS5yYW1fc2xhdmUnIHN0YXJ0PScweDIxMDQwJyBlbmQ9JzB4MjEwODAnIHR5cGU9J3NlbS5yYW1fc2xhdmUnIC8+PHNsYXZlIG5hbWU9J3N5c19jbGtfdGltZXIuczEnIHN0YXJ0PScweDIxMDgwJyBlbmQ9JzB4MjEwQTAnIHR5cGU9J2FsdGVyYV9hdmFsb25fdGltZXIuczEnIC8+PHNsYXZlIG5hbWU9J3NlbS5jdGxfc2xhdmUnIHN0YXJ0PScweDIxMEEwJyBlbmQ9JzB4MjEwQTgnIHR5cGU9J3NlbS5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwQTgnIGVuZD0nMHgyMTBCMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" -set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=" +set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8+PHNsYXZlIG5hbWU9ImNvdW50b25lcyIgYmFzZUFkZHJlc3M9IjAiIGFkZHJlc3NTcGFuPSIxIiBjbG9ja0N5Y2xlVHlwZT0iQ09NQklOQVRPUklBTCIgLz48L2luZm8+::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j" @@ -1042,12 +1105,17 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" -set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" +set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdwZXJmX2NvdW50ZXIuY29udHJvbF9zbGF2ZScgc3RhcnQ9JzB4MjEwMDAnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9wZXJmb3JtYW5jZV9jb3VudGVyLmNvbnRyb2xfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J3NlbS5yYW1fc2xhdmUnIHN0YXJ0PScweDIxMDQwJyBlbmQ9JzB4MjEwODAnIHR5cGU9J3NlbS5yYW1fc2xhdmUnIC8+PHNsYXZlIG5hbWU9J3N5c19jbGtfdGltZXIuczEnIHN0YXJ0PScweDIxMDgwJyBlbmQ9JzB4MjEwQTAnIHR5cGU9J2FsdGVyYV9hdmFsb25fdGltZXIuczEnIC8+PHNsYXZlIG5hbWU9J3NlbS5jdGxfc2xhdmUnIHN0YXJ0PScweDIxMEEwJyBlbmQ9JzB4MjEwQTgnIHR5cGU9J3NlbS5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwQTgnIGVuZD0nMHgyMTBCMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" -set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=" +set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8+PHNsYXZlIG5hbWU9ImNvdW50b25lcyIgYmFzZUFkZHJlc3M9IjAiIGFkZHJlc3NTcGFuPSIxIiBjbG9ja0N5Y2xlVHlwZT0iQ09NQklOQVRPUklBTCIgLz48L2luZm8+::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv" +set_global_assignment -entity "countones" -library "niosII" -name IP_COMPONENT_NAME "Y291bnRvbmVz" +set_global_assignment -entity "countones" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "Y291bnRvbmVzX2Np" +set_global_assignment -entity "countones" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "countones" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "countones" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "niosII.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] @@ -1061,12 +1129,12 @@ set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::q set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_rsp_mux.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_rsp_demux.sv"] -set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"] +set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_mux_003.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_mux.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_demux.sv"] -set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_008.sv"] -set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_004.sv"] +set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_009.sv"] +set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_005.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_002.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_001.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router.sv"] @@ -1076,9 +1144,13 @@ set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::q set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"] +set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_customins_slave_translator.sv"] +set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_custom_instruction_master_comb_xconnect.sv"] +set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_customins_master_translator.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_sys_clk_timer.v"] set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/dec.sv"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/periodram.v"] +set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_perf_counter.v"] set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.hex"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"] @@ -1092,6 +1164,7 @@ set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus( set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_a.mif"] set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"] +set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/countones.v"] set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_NAME "altera_reset_controller" set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_VERSION "18.1" @@ -1117,9 +1190,9 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosI set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_TOOL_NAME "altera_merlin_demultiplexer" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_TOOL_NAME "altera_merlin_multiplexer" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_003" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_TOOL_NAME "altera_merlin_multiplexer" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_TOOL_ENV "Qsys" @@ -1129,12 +1202,12 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_NAME "altera_merlin_demultiplexer" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "niosII_mm_interconnect_0_router_009" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "niosII_mm_interconnect_0_router_005" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_TOOL_ENV "Qsys" @@ -1159,9 +1232,21 @@ set_global_assignment -entity "altera_merlin_slave_translator" -library "niosII" set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_TOOL_NAME "altera_merlin_master_translator" set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "altera_merlin_master_translator" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_TOOL_NAME "altera_customins_slave_translator" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "altera_customins_slave_translator" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_TOOL_NAME "altera_customins_xconnect" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "niosII_cpu_custom_instruction_master_comb_xconnect" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_TOOL_NAME "altera_customins_master_translator" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "altera_customins_master_translator" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_TOOL_NAME "altera_avalon_timer" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_TOOL_NAME "altera_avalon_performance_counter" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "niosII_perf_counter" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_TOOL_NAME "altera_avalon_onchip_memory2" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_TOOL_ENV "Qsys" diff --git a/Top/niosII/synthesis/niosII.v b/Top/niosII/synthesis/niosII.v index 5ac864a..bee0b2c 100644 --- a/Top/niosII/synthesis/niosII.v +++ b/Top/niosII/synthesis/niosII.v @@ -12,66 +12,114 @@ module niosII ( output wire sem_export_green // .green ); - wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata - wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest - wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess - wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address - wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable - wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read - wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write - wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata - wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata - wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest - wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address - wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read - wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect - wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata - wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest - wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address - wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n - wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n - wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata - wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata - wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr - wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd - wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr - wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata - wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata - wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest - wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess - wire [8:0] mm_interconnect_0_cpu_debug_mem_slave_address; // mm_interconnect_0:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address - wire mm_interconnect_0_cpu_debug_mem_slave_read; // mm_interconnect_0:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read - wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable - wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write - wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata - wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr - wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr - wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata - wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect - wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata - wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address - wire mm_interconnect_0_sys_clk_timer_s1_write; // mm_interconnect_0:sys_clk_timer_s1_write -> sys_clk_timer:write_n - wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata - wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2 - wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata - wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2 - wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2 - wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2 - wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2 - wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2 - wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect - wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata - wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address - wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable - wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write - wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata - wire mm_interconnect_0_mem_s1_clken; // mm_interconnect_0:mem_s1_clken -> mem:clken - wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq - wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq - wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq - wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n] - wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in] - wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1 + wire cpu_custom_instruction_master_readra; // cpu:D_ci_readra -> cpu_custom_instruction_master_translator:ci_slave_readra + wire [4:0] cpu_custom_instruction_master_a; // cpu:D_ci_a -> cpu_custom_instruction_master_translator:ci_slave_a + wire [4:0] cpu_custom_instruction_master_b; // cpu:D_ci_b -> cpu_custom_instruction_master_translator:ci_slave_b + wire [4:0] cpu_custom_instruction_master_c; // cpu:D_ci_c -> cpu_custom_instruction_master_translator:ci_slave_c + wire cpu_custom_instruction_master_readrb; // cpu:D_ci_readrb -> cpu_custom_instruction_master_translator:ci_slave_readrb + wire [31:0] cpu_custom_instruction_master_ipending; // cpu:W_ci_ipending -> cpu_custom_instruction_master_translator:ci_slave_ipending + wire [7:0] cpu_custom_instruction_master_n; // cpu:D_ci_n -> cpu_custom_instruction_master_translator:ci_slave_n + wire [31:0] cpu_custom_instruction_master_result; // cpu_custom_instruction_master_translator:ci_slave_result -> cpu:E_ci_result + wire cpu_custom_instruction_master_estatus; // cpu:W_ci_estatus -> cpu_custom_instruction_master_translator:ci_slave_estatus + wire [31:0] cpu_custom_instruction_master_datab; // cpu:E_ci_datab -> cpu_custom_instruction_master_translator:ci_slave_datab + wire [31:0] cpu_custom_instruction_master_dataa; // cpu:E_ci_dataa -> cpu_custom_instruction_master_translator:ci_slave_dataa + wire cpu_custom_instruction_master_writerc; // cpu:D_ci_writerc -> cpu_custom_instruction_master_translator:ci_slave_writerc + wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_result; // cpu_custom_instruction_master_comb_xconnect:ci_slave_result -> cpu_custom_instruction_master_translator:comb_ci_master_result + wire cpu_custom_instruction_master_translator_comb_ci_master_readra; // cpu_custom_instruction_master_translator:comb_ci_master_readra -> cpu_custom_instruction_master_comb_xconnect:ci_slave_readra + wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_a; // cpu_custom_instruction_master_translator:comb_ci_master_a -> cpu_custom_instruction_master_comb_xconnect:ci_slave_a + wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_b; // cpu_custom_instruction_master_translator:comb_ci_master_b -> cpu_custom_instruction_master_comb_xconnect:ci_slave_b + wire cpu_custom_instruction_master_translator_comb_ci_master_readrb; // cpu_custom_instruction_master_translator:comb_ci_master_readrb -> cpu_custom_instruction_master_comb_xconnect:ci_slave_readrb + wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_c; // cpu_custom_instruction_master_translator:comb_ci_master_c -> cpu_custom_instruction_master_comb_xconnect:ci_slave_c + wire cpu_custom_instruction_master_translator_comb_ci_master_estatus; // cpu_custom_instruction_master_translator:comb_ci_master_estatus -> cpu_custom_instruction_master_comb_xconnect:ci_slave_estatus + wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_ipending; // cpu_custom_instruction_master_translator:comb_ci_master_ipending -> cpu_custom_instruction_master_comb_xconnect:ci_slave_ipending + wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_datab; // cpu_custom_instruction_master_translator:comb_ci_master_datab -> cpu_custom_instruction_master_comb_xconnect:ci_slave_datab + wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_dataa; // cpu_custom_instruction_master_translator:comb_ci_master_dataa -> cpu_custom_instruction_master_comb_xconnect:ci_slave_dataa + wire cpu_custom_instruction_master_translator_comb_ci_master_writerc; // cpu_custom_instruction_master_translator:comb_ci_master_writerc -> cpu_custom_instruction_master_comb_xconnect:ci_slave_writerc + wire [7:0] cpu_custom_instruction_master_translator_comb_ci_master_n; // cpu_custom_instruction_master_translator:comb_ci_master_n -> cpu_custom_instruction_master_comb_xconnect:ci_slave_n + wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_result; // cpu_custom_instruction_master_comb_slave_translator0:ci_slave_result -> cpu_custom_instruction_master_comb_xconnect:ci_master0_result + wire cpu_custom_instruction_master_comb_xconnect_ci_master0_readra; // cpu_custom_instruction_master_comb_xconnect:ci_master0_readra -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_readra + wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_a; // cpu_custom_instruction_master_comb_xconnect:ci_master0_a -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_a + wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_b; // cpu_custom_instruction_master_comb_xconnect:ci_master0_b -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_b + wire cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb; // cpu_custom_instruction_master_comb_xconnect:ci_master0_readrb -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_readrb + wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_c; // cpu_custom_instruction_master_comb_xconnect:ci_master0_c -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_c + wire cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus; // cpu_custom_instruction_master_comb_xconnect:ci_master0_estatus -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_estatus + wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending; // cpu_custom_instruction_master_comb_xconnect:ci_master0_ipending -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_ipending + wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_datab; // cpu_custom_instruction_master_comb_xconnect:ci_master0_datab -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_datab + wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa; // cpu_custom_instruction_master_comb_xconnect:ci_master0_dataa -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_dataa + wire cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc; // cpu_custom_instruction_master_comb_xconnect:ci_master0_writerc -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_writerc + wire [7:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_n; // cpu_custom_instruction_master_comb_xconnect:ci_master0_n -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_n + wire [31:0] cpu_custom_instruction_master_comb_slave_translator0_ci_master_result; // countones:ones -> cpu_custom_instruction_master_comb_slave_translator0:ci_master_result + wire [31:0] cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa; // cpu_custom_instruction_master_comb_slave_translator0:ci_master_dataa -> countones:din + wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata + wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest + wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess + wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address + wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable + wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read + wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write + wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata + wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata + wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest + wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address + wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read + wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect + wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata + wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest + wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address + wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n + wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n + wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata + wire [31:0] mm_interconnect_0_perf_counter_control_slave_readdata; // perf_counter:readdata -> mm_interconnect_0:perf_counter_control_slave_readdata + wire [3:0] mm_interconnect_0_perf_counter_control_slave_address; // mm_interconnect_0:perf_counter_control_slave_address -> perf_counter:address + wire mm_interconnect_0_perf_counter_control_slave_begintransfer; // mm_interconnect_0:perf_counter_control_slave_begintransfer -> perf_counter:begintransfer + wire mm_interconnect_0_perf_counter_control_slave_write; // mm_interconnect_0:perf_counter_control_slave_write -> perf_counter:write + wire [31:0] mm_interconnect_0_perf_counter_control_slave_writedata; // mm_interconnect_0:perf_counter_control_slave_writedata -> perf_counter:writedata + wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata + wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr + wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd + wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr + wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata + wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata + wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest + wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess + wire [8:0] mm_interconnect_0_cpu_debug_mem_slave_address; // mm_interconnect_0:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address + wire mm_interconnect_0_cpu_debug_mem_slave_read; // mm_interconnect_0:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read + wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable + wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write + wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata + wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr + wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr + wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata + wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect + wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata + wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address + wire mm_interconnect_0_sys_clk_timer_s1_write; // mm_interconnect_0:sys_clk_timer_s1_write -> sys_clk_timer:write_n + wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata + wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2 + wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata + wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2 + wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2 + wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2 + wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2 + wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2 + wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect + wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata + wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address + wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable + wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write + wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata + wire mm_interconnect_0_mem_s1_clken; // mm_interconnect_0:mem_s1_clken -> mem:clken + wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq + wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq + wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, perf_counter:reset_n, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n] + wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in] + wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1 + + countones countones ( + .din (cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa), // nios_custom_instruction_slave.dataa + .ones (cpu_custom_instruction_master_comb_slave_translator0_ci_master_result) // .result + ); niosII_cpu cpu ( .clk (clk_clk), // clk.clk @@ -99,7 +147,21 @@ module niosII ( .debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest .debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write .debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata - .dummy_ci_port () // custom_instruction_master.readra + .E_ci_result (cpu_custom_instruction_master_result), // custom_instruction_master.result + .D_ci_a (cpu_custom_instruction_master_a), // .a + .D_ci_b (cpu_custom_instruction_master_b), // .b + .D_ci_c (cpu_custom_instruction_master_c), // .c + .D_ci_n (cpu_custom_instruction_master_n), // .n + .D_ci_readra (cpu_custom_instruction_master_readra), // .readra + .D_ci_readrb (cpu_custom_instruction_master_readrb), // .readrb + .D_ci_writerc (cpu_custom_instruction_master_writerc), // .writerc + .E_ci_dataa (cpu_custom_instruction_master_dataa), // .dataa + .E_ci_datab (cpu_custom_instruction_master_datab), // .datab + .E_ci_multi_clock (), // .clk + .E_ci_multi_reset (), // .reset + .E_ci_multi_reset_req (), // .reset_req + .W_ci_estatus (cpu_custom_instruction_master_estatus), // .estatus + .W_ci_ipending (cpu_custom_instruction_master_ipending) // .ipending ); niosII_jtag_uart jtag_uart ( @@ -136,6 +198,16 @@ module niosII ( .freeze (1'b0) // (terminated) ); + niosII_perf_counter perf_counter ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (mm_interconnect_0_perf_counter_control_slave_address), // control_slave.address + .begintransfer (mm_interconnect_0_perf_counter_control_slave_begintransfer), // .begintransfer + .readdata (mm_interconnect_0_perf_counter_control_slave_readdata), // .readdata + .write (mm_interconnect_0_perf_counter_control_slave_write), // .write + .writedata (mm_interconnect_0_perf_counter_control_slave_writedata) // .writedata + ); + dec #( .m (32) ) sem ( @@ -166,63 +238,199 @@ module niosII ( .irq (irq_mapper_receiver0_irq) // irq.irq ); + altera_customins_master_translator #( + .SHARED_COMB_AND_MULTI (1) + ) cpu_custom_instruction_master_translator ( + .ci_slave_dataa (cpu_custom_instruction_master_dataa), // ci_slave.dataa + .ci_slave_datab (cpu_custom_instruction_master_datab), // .datab + .ci_slave_result (cpu_custom_instruction_master_result), // .result + .ci_slave_n (cpu_custom_instruction_master_n), // .n + .ci_slave_readra (cpu_custom_instruction_master_readra), // .readra + .ci_slave_readrb (cpu_custom_instruction_master_readrb), // .readrb + .ci_slave_writerc (cpu_custom_instruction_master_writerc), // .writerc + .ci_slave_a (cpu_custom_instruction_master_a), // .a + .ci_slave_b (cpu_custom_instruction_master_b), // .b + .ci_slave_c (cpu_custom_instruction_master_c), // .c + .ci_slave_ipending (cpu_custom_instruction_master_ipending), // .ipending + .ci_slave_estatus (cpu_custom_instruction_master_estatus), // .estatus + .comb_ci_master_dataa (cpu_custom_instruction_master_translator_comb_ci_master_dataa), // comb_ci_master.dataa + .comb_ci_master_datab (cpu_custom_instruction_master_translator_comb_ci_master_datab), // .datab + .comb_ci_master_result (cpu_custom_instruction_master_translator_comb_ci_master_result), // .result + .comb_ci_master_n (cpu_custom_instruction_master_translator_comb_ci_master_n), // .n + .comb_ci_master_readra (cpu_custom_instruction_master_translator_comb_ci_master_readra), // .readra + .comb_ci_master_readrb (cpu_custom_instruction_master_translator_comb_ci_master_readrb), // .readrb + .comb_ci_master_writerc (cpu_custom_instruction_master_translator_comb_ci_master_writerc), // .writerc + .comb_ci_master_a (cpu_custom_instruction_master_translator_comb_ci_master_a), // .a + .comb_ci_master_b (cpu_custom_instruction_master_translator_comb_ci_master_b), // .b + .comb_ci_master_c (cpu_custom_instruction_master_translator_comb_ci_master_c), // .c + .comb_ci_master_ipending (cpu_custom_instruction_master_translator_comb_ci_master_ipending), // .ipending + .comb_ci_master_estatus (cpu_custom_instruction_master_translator_comb_ci_master_estatus), // .estatus + .ci_slave_multi_clk (1'b0), // (terminated) + .ci_slave_multi_reset (1'b0), // (terminated) + .ci_slave_multi_clken (1'b0), // (terminated) + .ci_slave_multi_reset_req (1'b0), // (terminated) + .ci_slave_multi_start (1'b0), // (terminated) + .ci_slave_multi_done (), // (terminated) + .ci_slave_multi_dataa (32'b00000000000000000000000000000000), // (terminated) + .ci_slave_multi_datab (32'b00000000000000000000000000000000), // (terminated) + .ci_slave_multi_result (), // (terminated) + .ci_slave_multi_n (8'b00000000), // (terminated) + .ci_slave_multi_readra (1'b0), // (terminated) + .ci_slave_multi_readrb (1'b0), // (terminated) + .ci_slave_multi_writerc (1'b0), // (terminated) + .ci_slave_multi_a (5'b00000), // (terminated) + .ci_slave_multi_b (5'b00000), // (terminated) + .ci_slave_multi_c (5'b00000), // (terminated) + .multi_ci_master_clk (), // (terminated) + .multi_ci_master_reset (), // (terminated) + .multi_ci_master_clken (), // (terminated) + .multi_ci_master_reset_req (), // (terminated) + .multi_ci_master_start (), // (terminated) + .multi_ci_master_done (1'b0), // (terminated) + .multi_ci_master_dataa (), // (terminated) + .multi_ci_master_datab (), // (terminated) + .multi_ci_master_result (32'b00000000000000000000000000000000), // (terminated) + .multi_ci_master_n (), // (terminated) + .multi_ci_master_readra (), // (terminated) + .multi_ci_master_readrb (), // (terminated) + .multi_ci_master_writerc (), // (terminated) + .multi_ci_master_a (), // (terminated) + .multi_ci_master_b (), // (terminated) + .multi_ci_master_c () // (terminated) + ); + + niosII_cpu_custom_instruction_master_comb_xconnect cpu_custom_instruction_master_comb_xconnect ( + .ci_slave_dataa (cpu_custom_instruction_master_translator_comb_ci_master_dataa), // ci_slave.dataa + .ci_slave_datab (cpu_custom_instruction_master_translator_comb_ci_master_datab), // .datab + .ci_slave_result (cpu_custom_instruction_master_translator_comb_ci_master_result), // .result + .ci_slave_n (cpu_custom_instruction_master_translator_comb_ci_master_n), // .n + .ci_slave_readra (cpu_custom_instruction_master_translator_comb_ci_master_readra), // .readra + .ci_slave_readrb (cpu_custom_instruction_master_translator_comb_ci_master_readrb), // .readrb + .ci_slave_writerc (cpu_custom_instruction_master_translator_comb_ci_master_writerc), // .writerc + .ci_slave_a (cpu_custom_instruction_master_translator_comb_ci_master_a), // .a + .ci_slave_b (cpu_custom_instruction_master_translator_comb_ci_master_b), // .b + .ci_slave_c (cpu_custom_instruction_master_translator_comb_ci_master_c), // .c + .ci_slave_ipending (cpu_custom_instruction_master_translator_comb_ci_master_ipending), // .ipending + .ci_slave_estatus (cpu_custom_instruction_master_translator_comb_ci_master_estatus), // .estatus + .ci_master0_dataa (cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa), // ci_master0.dataa + .ci_master0_datab (cpu_custom_instruction_master_comb_xconnect_ci_master0_datab), // .datab + .ci_master0_result (cpu_custom_instruction_master_comb_xconnect_ci_master0_result), // .result + .ci_master0_n (cpu_custom_instruction_master_comb_xconnect_ci_master0_n), // .n + .ci_master0_readra (cpu_custom_instruction_master_comb_xconnect_ci_master0_readra), // .readra + .ci_master0_readrb (cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb), // .readrb + .ci_master0_writerc (cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc), // .writerc + .ci_master0_a (cpu_custom_instruction_master_comb_xconnect_ci_master0_a), // .a + .ci_master0_b (cpu_custom_instruction_master_comb_xconnect_ci_master0_b), // .b + .ci_master0_c (cpu_custom_instruction_master_comb_xconnect_ci_master0_c), // .c + .ci_master0_ipending (cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending), // .ipending + .ci_master0_estatus (cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus) // .estatus + ); + + altera_customins_slave_translator #( + .N_WIDTH (8), + .USE_DONE (0), + .NUM_FIXED_CYCLES (0) + ) cpu_custom_instruction_master_comb_slave_translator0 ( + .ci_slave_dataa (cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa), // ci_slave.dataa + .ci_slave_datab (cpu_custom_instruction_master_comb_xconnect_ci_master0_datab), // .datab + .ci_slave_result (cpu_custom_instruction_master_comb_xconnect_ci_master0_result), // .result + .ci_slave_n (cpu_custom_instruction_master_comb_xconnect_ci_master0_n), // .n + .ci_slave_readra (cpu_custom_instruction_master_comb_xconnect_ci_master0_readra), // .readra + .ci_slave_readrb (cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb), // .readrb + .ci_slave_writerc (cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc), // .writerc + .ci_slave_a (cpu_custom_instruction_master_comb_xconnect_ci_master0_a), // .a + .ci_slave_b (cpu_custom_instruction_master_comb_xconnect_ci_master0_b), // .b + .ci_slave_c (cpu_custom_instruction_master_comb_xconnect_ci_master0_c), // .c + .ci_slave_ipending (cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending), // .ipending + .ci_slave_estatus (cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus), // .estatus + .ci_master_dataa (cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa), // ci_master.dataa + .ci_master_result (cpu_custom_instruction_master_comb_slave_translator0_ci_master_result), // .result + .ci_master_datab (), // (terminated) + .ci_master_n (), // (terminated) + .ci_master_readra (), // (terminated) + .ci_master_readrb (), // (terminated) + .ci_master_writerc (), // (terminated) + .ci_master_a (), // (terminated) + .ci_master_b (), // (terminated) + .ci_master_c (), // (terminated) + .ci_master_ipending (), // (terminated) + .ci_master_estatus (), // (terminated) + .ci_master_clk (), // (terminated) + .ci_master_clken (), // (terminated) + .ci_master_reset_req (), // (terminated) + .ci_master_reset (), // (terminated) + .ci_master_start (), // (terminated) + .ci_master_done (1'b0), // (terminated) + .ci_slave_clk (1'b0), // (terminated) + .ci_slave_clken (1'b0), // (terminated) + .ci_slave_reset_req (1'b0), // (terminated) + .ci_slave_reset (1'b0), // (terminated) + .ci_slave_start (1'b0), // (terminated) + .ci_slave_done () // (terminated) + ); + niosII_mm_interconnect_0 mm_interconnect_0 ( - .clk_clk_clk (clk_clk), // clk_clk.clk - .cpu_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_reset_reset_bridge_in_reset.reset - .cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address - .cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest - .cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable - .cpu_data_master_read (cpu_data_master_read), // .read - .cpu_data_master_readdata (cpu_data_master_readdata), // .readdata - .cpu_data_master_write (cpu_data_master_write), // .write - .cpu_data_master_writedata (cpu_data_master_writedata), // .writedata - .cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess - .cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address - .cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest - .cpu_instruction_master_read (cpu_instruction_master_read), // .read - .cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata - .cpu_debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // cpu_debug_mem_slave.address - .cpu_debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write - .cpu_debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read - .cpu_debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata - .cpu_debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata - .cpu_debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable - .cpu_debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest - .cpu_debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess - .jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address - .jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write - .jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read - .jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata - .jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata - .jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest - .jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect - .mem_s1_address (mm_interconnect_0_mem_s1_address), // mem_s1.address - .mem_s1_write (mm_interconnect_0_mem_s1_write), // .write - .mem_s1_readdata (mm_interconnect_0_mem_s1_readdata), // .readdata - .mem_s1_writedata (mm_interconnect_0_mem_s1_writedata), // .writedata - .mem_s1_byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable - .mem_s1_chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect - .mem_s1_clken (mm_interconnect_0_mem_s1_clken), // .clken - .mem_s2_address (mm_interconnect_0_mem_s2_address), // mem_s2.address - .mem_s2_write (mm_interconnect_0_mem_s2_write), // .write - .mem_s2_readdata (mm_interconnect_0_mem_s2_readdata), // .readdata - .mem_s2_writedata (mm_interconnect_0_mem_s2_writedata), // .writedata - .mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable - .mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect - .mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken - .sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address - .sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write - .sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read - .sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata - .sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata - .sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address - .sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write - .sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata - .sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address - .sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write - .sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata - .sys_clk_timer_s1_writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata - .sys_clk_timer_s1_chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect) // .chipselect + .clk_clk_clk (clk_clk), // clk_clk.clk + .cpu_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_reset_reset_bridge_in_reset.reset + .cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address + .cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest + .cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable + .cpu_data_master_read (cpu_data_master_read), // .read + .cpu_data_master_readdata (cpu_data_master_readdata), // .readdata + .cpu_data_master_write (cpu_data_master_write), // .write + .cpu_data_master_writedata (cpu_data_master_writedata), // .writedata + .cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess + .cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address + .cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest + .cpu_instruction_master_read (cpu_instruction_master_read), // .read + .cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata + .cpu_debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // cpu_debug_mem_slave.address + .cpu_debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write + .cpu_debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read + .cpu_debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata + .cpu_debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata + .cpu_debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable + .cpu_debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest + .cpu_debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess + .jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address + .jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write + .jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read + .jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata + .jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata + .jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest + .jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect + .mem_s1_address (mm_interconnect_0_mem_s1_address), // mem_s1.address + .mem_s1_write (mm_interconnect_0_mem_s1_write), // .write + .mem_s1_readdata (mm_interconnect_0_mem_s1_readdata), // .readdata + .mem_s1_writedata (mm_interconnect_0_mem_s1_writedata), // .writedata + .mem_s1_byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable + .mem_s1_chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect + .mem_s1_clken (mm_interconnect_0_mem_s1_clken), // .clken + .mem_s2_address (mm_interconnect_0_mem_s2_address), // mem_s2.address + .mem_s2_write (mm_interconnect_0_mem_s2_write), // .write + .mem_s2_readdata (mm_interconnect_0_mem_s2_readdata), // .readdata + .mem_s2_writedata (mm_interconnect_0_mem_s2_writedata), // .writedata + .mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable + .mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect + .mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken + .perf_counter_control_slave_address (mm_interconnect_0_perf_counter_control_slave_address), // perf_counter_control_slave.address + .perf_counter_control_slave_write (mm_interconnect_0_perf_counter_control_slave_write), // .write + .perf_counter_control_slave_readdata (mm_interconnect_0_perf_counter_control_slave_readdata), // .readdata + .perf_counter_control_slave_writedata (mm_interconnect_0_perf_counter_control_slave_writedata), // .writedata + .perf_counter_control_slave_begintransfer (mm_interconnect_0_perf_counter_control_slave_begintransfer), // .begintransfer + .sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address + .sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write + .sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read + .sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata + .sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata + .sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address + .sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write + .sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata + .sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address + .sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write + .sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata + .sys_clk_timer_s1_writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata + .sys_clk_timer_s1_chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect) // .chipselect ); niosII_irq_mapper irq_mapper ( diff --git a/Top/niosII/synthesis/submodules/niosII_cpu.v b/Top/niosII/synthesis/submodules/niosII_cpu.v index 5c0d61e..60d5ffa 100644 --- a/Top/niosII/synthesis/submodules/niosII_cpu.v +++ b/Top/niosII/synthesis/submodules/niosII_cpu.v @@ -32,7 +32,21 @@ module niosII_cpu ( output wire debug_mem_slave_waitrequest, // .waitrequest input wire debug_mem_slave_write, // .write input wire [31:0] debug_mem_slave_writedata, // .writedata - output wire dummy_ci_port // custom_instruction_master.readra + input wire [31:0] E_ci_result, // custom_instruction_master.result + output wire [4:0] D_ci_a, // .a + output wire [4:0] D_ci_b, // .b + output wire [4:0] D_ci_c, // .c + output wire [7:0] D_ci_n, // .n + output wire D_ci_readra, // .readra + output wire D_ci_readrb, // .readrb + output wire D_ci_writerc, // .writerc + output wire [31:0] E_ci_dataa, // .dataa + output wire [31:0] E_ci_datab, // .datab + output wire E_ci_multi_clock, // .clk + output wire E_ci_multi_reset, // .reset + output wire E_ci_multi_reset_req, // .reset_req + output wire W_ci_estatus, // .estatus + output wire [31:0] W_ci_ipending // .ipending ); niosII_cpu_cpu cpu ( @@ -61,7 +75,21 @@ module niosII_cpu ( .debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest .debug_mem_slave_write (debug_mem_slave_write), // .write .debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata - .dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra + .E_ci_result (E_ci_result), // custom_instruction_master.result + .D_ci_a (D_ci_a), // .a + .D_ci_b (D_ci_b), // .b + .D_ci_c (D_ci_c), // .c + .D_ci_n (D_ci_n), // .n + .D_ci_readra (D_ci_readra), // .readra + .D_ci_readrb (D_ci_readrb), // .readrb + .D_ci_writerc (D_ci_writerc), // .writerc + .E_ci_dataa (E_ci_dataa), // .dataa + .E_ci_datab (E_ci_datab), // .datab + .E_ci_multi_clock (E_ci_multi_clock), // .clk + .E_ci_multi_reset (E_ci_multi_reset), // .reset + .E_ci_multi_reset_req (E_ci_multi_reset_req), // .reset_req + .W_ci_estatus (W_ci_estatus), // .estatus + .W_ci_ipending (W_ci_ipending) // .ipending ); endmodule diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v index a9765e0..da7a358 100644 --- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v +++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v @@ -2833,6 +2833,7 @@ endmodule module niosII_cpu_cpu ( // inputs: + E_ci_result, clk, d_readdata, d_waitrequest, @@ -2849,6 +2850,21 @@ module niosII_cpu_cpu ( reset_req, // outputs: + D_ci_a, + D_ci_b, + D_ci_c, + D_ci_n, + D_ci_readra, + D_ci_readrb, + D_ci_writerc, + E_ci_dataa, + E_ci_datab, + E_ci_multi_clock, + E_ci_multi_reset, + E_ci_multi_reset_req, + W_ci_estatus, + W_ci_ipending, + W_ci_status, d_address, d_byteenable, d_read, @@ -2858,12 +2874,26 @@ module niosII_cpu_cpu ( debug_mem_slave_readdata, debug_mem_slave_waitrequest, debug_reset_request, - dummy_ci_port, i_address, i_read ) ; + output [ 4: 0] D_ci_a; + output [ 4: 0] D_ci_b; + output [ 4: 0] D_ci_c; + output [ 7: 0] D_ci_n; + output D_ci_readra; + output D_ci_readrb; + output D_ci_writerc; + output [ 31: 0] E_ci_dataa; + output [ 31: 0] E_ci_datab; + output E_ci_multi_clock; + output E_ci_multi_reset; + output E_ci_multi_reset_req; + output W_ci_estatus; + output [ 31: 0] W_ci_ipending; + output W_ci_status; output [ 17: 0] d_address; output [ 3: 0] d_byteenable; output d_read; @@ -2873,9 +2903,9 @@ module niosII_cpu_cpu ( output [ 31: 0] debug_mem_slave_readdata; output debug_mem_slave_waitrequest; output debug_reset_request; - output dummy_ci_port; output [ 17: 0] i_address; output i_read; + input [ 31: 0] E_ci_result; input clk; input [ 31: 0] d_readdata; input d_waitrequest; @@ -2893,6 +2923,13 @@ module niosII_cpu_cpu ( reg A_valid_from_M /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; +wire [ 4: 0] D_ci_a; +wire [ 4: 0] D_ci_b; +wire [ 4: 0] D_ci_c; +wire [ 7: 0] D_ci_n; +wire D_ci_readra; +wire D_ci_readrb; +wire D_ci_writerc; wire [ 1: 0] D_compare_op; wire D_ctrl_alu_force_and; wire D_ctrl_alu_force_xor; @@ -2942,7 +2979,7 @@ wire D_ctrl_uncond_cti_non_br; wire D_ctrl_unsigned_lo_imm16; wire D_ctrl_wrctl_inst; wire [ 4: 0] D_dst_regnum; -wire [ 55: 0] D_inst; +wire [ 71: 0] D_inst; wire D_is_opx_inst; reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; wire [ 4: 0] D_iw_a; @@ -2993,6 +3030,7 @@ wire D_op_cmpltu; wire D_op_cmpltui; wire D_op_cmpne; wire D_op_cmpnei; +wire D_op_countones; wire D_op_crst; wire D_op_custom; wire D_op_div; @@ -3100,8 +3138,12 @@ reg E_alu_sub; wire [ 32: 0] E_arith_result; wire [ 31: 0] E_arith_src1; wire [ 31: 0] E_arith_src2; +wire [ 31: 0] E_ci_dataa; +wire [ 31: 0] E_ci_datab; +wire E_ci_multi_clock; +wire E_ci_multi_reset; +wire E_ci_multi_reset_req; wire E_ci_multi_stall; -wire [ 31: 0] E_ci_result; wire E_cmp_result; wire [ 31: 0] E_control_rd_data; wire E_eq; @@ -3154,7 +3196,7 @@ wire [ 5: 0] F_av_iw_opx; wire F_av_mem16; wire F_av_mem32; wire F_av_mem8; -wire [ 55: 0] F_inst; +wire [ 71: 0] F_inst; wire F_is_opx_inst; wire [ 31: 0] F_iw; wire [ 4: 0] F_iw_a; @@ -3202,6 +3244,7 @@ wire F_op_cmpltu; wire F_op_cmpltui; wire F_op_cmpne; wire F_op_cmpnei; +wire F_op_countones; wire F_op_crst; wire F_op_custom; wire F_op_div; @@ -3432,6 +3475,9 @@ reg W_bstatus_reg; wire W_bstatus_reg_inst_nxt; wire W_bstatus_reg_nxt; reg [ 31: 0] W_cdsr_reg; +wire W_ci_estatus; +wire [ 31: 0] W_ci_ipending; +wire W_ci_status; reg W_cmp_result; reg [ 31: 0] W_control_rd_data; wire [ 31: 0] W_cpuid_reg; @@ -3496,7 +3542,6 @@ wire [ 31: 0] debug_mem_slave_readdata; wire debug_mem_slave_reset; wire debug_mem_slave_waitrequest; wire debug_reset_request; -wire dummy_ci_port; reg hbreak_enabled; reg hbreak_pending; wire hbreak_pending_nxt; @@ -3722,6 +3767,7 @@ reg wait_for_one_post_bret_inst; assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst; assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst; assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst; + assign F_op_countones = F_op_custom & 1'b1; assign F_is_opx_inst = F_iw_op == 58; assign D_op_call = D_iw_op == 0; assign D_op_jmpi = D_iw_op == 1; @@ -3850,11 +3896,25 @@ reg wait_for_one_post_bret_inst; assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst; assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst; assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst; + assign D_op_countones = D_op_custom & 1'b1; assign D_is_opx_inst = D_iw_op == 58; assign R_en = 1'b1; - assign E_ci_result = 0; + assign E_ci_dataa = E_src1; + assign E_ci_datab = E_src2; + assign W_ci_ipending = W_ipending_reg; + assign W_ci_status = W_status_reg; + assign W_ci_estatus = W_estatus_reg; + assign D_ci_n = D_iw_custom_n; + assign D_ci_a = D_iw_a; + assign D_ci_b = D_iw_b; + assign D_ci_c = D_iw_c; + assign D_ci_readra = D_iw_custom_readra; + assign D_ci_readrb = D_iw_custom_readrb; + assign D_ci_writerc = D_iw_custom_writerc; + assign E_ci_multi_clock = clk; + assign E_ci_multi_reset = ~reset_n; + assign E_ci_multi_reset_req = reset_req; //custom_instruction_master, which is an e_custom_instruction_master - assign dummy_ci_port = 1'b0; assign E_ci_multi_stall = 1'b0; assign iactive = irq[31 : 0] & 32'b00000000000000000000000000000011; assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 : @@ -4577,7 +4637,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" //debug_mem_slave, which is an e_avalon_slave assign debug_mem_slave_clk = clk; assign debug_mem_slave_reset = ~reset_n; - assign D_ctrl_custom = 1'b0; + assign D_ctrl_custom = D_op_countones; assign R_ctrl_custom_nxt = D_ctrl_custom; always @(posedge clk or negedge reset_n) begin @@ -5226,7 +5286,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" end - assign D_ctrl_b_is_dst = D_op_addi| + assign D_ctrl_b_is_dst = (D_op_addi| D_op_andhi| D_op_orhi| D_op_xorhi| @@ -5254,7 +5314,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" D_op_initd| D_op_initda| D_op_flushd| - D_op_flushda; + D_op_flushda) & ~D_op_custom; assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; always @(posedge clk or negedge reset_n) @@ -5266,7 +5326,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" end - assign D_ctrl_ignore_dst = D_op_br| + assign D_ctrl_ignore_dst = (D_op_br| D_op_bge| D_op_blt| D_op_bne| @@ -5279,7 +5339,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" D_op_stbio| D_op_sthio| D_op_stwio| - D_op_jmpi; + D_op_jmpi) | (D_op_custom & ~D_iw_custom_writerc); assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; always @(posedge clk or negedge reset_n) @@ -5466,183 +5526,185 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex" //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS - assign F_inst = (F_op_call)? 56'h20202063616c6c : - (F_op_jmpi)? 56'h2020206a6d7069 : - (F_op_ldbu)? 56'h2020206c646275 : - (F_op_addi)? 56'h20202061646469 : - (F_op_stb)? 56'h20202020737462 : - (F_op_br)? 56'h20202020206272 : - (F_op_ldb)? 56'h202020206c6462 : - (F_op_cmpgei)? 56'h20636d70676569 : - (F_op_ldhu)? 56'h2020206c646875 : - (F_op_andi)? 56'h202020616e6469 : - (F_op_sth)? 56'h20202020737468 : - (F_op_bge)? 56'h20202020626765 : - (F_op_ldh)? 56'h202020206c6468 : - (F_op_cmplti)? 56'h20636d706c7469 : - (F_op_initda)? 56'h20696e69746461 : - (F_op_ori)? 56'h202020206f7269 : - (F_op_stw)? 56'h20202020737477 : - (F_op_blt)? 56'h20202020626c74 : - (F_op_ldw)? 56'h202020206c6477 : - (F_op_cmpnei)? 56'h20636d706e6569 : - (F_op_flushda)? 56'h666c7573686461 : - (F_op_xori)? 56'h202020786f7269 : - (F_op_bne)? 56'h20202020626e65 : - (F_op_cmpeqi)? 56'h20636d70657169 : - (F_op_ldbuio)? 56'h206c646275696f : - (F_op_muli)? 56'h2020206d756c69 : - (F_op_stbio)? 56'h2020737462696f : - (F_op_beq)? 56'h20202020626571 : - (F_op_ldbio)? 56'h20206c6462696f : - (F_op_cmpgeui)? 56'h636d7067657569 : - (F_op_ldhuio)? 56'h206c646875696f : - (F_op_andhi)? 56'h2020616e646869 : - (F_op_sthio)? 56'h2020737468696f : - (F_op_bgeu)? 56'h20202062676575 : - (F_op_ldhio)? 56'h20206c6468696f : - (F_op_cmpltui)? 56'h636d706c747569 : - (F_op_custom)? 56'h20637573746f6d : - (F_op_initd)? 56'h2020696e697464 : - (F_op_orhi)? 56'h2020206f726869 : - (F_op_stwio)? 56'h2020737477696f : - (F_op_bltu)? 56'h202020626c7475 : - (F_op_ldwio)? 56'h20206c6477696f : - (F_op_flushd)? 56'h20666c75736864 : - (F_op_xorhi)? 56'h2020786f726869 : - (F_op_eret)? 56'h20202065726574 : - (F_op_roli)? 56'h202020726f6c69 : - (F_op_rol)? 56'h20202020726f6c : - (F_op_flushp)? 56'h20666c75736870 : - (F_op_ret)? 56'h20202020726574 : - (F_op_nor)? 56'h202020206e6f72 : - (F_op_mulxuu)? 56'h206d756c787575 : - (F_op_cmpge)? 56'h2020636d706765 : - (F_op_bret)? 56'h20202062726574 : - (F_op_ror)? 56'h20202020726f72 : - (F_op_flushi)? 56'h20666c75736869 : - (F_op_jmp)? 56'h202020206a6d70 : - (F_op_and)? 56'h20202020616e64 : - (F_op_cmplt)? 56'h2020636d706c74 : - (F_op_slli)? 56'h202020736c6c69 : - (F_op_sll)? 56'h20202020736c6c : - (F_op_or)? 56'h20202020206f72 : - (F_op_mulxsu)? 56'h206d756c787375 : - (F_op_cmpne)? 56'h2020636d706e65 : - (F_op_srli)? 56'h20202073726c69 : - (F_op_srl)? 56'h2020202073726c : - (F_op_nextpc)? 56'h206e6578747063 : - (F_op_callr)? 56'h202063616c6c72 : - (F_op_xor)? 56'h20202020786f72 : - (F_op_mulxss)? 56'h206d756c787373 : - (F_op_cmpeq)? 56'h2020636d706571 : - (F_op_divu)? 56'h20202064697675 : - (F_op_div)? 56'h20202020646976 : - (F_op_rdctl)? 56'h2020726463746c : - (F_op_mul)? 56'h202020206d756c : - (F_op_cmpgeu)? 56'h20636d70676575 : - (F_op_initi)? 56'h2020696e697469 : - (F_op_trap)? 56'h20202074726170 : - (F_op_wrctl)? 56'h2020777263746c : - (F_op_cmpltu)? 56'h20636d706c7475 : - (F_op_add)? 56'h20202020616464 : - (F_op_break)? 56'h2020627265616b : - (F_op_hbreak)? 56'h2068627265616b : - (F_op_sync)? 56'h20202073796e63 : - (F_op_sub)? 56'h20202020737562 : - (F_op_srai)? 56'h20202073726169 : - (F_op_sra)? 56'h20202020737261 : - (F_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; + assign F_inst = (F_op_call)? 72'h202020202063616c6c : + (F_op_jmpi)? 72'h20202020206a6d7069 : + (F_op_ldbu)? 72'h20202020206c646275 : + (F_op_addi)? 72'h202020202061646469 : + (F_op_stb)? 72'h202020202020737462 : + (F_op_br)? 72'h202020202020206272 : + (F_op_ldb)? 72'h2020202020206c6462 : + (F_op_cmpgei)? 72'h202020636d70676569 : + (F_op_ldhu)? 72'h20202020206c646875 : + (F_op_andi)? 72'h2020202020616e6469 : + (F_op_sth)? 72'h202020202020737468 : + (F_op_bge)? 72'h202020202020626765 : + (F_op_ldh)? 72'h2020202020206c6468 : + (F_op_cmplti)? 72'h202020636d706c7469 : + (F_op_initda)? 72'h202020696e69746461 : + (F_op_ori)? 72'h2020202020206f7269 : + (F_op_stw)? 72'h202020202020737477 : + (F_op_blt)? 72'h202020202020626c74 : + (F_op_ldw)? 72'h2020202020206c6477 : + (F_op_cmpnei)? 72'h202020636d706e6569 : + (F_op_flushda)? 72'h2020666c7573686461 : + (F_op_xori)? 72'h2020202020786f7269 : + (F_op_bne)? 72'h202020202020626e65 : + (F_op_cmpeqi)? 72'h202020636d70657169 : + (F_op_ldbuio)? 72'h2020206c646275696f : + (F_op_muli)? 72'h20202020206d756c69 : + (F_op_stbio)? 72'h20202020737462696f : + (F_op_beq)? 72'h202020202020626571 : + (F_op_ldbio)? 72'h202020206c6462696f : + (F_op_cmpgeui)? 72'h2020636d7067657569 : + (F_op_ldhuio)? 72'h2020206c646875696f : + (F_op_andhi)? 72'h20202020616e646869 : + (F_op_sthio)? 72'h20202020737468696f : + (F_op_bgeu)? 72'h202020202062676575 : + (F_op_ldhio)? 72'h202020206c6468696f : + (F_op_cmpltui)? 72'h2020636d706c747569 : + (F_op_custom)? 72'h202020637573746f6d : + (F_op_initd)? 72'h20202020696e697464 : + (F_op_orhi)? 72'h20202020206f726869 : + (F_op_stwio)? 72'h20202020737477696f : + (F_op_bltu)? 72'h2020202020626c7475 : + (F_op_ldwio)? 72'h202020206c6477696f : + (F_op_flushd)? 72'h202020666c75736864 : + (F_op_xorhi)? 72'h20202020786f726869 : + (F_op_eret)? 72'h202020202065726574 : + (F_op_roli)? 72'h2020202020726f6c69 : + (F_op_rol)? 72'h202020202020726f6c : + (F_op_flushp)? 72'h202020666c75736870 : + (F_op_ret)? 72'h202020202020726574 : + (F_op_nor)? 72'h2020202020206e6f72 : + (F_op_mulxuu)? 72'h2020206d756c787575 : + (F_op_cmpge)? 72'h20202020636d706765 : + (F_op_bret)? 72'h202020202062726574 : + (F_op_ror)? 72'h202020202020726f72 : + (F_op_flushi)? 72'h202020666c75736869 : + (F_op_jmp)? 72'h2020202020206a6d70 : + (F_op_and)? 72'h202020202020616e64 : + (F_op_cmplt)? 72'h20202020636d706c74 : + (F_op_slli)? 72'h2020202020736c6c69 : + (F_op_sll)? 72'h202020202020736c6c : + (F_op_or)? 72'h202020202020206f72 : + (F_op_mulxsu)? 72'h2020206d756c787375 : + (F_op_cmpne)? 72'h20202020636d706e65 : + (F_op_srli)? 72'h202020202073726c69 : + (F_op_srl)? 72'h20202020202073726c : + (F_op_nextpc)? 72'h2020206e6578747063 : + (F_op_callr)? 72'h2020202063616c6c72 : + (F_op_xor)? 72'h202020202020786f72 : + (F_op_mulxss)? 72'h2020206d756c787373 : + (F_op_cmpeq)? 72'h20202020636d706571 : + (F_op_divu)? 72'h202020202064697675 : + (F_op_div)? 72'h202020202020646976 : + (F_op_rdctl)? 72'h20202020726463746c : + (F_op_mul)? 72'h2020202020206d756c : + (F_op_cmpgeu)? 72'h202020636d70676575 : + (F_op_initi)? 72'h20202020696e697469 : + (F_op_trap)? 72'h202020202074726170 : + (F_op_wrctl)? 72'h20202020777263746c : + (F_op_cmpltu)? 72'h202020636d706c7475 : + (F_op_add)? 72'h202020202020616464 : + (F_op_break)? 72'h20202020627265616b : + (F_op_hbreak)? 72'h20202068627265616b : + (F_op_sync)? 72'h202020202073796e63 : + (F_op_sub)? 72'h202020202020737562 : + (F_op_srai)? 72'h202020202073726169 : + (F_op_sra)? 72'h202020202020737261 : + (F_op_intr)? 72'h2020202020696e7472 : + (F_op_countones)? 72'h636f756e746f6e6573 : + 72'h202020202020424144; - assign D_inst = (D_op_call)? 56'h20202063616c6c : - (D_op_jmpi)? 56'h2020206a6d7069 : - (D_op_ldbu)? 56'h2020206c646275 : - (D_op_addi)? 56'h20202061646469 : - (D_op_stb)? 56'h20202020737462 : - (D_op_br)? 56'h20202020206272 : - (D_op_ldb)? 56'h202020206c6462 : - (D_op_cmpgei)? 56'h20636d70676569 : - (D_op_ldhu)? 56'h2020206c646875 : - (D_op_andi)? 56'h202020616e6469 : - (D_op_sth)? 56'h20202020737468 : - (D_op_bge)? 56'h20202020626765 : - (D_op_ldh)? 56'h202020206c6468 : - (D_op_cmplti)? 56'h20636d706c7469 : - (D_op_initda)? 56'h20696e69746461 : - (D_op_ori)? 56'h202020206f7269 : - (D_op_stw)? 56'h20202020737477 : - (D_op_blt)? 56'h20202020626c74 : - (D_op_ldw)? 56'h202020206c6477 : - (D_op_cmpnei)? 56'h20636d706e6569 : - (D_op_flushda)? 56'h666c7573686461 : - (D_op_xori)? 56'h202020786f7269 : - (D_op_bne)? 56'h20202020626e65 : - (D_op_cmpeqi)? 56'h20636d70657169 : - (D_op_ldbuio)? 56'h206c646275696f : - (D_op_muli)? 56'h2020206d756c69 : - (D_op_stbio)? 56'h2020737462696f : - (D_op_beq)? 56'h20202020626571 : - (D_op_ldbio)? 56'h20206c6462696f : - (D_op_cmpgeui)? 56'h636d7067657569 : - (D_op_ldhuio)? 56'h206c646875696f : - (D_op_andhi)? 56'h2020616e646869 : - (D_op_sthio)? 56'h2020737468696f : - (D_op_bgeu)? 56'h20202062676575 : - (D_op_ldhio)? 56'h20206c6468696f : - (D_op_cmpltui)? 56'h636d706c747569 : - (D_op_custom)? 56'h20637573746f6d : - (D_op_initd)? 56'h2020696e697464 : - (D_op_orhi)? 56'h2020206f726869 : - (D_op_stwio)? 56'h2020737477696f : - (D_op_bltu)? 56'h202020626c7475 : - (D_op_ldwio)? 56'h20206c6477696f : - (D_op_flushd)? 56'h20666c75736864 : - (D_op_xorhi)? 56'h2020786f726869 : - (D_op_eret)? 56'h20202065726574 : - (D_op_roli)? 56'h202020726f6c69 : - (D_op_rol)? 56'h20202020726f6c : - (D_op_flushp)? 56'h20666c75736870 : - (D_op_ret)? 56'h20202020726574 : - (D_op_nor)? 56'h202020206e6f72 : - (D_op_mulxuu)? 56'h206d756c787575 : - (D_op_cmpge)? 56'h2020636d706765 : - (D_op_bret)? 56'h20202062726574 : - (D_op_ror)? 56'h20202020726f72 : - (D_op_flushi)? 56'h20666c75736869 : - (D_op_jmp)? 56'h202020206a6d70 : - (D_op_and)? 56'h20202020616e64 : - (D_op_cmplt)? 56'h2020636d706c74 : - (D_op_slli)? 56'h202020736c6c69 : - (D_op_sll)? 56'h20202020736c6c : - (D_op_or)? 56'h20202020206f72 : - (D_op_mulxsu)? 56'h206d756c787375 : - (D_op_cmpne)? 56'h2020636d706e65 : - (D_op_srli)? 56'h20202073726c69 : - (D_op_srl)? 56'h2020202073726c : - (D_op_nextpc)? 56'h206e6578747063 : - (D_op_callr)? 56'h202063616c6c72 : - (D_op_xor)? 56'h20202020786f72 : - (D_op_mulxss)? 56'h206d756c787373 : - (D_op_cmpeq)? 56'h2020636d706571 : - (D_op_divu)? 56'h20202064697675 : - (D_op_div)? 56'h20202020646976 : - (D_op_rdctl)? 56'h2020726463746c : - (D_op_mul)? 56'h202020206d756c : - (D_op_cmpgeu)? 56'h20636d70676575 : - (D_op_initi)? 56'h2020696e697469 : - (D_op_trap)? 56'h20202074726170 : - (D_op_wrctl)? 56'h2020777263746c : - (D_op_cmpltu)? 56'h20636d706c7475 : - (D_op_add)? 56'h20202020616464 : - (D_op_break)? 56'h2020627265616b : - (D_op_hbreak)? 56'h2068627265616b : - (D_op_sync)? 56'h20202073796e63 : - (D_op_sub)? 56'h20202020737562 : - (D_op_srai)? 56'h20202073726169 : - (D_op_sra)? 56'h20202020737261 : - (D_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; + assign D_inst = (D_op_call)? 72'h202020202063616c6c : + (D_op_jmpi)? 72'h20202020206a6d7069 : + (D_op_ldbu)? 72'h20202020206c646275 : + (D_op_addi)? 72'h202020202061646469 : + (D_op_stb)? 72'h202020202020737462 : + (D_op_br)? 72'h202020202020206272 : + (D_op_ldb)? 72'h2020202020206c6462 : + (D_op_cmpgei)? 72'h202020636d70676569 : + (D_op_ldhu)? 72'h20202020206c646875 : + (D_op_andi)? 72'h2020202020616e6469 : + (D_op_sth)? 72'h202020202020737468 : + (D_op_bge)? 72'h202020202020626765 : + (D_op_ldh)? 72'h2020202020206c6468 : + (D_op_cmplti)? 72'h202020636d706c7469 : + (D_op_initda)? 72'h202020696e69746461 : + (D_op_ori)? 72'h2020202020206f7269 : + (D_op_stw)? 72'h202020202020737477 : + (D_op_blt)? 72'h202020202020626c74 : + (D_op_ldw)? 72'h2020202020206c6477 : + (D_op_cmpnei)? 72'h202020636d706e6569 : + (D_op_flushda)? 72'h2020666c7573686461 : + (D_op_xori)? 72'h2020202020786f7269 : + (D_op_bne)? 72'h202020202020626e65 : + (D_op_cmpeqi)? 72'h202020636d70657169 : + (D_op_ldbuio)? 72'h2020206c646275696f : + (D_op_muli)? 72'h20202020206d756c69 : + (D_op_stbio)? 72'h20202020737462696f : + (D_op_beq)? 72'h202020202020626571 : + (D_op_ldbio)? 72'h202020206c6462696f : + (D_op_cmpgeui)? 72'h2020636d7067657569 : + (D_op_ldhuio)? 72'h2020206c646875696f : + (D_op_andhi)? 72'h20202020616e646869 : + (D_op_sthio)? 72'h20202020737468696f : + (D_op_bgeu)? 72'h202020202062676575 : + (D_op_ldhio)? 72'h202020206c6468696f : + (D_op_cmpltui)? 72'h2020636d706c747569 : + (D_op_custom)? 72'h202020637573746f6d : + (D_op_initd)? 72'h20202020696e697464 : + (D_op_orhi)? 72'h20202020206f726869 : + (D_op_stwio)? 72'h20202020737477696f : + (D_op_bltu)? 72'h2020202020626c7475 : + (D_op_ldwio)? 72'h202020206c6477696f : + (D_op_flushd)? 72'h202020666c75736864 : + (D_op_xorhi)? 72'h20202020786f726869 : + (D_op_eret)? 72'h202020202065726574 : + (D_op_roli)? 72'h2020202020726f6c69 : + (D_op_rol)? 72'h202020202020726f6c : + (D_op_flushp)? 72'h202020666c75736870 : + (D_op_ret)? 72'h202020202020726574 : + (D_op_nor)? 72'h2020202020206e6f72 : + (D_op_mulxuu)? 72'h2020206d756c787575 : + (D_op_cmpge)? 72'h20202020636d706765 : + (D_op_bret)? 72'h202020202062726574 : + (D_op_ror)? 72'h202020202020726f72 : + (D_op_flushi)? 72'h202020666c75736869 : + (D_op_jmp)? 72'h2020202020206a6d70 : + (D_op_and)? 72'h202020202020616e64 : + (D_op_cmplt)? 72'h20202020636d706c74 : + (D_op_slli)? 72'h2020202020736c6c69 : + (D_op_sll)? 72'h202020202020736c6c : + (D_op_or)? 72'h202020202020206f72 : + (D_op_mulxsu)? 72'h2020206d756c787375 : + (D_op_cmpne)? 72'h20202020636d706e65 : + (D_op_srli)? 72'h202020202073726c69 : + (D_op_srl)? 72'h20202020202073726c : + (D_op_nextpc)? 72'h2020206e6578747063 : + (D_op_callr)? 72'h2020202063616c6c72 : + (D_op_xor)? 72'h202020202020786f72 : + (D_op_mulxss)? 72'h2020206d756c787373 : + (D_op_cmpeq)? 72'h20202020636d706571 : + (D_op_divu)? 72'h202020202064697675 : + (D_op_div)? 72'h202020202020646976 : + (D_op_rdctl)? 72'h20202020726463746c : + (D_op_mul)? 72'h2020202020206d756c : + (D_op_cmpgeu)? 72'h202020636d70676575 : + (D_op_initi)? 72'h20202020696e697469 : + (D_op_trap)? 72'h202020202074726170 : + (D_op_wrctl)? 72'h20202020777263746c : + (D_op_cmpltu)? 72'h202020636d706c7475 : + (D_op_add)? 72'h202020202020616464 : + (D_op_break)? 72'h20202020627265616b : + (D_op_hbreak)? 72'h20202068627265616b : + (D_op_sync)? 72'h202020202073796e63 : + (D_op_sub)? 72'h202020202020737562 : + (D_op_srai)? 72'h202020202073726169 : + (D_op_sra)? 72'h202020202020737261 : + (D_op_intr)? 72'h2020202020696e7472 : + (D_op_countones)? 72'h636f756e746f6e6573 : + 72'h202020202020424144; assign F_vinst = F_valid ? F_inst : {9{8'h2d}}; assign D_vinst = D_valid ? D_inst : {9{8'h2d}}; diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v index 17751ab..ed327c5 100644 --- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v +++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v @@ -110,6 +110,7 @@ wire D_op_cmpltu; wire D_op_cmpltui; wire D_op_cmpne; wire D_op_cmpnei; +wire D_op_countones; wire D_op_crst; wire D_op_custom; wire D_op_div; @@ -370,6 +371,7 @@ wire test_has_ended; assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst; assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst; assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst; + assign D_op_countones = D_op_custom & 1'b1; assign D_is_opx_inst = D_iw_op == 58; assign test_has_ended = 1'b0; diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v index 89434ce..4439f5b 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v @@ -7,62 +7,67 @@ `timescale 1 ps / 1 ps module niosII_mm_interconnect_0 ( - input wire clk_clk_clk, // clk_clk.clk - input wire cpu_reset_reset_bridge_in_reset_reset, // cpu_reset_reset_bridge_in_reset.reset - input wire [17:0] cpu_data_master_address, // cpu_data_master.address - output wire cpu_data_master_waitrequest, // .waitrequest - input wire [3:0] cpu_data_master_byteenable, // .byteenable - input wire cpu_data_master_read, // .read - output wire [31:0] cpu_data_master_readdata, // .readdata - input wire cpu_data_master_write, // .write - input wire [31:0] cpu_data_master_writedata, // .writedata - input wire cpu_data_master_debugaccess, // .debugaccess - input wire [17:0] cpu_instruction_master_address, // cpu_instruction_master.address - output wire cpu_instruction_master_waitrequest, // .waitrequest - input wire cpu_instruction_master_read, // .read - output wire [31:0] cpu_instruction_master_readdata, // .readdata - output wire [8:0] cpu_debug_mem_slave_address, // cpu_debug_mem_slave.address - output wire cpu_debug_mem_slave_write, // .write - output wire cpu_debug_mem_slave_read, // .read - input wire [31:0] cpu_debug_mem_slave_readdata, // .readdata - output wire [31:0] cpu_debug_mem_slave_writedata, // .writedata - output wire [3:0] cpu_debug_mem_slave_byteenable, // .byteenable - input wire cpu_debug_mem_slave_waitrequest, // .waitrequest - output wire cpu_debug_mem_slave_debugaccess, // .debugaccess - output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address - output wire jtag_uart_avalon_jtag_slave_write, // .write - output wire jtag_uart_avalon_jtag_slave_read, // .read - input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata - output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata - input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest - output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect - output wire [14:0] mem_s1_address, // mem_s1.address - output wire mem_s1_write, // .write - input wire [31:0] mem_s1_readdata, // .readdata - output wire [31:0] mem_s1_writedata, // .writedata - output wire [3:0] mem_s1_byteenable, // .byteenable - output wire mem_s1_chipselect, // .chipselect - output wire mem_s1_clken, // .clken - output wire [14:0] mem_s2_address, // mem_s2.address - output wire mem_s2_write, // .write - input wire [31:0] mem_s2_readdata, // .readdata - output wire [31:0] mem_s2_writedata, // .writedata - output wire [3:0] mem_s2_byteenable, // .byteenable - output wire mem_s2_chipselect, // .chipselect - output wire mem_s2_clken, // .clken - output wire [0:0] sem_ctl_slave_address, // sem_ctl_slave.address - output wire sem_ctl_slave_write, // .write - output wire sem_ctl_slave_read, // .read - input wire [31:0] sem_ctl_slave_readdata, // .readdata - output wire [31:0] sem_ctl_slave_writedata, // .writedata - output wire [3:0] sem_ram_slave_address, // sem_ram_slave.address - output wire sem_ram_slave_write, // .write - output wire [31:0] sem_ram_slave_writedata, // .writedata - output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address - output wire sys_clk_timer_s1_write, // .write - input wire [15:0] sys_clk_timer_s1_readdata, // .readdata - output wire [15:0] sys_clk_timer_s1_writedata, // .writedata - output wire sys_clk_timer_s1_chipselect // .chipselect + input wire clk_clk_clk, // clk_clk.clk + input wire cpu_reset_reset_bridge_in_reset_reset, // cpu_reset_reset_bridge_in_reset.reset + input wire [17:0] cpu_data_master_address, // cpu_data_master.address + output wire cpu_data_master_waitrequest, // .waitrequest + input wire [3:0] cpu_data_master_byteenable, // .byteenable + input wire cpu_data_master_read, // .read + output wire [31:0] cpu_data_master_readdata, // .readdata + input wire cpu_data_master_write, // .write + input wire [31:0] cpu_data_master_writedata, // .writedata + input wire cpu_data_master_debugaccess, // .debugaccess + input wire [17:0] cpu_instruction_master_address, // cpu_instruction_master.address + output wire cpu_instruction_master_waitrequest, // .waitrequest + input wire cpu_instruction_master_read, // .read + output wire [31:0] cpu_instruction_master_readdata, // .readdata + output wire [8:0] cpu_debug_mem_slave_address, // cpu_debug_mem_slave.address + output wire cpu_debug_mem_slave_write, // .write + output wire cpu_debug_mem_slave_read, // .read + input wire [31:0] cpu_debug_mem_slave_readdata, // .readdata + output wire [31:0] cpu_debug_mem_slave_writedata, // .writedata + output wire [3:0] cpu_debug_mem_slave_byteenable, // .byteenable + input wire cpu_debug_mem_slave_waitrequest, // .waitrequest + output wire cpu_debug_mem_slave_debugaccess, // .debugaccess + output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address + output wire jtag_uart_avalon_jtag_slave_write, // .write + output wire jtag_uart_avalon_jtag_slave_read, // .read + input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata + output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata + input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest + output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect + output wire [14:0] mem_s1_address, // mem_s1.address + output wire mem_s1_write, // .write + input wire [31:0] mem_s1_readdata, // .readdata + output wire [31:0] mem_s1_writedata, // .writedata + output wire [3:0] mem_s1_byteenable, // .byteenable + output wire mem_s1_chipselect, // .chipselect + output wire mem_s1_clken, // .clken + output wire [14:0] mem_s2_address, // mem_s2.address + output wire mem_s2_write, // .write + input wire [31:0] mem_s2_readdata, // .readdata + output wire [31:0] mem_s2_writedata, // .writedata + output wire [3:0] mem_s2_byteenable, // .byteenable + output wire mem_s2_chipselect, // .chipselect + output wire mem_s2_clken, // .clken + output wire [3:0] perf_counter_control_slave_address, // perf_counter_control_slave.address + output wire perf_counter_control_slave_write, // .write + input wire [31:0] perf_counter_control_slave_readdata, // .readdata + output wire [31:0] perf_counter_control_slave_writedata, // .writedata + output wire perf_counter_control_slave_begintransfer, // .begintransfer + output wire [0:0] sem_ctl_slave_address, // sem_ctl_slave.address + output wire sem_ctl_slave_write, // .write + output wire sem_ctl_slave_read, // .read + input wire [31:0] sem_ctl_slave_readdata, // .readdata + output wire [31:0] sem_ctl_slave_writedata, // .writedata + output wire [3:0] sem_ram_slave_address, // sem_ram_slave.address + output wire sem_ram_slave_write, // .write + output wire [31:0] sem_ram_slave_writedata, // .writedata + output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address + output wire sys_clk_timer_s1_write, // .write + input wire [15:0] sys_clk_timer_s1_readdata, // .readdata + output wire [15:0] sys_clk_timer_s1_writedata, // .writedata + output wire sys_clk_timer_s1_chipselect // .chipselect ); wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest @@ -79,7 +84,7 @@ module niosII_mm_interconnect_0 ( wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid wire [93:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready - wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel + wire [7:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest @@ -96,7 +101,7 @@ module niosII_mm_interconnect_0 ( wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid wire [93:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready - wire [6:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel + wire [7:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata @@ -123,9 +128,36 @@ module niosII_mm_interconnect_0 ( wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid wire [93:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data wire cmd_mux_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready - wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel + wire [7:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket + wire [31:0] perf_counter_control_slave_agent_m0_readdata; // perf_counter_control_slave_translator:uav_readdata -> perf_counter_control_slave_agent:m0_readdata + wire perf_counter_control_slave_agent_m0_waitrequest; // perf_counter_control_slave_translator:uav_waitrequest -> perf_counter_control_slave_agent:m0_waitrequest + wire perf_counter_control_slave_agent_m0_debugaccess; // perf_counter_control_slave_agent:m0_debugaccess -> perf_counter_control_slave_translator:uav_debugaccess + wire [17:0] perf_counter_control_slave_agent_m0_address; // perf_counter_control_slave_agent:m0_address -> perf_counter_control_slave_translator:uav_address + wire [3:0] perf_counter_control_slave_agent_m0_byteenable; // perf_counter_control_slave_agent:m0_byteenable -> perf_counter_control_slave_translator:uav_byteenable + wire perf_counter_control_slave_agent_m0_read; // perf_counter_control_slave_agent:m0_read -> perf_counter_control_slave_translator:uav_read + wire perf_counter_control_slave_agent_m0_readdatavalid; // perf_counter_control_slave_translator:uav_readdatavalid -> perf_counter_control_slave_agent:m0_readdatavalid + wire perf_counter_control_slave_agent_m0_lock; // perf_counter_control_slave_agent:m0_lock -> perf_counter_control_slave_translator:uav_lock + wire [31:0] perf_counter_control_slave_agent_m0_writedata; // perf_counter_control_slave_agent:m0_writedata -> perf_counter_control_slave_translator:uav_writedata + wire perf_counter_control_slave_agent_m0_write; // perf_counter_control_slave_agent:m0_write -> perf_counter_control_slave_translator:uav_write + wire [2:0] perf_counter_control_slave_agent_m0_burstcount; // perf_counter_control_slave_agent:m0_burstcount -> perf_counter_control_slave_translator:uav_burstcount + wire perf_counter_control_slave_agent_rf_source_valid; // perf_counter_control_slave_agent:rf_source_valid -> perf_counter_control_slave_agent_rsp_fifo:in_valid + wire [94:0] perf_counter_control_slave_agent_rf_source_data; // perf_counter_control_slave_agent:rf_source_data -> perf_counter_control_slave_agent_rsp_fifo:in_data + wire perf_counter_control_slave_agent_rf_source_ready; // perf_counter_control_slave_agent_rsp_fifo:in_ready -> perf_counter_control_slave_agent:rf_source_ready + wire perf_counter_control_slave_agent_rf_source_startofpacket; // perf_counter_control_slave_agent:rf_source_startofpacket -> perf_counter_control_slave_agent_rsp_fifo:in_startofpacket + wire perf_counter_control_slave_agent_rf_source_endofpacket; // perf_counter_control_slave_agent:rf_source_endofpacket -> perf_counter_control_slave_agent_rsp_fifo:in_endofpacket + wire perf_counter_control_slave_agent_rsp_fifo_out_valid; // perf_counter_control_slave_agent_rsp_fifo:out_valid -> perf_counter_control_slave_agent:rf_sink_valid + wire [94:0] perf_counter_control_slave_agent_rsp_fifo_out_data; // perf_counter_control_slave_agent_rsp_fifo:out_data -> perf_counter_control_slave_agent:rf_sink_data + wire perf_counter_control_slave_agent_rsp_fifo_out_ready; // perf_counter_control_slave_agent:rf_sink_ready -> perf_counter_control_slave_agent_rsp_fifo:out_ready + wire perf_counter_control_slave_agent_rsp_fifo_out_startofpacket; // perf_counter_control_slave_agent_rsp_fifo:out_startofpacket -> perf_counter_control_slave_agent:rf_sink_startofpacket + wire perf_counter_control_slave_agent_rsp_fifo_out_endofpacket; // perf_counter_control_slave_agent_rsp_fifo:out_endofpacket -> perf_counter_control_slave_agent:rf_sink_endofpacket + wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> perf_counter_control_slave_agent:cp_valid + wire [93:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> perf_counter_control_slave_agent:cp_data + wire cmd_mux_001_src_ready; // perf_counter_control_slave_agent:cp_ready -> cmd_mux_001:src_ready + wire [7:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> perf_counter_control_slave_agent:cp_channel + wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> perf_counter_control_slave_agent:cp_startofpacket + wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> perf_counter_control_slave_agent:cp_endofpacket wire [31:0] sem_ctl_slave_agent_m0_readdata; // sem_ctl_slave_translator:uav_readdata -> sem_ctl_slave_agent:m0_readdata wire sem_ctl_slave_agent_m0_waitrequest; // sem_ctl_slave_translator:uav_waitrequest -> sem_ctl_slave_agent:m0_waitrequest wire sem_ctl_slave_agent_m0_debugaccess; // sem_ctl_slave_agent:m0_debugaccess -> sem_ctl_slave_translator:uav_debugaccess @@ -147,12 +179,12 @@ module niosII_mm_interconnect_0 ( wire sem_ctl_slave_agent_rsp_fifo_out_ready; // sem_ctl_slave_agent:rf_sink_ready -> sem_ctl_slave_agent_rsp_fifo:out_ready wire sem_ctl_slave_agent_rsp_fifo_out_startofpacket; // sem_ctl_slave_agent_rsp_fifo:out_startofpacket -> sem_ctl_slave_agent:rf_sink_startofpacket wire sem_ctl_slave_agent_rsp_fifo_out_endofpacket; // sem_ctl_slave_agent_rsp_fifo:out_endofpacket -> sem_ctl_slave_agent:rf_sink_endofpacket - wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sem_ctl_slave_agent:cp_valid - wire [93:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sem_ctl_slave_agent:cp_data - wire cmd_mux_001_src_ready; // sem_ctl_slave_agent:cp_ready -> cmd_mux_001:src_ready - wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sem_ctl_slave_agent:cp_channel - wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sem_ctl_slave_agent:cp_startofpacket - wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sem_ctl_slave_agent:cp_endofpacket + wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sem_ctl_slave_agent:cp_valid + wire [93:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sem_ctl_slave_agent:cp_data + wire cmd_mux_002_src_ready; // sem_ctl_slave_agent:cp_ready -> cmd_mux_002:src_ready + wire [7:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sem_ctl_slave_agent:cp_channel + wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sem_ctl_slave_agent:cp_startofpacket + wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sem_ctl_slave_agent:cp_endofpacket wire [31:0] cpu_debug_mem_slave_agent_m0_readdata; // cpu_debug_mem_slave_translator:uav_readdata -> cpu_debug_mem_slave_agent:m0_readdata wire cpu_debug_mem_slave_agent_m0_waitrequest; // cpu_debug_mem_slave_translator:uav_waitrequest -> cpu_debug_mem_slave_agent:m0_waitrequest wire cpu_debug_mem_slave_agent_m0_debugaccess; // cpu_debug_mem_slave_agent:m0_debugaccess -> cpu_debug_mem_slave_translator:uav_debugaccess @@ -174,12 +206,12 @@ module niosII_mm_interconnect_0 ( wire cpu_debug_mem_slave_agent_rsp_fifo_out_ready; // cpu_debug_mem_slave_agent:rf_sink_ready -> cpu_debug_mem_slave_agent_rsp_fifo:out_ready wire cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // cpu_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> cpu_debug_mem_slave_agent:rf_sink_startofpacket wire cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // cpu_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> cpu_debug_mem_slave_agent:rf_sink_endofpacket - wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> cpu_debug_mem_slave_agent:cp_valid - wire [93:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> cpu_debug_mem_slave_agent:cp_data - wire cmd_mux_002_src_ready; // cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_002:src_ready - wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> cpu_debug_mem_slave_agent:cp_channel - wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> cpu_debug_mem_slave_agent:cp_startofpacket - wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> cpu_debug_mem_slave_agent:cp_endofpacket + wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> cpu_debug_mem_slave_agent:cp_valid + wire [93:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> cpu_debug_mem_slave_agent:cp_data + wire cmd_mux_003_src_ready; // cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_003:src_ready + wire [7:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> cpu_debug_mem_slave_agent:cp_channel + wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> cpu_debug_mem_slave_agent:cp_startofpacket + wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> cpu_debug_mem_slave_agent:cp_endofpacket wire [31:0] sem_ram_slave_agent_m0_readdata; // sem_ram_slave_translator:uav_readdata -> sem_ram_slave_agent:m0_readdata wire sem_ram_slave_agent_m0_waitrequest; // sem_ram_slave_translator:uav_waitrequest -> sem_ram_slave_agent:m0_waitrequest wire sem_ram_slave_agent_m0_debugaccess; // sem_ram_slave_agent:m0_debugaccess -> sem_ram_slave_translator:uav_debugaccess @@ -201,12 +233,12 @@ module niosII_mm_interconnect_0 ( wire sem_ram_slave_agent_rsp_fifo_out_ready; // sem_ram_slave_agent:rf_sink_ready -> sem_ram_slave_agent_rsp_fifo:out_ready wire sem_ram_slave_agent_rsp_fifo_out_startofpacket; // sem_ram_slave_agent_rsp_fifo:out_startofpacket -> sem_ram_slave_agent:rf_sink_startofpacket wire sem_ram_slave_agent_rsp_fifo_out_endofpacket; // sem_ram_slave_agent_rsp_fifo:out_endofpacket -> sem_ram_slave_agent:rf_sink_endofpacket - wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sem_ram_slave_agent:cp_valid - wire [93:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sem_ram_slave_agent:cp_data - wire cmd_mux_003_src_ready; // sem_ram_slave_agent:cp_ready -> cmd_mux_003:src_ready - wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sem_ram_slave_agent:cp_channel - wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sem_ram_slave_agent:cp_startofpacket - wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sem_ram_slave_agent:cp_endofpacket + wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> sem_ram_slave_agent:cp_valid + wire [93:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> sem_ram_slave_agent:cp_data + wire cmd_mux_004_src_ready; // sem_ram_slave_agent:cp_ready -> cmd_mux_004:src_ready + wire [7:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> sem_ram_slave_agent:cp_channel + wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> sem_ram_slave_agent:cp_startofpacket + wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> sem_ram_slave_agent:cp_endofpacket wire [31:0] sys_clk_timer_s1_agent_m0_readdata; // sys_clk_timer_s1_translator:uav_readdata -> sys_clk_timer_s1_agent:m0_readdata wire sys_clk_timer_s1_agent_m0_waitrequest; // sys_clk_timer_s1_translator:uav_waitrequest -> sys_clk_timer_s1_agent:m0_waitrequest wire sys_clk_timer_s1_agent_m0_debugaccess; // sys_clk_timer_s1_agent:m0_debugaccess -> sys_clk_timer_s1_translator:uav_debugaccess @@ -228,12 +260,12 @@ module niosII_mm_interconnect_0 ( wire sys_clk_timer_s1_agent_rsp_fifo_out_ready; // sys_clk_timer_s1_agent:rf_sink_ready -> sys_clk_timer_s1_agent_rsp_fifo:out_ready wire sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket; // sys_clk_timer_s1_agent_rsp_fifo:out_startofpacket -> sys_clk_timer_s1_agent:rf_sink_startofpacket wire sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket; // sys_clk_timer_s1_agent_rsp_fifo:out_endofpacket -> sys_clk_timer_s1_agent:rf_sink_endofpacket - wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> sys_clk_timer_s1_agent:cp_valid - wire [93:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> sys_clk_timer_s1_agent:cp_data - wire cmd_mux_004_src_ready; // sys_clk_timer_s1_agent:cp_ready -> cmd_mux_004:src_ready - wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> sys_clk_timer_s1_agent:cp_channel - wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> sys_clk_timer_s1_agent:cp_startofpacket - wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> sys_clk_timer_s1_agent:cp_endofpacket + wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sys_clk_timer_s1_agent:cp_valid + wire [93:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sys_clk_timer_s1_agent:cp_data + wire cmd_mux_005_src_ready; // sys_clk_timer_s1_agent:cp_ready -> cmd_mux_005:src_ready + wire [7:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sys_clk_timer_s1_agent:cp_channel + wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sys_clk_timer_s1_agent:cp_startofpacket + wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sys_clk_timer_s1_agent:cp_endofpacket wire [31:0] mem_s2_agent_m0_readdata; // mem_s2_translator:uav_readdata -> mem_s2_agent:m0_readdata wire mem_s2_agent_m0_waitrequest; // mem_s2_translator:uav_waitrequest -> mem_s2_agent:m0_waitrequest wire mem_s2_agent_m0_debugaccess; // mem_s2_agent:m0_debugaccess -> mem_s2_translator:uav_debugaccess @@ -255,12 +287,12 @@ module niosII_mm_interconnect_0 ( wire mem_s2_agent_rsp_fifo_out_ready; // mem_s2_agent:rf_sink_ready -> mem_s2_agent_rsp_fifo:out_ready wire mem_s2_agent_rsp_fifo_out_startofpacket; // mem_s2_agent_rsp_fifo:out_startofpacket -> mem_s2_agent:rf_sink_startofpacket wire mem_s2_agent_rsp_fifo_out_endofpacket; // mem_s2_agent_rsp_fifo:out_endofpacket -> mem_s2_agent:rf_sink_endofpacket - wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> mem_s2_agent:cp_valid - wire [93:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> mem_s2_agent:cp_data - wire cmd_mux_005_src_ready; // mem_s2_agent:cp_ready -> cmd_mux_005:src_ready - wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> mem_s2_agent:cp_channel - wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> mem_s2_agent:cp_startofpacket - wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> mem_s2_agent:cp_endofpacket + wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> mem_s2_agent:cp_valid + wire [93:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> mem_s2_agent:cp_data + wire cmd_mux_006_src_ready; // mem_s2_agent:cp_ready -> cmd_mux_006:src_ready + wire [7:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> mem_s2_agent:cp_channel + wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> mem_s2_agent:cp_startofpacket + wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> mem_s2_agent:cp_endofpacket wire [31:0] mem_s1_agent_m0_readdata; // mem_s1_translator:uav_readdata -> mem_s1_agent:m0_readdata wire mem_s1_agent_m0_waitrequest; // mem_s1_translator:uav_waitrequest -> mem_s1_agent:m0_waitrequest wire mem_s1_agent_m0_debugaccess; // mem_s1_agent:m0_debugaccess -> mem_s1_translator:uav_debugaccess @@ -282,12 +314,12 @@ module niosII_mm_interconnect_0 ( wire mem_s1_agent_rsp_fifo_out_ready; // mem_s1_agent:rf_sink_ready -> mem_s1_agent_rsp_fifo:out_ready wire mem_s1_agent_rsp_fifo_out_startofpacket; // mem_s1_agent_rsp_fifo:out_startofpacket -> mem_s1_agent:rf_sink_startofpacket wire mem_s1_agent_rsp_fifo_out_endofpacket; // mem_s1_agent_rsp_fifo:out_endofpacket -> mem_s1_agent:rf_sink_endofpacket - wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> mem_s1_agent:cp_valid - wire [93:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> mem_s1_agent:cp_data - wire cmd_mux_006_src_ready; // mem_s1_agent:cp_ready -> cmd_mux_006:src_ready - wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> mem_s1_agent:cp_channel - wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> mem_s1_agent:cp_startofpacket - wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> mem_s1_agent:cp_endofpacket + wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> mem_s1_agent:cp_valid + wire [93:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> mem_s1_agent:cp_data + wire cmd_mux_007_src_ready; // mem_s1_agent:cp_ready -> cmd_mux_007:src_ready + wire [7:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> mem_s1_agent:cp_channel + wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> mem_s1_agent:cp_startofpacket + wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> mem_s1_agent:cp_endofpacket wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid wire [93:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready @@ -296,7 +328,7 @@ module niosII_mm_interconnect_0 ( wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid wire [93:0] router_src_data; // router:src_data -> cmd_demux:sink_data wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready - wire [6:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel + wire [7:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid @@ -307,7 +339,7 @@ module niosII_mm_interconnect_0 ( wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid wire [93:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready - wire [6:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel + wire [7:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid @@ -318,171 +350,194 @@ module niosII_mm_interconnect_0 ( wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid wire [93:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready - wire [6:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel + wire [7:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket - wire sem_ctl_slave_agent_rp_valid; // sem_ctl_slave_agent:rp_valid -> router_003:sink_valid - wire [93:0] sem_ctl_slave_agent_rp_data; // sem_ctl_slave_agent:rp_data -> router_003:sink_data - wire sem_ctl_slave_agent_rp_ready; // router_003:sink_ready -> sem_ctl_slave_agent:rp_ready - wire sem_ctl_slave_agent_rp_startofpacket; // sem_ctl_slave_agent:rp_startofpacket -> router_003:sink_startofpacket - wire sem_ctl_slave_agent_rp_endofpacket; // sem_ctl_slave_agent:rp_endofpacket -> router_003:sink_endofpacket + wire perf_counter_control_slave_agent_rp_valid; // perf_counter_control_slave_agent:rp_valid -> router_003:sink_valid + wire [93:0] perf_counter_control_slave_agent_rp_data; // perf_counter_control_slave_agent:rp_data -> router_003:sink_data + wire perf_counter_control_slave_agent_rp_ready; // router_003:sink_ready -> perf_counter_control_slave_agent:rp_ready + wire perf_counter_control_slave_agent_rp_startofpacket; // perf_counter_control_slave_agent:rp_startofpacket -> router_003:sink_startofpacket + wire perf_counter_control_slave_agent_rp_endofpacket; // perf_counter_control_slave_agent:rp_endofpacket -> router_003:sink_endofpacket wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid wire [93:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready - wire [6:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel + wire [7:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket - wire cpu_debug_mem_slave_agent_rp_valid; // cpu_debug_mem_slave_agent:rp_valid -> router_004:sink_valid - wire [93:0] cpu_debug_mem_slave_agent_rp_data; // cpu_debug_mem_slave_agent:rp_data -> router_004:sink_data - wire cpu_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> cpu_debug_mem_slave_agent:rp_ready - wire cpu_debug_mem_slave_agent_rp_startofpacket; // cpu_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket - wire cpu_debug_mem_slave_agent_rp_endofpacket; // cpu_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket + wire sem_ctl_slave_agent_rp_valid; // sem_ctl_slave_agent:rp_valid -> router_004:sink_valid + wire [93:0] sem_ctl_slave_agent_rp_data; // sem_ctl_slave_agent:rp_data -> router_004:sink_data + wire sem_ctl_slave_agent_rp_ready; // router_004:sink_ready -> sem_ctl_slave_agent:rp_ready + wire sem_ctl_slave_agent_rp_startofpacket; // sem_ctl_slave_agent:rp_startofpacket -> router_004:sink_startofpacket + wire sem_ctl_slave_agent_rp_endofpacket; // sem_ctl_slave_agent:rp_endofpacket -> router_004:sink_endofpacket wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid wire [93:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready - wire [6:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel + wire [7:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket - wire sem_ram_slave_agent_rp_valid; // sem_ram_slave_agent:rp_valid -> router_005:sink_valid - wire [93:0] sem_ram_slave_agent_rp_data; // sem_ram_slave_agent:rp_data -> router_005:sink_data - wire sem_ram_slave_agent_rp_ready; // router_005:sink_ready -> sem_ram_slave_agent:rp_ready - wire sem_ram_slave_agent_rp_startofpacket; // sem_ram_slave_agent:rp_startofpacket -> router_005:sink_startofpacket - wire sem_ram_slave_agent_rp_endofpacket; // sem_ram_slave_agent:rp_endofpacket -> router_005:sink_endofpacket + wire cpu_debug_mem_slave_agent_rp_valid; // cpu_debug_mem_slave_agent:rp_valid -> router_005:sink_valid + wire [93:0] cpu_debug_mem_slave_agent_rp_data; // cpu_debug_mem_slave_agent:rp_data -> router_005:sink_data + wire cpu_debug_mem_slave_agent_rp_ready; // router_005:sink_ready -> cpu_debug_mem_slave_agent:rp_ready + wire cpu_debug_mem_slave_agent_rp_startofpacket; // cpu_debug_mem_slave_agent:rp_startofpacket -> router_005:sink_startofpacket + wire cpu_debug_mem_slave_agent_rp_endofpacket; // cpu_debug_mem_slave_agent:rp_endofpacket -> router_005:sink_endofpacket wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid wire [93:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready - wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel + wire [7:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket - wire sys_clk_timer_s1_agent_rp_valid; // sys_clk_timer_s1_agent:rp_valid -> router_006:sink_valid - wire [93:0] sys_clk_timer_s1_agent_rp_data; // sys_clk_timer_s1_agent:rp_data -> router_006:sink_data - wire sys_clk_timer_s1_agent_rp_ready; // router_006:sink_ready -> sys_clk_timer_s1_agent:rp_ready - wire sys_clk_timer_s1_agent_rp_startofpacket; // sys_clk_timer_s1_agent:rp_startofpacket -> router_006:sink_startofpacket - wire sys_clk_timer_s1_agent_rp_endofpacket; // sys_clk_timer_s1_agent:rp_endofpacket -> router_006:sink_endofpacket + wire sem_ram_slave_agent_rp_valid; // sem_ram_slave_agent:rp_valid -> router_006:sink_valid + wire [93:0] sem_ram_slave_agent_rp_data; // sem_ram_slave_agent:rp_data -> router_006:sink_data + wire sem_ram_slave_agent_rp_ready; // router_006:sink_ready -> sem_ram_slave_agent:rp_ready + wire sem_ram_slave_agent_rp_startofpacket; // sem_ram_slave_agent:rp_startofpacket -> router_006:sink_startofpacket + wire sem_ram_slave_agent_rp_endofpacket; // sem_ram_slave_agent:rp_endofpacket -> router_006:sink_endofpacket wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid wire [93:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready - wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel + wire [7:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket - wire mem_s2_agent_rp_valid; // mem_s2_agent:rp_valid -> router_007:sink_valid - wire [93:0] mem_s2_agent_rp_data; // mem_s2_agent:rp_data -> router_007:sink_data - wire mem_s2_agent_rp_ready; // router_007:sink_ready -> mem_s2_agent:rp_ready - wire mem_s2_agent_rp_startofpacket; // mem_s2_agent:rp_startofpacket -> router_007:sink_startofpacket - wire mem_s2_agent_rp_endofpacket; // mem_s2_agent:rp_endofpacket -> router_007:sink_endofpacket + wire sys_clk_timer_s1_agent_rp_valid; // sys_clk_timer_s1_agent:rp_valid -> router_007:sink_valid + wire [93:0] sys_clk_timer_s1_agent_rp_data; // sys_clk_timer_s1_agent:rp_data -> router_007:sink_data + wire sys_clk_timer_s1_agent_rp_ready; // router_007:sink_ready -> sys_clk_timer_s1_agent:rp_ready + wire sys_clk_timer_s1_agent_rp_startofpacket; // sys_clk_timer_s1_agent:rp_startofpacket -> router_007:sink_startofpacket + wire sys_clk_timer_s1_agent_rp_endofpacket; // sys_clk_timer_s1_agent:rp_endofpacket -> router_007:sink_endofpacket wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid wire [93:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready - wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel + wire [7:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket - wire mem_s1_agent_rp_valid; // mem_s1_agent:rp_valid -> router_008:sink_valid - wire [93:0] mem_s1_agent_rp_data; // mem_s1_agent:rp_data -> router_008:sink_data - wire mem_s1_agent_rp_ready; // router_008:sink_ready -> mem_s1_agent:rp_ready - wire mem_s1_agent_rp_startofpacket; // mem_s1_agent:rp_startofpacket -> router_008:sink_startofpacket - wire mem_s1_agent_rp_endofpacket; // mem_s1_agent:rp_endofpacket -> router_008:sink_endofpacket + wire mem_s2_agent_rp_valid; // mem_s2_agent:rp_valid -> router_008:sink_valid + wire [93:0] mem_s2_agent_rp_data; // mem_s2_agent:rp_data -> router_008:sink_data + wire mem_s2_agent_rp_ready; // router_008:sink_ready -> mem_s2_agent:rp_ready + wire mem_s2_agent_rp_startofpacket; // mem_s2_agent:rp_startofpacket -> router_008:sink_startofpacket + wire mem_s2_agent_rp_endofpacket; // mem_s2_agent:rp_endofpacket -> router_008:sink_endofpacket wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid wire [93:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready - wire [6:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel + wire [7:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket + wire mem_s1_agent_rp_valid; // mem_s1_agent:rp_valid -> router_009:sink_valid + wire [93:0] mem_s1_agent_rp_data; // mem_s1_agent:rp_data -> router_009:sink_data + wire mem_s1_agent_rp_ready; // router_009:sink_ready -> mem_s1_agent:rp_ready + wire mem_s1_agent_rp_startofpacket; // mem_s1_agent:rp_startofpacket -> router_009:sink_startofpacket + wire mem_s1_agent_rp_endofpacket; // mem_s1_agent:rp_endofpacket -> router_009:sink_endofpacket + wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid + wire [93:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data + wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready + wire [7:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel + wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket + wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid wire [93:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready - wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel + wire [7:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid wire [93:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready - wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel + wire [7:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid wire [93:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready - wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel + wire [7:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid wire [93:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready - wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel + wire [7:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid wire [93:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready - wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel + wire [7:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid wire [93:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready - wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel + wire [7:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket - wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_002:sink1_valid - wire [93:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_002:sink1_data - wire cmd_demux_001_src0_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src0_ready - wire [6:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_002:sink1_channel - wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_002:sink1_startofpacket - wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_002:sink1_endofpacket - wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_006:sink0_valid - wire [93:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_006:sink0_data - wire cmd_demux_001_src1_ready; // cmd_mux_006:sink0_ready -> cmd_demux_001:src1_ready - wire [6:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_006:sink0_channel - wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_006:sink0_startofpacket - wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_006:sink0_endofpacket + wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid + wire [93:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data + wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready + wire [7:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel + wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket + wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket + wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_003:sink1_valid + wire [93:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_003:sink1_data + wire cmd_demux_001_src0_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src0_ready + wire [7:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_003:sink1_channel + wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_003:sink1_startofpacket + wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_003:sink1_endofpacket + wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_007:sink0_valid + wire [93:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_007:sink0_data + wire cmd_demux_001_src1_ready; // cmd_mux_007:sink0_ready -> cmd_demux_001:src1_ready + wire [7:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_007:sink0_channel + wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_007:sink0_startofpacket + wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_007:sink0_endofpacket wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid wire [93:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready - wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel + wire [7:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid wire [93:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready - wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel + wire [7:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid wire [93:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready - wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel + wire [7:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket - wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink0_valid - wire [93:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink0_data - wire rsp_demux_002_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_002:src1_ready - wire [6:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink0_channel - wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink0_startofpacket - wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink0_endofpacket wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid wire [93:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready - wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel + wire [7:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket + wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink0_valid + wire [93:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink0_data + wire rsp_demux_003_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_003:src1_ready + wire [7:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink0_channel + wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink0_startofpacket + wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink0_endofpacket wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid wire [93:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready - wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel + wire [7:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid wire [93:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready - wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel + wire [7:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket - wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux_001:sink1_valid - wire [93:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux_001:sink1_data - wire rsp_demux_006_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_006:src0_ready - wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux_001:sink1_channel - wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux_001:sink1_startofpacket - wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux_001:sink1_endofpacket + wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid + wire [93:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data + wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready + wire [7:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel + wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket + wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket + wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux_001:sink1_valid + wire [93:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux_001:sink1_data + wire rsp_demux_007_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_007:src0_ready + wire [7:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux_001:sink1_channel + wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink1_startofpacket + wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink1_endofpacket wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready @@ -490,48 +545,55 @@ module niosII_mm_interconnect_0 ( wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data wire avalon_st_adapter_out_0_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error - wire sem_ctl_slave_agent_rdata_fifo_src_valid; // sem_ctl_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid - wire [33:0] sem_ctl_slave_agent_rdata_fifo_src_data; // sem_ctl_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data - wire sem_ctl_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> sem_ctl_slave_agent:rdata_fifo_src_ready - wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> sem_ctl_slave_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> sem_ctl_slave_agent:rdata_fifo_sink_data - wire avalon_st_adapter_001_out_0_ready; // sem_ctl_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready - wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> sem_ctl_slave_agent:rdata_fifo_sink_error - wire cpu_debug_mem_slave_agent_rdata_fifo_src_valid; // cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid - wire [33:0] cpu_debug_mem_slave_agent_rdata_fifo_src_data; // cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data - wire cpu_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> cpu_debug_mem_slave_agent:rdata_fifo_src_ready - wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> cpu_debug_mem_slave_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> cpu_debug_mem_slave_agent:rdata_fifo_sink_data - wire avalon_st_adapter_002_out_0_ready; // cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready - wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> cpu_debug_mem_slave_agent:rdata_fifo_sink_error - wire sem_ram_slave_agent_rdata_fifo_src_valid; // sem_ram_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid - wire [33:0] sem_ram_slave_agent_rdata_fifo_src_data; // sem_ram_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data - wire sem_ram_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sem_ram_slave_agent:rdata_fifo_src_ready - wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sem_ram_slave_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sem_ram_slave_agent:rdata_fifo_sink_data - wire avalon_st_adapter_003_out_0_ready; // sem_ram_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready - wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sem_ram_slave_agent:rdata_fifo_sink_error - wire sys_clk_timer_s1_agent_rdata_fifo_src_valid; // sys_clk_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid - wire [33:0] sys_clk_timer_s1_agent_rdata_fifo_src_data; // sys_clk_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data - wire sys_clk_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> sys_clk_timer_s1_agent:rdata_fifo_src_ready - wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> sys_clk_timer_s1_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> sys_clk_timer_s1_agent:rdata_fifo_sink_data - wire avalon_st_adapter_004_out_0_ready; // sys_clk_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready - wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> sys_clk_timer_s1_agent:rdata_fifo_sink_error - wire mem_s2_agent_rdata_fifo_src_valid; // mem_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid - wire [33:0] mem_s2_agent_rdata_fifo_src_data; // mem_s2_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data - wire mem_s2_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> mem_s2_agent:rdata_fifo_src_ready - wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> mem_s2_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> mem_s2_agent:rdata_fifo_sink_data - wire avalon_st_adapter_005_out_0_ready; // mem_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready - wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> mem_s2_agent:rdata_fifo_sink_error - wire mem_s1_agent_rdata_fifo_src_valid; // mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid - wire [33:0] mem_s1_agent_rdata_fifo_src_data; // mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data - wire mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> mem_s1_agent:rdata_fifo_src_ready - wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> mem_s1_agent:rdata_fifo_sink_valid - wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> mem_s1_agent:rdata_fifo_sink_data - wire avalon_st_adapter_006_out_0_ready; // mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready - wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> mem_s1_agent:rdata_fifo_sink_error + wire perf_counter_control_slave_agent_rdata_fifo_src_valid; // perf_counter_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid + wire [33:0] perf_counter_control_slave_agent_rdata_fifo_src_data; // perf_counter_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data + wire perf_counter_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> perf_counter_control_slave_agent:rdata_fifo_src_ready + wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> perf_counter_control_slave_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> perf_counter_control_slave_agent:rdata_fifo_sink_data + wire avalon_st_adapter_001_out_0_ready; // perf_counter_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready + wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> perf_counter_control_slave_agent:rdata_fifo_sink_error + wire sem_ctl_slave_agent_rdata_fifo_src_valid; // sem_ctl_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid + wire [33:0] sem_ctl_slave_agent_rdata_fifo_src_data; // sem_ctl_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data + wire sem_ctl_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sem_ctl_slave_agent:rdata_fifo_src_ready + wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sem_ctl_slave_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sem_ctl_slave_agent:rdata_fifo_sink_data + wire avalon_st_adapter_002_out_0_ready; // sem_ctl_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready + wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sem_ctl_slave_agent:rdata_fifo_sink_error + wire cpu_debug_mem_slave_agent_rdata_fifo_src_valid; // cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid + wire [33:0] cpu_debug_mem_slave_agent_rdata_fifo_src_data; // cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data + wire cpu_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> cpu_debug_mem_slave_agent:rdata_fifo_src_ready + wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> cpu_debug_mem_slave_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> cpu_debug_mem_slave_agent:rdata_fifo_sink_data + wire avalon_st_adapter_003_out_0_ready; // cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready + wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> cpu_debug_mem_slave_agent:rdata_fifo_sink_error + wire sem_ram_slave_agent_rdata_fifo_src_valid; // sem_ram_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid + wire [33:0] sem_ram_slave_agent_rdata_fifo_src_data; // sem_ram_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data + wire sem_ram_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> sem_ram_slave_agent:rdata_fifo_src_ready + wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> sem_ram_slave_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> sem_ram_slave_agent:rdata_fifo_sink_data + wire avalon_st_adapter_004_out_0_ready; // sem_ram_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready + wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> sem_ram_slave_agent:rdata_fifo_sink_error + wire sys_clk_timer_s1_agent_rdata_fifo_src_valid; // sys_clk_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid + wire [33:0] sys_clk_timer_s1_agent_rdata_fifo_src_data; // sys_clk_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data + wire sys_clk_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> sys_clk_timer_s1_agent:rdata_fifo_src_ready + wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> sys_clk_timer_s1_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> sys_clk_timer_s1_agent:rdata_fifo_sink_data + wire avalon_st_adapter_005_out_0_ready; // sys_clk_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready + wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> sys_clk_timer_s1_agent:rdata_fifo_sink_error + wire mem_s2_agent_rdata_fifo_src_valid; // mem_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid + wire [33:0] mem_s2_agent_rdata_fifo_src_data; // mem_s2_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data + wire mem_s2_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> mem_s2_agent:rdata_fifo_src_ready + wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> mem_s2_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> mem_s2_agent:rdata_fifo_sink_data + wire avalon_st_adapter_006_out_0_ready; // mem_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready + wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> mem_s2_agent:rdata_fifo_sink_error + wire mem_s1_agent_rdata_fifo_src_valid; // mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid + wire [33:0] mem_s1_agent_rdata_fifo_src_data; // mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data + wire mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> mem_s1_agent:rdata_fifo_src_ready + wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> mem_s1_agent:rdata_fifo_sink_valid + wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> mem_s1_agent:rdata_fifo_sink_data + wire avalon_st_adapter_007_out_0_ready; // mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready + wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> mem_s1_agent:rdata_fifo_sink_error altera_merlin_master_translator #( .AV_ADDRESS_W (18), @@ -717,6 +779,70 @@ module niosII_mm_interconnect_0 ( .av_writeresponsevalid (1'b0) // (terminated) ); + altera_merlin_slave_translator #( + .AV_ADDRESS_W (4), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (18), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) perf_counter_control_slave_translator ( + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (perf_counter_control_slave_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (perf_counter_control_slave_agent_m0_burstcount), // .burstcount + .uav_read (perf_counter_control_slave_agent_m0_read), // .read + .uav_write (perf_counter_control_slave_agent_m0_write), // .write + .uav_waitrequest (perf_counter_control_slave_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (perf_counter_control_slave_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (perf_counter_control_slave_agent_m0_byteenable), // .byteenable + .uav_readdata (perf_counter_control_slave_agent_m0_readdata), // .readdata + .uav_writedata (perf_counter_control_slave_agent_m0_writedata), // .writedata + .uav_lock (perf_counter_control_slave_agent_m0_lock), // .lock + .uav_debugaccess (perf_counter_control_slave_agent_m0_debugaccess), // .debugaccess + .av_address (perf_counter_control_slave_address), // avalon_anti_slave_0.address + .av_write (perf_counter_control_slave_write), // .write + .av_readdata (perf_counter_control_slave_readdata), // .readdata + .av_writedata (perf_counter_control_slave_writedata), // .writedata + .av_begintransfer (perf_counter_control_slave_begintransfer), // .begintransfer + .av_read (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), @@ -1144,7 +1270,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .ST_DATA_W (94), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (0), @@ -1225,7 +1351,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .ST_DATA_W (94), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (1), @@ -1293,7 +1419,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1418,7 +1544,132 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), + .ST_DATA_W (94), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .ECC_ENABLE (0) + ) perf_counter_control_slave_agent ( + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .m0_address (perf_counter_control_slave_agent_m0_address), // m0.address + .m0_burstcount (perf_counter_control_slave_agent_m0_burstcount), // .burstcount + .m0_byteenable (perf_counter_control_slave_agent_m0_byteenable), // .byteenable + .m0_debugaccess (perf_counter_control_slave_agent_m0_debugaccess), // .debugaccess + .m0_lock (perf_counter_control_slave_agent_m0_lock), // .lock + .m0_readdata (perf_counter_control_slave_agent_m0_readdata), // .readdata + .m0_readdatavalid (perf_counter_control_slave_agent_m0_readdatavalid), // .readdatavalid + .m0_read (perf_counter_control_slave_agent_m0_read), // .read + .m0_waitrequest (perf_counter_control_slave_agent_m0_waitrequest), // .waitrequest + .m0_writedata (perf_counter_control_slave_agent_m0_writedata), // .writedata + .m0_write (perf_counter_control_slave_agent_m0_write), // .write + .rp_endofpacket (perf_counter_control_slave_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (perf_counter_control_slave_agent_rp_ready), // .ready + .rp_valid (perf_counter_control_slave_agent_rp_valid), // .valid + .rp_data (perf_counter_control_slave_agent_rp_data), // .data + .rp_startofpacket (perf_counter_control_slave_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_mux_001_src_ready), // cp.ready + .cp_valid (cmd_mux_001_src_valid), // .valid + .cp_data (cmd_mux_001_src_data), // .data + .cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_001_src_channel), // .channel + .rf_sink_ready (perf_counter_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (perf_counter_control_slave_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (perf_counter_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (perf_counter_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (perf_counter_control_slave_agent_rsp_fifo_out_data), // .data + .rf_source_ready (perf_counter_control_slave_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (perf_counter_control_slave_agent_rf_source_valid), // .valid + .rf_source_startofpacket (perf_counter_control_slave_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (perf_counter_control_slave_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (perf_counter_control_slave_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error + .rdata_fifo_src_ready (perf_counter_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (perf_counter_control_slave_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (perf_counter_control_slave_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (95), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) perf_counter_control_slave_agent_rsp_fifo ( + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .in_data (perf_counter_control_slave_agent_rf_source_data), // in.data + .in_valid (perf_counter_control_slave_agent_rf_source_valid), // .valid + .in_ready (perf_counter_control_slave_agent_rf_source_ready), // .ready + .in_startofpacket (perf_counter_control_slave_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (perf_counter_control_slave_agent_rf_source_endofpacket), // .endofpacket + .out_data (perf_counter_control_slave_agent_rsp_fifo_out_data), // out.data + .out_valid (perf_counter_control_slave_agent_rsp_fifo_out_valid), // .valid + .out_ready (perf_counter_control_slave_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (perf_counter_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (perf_counter_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_ORI_BURST_SIZE_H (93), + .PKT_ORI_BURST_SIZE_L (91), + .PKT_RESPONSE_STATUS_H (90), + .PKT_RESPONSE_STATUS_L (89), + .PKT_BURST_SIZE_H (68), + .PKT_BURST_SIZE_L (66), + .PKT_TRANS_LOCK (58), + .PKT_BEGIN_BURST (73), + .PKT_PROTECTION_H (84), + .PKT_PROTECTION_L (82), + .PKT_BURSTWRAP_H (65), + .PKT_BURSTWRAP_L (63), + .PKT_BYTE_CNT_H (62), + .PKT_BYTE_CNT_L (60), + .PKT_ADDR_H (53), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (54), + .PKT_TRANS_POSTED (55), + .PKT_TRANS_WRITE (56), + .PKT_TRANS_READ (57), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (77), + .PKT_SRC_ID_L (75), + .PKT_DEST_ID_H (80), + .PKT_DEST_ID_L (78), + .PKT_SYMBOL_W (8), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1445,12 +1696,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (sem_ctl_slave_agent_rp_valid), // .valid .rp_data (sem_ctl_slave_agent_rp_data), // .data .rp_startofpacket (sem_ctl_slave_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_001_src_ready), // cp.ready - .cp_valid (cmd_mux_001_src_valid), // .valid - .cp_data (cmd_mux_001_src_data), // .data - .cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_001_src_channel), // .channel + .cp_ready (cmd_mux_002_src_ready), // cp.ready + .cp_valid (cmd_mux_002_src_valid), // .valid + .cp_data (cmd_mux_002_src_data), // .data + .cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_002_src_channel), // .channel .rf_sink_ready (sem_ctl_slave_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sem_ctl_slave_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sem_ctl_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -1461,10 +1712,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (sem_ctl_slave_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sem_ctl_slave_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sem_ctl_slave_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error .rdata_fifo_src_ready (sem_ctl_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sem_ctl_slave_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sem_ctl_slave_agent_rdata_fifo_src_data), // .data @@ -1543,7 +1794,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1570,12 +1821,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (cpu_debug_mem_slave_agent_rp_valid), // .valid .rp_data (cpu_debug_mem_slave_agent_rp_data), // .data .rp_startofpacket (cpu_debug_mem_slave_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_002_src_ready), // cp.ready - .cp_valid (cmd_mux_002_src_valid), // .valid - .cp_data (cmd_mux_002_src_data), // .data - .cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_002_src_channel), // .channel + .cp_ready (cmd_mux_003_src_ready), // cp.ready + .cp_valid (cmd_mux_003_src_valid), // .valid + .cp_data (cmd_mux_003_src_data), // .data + .cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_003_src_channel), // .channel .rf_sink_ready (cpu_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (cpu_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -1586,10 +1837,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (cpu_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (cpu_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (cpu_debug_mem_slave_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error .rdata_fifo_src_ready (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (cpu_debug_mem_slave_agent_rdata_fifo_src_data), // .data @@ -1668,7 +1919,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1695,12 +1946,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (sem_ram_slave_agent_rp_valid), // .valid .rp_data (sem_ram_slave_agent_rp_data), // .data .rp_startofpacket (sem_ram_slave_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_003_src_ready), // cp.ready - .cp_valid (cmd_mux_003_src_valid), // .valid - .cp_data (cmd_mux_003_src_data), // .data - .cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_003_src_channel), // .channel + .cp_ready (cmd_mux_004_src_ready), // cp.ready + .cp_valid (cmd_mux_004_src_valid), // .valid + .cp_data (cmd_mux_004_src_data), // .data + .cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_004_src_channel), // .channel .rf_sink_ready (sem_ram_slave_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sem_ram_slave_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sem_ram_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -1711,10 +1962,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (sem_ram_slave_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sem_ram_slave_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sem_ram_slave_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error .rdata_fifo_src_ready (sem_ram_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sem_ram_slave_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sem_ram_slave_agent_rdata_fifo_src_data), // .data @@ -1793,7 +2044,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1820,12 +2071,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (sys_clk_timer_s1_agent_rp_valid), // .valid .rp_data (sys_clk_timer_s1_agent_rp_data), // .data .rp_startofpacket (sys_clk_timer_s1_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_004_src_ready), // cp.ready - .cp_valid (cmd_mux_004_src_valid), // .valid - .cp_data (cmd_mux_004_src_data), // .data - .cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_004_src_channel), // .channel + .cp_ready (cmd_mux_005_src_ready), // cp.ready + .cp_valid (cmd_mux_005_src_valid), // .valid + .cp_data (cmd_mux_005_src_data), // .data + .cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_005_src_channel), // .channel .rf_sink_ready (sys_clk_timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sys_clk_timer_s1_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -1836,10 +2087,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (sys_clk_timer_s1_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sys_clk_timer_s1_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sys_clk_timer_s1_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error .rdata_fifo_src_ready (sys_clk_timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sys_clk_timer_s1_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sys_clk_timer_s1_agent_rdata_fifo_src_data), // .data @@ -1918,7 +2169,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -1945,12 +2196,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (mem_s2_agent_rp_valid), // .valid .rp_data (mem_s2_agent_rp_data), // .data .rp_startofpacket (mem_s2_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_005_src_ready), // cp.ready - .cp_valid (cmd_mux_005_src_valid), // .valid - .cp_data (cmd_mux_005_src_data), // .data - .cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_005_src_channel), // .channel + .cp_ready (cmd_mux_006_src_ready), // cp.ready + .cp_valid (cmd_mux_006_src_valid), // .valid + .cp_data (cmd_mux_006_src_data), // .data + .cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_006_src_channel), // .channel .rf_sink_ready (mem_s2_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (mem_s2_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (mem_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -1961,10 +2212,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (mem_s2_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (mem_s2_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (mem_s2_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error .rdata_fifo_src_ready (mem_s2_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (mem_s2_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (mem_s2_agent_rdata_fifo_src_data), // .data @@ -2043,7 +2294,7 @@ module niosII_mm_interconnect_0 ( .PKT_DEST_ID_H (80), .PKT_DEST_ID_L (78), .PKT_SYMBOL_W (8), - .ST_CHANNEL_W (7), + .ST_CHANNEL_W (8), .ST_DATA_W (94), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), @@ -2070,12 +2321,12 @@ module niosII_mm_interconnect_0 ( .rp_valid (mem_s1_agent_rp_valid), // .valid .rp_data (mem_s1_agent_rp_data), // .data .rp_startofpacket (mem_s1_agent_rp_startofpacket), // .startofpacket - .cp_ready (cmd_mux_006_src_ready), // cp.ready - .cp_valid (cmd_mux_006_src_valid), // .valid - .cp_data (cmd_mux_006_src_data), // .data - .cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket - .cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket - .cp_channel (cmd_mux_006_src_channel), // .channel + .cp_ready (cmd_mux_007_src_ready), // cp.ready + .cp_valid (cmd_mux_007_src_valid), // .valid + .cp_data (cmd_mux_007_src_data), // .data + .cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket + .cp_channel (cmd_mux_007_src_channel), // .channel .rf_sink_ready (mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (mem_s1_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket @@ -2086,10 +2337,10 @@ module niosII_mm_interconnect_0 ( .rf_source_startofpacket (mem_s1_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (mem_s1_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (mem_s1_agent_rf_source_data), // .data - .rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready - .rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid - .rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data - .rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error + .rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid + .rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data + .rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error .rdata_fifo_src_ready (mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (mem_s1_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (mem_s1_agent_rdata_fifo_src_data), // .data @@ -2187,6 +2438,22 @@ module niosII_mm_interconnect_0 ( ); niosII_mm_interconnect_0_router_002 router_003 ( + .sink_ready (perf_counter_control_slave_agent_rp_ready), // sink.ready + .sink_valid (perf_counter_control_slave_agent_rp_valid), // .valid + .sink_data (perf_counter_control_slave_agent_rp_data), // .data + .sink_startofpacket (perf_counter_control_slave_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (perf_counter_control_slave_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_003_src_ready), // src.ready + .src_valid (router_003_src_valid), // .valid + .src_data (router_003_src_data), // .data + .src_channel (router_003_src_channel), // .channel + .src_startofpacket (router_003_src_startofpacket), // .startofpacket + .src_endofpacket (router_003_src_endofpacket) // .endofpacket + ); + + niosII_mm_interconnect_0_router_002 router_004 ( .sink_ready (sem_ctl_slave_agent_rp_ready), // sink.ready .sink_valid (sem_ctl_slave_agent_rp_valid), // .valid .sink_data (sem_ctl_slave_agent_rp_data), // .data @@ -2194,15 +2461,15 @@ module niosII_mm_interconnect_0 ( .sink_endofpacket (sem_ctl_slave_agent_rp_endofpacket), // .endofpacket .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset - .src_ready (router_003_src_ready), // src.ready - .src_valid (router_003_src_valid), // .valid - .src_data (router_003_src_data), // .data - .src_channel (router_003_src_channel), // .channel - .src_startofpacket (router_003_src_startofpacket), // .startofpacket - .src_endofpacket (router_003_src_endofpacket) // .endofpacket + .src_ready (router_004_src_ready), // src.ready + .src_valid (router_004_src_valid), // .valid + .src_data (router_004_src_data), // .data + .src_channel (router_004_src_channel), // .channel + .src_startofpacket (router_004_src_startofpacket), // .startofpacket + .src_endofpacket (router_004_src_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_router_004 router_004 ( + niosII_mm_interconnect_0_router_005 router_005 ( .sink_ready (cpu_debug_mem_slave_agent_rp_ready), // sink.ready .sink_valid (cpu_debug_mem_slave_agent_rp_valid), // .valid .sink_data (cpu_debug_mem_slave_agent_rp_data), // .data @@ -2210,15 +2477,15 @@ module niosII_mm_interconnect_0 ( .sink_endofpacket (cpu_debug_mem_slave_agent_rp_endofpacket), // .endofpacket .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset - .src_ready (router_004_src_ready), // src.ready - .src_valid (router_004_src_valid), // .valid - .src_data (router_004_src_data), // .data - .src_channel (router_004_src_channel), // .channel - .src_startofpacket (router_004_src_startofpacket), // .startofpacket - .src_endofpacket (router_004_src_endofpacket) // .endofpacket + .src_ready (router_005_src_ready), // src.ready + .src_valid (router_005_src_valid), // .valid + .src_data (router_005_src_data), // .data + .src_channel (router_005_src_channel), // .channel + .src_startofpacket (router_005_src_startofpacket), // .startofpacket + .src_endofpacket (router_005_src_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_router_002 router_005 ( + niosII_mm_interconnect_0_router_002 router_006 ( .sink_ready (sem_ram_slave_agent_rp_ready), // sink.ready .sink_valid (sem_ram_slave_agent_rp_valid), // .valid .sink_data (sem_ram_slave_agent_rp_data), // .data @@ -2226,15 +2493,15 @@ module niosII_mm_interconnect_0 ( .sink_endofpacket (sem_ram_slave_agent_rp_endofpacket), // .endofpacket .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset - .src_ready (router_005_src_ready), // src.ready - .src_valid (router_005_src_valid), // .valid - .src_data (router_005_src_data), // .data - .src_channel (router_005_src_channel), // .channel - .src_startofpacket (router_005_src_startofpacket), // .startofpacket - .src_endofpacket (router_005_src_endofpacket) // .endofpacket + .src_ready (router_006_src_ready), // src.ready + .src_valid (router_006_src_valid), // .valid + .src_data (router_006_src_data), // .data + .src_channel (router_006_src_channel), // .channel + .src_startofpacket (router_006_src_startofpacket), // .startofpacket + .src_endofpacket (router_006_src_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_router_002 router_006 ( + niosII_mm_interconnect_0_router_002 router_007 ( .sink_ready (sys_clk_timer_s1_agent_rp_ready), // sink.ready .sink_valid (sys_clk_timer_s1_agent_rp_valid), // .valid .sink_data (sys_clk_timer_s1_agent_rp_data), // .data @@ -2242,15 +2509,15 @@ module niosII_mm_interconnect_0 ( .sink_endofpacket (sys_clk_timer_s1_agent_rp_endofpacket), // .endofpacket .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset - .src_ready (router_006_src_ready), // src.ready - .src_valid (router_006_src_valid), // .valid - .src_data (router_006_src_data), // .data - .src_channel (router_006_src_channel), // .channel - .src_startofpacket (router_006_src_startofpacket), // .startofpacket - .src_endofpacket (router_006_src_endofpacket) // .endofpacket + .src_ready (router_007_src_ready), // src.ready + .src_valid (router_007_src_valid), // .valid + .src_data (router_007_src_data), // .data + .src_channel (router_007_src_channel), // .channel + .src_startofpacket (router_007_src_startofpacket), // .startofpacket + .src_endofpacket (router_007_src_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_router_002 router_007 ( + niosII_mm_interconnect_0_router_002 router_008 ( .sink_ready (mem_s2_agent_rp_ready), // sink.ready .sink_valid (mem_s2_agent_rp_valid), // .valid .sink_data (mem_s2_agent_rp_data), // .data @@ -2258,22 +2525,6 @@ module niosII_mm_interconnect_0 ( .sink_endofpacket (mem_s2_agent_rp_endofpacket), // .endofpacket .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset - .src_ready (router_007_src_ready), // src.ready - .src_valid (router_007_src_valid), // .valid - .src_data (router_007_src_data), // .data - .src_channel (router_007_src_channel), // .channel - .src_startofpacket (router_007_src_startofpacket), // .startofpacket - .src_endofpacket (router_007_src_endofpacket) // .endofpacket - ); - - niosII_mm_interconnect_0_router_008 router_008 ( - .sink_ready (mem_s1_agent_rp_ready), // sink.ready - .sink_valid (mem_s1_agent_rp_valid), // .valid - .sink_data (mem_s1_agent_rp_data), // .data - .sink_startofpacket (mem_s1_agent_rp_startofpacket), // .startofpacket - .sink_endofpacket (mem_s1_agent_rp_endofpacket), // .endofpacket - .clk (clk_clk_clk), // clk.clk - .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset .src_ready (router_008_src_ready), // src.ready .src_valid (router_008_src_valid), // .valid .src_data (router_008_src_data), // .data @@ -2282,6 +2533,22 @@ module niosII_mm_interconnect_0 ( .src_endofpacket (router_008_src_endofpacket) // .endofpacket ); + niosII_mm_interconnect_0_router_009 router_009 ( + .sink_ready (mem_s1_agent_rp_ready), // sink.ready + .sink_valid (mem_s1_agent_rp_valid), // .valid + .sink_data (mem_s1_agent_rp_data), // .data + .sink_startofpacket (mem_s1_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (mem_s1_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (router_009_src_ready), // src.ready + .src_valid (router_009_src_valid), // .valid + .src_data (router_009_src_data), // .data + .src_channel (router_009_src_channel), // .channel + .src_startofpacket (router_009_src_startofpacket), // .startofpacket + .src_endofpacket (router_009_src_endofpacket) // .endofpacket + ); + niosII_mm_interconnect_0_cmd_demux cmd_demux ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset @@ -2326,7 +2593,13 @@ module niosII_mm_interconnect_0 ( .src5_data (cmd_demux_src5_data), // .data .src5_channel (cmd_demux_src5_channel), // .channel .src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket - .src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket + .src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket + .src6_ready (cmd_demux_src6_ready), // src6.ready + .src6_valid (cmd_demux_src6_valid), // .valid + .src6_data (cmd_demux_src6_data), // .data + .src6_channel (cmd_demux_src6_channel), // .channel + .src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket + .src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket ); niosII_mm_interconnect_0_cmd_demux_001 cmd_demux_001 ( @@ -2386,7 +2659,7 @@ module niosII_mm_interconnect_0 ( .sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_cmd_mux_002 cmd_mux_002 ( + niosII_mm_interconnect_0_cmd_mux cmd_mux_002 ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset .src_ready (cmd_mux_002_src_ready), // src.ready @@ -2400,16 +2673,10 @@ module niosII_mm_interconnect_0 ( .sink0_channel (cmd_demux_src2_channel), // .channel .sink0_data (cmd_demux_src2_data), // .data .sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket - .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready - .sink1_valid (cmd_demux_001_src0_valid), // .valid - .sink1_channel (cmd_demux_001_src0_channel), // .channel - .sink1_data (cmd_demux_001_src0_data), // .data - .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket - .sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket + .sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_cmd_mux cmd_mux_003 ( + niosII_mm_interconnect_0_cmd_mux_003 cmd_mux_003 ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset .src_ready (cmd_mux_003_src_ready), // src.ready @@ -2423,7 +2690,13 @@ module niosII_mm_interconnect_0 ( .sink0_channel (cmd_demux_src3_channel), // .channel .sink0_data (cmd_demux_src3_data), // .data .sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket - .sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket + .sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket + .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready + .sink1_valid (cmd_demux_001_src0_valid), // .valid + .sink1_channel (cmd_demux_001_src0_channel), // .channel + .sink1_data (cmd_demux_001_src0_data), // .data + .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket ); niosII_mm_interconnect_0_cmd_mux cmd_mux_004 ( @@ -2469,6 +2742,23 @@ module niosII_mm_interconnect_0 ( .src_channel (cmd_mux_006_src_channel), // .channel .src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket .src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket + .sink0_ready (cmd_demux_src6_ready), // sink0.ready + .sink0_valid (cmd_demux_src6_valid), // .valid + .sink0_channel (cmd_demux_src6_channel), // .channel + .sink0_data (cmd_demux_src6_data), // .data + .sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket + ); + + niosII_mm_interconnect_0_cmd_mux cmd_mux_007 ( + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .src_ready (cmd_mux_007_src_ready), // src.ready + .src_valid (cmd_mux_007_src_valid), // .valid + .src_data (cmd_mux_007_src_data), // .data + .src_channel (cmd_mux_007_src_channel), // .channel + .src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket .sink0_ready (cmd_demux_001_src1_ready), // sink0.ready .sink0_valid (cmd_demux_001_src1_valid), // .valid .sink0_channel (cmd_demux_001_src1_channel), // .channel @@ -2511,7 +2801,7 @@ module niosII_mm_interconnect_0 ( .src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_cmd_demux_001 rsp_demux_002 ( + niosII_mm_interconnect_0_rsp_demux rsp_demux_002 ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset .sink_ready (router_004_src_ready), // sink.ready @@ -2525,16 +2815,10 @@ module niosII_mm_interconnect_0 ( .src0_data (rsp_demux_002_src0_data), // .data .src0_channel (rsp_demux_002_src0_channel), // .channel .src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket - .src1_ready (rsp_demux_002_src1_ready), // src1.ready - .src1_valid (rsp_demux_002_src1_valid), // .valid - .src1_data (rsp_demux_002_src1_data), // .data - .src1_channel (rsp_demux_002_src1_channel), // .channel - .src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket - .src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket + .src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket ); - niosII_mm_interconnect_0_rsp_demux rsp_demux_003 ( + niosII_mm_interconnect_0_cmd_demux_001 rsp_demux_003 ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset .sink_ready (router_005_src_ready), // sink.ready @@ -2548,7 +2832,13 @@ module niosII_mm_interconnect_0 ( .src0_data (rsp_demux_003_src0_data), // .data .src0_channel (rsp_demux_003_src0_channel), // .channel .src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket - .src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket + .src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket + .src1_ready (rsp_demux_003_src1_ready), // src1.ready + .src1_valid (rsp_demux_003_src1_valid), // .valid + .src1_data (rsp_demux_003_src1_data), // .data + .src1_channel (rsp_demux_003_src1_channel), // .channel + .src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket ); niosII_mm_interconnect_0_rsp_demux rsp_demux_004 ( @@ -2602,6 +2892,23 @@ module niosII_mm_interconnect_0 ( .src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket ); + niosII_mm_interconnect_0_rsp_demux rsp_demux_007 ( + .clk (clk_clk_clk), // clk.clk + .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset + .sink_ready (router_009_src_ready), // sink.ready + .sink_channel (router_009_src_channel), // .channel + .sink_data (router_009_src_data), // .data + .sink_startofpacket (router_009_src_startofpacket), // .startofpacket + .sink_endofpacket (router_009_src_endofpacket), // .endofpacket + .sink_valid (router_009_src_valid), // .valid + .src0_ready (rsp_demux_007_src0_ready), // src0.ready + .src0_valid (rsp_demux_007_src0_valid), // .valid + .src0_data (rsp_demux_007_src0_data), // .data + .src0_channel (rsp_demux_007_src0_channel), // .channel + .src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket + ); + niosII_mm_interconnect_0_rsp_mux rsp_mux ( .clk (clk_clk_clk), // clk.clk .reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset @@ -2646,7 +2953,13 @@ module niosII_mm_interconnect_0 ( .sink5_channel (rsp_demux_005_src0_channel), // .channel .sink5_data (rsp_demux_005_src0_data), // .data .sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket - .sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket + .sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket + .sink6_ready (rsp_demux_006_src0_ready), // sink6.ready + .sink6_valid (rsp_demux_006_src0_valid), // .valid + .sink6_channel (rsp_demux_006_src0_channel), // .channel + .sink6_data (rsp_demux_006_src0_data), // .data + .sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket + .sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket ); niosII_mm_interconnect_0_rsp_mux_001 rsp_mux_001 ( @@ -2658,18 +2971,18 @@ module niosII_mm_interconnect_0 ( .src_channel (rsp_mux_001_src_channel), // .channel .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket - .sink0_ready (rsp_demux_002_src1_ready), // sink0.ready - .sink0_valid (rsp_demux_002_src1_valid), // .valid - .sink0_channel (rsp_demux_002_src1_channel), // .channel - .sink0_data (rsp_demux_002_src1_data), // .data - .sink0_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket - .sink0_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket - .sink1_ready (rsp_demux_006_src0_ready), // sink1.ready - .sink1_valid (rsp_demux_006_src0_valid), // .valid - .sink1_channel (rsp_demux_006_src0_channel), // .channel - .sink1_data (rsp_demux_006_src0_data), // .data - .sink1_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket - .sink1_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket + .sink0_ready (rsp_demux_003_src1_ready), // sink0.ready + .sink0_valid (rsp_demux_003_src1_valid), // .valid + .sink0_channel (rsp_demux_003_src1_channel), // .channel + .sink0_data (rsp_demux_003_src1_data), // .data + .sink0_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket + .sink1_ready (rsp_demux_007_src0_ready), // sink1.ready + .sink1_valid (rsp_demux_007_src0_valid), // .valid + .sink1_channel (rsp_demux_007_src0_channel), // .channel + .sink1_data (rsp_demux_007_src0_data), // .data + .sink1_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2719,15 +3032,15 @@ module niosII_mm_interconnect_0 ( .outUseReady (1), .outReadyLatency (0) ) avalon_st_adapter_001 ( - .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk - .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (sem_ctl_slave_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (sem_ctl_slave_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (sem_ctl_slave_agent_rdata_fifo_src_ready), // .ready - .out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data - .out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid - .out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready - .out_0_error (avalon_st_adapter_001_out_0_error) // .error + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (perf_counter_control_slave_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (perf_counter_control_slave_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (perf_counter_control_slave_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_001_out_0_error) // .error ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2748,15 +3061,15 @@ module niosII_mm_interconnect_0 ( .outUseReady (1), .outReadyLatency (0) ) avalon_st_adapter_002 ( - .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk - .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (cpu_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready - .out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data - .out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid - .out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready - .out_0_error (avalon_st_adapter_002_out_0_error) // .error + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sem_ctl_slave_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sem_ctl_slave_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sem_ctl_slave_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_002_out_0_error) // .error ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2777,15 +3090,15 @@ module niosII_mm_interconnect_0 ( .outUseReady (1), .outReadyLatency (0) ) avalon_st_adapter_003 ( - .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk - .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (sem_ram_slave_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (sem_ram_slave_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (sem_ram_slave_agent_rdata_fifo_src_ready), // .ready - .out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data - .out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid - .out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready - .out_0_error (avalon_st_adapter_003_out_0_error) // .error + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (cpu_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_003_out_0_error) // .error ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2806,15 +3119,15 @@ module niosII_mm_interconnect_0 ( .outUseReady (1), .outReadyLatency (0) ) avalon_st_adapter_004 ( - .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk - .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (sys_clk_timer_s1_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (sys_clk_timer_s1_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (sys_clk_timer_s1_agent_rdata_fifo_src_ready), // .ready - .out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data - .out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid - .out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready - .out_0_error (avalon_st_adapter_004_out_0_error) // .error + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sem_ram_slave_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sem_ram_slave_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sem_ram_slave_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_004_out_0_error) // .error ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2835,15 +3148,15 @@ module niosII_mm_interconnect_0 ( .outUseReady (1), .outReadyLatency (0) ) avalon_st_adapter_005 ( - .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk - .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (mem_s2_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (mem_s2_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (mem_s2_agent_rdata_fifo_src_ready), // .ready - .out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data - .out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid - .out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready - .out_0_error (avalon_st_adapter_005_out_0_error) // .error + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (sys_clk_timer_s1_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (sys_clk_timer_s1_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (sys_clk_timer_s1_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_005_out_0_error) // .error ); niosII_mm_interconnect_0_avalon_st_adapter #( @@ -2866,13 +3179,42 @@ module niosII_mm_interconnect_0 ( ) avalon_st_adapter_006 ( .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset - .in_0_data (mem_s1_agent_rdata_fifo_src_data), // in_0.data - .in_0_valid (mem_s1_agent_rdata_fifo_src_valid), // .valid - .in_0_ready (mem_s1_agent_rdata_fifo_src_ready), // .ready + .in_0_data (mem_s2_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (mem_s2_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (mem_s2_agent_rdata_fifo_src_ready), // .ready .out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data .out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid .out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready .out_0_error (avalon_st_adapter_006_out_0_error) // .error ); + niosII_mm_interconnect_0_avalon_st_adapter #( + .inBitsPerSymbol (34), + .inUsePackets (0), + .inDataWidth (34), + .inChannelWidth (0), + .inErrorWidth (0), + .inUseEmptyPort (0), + .inUseValid (1), + .inUseReady (1), + .inReadyLatency (0), + .outDataWidth (34), + .outChannelWidth (0), + .outErrorWidth (1), + .outUseEmptyPort (0), + .outUseValid (1), + .outUseReady (1), + .outReadyLatency (0) + ) avalon_st_adapter_007 ( + .in_clk_0_clk (clk_clk_clk), // in_clk_0.clk + .in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset + .in_0_data (mem_s1_agent_rdata_fifo_src_data), // in_0.data + .in_0_valid (mem_s1_agent_rdata_fifo_src_valid), // .valid + .in_0_ready (mem_s1_agent_rdata_fifo_src_ready), // .ready + .out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data + .out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid + .out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready + .out_0_error (avalon_st_adapter_007_out_0_error) // .error + ); + endmodule diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv index 14c3fcd..80fa956 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv @@ -29,8 +29,8 @@ // Generation parameters: // output_name: niosII_mm_interconnect_0_cmd_demux // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 -// NUM_OUTPUTS: 6 +// ST_CHANNEL_W: 8 +// NUM_OUTPUTS: 7 // VALID_WIDTH: 1 // ------------------------------------------ @@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux // ------------------- input [1-1 : 0] sink_valid, input [94-1 : 0] sink_data, // ST_DATA_W=94 - input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7 + input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8 input sink_startofpacket, input sink_endofpacket, output sink_ready, @@ -57,46 +57,53 @@ module niosII_mm_interconnect_0_cmd_demux // ------------------- output reg src0_valid, output reg [94-1 : 0] src0_data, // ST_DATA_W=94 - output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8 output reg src0_startofpacket, output reg src0_endofpacket, input src0_ready, output reg src1_valid, output reg [94-1 : 0] src1_data, // ST_DATA_W=94 - output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src1_channel, // ST_CHANNEL_W=8 output reg src1_startofpacket, output reg src1_endofpacket, input src1_ready, output reg src2_valid, output reg [94-1 : 0] src2_data, // ST_DATA_W=94 - output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src2_channel, // ST_CHANNEL_W=8 output reg src2_startofpacket, output reg src2_endofpacket, input src2_ready, output reg src3_valid, output reg [94-1 : 0] src3_data, // ST_DATA_W=94 - output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src3_channel, // ST_CHANNEL_W=8 output reg src3_startofpacket, output reg src3_endofpacket, input src3_ready, output reg src4_valid, output reg [94-1 : 0] src4_data, // ST_DATA_W=94 - output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src4_channel, // ST_CHANNEL_W=8 output reg src4_startofpacket, output reg src4_endofpacket, input src4_ready, output reg src5_valid, output reg [94-1 : 0] src5_data, // ST_DATA_W=94 - output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src5_channel, // ST_CHANNEL_W=8 output reg src5_startofpacket, output reg src5_endofpacket, input src5_ready, + output reg src6_valid, + output reg [94-1 : 0] src6_data, // ST_DATA_W=94 + output reg [8-1 : 0] src6_channel, // ST_CHANNEL_W=8 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + // ------------------- // Clock & Reset @@ -108,7 +115,7 @@ module niosII_mm_interconnect_0_cmd_demux ); - localparam NUM_OUTPUTS = 6; + localparam NUM_OUTPUTS = 7; wire [NUM_OUTPUTS - 1 : 0] ready_vector; // ------------------- @@ -157,6 +164,13 @@ module niosII_mm_interconnect_0_cmd_demux src5_valid = sink_channel[5] && sink_valid; + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid; + end // ------------------- @@ -168,6 +182,7 @@ module niosII_mm_interconnect_0_cmd_demux assign ready_vector[3] = src3_ready; assign ready_vector[4] = src4_ready; assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv index 34b17f2..d596b8f 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv @@ -29,7 +29,7 @@ // Generation parameters: // output_name: niosII_mm_interconnect_0_cmd_demux_001 // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 +// ST_CHANNEL_W: 8 // NUM_OUTPUTS: 2 // VALID_WIDTH: 1 // ------------------------------------------ @@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux_001 // ------------------- input [1-1 : 0] sink_valid, input [94-1 : 0] sink_data, // ST_DATA_W=94 - input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7 + input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8 input sink_startofpacket, input sink_endofpacket, output sink_ready, @@ -57,14 +57,14 @@ module niosII_mm_interconnect_0_cmd_demux_001 // ------------------- output reg src0_valid, output reg [94-1 : 0] src0_data, // ST_DATA_W=94 - output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8 output reg src0_startofpacket, output reg src0_endofpacket, input src0_ready, output reg src1_valid, output reg [94-1 : 0] src1_data, // ST_DATA_W=94 - output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src1_channel, // ST_CHANNEL_W=8 output reg src1_startofpacket, output reg src1_endofpacket, input src1_ready, @@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001 assign ready_vector[0] = src0_ready; assign ready_vector[1] = src1_ready; - assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); endmodule diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv index b2f14c8..f89224d 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv @@ -45,7 +45,7 @@ // PIPELINE_ARB: 1 // PKT_TRANS_LOCK: 58 (arbitration locking enabled) // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 +// ST_CHANNEL_W: 8 // ------------------------------------------ module niosII_mm_interconnect_0_cmd_mux @@ -55,7 +55,7 @@ module niosII_mm_interconnect_0_cmd_mux // ---------------------- input sink0_valid, input [94-1 : 0] sink0_data, - input [7-1: 0] sink0_channel, + input [8-1: 0] sink0_channel, input sink0_startofpacket, input sink0_endofpacket, output sink0_ready, @@ -66,7 +66,7 @@ module niosII_mm_interconnect_0_cmd_mux // ---------------------- output src_valid, output [94-1 : 0] src_data, - output [7-1 : 0] src_channel, + output [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready, @@ -77,12 +77,12 @@ module niosII_mm_interconnect_0_cmd_mux input clk, input reset ); - localparam PAYLOAD_W = 94 + 7 + 2; + localparam PAYLOAD_W = 94 + 8 + 2; localparam NUM_INPUTS = 1; localparam SHARE_COUNTER_W = 1; localparam PIPELINE_ARB = 1; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam PKT_TRANS_LOCK = 58; assign src_valid = sink0_valid; diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv index 1ae7b5c..8853c96 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv @@ -44,15 +44,15 @@ module niosII_mm_interconnect_0_router_default_decode #( - parameter DEFAULT_CHANNEL = 5, + parameter DEFAULT_CHANNEL = 6, DEFAULT_WR_CHANNEL = -1, DEFAULT_RD_CHANNEL = -1, DEFAULT_DESTID = 3 ) (output [80 - 78 : 0] default_destination_id, - output [7-1 : 0] default_wr_channel, - output [7-1 : 0] default_rd_channel, - output [7-1 : 0] default_src_channel + output [8-1 : 0] default_wr_channel, + output [8-1 : 0] default_rd_channel, + output [8-1 : 0] default_src_channel ); assign default_destination_id = @@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_default_decode assign default_src_channel = '0; end else begin : default_channel_assignment - assign default_src_channel = 7'b1 << DEFAULT_CHANNEL; + assign default_src_channel = 8'b1 << DEFAULT_CHANNEL; end endgenerate @@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode assign default_rd_channel = '0; end else begin : default_rw_channel_assignment - assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL; + assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL; end endgenerate @@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router // ------------------- output src_valid, output reg [94-1 : 0] src_data, - output reg [7-1 : 0] src_channel, + output reg [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready @@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_L = 82; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam DECODER_TYPE = 0; localparam PKT_TRANS_WRITE = 56; @@ -137,15 +137,16 @@ module niosII_mm_interconnect_0_router localparam PAD0 = log2ceil(64'h20000 - 64'h0); localparam PAD1 = log2ceil(64'h21000 - 64'h20800); localparam PAD2 = log2ceil(64'h21040 - 64'h21000); - localparam PAD3 = log2ceil(64'h21060 - 64'h21040); - localparam PAD4 = log2ceil(64'h21068 - 64'h21060); - localparam PAD5 = log2ceil(64'h21070 - 64'h21068); + localparam PAD3 = log2ceil(64'h21080 - 64'h21040); + localparam PAD4 = log2ceil(64'h210a0 - 64'h21080); + localparam PAD5 = log2ceil(64'h210a8 - 64'h210a0); + localparam PAD6 = log2ceil(64'h210b0 - 64'h210a8); // ------------------------------------------------------- // Work out which address bits are significant based on the // address range of the slaves. If the required width is too // large or too small, we use the address field width instead. // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h21070; + localparam ADDR_RANGE = 64'h210b0; localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || (RANGE_ADDR_WIDTH == 0) ? @@ -169,7 +170,7 @@ module niosII_mm_interconnect_0_router assign src_startofpacket = sink_startofpacket; assign src_endofpacket = sink_endofpacket; wire [PKT_DEST_ID_W-1:0] default_destid; - wire [7-1 : 0] default_src_channel; + wire [8-1 : 0] default_src_channel; @@ -200,37 +201,43 @@ module niosII_mm_interconnect_0_router // ( 0x0 .. 0x20000 ) if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin - src_channel = 7'b100000; + src_channel = 8'b1000000; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; end // ( 0x20800 .. 0x21000 ) if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin - src_channel = 7'b000100; + src_channel = 8'b0001000; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; end // ( 0x21000 .. 0x21040 ) - if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin - src_channel = 7'b001000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; - end - - // ( 0x21040 .. 0x21060 ) - if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin - src_channel = 7'b010000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; - end - - // ( 0x21060 .. 0x21068 ) - if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin - src_channel = 7'b000010; + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin + src_channel = 8'b0000010; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; end - // ( 0x21068 .. 0x21070 ) - if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin - src_channel = 7'b000001; + // ( 0x21040 .. 0x21080 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 && write_transaction ) begin + src_channel = 8'b0010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x21080 .. 0x210a0 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21080 ) begin + src_channel = 8'b0100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x210a0 .. 0x210a8 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h210a0 ) begin + src_channel = 8'b0000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x210a8 .. 0x210b0 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 18'h210a8 ) begin + src_channel = 8'b0000001; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; end diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv index 91db8fd..ba72e2d 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv @@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_001_default_decode DEFAULT_DESTID = 2 ) (output [80 - 78 : 0] default_destination_id, - output [7-1 : 0] default_wr_channel, - output [7-1 : 0] default_rd_channel, - output [7-1 : 0] default_src_channel + output [8-1 : 0] default_wr_channel, + output [8-1 : 0] default_rd_channel, + output [8-1 : 0] default_src_channel ); assign default_destination_id = @@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_001_default_decode assign default_src_channel = '0; end else begin : default_channel_assignment - assign default_src_channel = 7'b1 << DEFAULT_CHANNEL; + assign default_src_channel = 8'b1 << DEFAULT_CHANNEL; end endgenerate @@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode assign default_rd_channel = '0; end else begin : default_rw_channel_assignment - assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL; + assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL; end endgenerate @@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_001 // ------------------- output src_valid, output reg [94-1 : 0] src_data, - output reg [7-1 : 0] src_channel, + output reg [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready @@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_001 localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_L = 82; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam DECODER_TYPE = 0; localparam PKT_TRANS_WRITE = 56; @@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001 assign src_startofpacket = sink_startofpacket; assign src_endofpacket = sink_endofpacket; wire [PKT_DEST_ID_W-1:0] default_destid; - wire [7-1 : 0] default_src_channel; + wire [8-1 : 0] default_src_channel; @@ -191,13 +191,13 @@ module niosII_mm_interconnect_0_router_001 // ( 0x0 .. 0x20000 ) if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin - src_channel = 7'b10; + src_channel = 8'b10; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; end // ( 0x20800 .. 0x21000 ) if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin - src_channel = 7'b01; + src_channel = 8'b01; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; end diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv index dc8ad68..5bef2c5 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv @@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_002_default_decode DEFAULT_DESTID = 0 ) (output [80 - 78 : 0] default_destination_id, - output [7-1 : 0] default_wr_channel, - output [7-1 : 0] default_rd_channel, - output [7-1 : 0] default_src_channel + output [8-1 : 0] default_wr_channel, + output [8-1 : 0] default_rd_channel, + output [8-1 : 0] default_src_channel ); assign default_destination_id = @@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_002_default_decode assign default_src_channel = '0; end else begin : default_channel_assignment - assign default_src_channel = 7'b1 << DEFAULT_CHANNEL; + assign default_src_channel = 8'b1 << DEFAULT_CHANNEL; end endgenerate @@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode assign default_rd_channel = '0; end else begin : default_rw_channel_assignment - assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL; + assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL; end endgenerate @@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_002 // ------------------- output src_valid, output reg [94-1 : 0] src_data, - output reg [7-1 : 0] src_channel, + output reg [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready @@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_002 localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_L = 82; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam DECODER_TYPE = 1; localparam PKT_TRANS_WRITE = 56; @@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002 assign src_valid = sink_valid; assign src_startofpacket = sink_startofpacket; assign src_endofpacket = sink_endofpacket; - wire [7-1 : 0] default_src_channel; + wire [8-1 : 0] default_src_channel; @@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002 if (destid == 0 ) begin - src_channel = 7'b1; + src_channel = 8'b1; end diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv index f46f1ba..3e6bee9 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv @@ -29,7 +29,7 @@ // Generation parameters: // output_name: niosII_mm_interconnect_0_rsp_demux // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 +// ST_CHANNEL_W: 8 // NUM_OUTPUTS: 1 // VALID_WIDTH: 1 // ------------------------------------------ @@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_rsp_demux // ------------------- input [1-1 : 0] sink_valid, input [94-1 : 0] sink_data, // ST_DATA_W=94 - input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7 + input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8 input sink_startofpacket, input sink_endofpacket, output sink_ready, @@ -57,7 +57,7 @@ module niosII_mm_interconnect_0_rsp_demux // ------------------- output reg src0_valid, output reg [94-1 : 0] src0_data, // ST_DATA_W=94 - output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7 + output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8 output reg src0_startofpacket, output reg src0_endofpacket, input src0_ready, @@ -94,7 +94,7 @@ module niosII_mm_interconnect_0_rsp_demux // ------------------- assign ready_vector[0] = src0_ready; - assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + assign sink_ready = |(sink_channel & {{7{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); endmodule diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv index a370648..02e39d8 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv @@ -39,13 +39,13 @@ // ------------------------------------------ // Generation parameters: // output_name: niosII_mm_interconnect_0_rsp_mux -// NUM_INPUTS: 6 -// ARBITRATION_SHARES: 1 1 1 1 1 1 +// NUM_INPUTS: 7 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 // ARBITRATION_SCHEME "no-arb" // PIPELINE_ARB: 0 // PKT_TRANS_LOCK: 58 (arbitration locking enabled) // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 +// ST_CHANNEL_W: 8 // ------------------------------------------ module niosII_mm_interconnect_0_rsp_mux @@ -55,53 +55,60 @@ module niosII_mm_interconnect_0_rsp_mux // ---------------------- input sink0_valid, input [94-1 : 0] sink0_data, - input [7-1: 0] sink0_channel, + input [8-1: 0] sink0_channel, input sink0_startofpacket, input sink0_endofpacket, output sink0_ready, input sink1_valid, input [94-1 : 0] sink1_data, - input [7-1: 0] sink1_channel, + input [8-1: 0] sink1_channel, input sink1_startofpacket, input sink1_endofpacket, output sink1_ready, input sink2_valid, input [94-1 : 0] sink2_data, - input [7-1: 0] sink2_channel, + input [8-1: 0] sink2_channel, input sink2_startofpacket, input sink2_endofpacket, output sink2_ready, input sink3_valid, input [94-1 : 0] sink3_data, - input [7-1: 0] sink3_channel, + input [8-1: 0] sink3_channel, input sink3_startofpacket, input sink3_endofpacket, output sink3_ready, input sink4_valid, input [94-1 : 0] sink4_data, - input [7-1: 0] sink4_channel, + input [8-1: 0] sink4_channel, input sink4_startofpacket, input sink4_endofpacket, output sink4_ready, input sink5_valid, input [94-1 : 0] sink5_data, - input [7-1: 0] sink5_channel, + input [8-1: 0] sink5_channel, input sink5_startofpacket, input sink5_endofpacket, output sink5_ready, + input sink6_valid, + input [94-1 : 0] sink6_data, + input [8-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + // ---------------------- // Source // ---------------------- output src_valid, output [94-1 : 0] src_data, - output [7-1 : 0] src_channel, + output [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready, @@ -112,12 +119,12 @@ module niosII_mm_interconnect_0_rsp_mux input clk, input reset ); - localparam PAYLOAD_W = 94 + 7 + 2; - localparam NUM_INPUTS = 6; + localparam PAYLOAD_W = 94 + 8 + 2; + localparam NUM_INPUTS = 7; localparam SHARE_COUNTER_W = 1; localparam PIPELINE_ARB = 0; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam PKT_TRANS_LOCK = 58; // ------------------------------------------ @@ -139,6 +146,7 @@ module niosII_mm_interconnect_0_rsp_mux wire [PAYLOAD_W - 1 : 0] sink3_payload; wire [PAYLOAD_W - 1 : 0] sink4_payload; wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; assign valid[0] = sink0_valid; assign valid[1] = sink1_valid; @@ -146,6 +154,7 @@ module niosII_mm_interconnect_0_rsp_mux assign valid[3] = sink3_valid; assign valid[4] = sink4_valid; assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; // ------------------------------------------ @@ -161,6 +170,7 @@ module niosII_mm_interconnect_0_rsp_mux lock[3] = sink3_data[58]; lock[4] = sink4_data[58]; lock[5] = sink5_data[58]; + lock[6] = sink6_data[58]; end assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); @@ -197,12 +207,14 @@ module niosII_mm_interconnect_0_rsp_mux // 3 | 1 | 0 // 4 | 1 | 0 // 5 | 1 | 0 + // 6 | 1 | 0 wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; // ------------------------------------------ // Choose the share value corresponding to the grant. @@ -215,7 +227,8 @@ module niosII_mm_interconnect_0_rsp_mux share_2 & { SHARE_COUNTER_W {next_grant[2]} } | share_3 & { SHARE_COUNTER_W {next_grant[3]} } | share_4 & { SHARE_COUNTER_W {next_grant[4]} } | - share_5 & { SHARE_COUNTER_W {next_grant[5]} }; + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} }; end // ------------------------------------------ @@ -289,11 +302,14 @@ module niosII_mm_interconnect_0_rsp_mux wire final_packet_5 = 1'b1; + wire final_packet_6 = 1'b1; + // ------------------------------------------ // Concatenate all final_packet signals (wire or reg) into a handy vector. // ------------------------------------------ wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_6, final_packet_5, final_packet_4, final_packet_3, @@ -389,6 +405,7 @@ module niosII_mm_interconnect_0_rsp_mux assign sink3_ready = src_ready && grant[3]; assign sink4_ready = src_ready && grant[4]; assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; assign src_valid = |(grant & valid); @@ -399,7 +416,8 @@ module niosII_mm_interconnect_0_rsp_mux sink2_payload & {PAYLOAD_W {grant[2]} } | sink3_payload & {PAYLOAD_W {grant[3]} } | sink4_payload & {PAYLOAD_W {grant[4]} } | - sink5_payload & {PAYLOAD_W {grant[5]} }; + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} }; end // ------------------------------------------ @@ -418,6 +436,8 @@ module niosII_mm_interconnect_0_rsp_mux sink4_startofpacket,sink4_endofpacket}; assign sink5_payload = {sink5_channel,sink5_data, sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; endmodule diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv index bde1d55..67023d1 100644 --- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv +++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv @@ -45,7 +45,7 @@ // PIPELINE_ARB: 0 // PKT_TRANS_LOCK: 58 (arbitration locking enabled) // ST_DATA_W: 94 -// ST_CHANNEL_W: 7 +// ST_CHANNEL_W: 8 // ------------------------------------------ module niosII_mm_interconnect_0_rsp_mux_001 @@ -55,14 +55,14 @@ module niosII_mm_interconnect_0_rsp_mux_001 // ---------------------- input sink0_valid, input [94-1 : 0] sink0_data, - input [7-1: 0] sink0_channel, + input [8-1: 0] sink0_channel, input sink0_startofpacket, input sink0_endofpacket, output sink0_ready, input sink1_valid, input [94-1 : 0] sink1_data, - input [7-1: 0] sink1_channel, + input [8-1: 0] sink1_channel, input sink1_startofpacket, input sink1_endofpacket, output sink1_ready, @@ -73,7 +73,7 @@ module niosII_mm_interconnect_0_rsp_mux_001 // ---------------------- output src_valid, output [94-1 : 0] src_data, - output [7-1 : 0] src_channel, + output [8-1 : 0] src_channel, output src_startofpacket, output src_endofpacket, input src_ready, @@ -84,12 +84,12 @@ module niosII_mm_interconnect_0_rsp_mux_001 input clk, input reset ); - localparam PAYLOAD_W = 94 + 7 + 2; + localparam PAYLOAD_W = 94 + 8 + 2; localparam NUM_INPUTS = 2; localparam SHARE_COUNTER_W = 1; localparam PIPELINE_ARB = 0; localparam ST_DATA_W = 94; - localparam ST_CHANNEL_W = 7; + localparam ST_CHANNEL_W = 8; localparam PKT_TRANS_LOCK = 58; // ------------------------------------------ diff --git a/Top/semafor.qws b/Top/semafor.qws deleted file mode 100644 index 045a66f..0000000 Binary files a/Top/semafor.qws and /dev/null differ