diff --git a/HDL/IP/periodram.v b/HDL/IP/periodram.v
index b0a05bc..f7f7363 100644
--- a/HDL/IP/periodram.v
+++ b/HDL/IP/periodram.v
@@ -92,6 +92,13 @@ module periodram (
 		altsyncram_component.clock_enable_input_a = "BYPASS",
 		altsyncram_component.clock_enable_input_b = "BYPASS",
 		altsyncram_component.clock_enable_output_b = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "periodram.rif"
+`else
+		altsyncram_component.init_file = "periodram.hex"
+`endif
+,
+		altsyncram_component.init_file_layout = "PORT_B",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
 		altsyncram_component.lpm_type = "altsyncram",
 		altsyncram_component.numwords_a = 16,
@@ -120,7 +127,7 @@ endmodule
 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
@@ -145,7 +152,7 @@ endmodule
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
@@ -178,6 +185,8 @@ endmodule
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
+// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
diff --git a/Testbench/dec/dec.qsf b/Testbench/dec/dec.qsf
index afc4529..11fde70 100644
--- a/Testbench/dec/dec.qsf
+++ b/Testbench/dec/dec.qsf
@@ -64,4 +64,5 @@ set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulatio
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
 set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
+set_global_assignment -name HEX_FILE periodram.hex
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Testbench/dec/dec.qws b/Testbench/dec/dec.qws
index 045a66f..937c2ba 100644
Binary files a/Testbench/dec/dec.qws and b/Testbench/dec/dec.qws differ
diff --git a/Testbench/dec/periodram.hex b/Testbench/dec/periodram.hex
new file mode 100644
index 0000000..229095d
--- /dev/null
+++ b/Testbench/dec/periodram.hex
@@ -0,0 +1,17 @@
+:040000000000006498
+:040001000000006497
+:0400020000000032C8
+:040003000000000AEF
+:040004000000006494
+:04000500000000C82F
+:040006000000006492
+:040007000000000AEB
+:04000800000000965E
+:04000900000000FAF9
+:04000A00000000C82A
+:04000B000000000AE7
+:04000C00000000FAF6
+:04000D00000000FAF5
+:04000E00000000FAF4
+:04000F000000000AE3
+:00000001FF
diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo
index ef8ac5d..692fcde 100644
--- a/Top/niosII.sopcinfo
+++ b/Top/niosII.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2022.12.21.21:03:50 -->
+ <!-- 2022.12.22.17:19:01 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1671642230</value>
+  <value>1671715140</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
diff --git a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v
index b883521..0ebbcef 100644
--- a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v
+++ b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v
@@ -4,14 +4,16 @@ module niosII_tb (
 
     wire    niosii_inst_clk_bfm_clk_clk;       // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
     wire    niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
+    reg     train;
+    wire    red, yellow, green;
 
     niosII niosii_inst (
         .clk_clk           (niosii_inst_clk_bfm_clk_clk),       //        clk.clk
         .reset_reset_n     (niosii_inst_reset_bfm_reset_reset), //      reset.reset_n
-        .sem_export_train  (),                                  // sem_export.train
-        .sem_export_red    (),                                  //           .red
-        .sem_export_yellow (),                                  //           .yellow
-        .sem_export_green  ()                                   //           .green
+        .sem_export_train  (train),                             // sem_export.train
+        .sem_export_red    (red),                               //           .red
+        .sem_export_yellow (yellow),                            //           .yellow
+        .sem_export_green  (green)                              //           .green
     );
 
     altera_avalon_clock_source #(
@@ -33,9 +35,9 @@ module niosII_tb (
         train = 0;
         wait (niosii_inst_reset_bfm_reset_reset);
         forever begin
-            repeat (29000) @(posedge niosII_inst_clk_bfm_clk_clk);
+            repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
             train = 1;
-            repeat (10) @(posedge niosII_inst_clk_bfm_clk_clk);
+            repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
             train = 0;
         end
     end
diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp
index 9abac2b..bee392c 100644
--- a/Top/software/semafor_bsp/settings.bsp
+++ b/Top/software/semafor_bsp/settings.bsp
@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>21.12.2022 21:06:52</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1671642412929</BspGeneratedUnixTimeStamp>
+        <BspGeneratedTimeStamp>22.12.2022 17:21:19</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1671715279678</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html
index f4c0076..7d9cba6 100644
--- a/Top/software/semafor_bsp/summary.html
+++ b/Top/software/semafor_bsp/summary.html
@@ -22,10 +22,10 @@
 <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>21.12.2022 21:06:52</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 17:21:19</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671642412929</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671715279678</td>
 </tr>
 <tr mode="wrap">
 <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>