From 6291090406f6153fdcc6223c1e0959f1e478fd44 Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Thu, 22 Dec 2022 17:32:08 +0300 Subject: [PATCH] added ram hex(no luck) --- HDL/IP/periodram.v | 13 +++++++++++-- Testbench/dec/dec.qsf | 1 + Testbench/dec/dec.qws | Bin 619 -> 1110 bytes Testbench/dec/periodram.hex | 17 +++++++++++++++++ Top/niosII.sopcinfo | 4 ++-- .../testbench/niosII_tb/simulation/niosII_tb.v | 14 ++++++++------ Top/software/semafor_bsp/settings.bsp | 4 ++-- Top/software/semafor_bsp/summary.html | 4 ++-- 8 files changed, 43 insertions(+), 14 deletions(-) create mode 100644 Testbench/dec/periodram.hex diff --git a/HDL/IP/periodram.v b/HDL/IP/periodram.v index b0a05bc..f7f7363 100644 --- a/HDL/IP/periodram.v +++ b/HDL/IP/periodram.v @@ -92,6 +92,13 @@ module periodram ( altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_b = "BYPASS", altsyncram_component.clock_enable_output_b = "BYPASS", +`ifdef NO_PLI + altsyncram_component.init_file = "periodram.rif" +`else + altsyncram_component.init_file = "periodram.hex" +`endif +, + altsyncram_component.init_file_layout = "PORT_B", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 16, @@ -120,7 +127,7 @@ endmodule // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" @@ -145,7 +152,7 @@ endmodule // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" @@ -178,6 +185,8 @@ endmodule // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex" +// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" diff --git a/Testbench/dec/dec.qsf b/Testbench/dec/dec.qsf index afc4529..11fde70 100644 --- a/Testbench/dec/dec.qsf +++ b/Testbench/dec/dec.qsf @@ -64,4 +64,5 @@ set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulatio set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb +set_global_assignment -name HEX_FILE periodram.hex set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Testbench/dec/dec.qws b/Testbench/dec/dec.qws index 045a66f76c7eeafeba764a56b7a06f33d5350a32..937c2bae503e198e70cde1b045249fcb8255ea8b 100644 GIT binary patch delta 171 zcmaFOa*bnxemxTd1A`AkHG?Tb3WG6&1%nAgG7zUS=mOc6K#^o1%Mb`tfLNCyk--2c zZVqG_0HF~OCo-e~VIokEF_1Q5sQnKFKr - + java.lang.Integer - 1671642230 + 1671715140 false true false diff --git a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v index b883521..0ebbcef 100644 --- a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v +++ b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v @@ -4,14 +4,16 @@ module niosII_tb ( wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk] wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n + reg train; + wire red, yellow, green; niosII niosii_inst ( .clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk .reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n - .sem_export_train (), // sem_export.train - .sem_export_red (), // .red - .sem_export_yellow (), // .yellow - .sem_export_green () // .green + .sem_export_train (train), // sem_export.train + .sem_export_red (red), // .red + .sem_export_yellow (yellow), // .yellow + .sem_export_green (green) // .green ); altera_avalon_clock_source #( @@ -33,9 +35,9 @@ module niosII_tb ( train = 0; wait (niosii_inst_reset_bfm_reset_reset); forever begin - repeat (29000) @(posedge niosII_inst_clk_bfm_clk_clk); + repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk); train = 1; - repeat (10) @(posedge niosII_inst_clk_bfm_clk_clk); + repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); train = 0; end end diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp index 9abac2b..bee392c 100644 --- a/Top/software/semafor_bsp/settings.bsp +++ b/Top/software/semafor_bsp/settings.bsp @@ -2,8 +2,8 @@ hal default - 21.12.2022 21:06:52 - 1671642412929 + 22.12.2022 17:21:19 + 1671715279678 C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp settings.bsp ..\..\niosII.sopcinfo diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html index f4c0076..7d9cba6 100644 --- a/Top/software/semafor_bsp/summary.html +++ b/Top/software/semafor_bsp/summary.html @@ -22,10 +22,10 @@ BSP Version:default -BSP Generated On:21.12.2022 21:06:52 +BSP Generated On:22.12.2022 17:21:19 -BSP Generated Timestamp:1671642412929 +BSP Generated Timestamp:1671715279678 BSP Generated Location:C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp