diff --git a/HDL/dec.sv b/HDL/dec.sv
index c80033a..e14fc41 100644
--- a/HDL/dec.sv
+++ b/HDL/dec.sv
@@ -83,6 +83,7 @@ module dec
colors <= 3'b001;
state <= GREEN;
end
+
if (train) begin
colors <= 3'b100;
state <= RED;
diff --git a/Testbench/dec/dec.qws b/Testbench/dec/dec.qws
index 045a66f..63563b7 100644
Binary files a/Testbench/dec/dec.qws and b/Testbench/dec/dec.qws differ
diff --git a/Testbench/sigdel/db/prev_cmp_sigdel.qmsg b/Testbench/sigdel/db/prev_cmp_sigdel.qmsg
new file mode 100644
index 0000000..1a6f05d
--- /dev/null
+++ b/Testbench/sigdel/db/prev_cmp_sigdel.qmsg
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}
diff --git a/Testbench/sigdel/db/sigdel.(0).cnf.cdb b/Testbench/sigdel/db/sigdel.(0).cnf.cdb
new file mode 100644
index 0000000..0f55ee1
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.(0).cnf.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.(0).cnf.hdb b/Testbench/sigdel/db/sigdel.(0).cnf.hdb
new file mode 100644
index 0000000..c9098ef
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.(0).cnf.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.cbx.xml b/Testbench/sigdel/db/sigdel.cbx.xml
new file mode 100644
index 0000000..4c9d94f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.cbx.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/Testbench/sigdel/db/sigdel.cmp.rdb b/Testbench/sigdel/db/sigdel.cmp.rdb
new file mode 100644
index 0000000..d161ef5
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.cmp.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.cmp_merge.kpt b/Testbench/sigdel/db/sigdel.cmp_merge.kpt
new file mode 100644
index 0000000..049df89
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.cmp_merge.kpt differ
diff --git a/Testbench/sigdel/db/sigdel.db_info b/Testbench/sigdel/db/sigdel.db_info
new file mode 100644
index 0000000..132a34a
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Mon Jan 16 21:47:58 2023
diff --git a/Testbench/sigdel/db/sigdel.hier_info b/Testbench/sigdel/db/sigdel.hier_info
new file mode 100644
index 0000000..388f4ea
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.hier_info
@@ -0,0 +1,47 @@
+|sigdel
+phinc[0] => Add0.IN14
+phinc[1] => Add0.IN13
+phinc[2] => Add0.IN12
+phinc[3] => Add0.IN11
+phinc[4] => Add0.IN10
+phinc[5] => Add0.IN9
+phinc[6] => Add0.IN8
+phinc[7] => Add0.IN7
+clk => acc[0].CLK
+clk => acc[1].CLK
+clk => acc[2].CLK
+clk => acc[3].CLK
+clk => acc[4].CLK
+clk => acc[5].CLK
+clk => acc[6].CLK
+clk => acc[7].CLK
+clk => acc[8].CLK
+clk => acc[9].CLK
+clk => acc[10].CLK
+clk => acc[11].CLK
+clk => acc[12].CLK
+clk => acc[13].CLK
+clr_n => acc[0].ACLR
+clr_n => acc[1].ACLR
+clr_n => acc[2].ACLR
+clr_n => acc[3].ACLR
+clr_n => acc[4].ACLR
+clr_n => acc[5].ACLR
+clr_n => acc[6].ACLR
+clr_n => acc[7].ACLR
+clr_n => acc[8].ACLR
+clr_n => acc[9].ACLR
+clr_n => acc[10].ACLR
+clr_n => acc[11].ACLR
+clr_n => acc[12].ACLR
+clr_n => acc[13].ACLR
+phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
+phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
+phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
+phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
+phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
+phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
+phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
+phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Testbench/sigdel/db/sigdel.hif b/Testbench/sigdel/db/sigdel.hif
new file mode 100644
index 0000000..c478932
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.hif differ
diff --git a/Testbench/sigdel/db/sigdel.lpc.html b/Testbench/sigdel/db/sigdel.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.lpc.html
@@ -0,0 +1,18 @@
+
+
+Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
diff --git a/Testbench/sigdel/db/sigdel.lpc.rdb b/Testbench/sigdel/db/sigdel.lpc.rdb
new file mode 100644
index 0000000..6da93af
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.lpc.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.lpc.txt b/Testbench/sigdel/db/sigdel.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Testbench/sigdel/db/sigdel.map.ammdb b/Testbench/sigdel/db/sigdel.map.ammdb
new file mode 100644
index 0000000..46055fc
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.ammdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.bpm b/Testbench/sigdel/db/sigdel.map.bpm
new file mode 100644
index 0000000..c0ec0ab
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.bpm differ
diff --git a/Testbench/sigdel/db/sigdel.map.cdb b/Testbench/sigdel/db/sigdel.map.cdb
new file mode 100644
index 0000000..4f7368c
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.hdb b/Testbench/sigdel/db/sigdel.map.hdb
new file mode 100644
index 0000000..33b95dd
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.kpt b/Testbench/sigdel/db/sigdel.map.kpt
new file mode 100644
index 0000000..3da6623
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.kpt differ
diff --git a/Testbench/sigdel/db/sigdel.map.logdb b/Testbench/sigdel/db/sigdel.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Testbench/sigdel/db/sigdel.map.qmsg b/Testbench/sigdel/db/sigdel.map.qmsg
new file mode 100644
index 0000000..94d2057
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}
diff --git a/Testbench/sigdel/db/sigdel.map.rdb b/Testbench/sigdel/db/sigdel.map.rdb
new file mode 100644
index 0000000..f833721
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.cdb b/Testbench/sigdel/db/sigdel.map_bb.cdb
new file mode 100644
index 0000000..8caa875
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map_bb.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.hdb b/Testbench/sigdel/db/sigdel.map_bb.hdb
new file mode 100644
index 0000000..a750c1f
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map_bb.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.logdb b/Testbench/sigdel/db/sigdel.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Testbench/sigdel/db/sigdel.pre_map.hdb b/Testbench/sigdel/db/sigdel.pre_map.hdb
new file mode 100644
index 0000000..2016702
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.pre_map.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb b/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..24e9fc3
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.rtlv.hdb b/Testbench/sigdel/db/sigdel.rtlv.hdb
new file mode 100644
index 0000000..5597348
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diff --git a/Testbench/sigdel/db/sigdel.rtlv_sg.cdb b/Testbench/sigdel/db/sigdel.rtlv_sg.cdb
new file mode 100644
index 0000000..d586076
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.rtlv_sg.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb b/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..96b5aa3
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.sld_design_entry.sci b/Testbench/sigdel/db/sigdel.sld_design_entry.sci
new file mode 100644
index 0000000..6849b47
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.sld_design_entry.sci differ
diff --git a/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci b/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..6849b47
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci differ
diff --git a/Testbench/sigdel/db/sigdel.smart_action.txt b/Testbench/sigdel/db/sigdel.smart_action.txt
new file mode 100644
index 0000000..e04bbcf
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/Testbench/sigdel/db/sigdel.tis_db_list.ddb b/Testbench/sigdel/db/sigdel.tis_db_list.ddb
new file mode 100644
index 0000000..9b5e0bf
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.tis_db_list.ddb differ
diff --git a/Testbench/sigdel/db/sigdel_partition_pins.json b/Testbench/sigdel/db/sigdel_partition_pins.json
new file mode 100644
index 0000000..42834f5
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel_partition_pins.json
@@ -0,0 +1,81 @@
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "phase[0]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[1]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[2]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[3]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[4]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[5]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[6]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[7]",
+ "strict" : false
+ },
+ {
+ "name" : "clk",
+ "strict" : false
+ },
+ {
+ "name" : "clr_n",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[6]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[7]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[5]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[4]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[3]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[2]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[1]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[0]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/Testbench/sigdel/incremental_db/README b/Testbench/sigdel/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info
new file mode 100644
index 0000000..faa6190
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Thu Jan 12 13:26:18 2023
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb
new file mode 100644
index 0000000..71d080d
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi
new file mode 100644
index 0000000..96aaa29
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..c88e3ee
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..d831a4a
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..af9b8e9
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb
new file mode 100644
index 0000000..5fd74e7
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt
new file mode 100644
index 0000000..7c434b5
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt differ
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml
index 0d613c3..a5dcdfa 100644
--- a/Top/niosII/niosII.xml
+++ b/Top/niosII/niosII.xml
@@ -88,7 +88,7 @@
@@ -100,51 +100,51 @@
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu.v"
type="VERILOG" />
+
+
+
+
+
+
-
-
-
-
-
-
+
-
+
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
+
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
queue size: 0 starting:niosII "niosII"
@@ -1414,54 +1420,54 @@
+
+
+
+
+
+
-
-
-
-
-
-
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
@@ -1524,14 +1530,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
@@ -1589,18 +1595,18 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
@@ -1652,17 +1658,18 @@
-
+
@@ -1697,14 +1704,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
@@ -2056,44 +2063,44 @@
};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ID} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ECC_ENABLE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {perf_counter_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {perf_counter_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {perf_counter_control_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {perf_counter_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {perf_counter_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {perf_counter_control_slave_agent} {ID} {4};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {perf_counter_control_slave_agent} {ECC_ENABLE} {0};add_instance {perf_counter_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {perf_counter_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ctl_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ctl_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ctl_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ctl_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ctl_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ctl_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ctl_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ctl_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ctl_slave_agent} {ID} {5};set_instance_parameter_value {sem_ctl_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ctl_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ctl_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ctl_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sem_ram_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sem_ram_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sem_ram_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sem_ram_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sem_ram_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sem_ram_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sem_ram_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sem_ram_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sem_ram_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sem_ram_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sem_ram_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sem_ram_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sem_ram_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sem_ram_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sem_ram_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sem_ram_slave_agent} {ID} {6};set_instance_parameter_value {sem_ram_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sem_ram_slave_agent} {ECC_ENABLE} {0};add_instance {sem_ram_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sem_ram_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {7};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s2_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s2_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s2_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s2_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s2_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s2_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s2_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s2_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s2_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s2_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s2_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s2_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s2_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s2_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s2_agent} {ID} {3};set_instance_parameter_value {mem_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s2_agent} {ECC_ENABLE} {0};add_instance {mem_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mem_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {mem_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {mem_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {mem_s1_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {mem_s1_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {mem_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {mem_s1_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {mem_s1_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {mem_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {mem_s1_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mem_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mem_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {mem_s1_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {mem_s1_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {mem_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_CHANNEL_W} {8};set_instance_parameter_value {mem_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mem_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mem_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mem_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mem_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mem_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mem_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mem_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mem_s1_agent} {ID} {2};set_instance_parameter_value {mem_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mem_s1_agent} {ECC_ENABLE} {0};add_instance {mem_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mem_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 0 4 6 7 5 1 };set_instance_parameter_value {router} {CHANNEL_ID} {1000000 0001000 0000010 0010000 0100000 0000100 0000001 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both write both both both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x20800 0x21000 0x21040 0x21080 0x210a0 0x210a8 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 0x21000 0x21040 0x21080 0x210a0 0x210a8 0x210b0 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {53};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router} {PKT_TRANS_READ} {57};set_instance_parameter_value {router} {ST_DATA_W} {94};set_instance_parameter_value {router} {ST_CHANNEL_W} {8};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {6};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {2 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {10 01 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x20800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 0x21000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {53};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_001} {ST_DATA_W} {94};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {2};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {53};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_002} {ST_DATA_W} {94};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {53};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {0 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {53};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_004} {ST_DATA_W} {94};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_005} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_005} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {53};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_005} {ST_DATA_W} {94};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_005} {DECODER_TYPE} {1};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {0 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {53};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_006} {ST_DATA_W} {94};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_006} {DECODER_TYPE} {1};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {0 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {53};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_007} {ST_DATA_W} {94};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_007} {DECODER_TYPE} {1};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 };set_instance_parameter_value {router_008} {CHANNEL_ID} {1 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {53};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_008} {ST_DATA_W} {94};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {1 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {53};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {80};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {78};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {57};set_instance_parameter_value {router_009} {ST_DATA_W} {94};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {8};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {7};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {94};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {94};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {7};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {94};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {8};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {jtag_uart_avalon_jtag_slave_agent.m0} {jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.rf_source} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.out} {jtag_uart_avalon_jtag_slave_agent.rf_sink} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_src} {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {jtag_uart_avalon_jtag_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/jtag_uart_avalon_jtag_slave_agent.cp} {qsys_mm.command};add_connection {perf_counter_control_slave_agent.m0} {perf_counter_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {perf_counter_control_slave_agent.m0/perf_counter_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {perf_counter_control_slave_agent.rf_source} {perf_counter_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {perf_counter_control_slave_agent_rsp_fifo.out} {perf_counter_control_slave_agent.rf_sink} {avalon_streaming};add_connection {perf_counter_control_slave_agent.rdata_fifo_src} {perf_counter_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {perf_counter_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/perf_counter_control_slave_agent.cp} {qsys_mm.command};add_connection {sem_ctl_slave_agent.m0} {sem_ctl_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ctl_slave_agent.m0/sem_ctl_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ctl_slave_agent.rf_source} {sem_ctl_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ctl_slave_agent_rsp_fifo.out} {sem_ctl_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ctl_slave_agent.rdata_fifo_src} {sem_ctl_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_002.src} {sem_ctl_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/sem_ctl_slave_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {sem_ram_slave_agent.m0} {sem_ram_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sem_ram_slave_agent.m0/sem_ram_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sem_ram_slave_agent.rf_source} {sem_ram_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sem_ram_slave_agent_rsp_fifo.out} {sem_ram_slave_agent.rf_sink} {avalon_streaming};add_connection {sem_ram_slave_agent.rdata_fifo_src} {sem_ram_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sem_ram_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sem_ram_slave_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {mem_s2_agent.m0} {mem_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s2_agent.m0/mem_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s2_agent.rf_source} {mem_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s2_agent_rsp_fifo.out} {mem_s2_agent.rf_sink} {avalon_streaming};add_connection {mem_s2_agent.rdata_fifo_src} {mem_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {mem_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/mem_s2_agent.cp} {qsys_mm.command};add_connection {mem_s1_agent.m0} {mem_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mem_s1_agent.m0/mem_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mem_s1_agent.rf_source} {mem_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mem_s1_agent_rsp_fifo.out} {mem_s1_agent.rf_sink} {avalon_streaming};add_connection {mem_s1_agent.rdata_fifo_src} {mem_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {mem_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/mem_s1_agent.cp} {qsys_mm.command};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {jtag_uart_avalon_jtag_slave_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {jtag_uart_avalon_jtag_slave_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {perf_counter_control_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {perf_counter_control_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {sem_ctl_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {sem_ctl_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_005.sink} {qsys_mm.response};add_connection {router_005.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sem_ram_slave_agent.rp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {sem_ram_slave_agent.rp/router_006.sink} {qsys_mm.response};add_connection {router_006.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_007.sink} {qsys_mm.response};add_connection {router_007.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {mem_s2_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {mem_s2_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {mem_s1_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {mem_s1_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux_003.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux_003.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_007.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_003.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {perf_counter_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ctl_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sem_ram_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {mem_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_translator.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {perf_counter_control_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ctl_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sem_ram_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s2_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {mem_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_interface {clk_clk} {clock} {slave};set_interface_property {clk_clk} {EXPORT_OF} {clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {jtag_uart_avalon_jtag_slave} {avalon} {master};set_interface_property {jtag_uart_avalon_jtag_slave} {EXPORT_OF} {jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0};add_interface {mem_s1} {avalon} {master};set_interface_property {mem_s1} {EXPORT_OF} {mem_s1_translator.avalon_anti_slave_0};add_interface {mem_s2} {avalon} {master};set_interface_property {mem_s2} {EXPORT_OF} {mem_s2_translator.avalon_anti_slave_0};add_interface {perf_counter_control_slave} {avalon} {master};set_interface_property {perf_counter_control_slave} {EXPORT_OF} {perf_counter_control_slave_translator.avalon_anti_slave_0};add_interface {sem_ctl_slave} {avalon} {master};set_interface_property {sem_ctl_slave} {EXPORT_OF} {sem_ctl_slave_translator.avalon_anti_slave_0};add_interface {sem_ram_slave} {avalon} {master};set_interface_property {sem_ram_slave} {EXPORT_OF} {sem_ram_slave_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {0};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.jtag_uart.avalon_jtag_slave} {1};set_module_assignment {interconnect_id.mem.s1} {2};set_module_assignment {interconnect_id.mem.s2} {3};set_module_assignment {interconnect_id.perf_counter.control_slave} {4};set_module_assignment {interconnect_id.sem.ctl_slave} {5};set_module_assignment {interconnect_id.sem.ram_slave} {6};set_module_assignment {interconnect_id.sys_clk_timer.s1} {7};" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
@@ -2670,14 +2677,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
@@ -2695,22 +2702,22 @@
name="altera_reset_controller">
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
@@ -2918,46 +2925,46 @@
+
+
+
+
+
+
-
-
-
-
-
-
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
@@ -2991,14 +2998,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
@@ -3281,14 +3288,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
@@ -3335,14 +3342,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
@@ -3454,7 +3461,7 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
@@ -3481,14 +3488,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
@@ -3515,14 +3522,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
@@ -3634,14 +3641,14 @@
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
queue size: 9 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"
mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]>
- C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]>
+ /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]>
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"
mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]>
- C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]>
+ /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]>
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+ path="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+
niosII
diff --git a/Top/niosII/synthesis/submodules/dec.sv b/Top/niosII/synthesis/submodules/dec.sv
index c80033a..e14fc41 100644
--- a/Top/niosII/synthesis/submodules/dec.sv
+++ b/Top/niosII/synthesis/submodules/dec.sv
@@ -83,6 +83,7 @@ module dec
colors <= 3'b001;
state <= GREEN;
end
+
if (train) begin
colors <= 3'b100;
state <= RED;
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc
index ffa3eff..76ab913 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc
@@ -1,4 +1,4 @@
-# Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+# Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
# use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any
# output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
index da7a358..2c443ea 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v
index c866a30..e1065e3 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v
index 646f301..de6c28a 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v
index c292ca3..1a102d9 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif
index aee33b3..2670de9 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif
@@ -7,261 +7,261 @@ DATA_RADIX=HEX;
CONTENT BEGIN
-00 : 88997af9;
-01 : abaae595;
-02 : 32fd14d1;
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-4a : 3ee8b71c;
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-67 : b8c4da74;
-68 : f69070ee;
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-6d : d11663ed;
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-71 : 2edfd7b0;
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-73 : 49535c30;
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-78 : bf8414e4;
-79 : 7451c212;
-7a : 74ede6d2;
-7b : 080eafa5;
-7c : f21052d8;
-7d : cc0819fb;
-7e : 8993e5b6;
-7f : e20f2df6;
-80 : 0f267a65;
-81 : 7a8e8407;
-82 : e7be656d;
-83 : 01ba4ca3;
-84 : 7f998e44;
-85 : 29d83420;
-86 : 149f9a73;
-87 : 643ae51e;
-88 : 125714d3;
-89 : 6e49dc21;
-8a : 0b227946;
-8b : 360a837d;
-8c : b2187074;
-8d : 17b0bdbd;
-8e : 938fc73d;
-8f : e73f501e;
-90 : 70b5b87e;
-91 : 2a2aed8a;
-92 : f96cc881;
-93 : 021b49e1;
-94 : 8691600d;
-95 : b45e1d12;
-96 : 64d9644e;
-97 : 486cbaf9;
-98 : 386acf20;
-99 : 0d1384d4;
-9a : 62455f77;
-9b : 866fde20;
-9c : 006fecec;
-9d : 94e84514;
-9e : 7babc333;
-9f : afaa8445;
-a0 : b1175e3a;
-a1 : e08de629;
-a2 : 7f12a52d;
-a3 : 0e322909;
-a4 : 18784dc6;
-a5 : b23bcc20;
-a6 : 266c9e34;
-a7 : c857eaf3;
-a8 : 2ae3b164;
-a9 : 038acf2a;
-aa : c1abc60d;
-ab : 8af787bd;
-ac : 043723a9;
-ad : c37c952d;
-ae : 693a361f;
-af : da4b8e99;
-b0 : fb8fdb10;
-b1 : 4d6365f2;
-b2 : 712358e9;
-b3 : 85dae0fa;
-b4 : 7e82a418;
-b5 : d3493768;
-b6 : 739c65ec;
-b7 : 73b66b19;
-b8 : 22142816;
-b9 : ff498322;
-ba : 3266495e;
-bb : e26e8214;
-bc : c8c47131;
-bd : 660793d8;
-be : 689f8d69;
-bf : faae340b;
-c0 : 37518ba7;
-c1 : f2865fe5;
-c2 : 1bb44f3d;
-c3 : 3bce44c5;
-c4 : aff2d188;
-c5 : 985442da;
-c6 : 85bb58bd;
-c7 : 0c53135d;
-c8 : 495f80bc;
-c9 : 853c95dc;
-ca : dde937f1;
-cb : 418f9452;
-cc : 7669641c;
-cd : 0e752434;
-ce : b0fe17a7;
-cf : d1be9b88;
-d0 : cfbfeb76;
-d1 : 80b48a11;
-d2 : 9327c69e;
-d3 : beca5a88;
-d4 : e71d428f;
-d5 : b318d275;
-d6 : 56fea35e;
-d7 : 140cd6bd;
-d8 : b8c937ce;
-d9 : 540eea36;
-da : ee58fc7f;
-db : 5615c389;
-dc : 46692ad0;
-dd : 5c713e51;
-de : 6ba95f60;
-df : 0e166732;
-e0 : ac0e49f5;
-e1 : c9a5ea76;
-e2 : 05b04d86;
-e3 : b29ac712;
-e4 : 4e344493;
-e5 : d45ede48;
-e6 : 3da7e426;
-e7 : 4d6a8937;
-e8 : 99b59bd4;
-e9 : 1f8a5751;
-ea : 8b07e64e;
-eb : b4dcd496;
-ec : 42f84fe6;
-ed : f1d5952f;
-ee : a2e5a42d;
-ef : 15b1af16;
-f0 : 168012bc;
-f1 : 2e276612;
-f2 : 89913eaa;
-f3 : c607a1a2;
-f4 : fd8b544d;
-f5 : aec31a53;
-f6 : 25f958ad;
-f7 : 365903ec;
-f8 : 14761865;
-f9 : 568cc23b;
-fa : b0386305;
-fb : fb9ebd8a;
-fc : a25911d4;
-fd : 806e3fbb;
-fe : 9df35264;
-ff : d62b3814;
+00 : 5870e850;
+01 : c7a32b0d;
+02 : 6f82d8fd;
+03 : 40bb3819;
+04 : 03c0b473;
+05 : 8f16cf30;
+06 : d708360b;
+07 : 880f36dc;
+08 : d1a275f0;
+09 : 5944e053;
+0a : c1313a53;
+0b : 4cb0c559;
+0c : 528cd209;
+0d : 1ed6d1c2;
+0e : 3fe378c9;
+0f : aa1b9ac8;
+10 : 31d374f0;
+11 : be61ec44;
+12 : 2c7a1043;
+13 : 2641125e;
+14 : 0c46e1e9;
+15 : 9860f4c3;
+16 : d9980c45;
+17 : 85005ae5;
+18 : b156d9cb;
+19 : 8a5321c3;
+1a : b603ed2b;
+1b : 2a1eb3a0;
+1c : f4b7b88b;
+1d : a1ce694f;
+1e : 469d3811;
+1f : 2185240b;
+20 : a745eb3e;
+21 : 3d2ce9c9;
+22 : e4f87c64;
+23 : 4e473b66;
+24 : f25af5e6;
+25 : 5bf0ba5c;
+26 : d9f793ee;
+27 : a5410324;
+28 : 298d0d25;
+29 : e60402c3;
+2a : 97132679;
+2b : bcd9897b;
+2c : 82a038f5;
+2d : 201cbf45;
+2e : fe6ce958;
+2f : c368dfdf;
+30 : 6a3f8ef7;
+31 : 83368a01;
+32 : 65976a6a;
+33 : 821cfabf;
+34 : 20bdc8df;
+35 : 60d97952;
+36 : 73819628;
+37 : 674070d1;
+38 : fc155d79;
+39 : d3a408b1;
+3a : bfdf2c88;
+3b : 22a2fce0;
+3c : 01e7c505;
+3d : e3e78ba0;
+3e : a049e343;
+3f : c0f1b055;
+40 : 877e1ef1;
+41 : ca871fa5;
+42 : 25ab3e85;
+43 : f9f4b822;
+44 : 90aad39a;
+45 : 08f5e44c;
+46 : 39d12cce;
+47 : 80f2ed6f;
+48 : 6a29b7d6;
+49 : 8b913cf5;
+4a : 63815e88;
+4b : 3b598e73;
+4c : 73bfa5d4;
+4d : 77c09ce3;
+4e : 839a407b;
+4f : 6433730b;
+50 : 44284f24;
+51 : f5d5762e;
+52 : b65d636d;
+53 : d1c786b8;
+54 : f3c8d2f5;
+55 : 356dc558;
+56 : 591772eb;
+57 : 79e0fdb4;
+58 : e8932f59;
+59 : 259d108a;
+5a : bb57a7f8;
+5b : 4825e3bc;
+5c : 52cf4522;
+5d : 79e4316b;
+5e : 8c0d6004;
+5f : a754e118;
+60 : 4e281ca2;
+61 : fbbc819a;
+62 : 4aee7640;
+63 : 7d333e63;
+64 : b15aaa9c;
+65 : 4f43ec26;
+66 : 1ec71c75;
+67 : 8836d7ff;
+68 : 03bf3159;
+69 : 64fe92e3;
+6a : 967a0361;
+6b : 52d392c1;
+6c : ed91cb89;
+6d : 576cc97b;
+6e : 6b3ffb6a;
+6f : 35d248a1;
+70 : f9045e40;
+71 : 67ec2a14;
+72 : c6a8d3b4;
+73 : 215bfb86;
+74 : c69c1f66;
+75 : 4244d56d;
+76 : 1b3928f3;
+77 : 731a2236;
+78 : 38d78b27;
+79 : 059c9248;
+7a : 5f87a44a;
+7b : aba5ed2e;
+7c : c0524059;
+7d : 980abb72;
+7e : 7437c9f5;
+7f : 7eceac74;
+80 : e459de2d;
+81 : 70371382;
+82 : 9e5c9169;
+83 : e019ec71;
+84 : 8a8a254a;
+85 : 5d6b1e75;
+86 : b69a1826;
+87 : 1895f4fa;
+88 : f357cacf;
+89 : d52486ab;
+8a : 1e598442;
+8b : d8d4c72d;
+8c : f8973f5f;
+8d : 7df07844;
+8e : 603c0386;
+8f : 5fa48cd0;
+90 : 7dad0b4e;
+91 : d8063146;
+92 : dd06b1d5;
+93 : a42cea93;
+94 : 937d88ca;
+95 : 0c6e9a23;
+96 : b81bdfa3;
+97 : 28077cf0;
+98 : 9aab97aa;
+99 : b6597e34;
+9a : 436fcd2b;
+9b : be8fe3e1;
+9c : dae80c2f;
+9d : e95b81e6;
+9e : 767f7b1b;
+9f : 23d2190d;
+a0 : dbd13b92;
+a1 : ba04bced;
+a2 : c59ab4a9;
+a3 : d18cd97a;
+a4 : fdc9eef9;
+a5 : e5d3431b;
+a6 : 36145dba;
+a7 : 381901fd;
+a8 : 2b84a31d;
+a9 : 56d3b835;
+aa : 82d83a4f;
+ab : 521d2b9a;
+ac : 0224591a;
+ad : 80d7ea50;
+ae : 49815eac;
+af : 9c8177e2;
+b0 : d83c171d;
+b1 : 82d4e894;
+b2 : 2da7a2cf;
+b3 : ae082f05;
+b4 : ea847ea7;
+b5 : c53a36ee;
+b6 : 9044fe8d;
+b7 : dadb18f9;
+b8 : 3631522b;
+b9 : 2bae3746;
+ba : 02d78d99;
+bb : 8e0e2771;
+bc : 2ed189db;
+bd : 63aa82eb;
+be : 754229af;
+bf : a11062b5;
+c0 : e28618e1;
+c1 : fcaf3400;
+c2 : c8a7faac;
+c3 : be56d9b0;
+c4 : 7c3f3063;
+c5 : 4d331f3f;
+c6 : 8cceb16d;
+c7 : 2d352b5d;
+c8 : 0db6cd22;
+c9 : 745ff58e;
+ca : e450c6d2;
+cb : 5567ae51;
+cc : ec2ac609;
+cd : fcced128;
+ce : 193f8e92;
+cf : 5719a6cc;
+d0 : 065cddb6;
+d1 : 04f4e1f9;
+d2 : a95d8a1e;
+d3 : d516bf8e;
+d4 : e30d671e;
+d5 : ebeeb2fe;
+d6 : b48fdd0f;
+d7 : f4b75c46;
+d8 : 4d9c9650;
+d9 : f2df58d8;
+da : 67ace373;
+db : 7ccace3c;
+dc : f4f3f5d5;
+dd : 2be9f598;
+de : f7889908;
+df : f67c2f07;
+e0 : 880a8491;
+e1 : 9c3967d0;
+e2 : d89b44d2;
+e3 : 7c21987c;
+e4 : 495e0377;
+e5 : 1c88706d;
+e6 : bf0b4325;
+e7 : 79fcc944;
+e8 : fd8c1d81;
+e9 : f4f168ae;
+ea : cf67e751;
+eb : 75907b16;
+ec : d859c7c1;
+ed : 05ef2e02;
+ee : 1f5802c9;
+ef : 8cb4928b;
+f0 : 19e65b5f;
+f1 : 9c3b7bab;
+f2 : 22bc8d7d;
+f3 : 03aa0e5f;
+f4 : 7d35f4ff;
+f5 : e5208a6e;
+f6 : 44fdd477;
+f7 : 74a81f1c;
+f8 : 6936d4f1;
+f9 : 375fc2a2;
+fa : 22a07f26;
+fb : 701c1a4d;
+fc : af4d2557;
+fd : bac85a82;
+fe : 29cff602;
+ff : 3e17ccab;
END;
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
index ed327c5..ca5d3a7 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_jtag_uart.v b/Top/niosII/synthesis/submodules/niosII_jtag_uart.v
index 21f5189..599aab4 100644
--- a/Top/niosII/synthesis/submodules/niosII_jtag_uart.v
+++ b/Top/niosII/synthesis/submodules/niosII_jtag_uart.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_mem.v b/Top/niosII/synthesis/submodules/niosII_mem.v
index 4d4e712..2a6a760 100644
--- a/Top/niosII/synthesis/submodules/niosII_mem.v
+++ b/Top/niosII/synthesis/submodules/niosII_mem.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v b/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v
index 2f2faac..88d7e56 100644
--- a/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v
+++ b/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v
@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
diff --git a/Top/niosII/testbench/mentor/msim_setup.tcl b/Top/niosII/testbench/mentor/msim_setup.tcl
index ab638d8..85f0e82 100644
--- a/Top/niosII/testbench/mentor/msim_setup.tcl
+++ b/Top/niosII/testbench/mentor/msim_setup.tcl
@@ -1,5 +1,5 @@
-# (C) 2001-2022 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
@@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# Initialize variables
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
}
if ![info exists QUARTUS_INSTALL_DIR] {
- set QUARTUS_INSTALL_DIR "C:/software/intelfpga_lite/18.1/quartus/"
+ set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
@@ -142,14 +142,14 @@ if ![ string match "*-64 vsim*" [ vsim -version ] ] {
alias file_copy {
echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
- file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
- file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
- file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
- file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
+ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
+ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
+ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
+ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
}
@@ -280,9 +280,9 @@ alias com {
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
- eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
diff --git a/Top/niosII/testbench/niosII.html b/Top/niosII/testbench/niosII.html
index 923458b..efb9ecc 100644
--- a/Top/niosII/testbench/niosII.html
+++ b/Top/niosII/testbench/niosII.html
@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- 2022.12.24.02:15:37 |
+ 2023.01.17.19:01:29 |
Datasheet |
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- generation took 0,01 seconds |
- rendering took 0,07 seconds |
+ generation took 0.00 seconds |
+ rendering took 0.01 seconds |