diff --git a/.gitignore b/.gitignore
index c394f5e..bdc1f79 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,6 +9,20 @@
/simulation
/.qsys*
# /atom_netlists
+greybox_tmp/
+.qsys_edit/
+synthesis/
+*output_files/
+simulation/
+obj/
+drivers/
+HAL/
+Part_test/
+.metadata/
+RemoteSystemsTempFiles/
+aldec/
+cadence/
+synopsys/
/testbenches/*.bak
@@ -17,3 +31,4 @@
/build/*
!/build/*.pdf
!/build/tikz*.sty
+
diff --git a/Top/.gitignore b/Top/.gitignore
index c394f5e..916133b 100644
--- a/Top/.gitignore
+++ b/Top/.gitignore
@@ -9,6 +9,20 @@
/simulation
/.qsys*
# /atom_netlists
+/greybox_tmp/
+/.qsys_edit/
+/synthesis/
+/*output_files/
+/simulation/
+/obj/
+/drivers/
+/HAL/
+/Part_test/
+/.metadata/
+/RemoteSystemsTempFiles/
+/aldec/
+/cadence/
+/synopsys/
/testbenches/*.bak
@@ -17,3 +31,4 @@
/build/*
!/build/*.pdf
!/build/tikz*.sty
+
diff --git a/Top/Semafor_hw.tcl b/Top/Semafor_hw.tcl
index 12e61bf..7151172 100644
--- a/Top/Semafor_hw.tcl
+++ b/Top/Semafor_hw.tcl
@@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
-# Wed Oct 19 14:12:17 MSK 2022
+# Wed Oct 19 14:56:56 MSK 2022
# DO NOT MODIFY
#
# Semafor "Semafor" v1.0
-# 2022.10.19.14:12:17
+# 2022.10.19.14:56:56
#
#
@@ -43,6 +43,12 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
+add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
+
#
# parameters
@@ -52,6 +58,7 @@ set_parameter_property m DEFAULT_VALUE 8
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
+set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m HDL_PARAMETER true
diff --git a/Top/Semafor_hw.tcl~ b/Top/Semafor_hw.tcl~
new file mode 100644
index 0000000..12e61bf
--- /dev/null
+++ b/Top/Semafor_hw.tcl~
@@ -0,0 +1,181 @@
+# TCL File Generated by Component Editor 18.1
+# Wed Oct 19 14:12:17 MSK 2022
+# DO NOT MODIFY
+
+
+#
+# Semafor "Semafor" v1.0
+# 2022.10.19.14:12:17
+#
+#
+
+#
+# request TCL package from ACDS 16.1
+#
+package require -exact qsys 16.1
+
+
+#
+# module Semafor
+#
+set_module_property DESCRIPTION ""
+set_module_property NAME Semafor
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "User Logic"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME Semafor
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL dec
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
+add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
+
+
+#
+# parameters
+#
+add_parameter m INTEGER 8
+set_parameter_property m DEFAULT_VALUE 8
+set_parameter_property m DISPLAY_NAME m
+set_parameter_property m TYPE INTEGER
+set_parameter_property m UNITS None
+set_parameter_property m HDL_PARAMETER true
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point ctl_slave
+#
+add_interface ctl_slave avalon end
+set_interface_property ctl_slave addressUnits WORDS
+set_interface_property ctl_slave associatedClock clock
+set_interface_property ctl_slave associatedReset reset_n
+set_interface_property ctl_slave bitsPerSymbol 8
+set_interface_property ctl_slave burstOnBurstBoundariesOnly false
+set_interface_property ctl_slave burstcountUnits WORDS
+set_interface_property ctl_slave explicitAddressSpan 0
+set_interface_property ctl_slave holdTime 0
+set_interface_property ctl_slave linewrapBursts false
+set_interface_property ctl_slave maximumPendingReadTransactions 0
+set_interface_property ctl_slave maximumPendingWriteTransactions 0
+set_interface_property ctl_slave readLatency 0
+set_interface_property ctl_slave readWaitStates 0
+set_interface_property ctl_slave readWaitTime 0
+set_interface_property ctl_slave setupTime 0
+set_interface_property ctl_slave timingUnits Cycles
+set_interface_property ctl_slave writeWaitTime 0
+set_interface_property ctl_slave ENABLED true
+set_interface_property ctl_slave EXPORT_OF ""
+set_interface_property ctl_slave PORT_NAME_MAP ""
+set_interface_property ctl_slave CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_slave ctl_wr write Input 1
+add_interface_port ctl_slave ctl_rd read Input 1
+add_interface_port ctl_slave ctl_addr address Input 1
+add_interface_port ctl_slave ctl_wrdata writedata Input 32
+add_interface_port ctl_slave ctl_rddata readdata Output 32
+set_interface_assignment ctl_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment ctl_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ctl_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ctl_slave embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point reset_n
+#
+add_interface reset_n reset end
+set_interface_property reset_n associatedClock clock
+set_interface_property reset_n synchronousEdges DEASSERT
+set_interface_property reset_n ENABLED true
+set_interface_property reset_n EXPORT_OF ""
+set_interface_property reset_n PORT_NAME_MAP ""
+set_interface_property reset_n CMSIS_SVD_VARIABLES ""
+set_interface_property reset_n SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_n clrn reset_n Input 1
+
+
+#
+# connection point ram_slave
+#
+add_interface ram_slave avalon end
+set_interface_property ram_slave addressUnits WORDS
+set_interface_property ram_slave associatedClock clock
+set_interface_property ram_slave associatedReset reset_n
+set_interface_property ram_slave bitsPerSymbol 8
+set_interface_property ram_slave burstOnBurstBoundariesOnly false
+set_interface_property ram_slave burstcountUnits WORDS
+set_interface_property ram_slave explicitAddressSpan 0
+set_interface_property ram_slave holdTime 0
+set_interface_property ram_slave linewrapBursts false
+set_interface_property ram_slave maximumPendingReadTransactions 0
+set_interface_property ram_slave maximumPendingWriteTransactions 0
+set_interface_property ram_slave readLatency 0
+set_interface_property ram_slave readWaitTime 1
+set_interface_property ram_slave setupTime 0
+set_interface_property ram_slave timingUnits Cycles
+set_interface_property ram_slave writeWaitTime 0
+set_interface_property ram_slave ENABLED true
+set_interface_property ram_slave EXPORT_OF ""
+set_interface_property ram_slave PORT_NAME_MAP ""
+set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
+set_interface_property ram_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_slave ram_wr write Input 1
+add_interface_port ram_slave ram_addr address Input 2
+add_interface_port ram_slave ram_wrdata writedata Input 32
+set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ram_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ram_slave embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point sem
+#
+add_interface sem conduit end
+set_interface_property sem associatedClock ""
+set_interface_property sem associatedReset reset_n
+set_interface_property sem ENABLED true
+set_interface_property sem EXPORT_OF ""
+set_interface_property sem PORT_NAME_MAP ""
+set_interface_property sem CMSIS_SVD_VARIABLES ""
+set_interface_property sem SVD_ADDRESS_GROUP ""
+
+add_interface_port sem train train Input 1
+add_interface_port sem red red Output 1
+add_interface_port sem yellow yellow Output 1
+add_interface_port sem green green Output 1
+
diff --git a/Top/niosII.qsys b/Top/niosII.qsys
index 20542f3..5971194 100644
--- a/Top/niosII.qsys
+++ b/Top/niosII.qsys
@@ -346,7 +346,7 @@
version="18.1"
enabled="1">
-
+
diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo
index 554f29c..e877c12 100644
--- a/Top/niosII.sopcinfo
+++ b/Top/niosII.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1666174998
+ 1666177115
false
true
false
diff --git a/Top/niosII/niosII.bsf b/Top/niosII/niosII.bsf
index c61f1b7..3f01ac6 100644
--- a/Top/niosII/niosII.bsf
+++ b/Top/niosII/niosII.bsf
@@ -75,7 +75,7 @@ refer to the applicable agreement for further details.
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
- (text " niosII " (rect 262 216 572 442)(font "Arial" ))
+ (text " system " (rect 253 216 554 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1))
diff --git a/Top/niosII/testbench/mentor/msim_setup.tcl b/Top/niosII/testbench/mentor/msim_setup.tcl
new file mode 100644
index 0000000..dfb0e0e
--- /dev/null
+++ b/Top/niosII/testbench/mentor/msim_setup.tcl
@@ -0,0 +1,376 @@
+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# niosII_tb
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR