From b163d17ea5d2cee4ccd8f3ac871fe5f72d457f64 Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Tue, 18 Oct 2022 16:30:42 +0300 Subject: [PATCH] pt1.2 added new project, modeling, waveform --- Testbench/dec/.gitignore | 19 +++++++++++ Testbench/dec/dec.qsf | 67 +++++++++++++++++++++++++++++++++++++++ Testbench/dec/semafor.qpf | 30 ++++++++++++++++++ Testbench/dec/wave.do | 35 ++++++++++++++++++++ 4 files changed, 151 insertions(+) create mode 100644 Testbench/dec/.gitignore create mode 100644 Testbench/dec/dec.qsf create mode 100644 Testbench/dec/semafor.qpf create mode 100644 Testbench/dec/wave.do diff --git a/Testbench/dec/.gitignore b/Testbench/dec/.gitignore new file mode 100644 index 0000000..c394f5e --- /dev/null +++ b/Testbench/dec/.gitignore @@ -0,0 +1,19 @@ +*.pdf +*.rpt +*.bak +.#* + +/db +/incremental_db +/output_files +/simulation +/.qsys* +# /atom_netlists + + +/testbenches/*.bak +/common_uart/*.bak + +/build/* +!/build/*.pdf +!/build/tikz*.sty diff --git a/Testbench/dec/dec.qsf b/Testbench/dec/dec.qsf new file mode 100644 index 0000000..8490cb1 --- /dev/null +++ b/Testbench/dec/dec.qsf @@ -0,0 +1,67 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 16:14:06 October 18, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# dec_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22A7 +set_global_assignment -name TOP_LEVEL_ENTITY dec +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06 OCTOBER 18, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip +set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv +set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb +set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb \ No newline at end of file diff --git a/Testbench/dec/semafor.qpf b/Testbench/dec/semafor.qpf new file mode 100644 index 0000000..23f10ea --- /dev/null +++ b/Testbench/dec/semafor.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 16:14:06 October 18, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "16:14:06 October 18, 2022" + +# Revisions + +PROJECT_REVISION = "dec" diff --git a/Testbench/dec/wave.do b/Testbench/dec/wave.do new file mode 100644 index 0000000..d3f216b --- /dev/null +++ b/Testbench/dec/wave.do @@ -0,0 +1,35 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /dec_tb/clk +add wave -noupdate /dec_tb/clrn +add wave -noupdate /dec_tb/train +add wave -noupdate /dec_tb/r +add wave -noupdate /dec_tb/y +add wave -noupdate /dec_tb/g +add wave -noupdate /dec_tb/div +add wave -noupdate /dec_tb/ctl_wr +add wave -noupdate /dec_tb/ctl_rd +add wave -noupdate /dec_tb/ctl_addr +add wave -noupdate /dec_tb/ctl_wrdata +add wave -noupdate /dec_tb/ctl_rddata +add wave -noupdate /dec_tb/ram_wr +add wave -noupdate /dec_tb/ram_addr +add wave -noupdate /dec_tb/ram_wrdata +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3346003 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {15928500 ps}