From b86b8e55dc86b9ac22fcd6ff9cda635b3383c2cb Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Sat, 24 Dec 2022 02:08:20 +0300 Subject: [PATCH] simulated individual, looks ok --- HDL/dec.sv | 273 ++++++++++-------- Testbench/dec/#dec_tb.sv# | 128 ++++++++ Testbench/dec/dec.qsf | 1 + Testbench/dec/dec_tb.sv | 8 +- Top/Semafor_hw.tcl | 4 +- Top/Semafor_hw.tcl~ | 6 +- Top/niosII.sopcinfo | 4 +- Top/niosII/niosII.html | 6 +- Top/niosII/niosII.xml | 188 ++++++------ Top/niosII/synthesis/niosII.debuginfo | 6 +- Top/niosII/synthesis/niosII.qip | 4 +- Top/niosII/synthesis/submodules/dec.sv | 273 ++++++++++-------- Top/niosII/testbench/mentor/msim_setup.tcl | 2 +- Top/niosII/testbench/niosII.html | 6 +- Top/niosII/testbench/niosII_tb.html | 8 +- .../niosII_tb/simulation/niosII_tb.v | 67 +++-- .../testbench/synopsys/vcs/vcs_setup.sh | 4 +- .../testbench/synopsys/vcsmx/vcsmx_setup.sh | 4 +- Top/niosII_tb.csv | 6 +- Top/semafor.qws | Bin 0 -> 619 bytes .../RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf | Bin 490538 -> 490538 bytes .../RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump | 4 +- .../semafor/mem_init/hdl_sim/niosII_mem.dat | 16 +- Top/software/semafor/mem_init/niosII_mem.hex | 2 +- Top/software/semafor/sem.c | 4 +- Top/software/semafor/transcript | 7 + Top/software/semafor_bsp/settings.bsp | 4 +- Top/software/semafor_bsp/summary.html | 4 +- 28 files changed, 622 insertions(+), 417 deletions(-) create mode 100644 Testbench/dec/#dec_tb.sv# create mode 100644 Top/semafor.qws diff --git a/HDL/dec.sv b/HDL/dec.sv index f9f5926..c80033a 100644 --- a/HDL/dec.sv +++ b/HDL/dec.sv @@ -1,132 +1,157 @@ module dec -#(m = 32) -( - //clock and reset - input logic clk, clrn, - //control slave - input logic ctl_wr, ctl_rd, - input logic ctl_addr, - input logic [31:0] ctl_wrdata, - output logic [31:0] ctl_rddata, - //memory slave - input logic ram_wr, - input logic [3:0] ram_addr, - input logic [31:0] ram_wrdata, - //external ports - input logic train, - output logic red, yellow, green -); - - logic run; - logic [1:0] divider; - - logic [m-1:0] divisor; - logic [1:0] contr; - logic [2:0] colors; - logic [m-1:0] cntdiv; - logic enacnt; + #(m = 32) + ( + //clock and reset + input logic clk, clrn, + //control slave + input logic ctl_wr, ctl_rd, + input logic ctl_addr, + input logic [31:0] ctl_wrdata, + output logic [31:0] ctl_rddata, + //memory slave + input logic ram_wr, + input logic [3:0] ram_addr, + input logic [31:0] ram_wrdata, + //external ports + input logic train, + output logic red, yellow, green + ); - //control slave logic - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) - begin - run <= 0; - divider <= 0; - end - else - begin - if (ctl_wr) - begin - case (ctl_addr) - 1'b0: run <= ctl_wrdata[0]; - 1'b1: divider <= ctl_wrdata[1:0]; - endcase - end - end - end - - always_comb - begin - case (ctl_addr) - 1'b0: ctl_rddata = {31'b0,run}; - 1'b1: ctl_rddata = {30'b0,divider}; - default: ctl_rddata = 'bx; - endcase - end - - //semaphore logic - - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) cntdiv<=0; - else - begin - if (train | ~run) cntdiv<=0; - else - begin - if (enacnt) cntdiv<=0; - else cntdiv<=cntdiv+1; - end - end - end - - always_comb - begin - enacnt=(cntdiv==divisor); - end - - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) - begin - colors <= 3'b100; - end - else - begin - if (train | ~run) - begin - colors <= 3'b100; - end - else - begin - if (enacnt) - begin - case (colors) - 3'b100: colors <= 3'b010; - 3'b010: colors <= 3'b011; - 3'b011: colors <= 3'b001; - 3'b001: colors <= 3'b001; - default: colors <= 3'b100; - endcase - end - end - end - end - - always_comb - begin - case (colors) - 3'b100: contr = 2'b00; - 3'b010: contr = 2'b01; - 3'b011: contr = 2'b10; - 3'b001: contr = 2'b11; - default : contr = 2'b00; + typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates; + + logic run; + logic [1:0] divider; + logic [1:0] state; + logic [31:0] greenSaved; + logic [31:0] greenCount; + + logic [m-1:0] divisor; + logic [1:0] contr; + logic [2:0] colors; + logic [m-1:0] cntdiv; + logic enacnt; + + //control slave logic + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) begin + run <= 0; + divider <= 0; + end else begin + if (ctl_wr) begin + case (ctl_addr) + 1'b0: run <= ctl_wrdata[0]; + 1'b1: divider <= ctl_wrdata[1:0]; + endcase + end + end + end + + always_comb begin + case (ctl_addr) + 1'b0: ctl_rddata = {31'b0,run}; + 1'b1: ctl_rddata = {30'b0,divider}; + default: ctl_rddata = 'bx; endcase end - - assign red = colors[2]; - assign yellow = colors[1]; - assign green = colors[0]; - periodram b2v_inst3( - .clock(clk), - .data (ram_wrdata), - .wraddress (ram_addr), - .wren (ram_wr), - .rdaddress({divider,contr}), - .q(divisor) - ); + //semaphore logic + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) + cntdiv <= 0; + else begin + if (train | ~run) + cntdiv<=0; + else begin + if (enacnt) cntdiv<=0; + else cntdiv<=cntdiv+1; + end + end + end + + // we don't enable counters, if color is green + always_comb begin + enacnt = ((cntdiv == divisor) && !(colors == 3'b001)); + end + + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) begin + colors <= 3'b001; + state <= GREEN; + greenCount <= 32'd0; + end else begin + if (~run) begin + colors <= 3'b001; + state <= GREEN; + end + if (train) begin + colors <= 3'b100; + state <= RED; + greenSaved <= divisor; + greenCount <= divisor; + end else begin + case (state) + RED: begin + colors <= 3'b100; + if (enacnt) begin + state <= state + 1'b1; + greenSaved <= divisor; + end + end + YELLOW: begin + colors <= 3'b010; + if (enacnt) begin + state <= state + 1'b1; + end + end + BLINK: begin + if (enacnt) begin + state <= state + 1'b1; + end + if (greenSaved[0] == 0) begin + colors <= 3'b011; + end else begin + greenCount <= greenCount - 1'b1; + if (greenCount == 32'd0) begin + colors[1] <= ~colors[1]; + greenCount <= greenSaved; + end + end + end + GREEN: begin + if (enacnt) begin + state <= state + 1'b1; + end + colors <= 3'b001; + end + default: colors <= 3'b100; + endcase + end + end + end + assign contr = state; + // always_comb begin + // case (state) + // 2'b00: contr = 2'b00; + // 2'b01: contr = 2'b01; + // 2'b10: contr = 2'b10; + // 2'b11: contr = 2'b11; + // default : contr = 2'b00; + // endcase + // end + + assign red = colors[2]; + assign yellow = colors[1]; + assign green = colors[0]; + + periodram b2v_inst3 + ( + .clock(clk), + .data (ram_wrdata), + .wraddress (ram_addr), + .wren (ram_wr), + .rdaddress({divider,contr}), + .q(divisor) + ); endmodule diff --git a/Testbench/dec/#dec_tb.sv# b/Testbench/dec/#dec_tb.sv# new file mode 100644 index 0000000..00becc7 --- /dev/null +++ b/Testbench/dec/#dec_tb.sv# @@ -0,0 +1,128 @@ +`timescale 1 ns/1 ns + +module dec_tb(); + + // Wires and variables to connect to UUT (unit under test) + logic clk, clrn, train; + logic r, y, g; + logic [1:0] div; + logic ctl_wr, ctl_rd; + logic ctl_addr; + logic [31:0] ctl_wrdata; + logic [31:0] ctl_rddata; + logic ram_wr; + logic [3:0] ram_addr; + logic [31:0] ram_wrdata; + + logic [31:0] divisor[3:0] = { + {8'd10, 8'd70, 8'd50, 8'd20}, + {8'd10, 8'd30, 8'd40, 8'd30}, + {8'd10, 8'd30, 8'd10, 8'd100}, + {8'd10, 8'd60, 8'd80, 8'd50} + }; + + // Instantiate UUT + dec my_sem( + .clk(clk), .clrn(clrn), + .ctl_wr(ctl_wr), .ctl_rd(ctl_rd), + .ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata), + .ram_wr(ram_wr), + .ram_addr(ram_addr), .ram_wrdata(ram_wrdata), + .train(train), .red(r), .yellow(y), .green(g) + ); + + // Clock definition + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Divisor and train definition + initial begin + //initial reset + clrn = 0; + div = 0; + train = 0; + //take reset off + @(negedge clk) clrn = 1; + //configure semaphore + for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM + write_reg_transaction(1,div); //write initial divisor + write_reg_transaction(0,1); //enable semaphore + //run trains + repeat (4) + begin + repeat (10) @(posedge clk); + train=1; + repeat (4) @(posedge clk); + train=0; + wait ({r,y,g}==3'b001); + repeat (10) @(posedge clk); + write_reg_transaction(1,div); + div=div+1; + end + //wait a little + repeat (10) @(posedge clk); + $stop; + end + + //Single register write transaction task + task write_reg_transaction; + //input signals + input [1:0] offs; + input [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ctl_wr = 1; + ctl_addr = offs; + ctl_wrdata = val; + @(posedge clk); + //deassert signals + ctl_wr = 0; + ctl_addr = 'bx; + ctl_wrdata = 'bx; + end + endtask + + //Single register read transaction task + task read_reg_transaction; + //input signals + input [1:0] offs; + output [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ctl_rd = 1; + ctl_addr = offs; + @(posedge clk); + val = ctl_rddata; + //deassert signals + ctl_rd = 0; + ctl_addr = 'bx; + end + endtask + + //RAM write transaction task + task write_ram_transaction; + //input signals + input [1:0] offs; + input [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ram_wr = 1; + ram_addr = offs; + ram_wrdata = val; + @(posedge clk); + //deassert signals + ram_wr = 0; + ram_addr = 'bx; + ram_wrdata = 'bx; + end + endtask + +endmodule diff --git a/Testbench/dec/dec.qsf b/Testbench/dec/dec.qsf index 11fde70..ed09ddb 100644 --- a/Testbench/dec/dec.qsf +++ b/Testbench/dec/dec.qsf @@ -65,4 +65,5 @@ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb set_global_assignment -name HEX_FILE periodram.hex +set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Testbench/dec/dec_tb.sv b/Testbench/dec/dec_tb.sv index 31200fa..7fe63df 100644 --- a/Testbench/dec/dec_tb.sv +++ b/Testbench/dec/dec_tb.sv @@ -15,10 +15,10 @@ module dec_tb(); logic [31:0] ram_wrdata; logic [31:0] divisor[3:0] = { - {8'd10, 8'd70, 8'd50, 8'd20}, - {8'd10, 8'd30, 8'd40, 8'd30}, - {8'd10, 8'd30, 8'd10, 8'd100}, - {8'd10, 8'd60, 8'd80, 8'd50} + {8'd11, 8'd71, 8'd51, 8'd21}, + {8'd11, 8'd31, 8'd41, 8'd31}, + {8'd11, 8'd31, 8'd11, 8'd101}, + {8'd11, 8'd61, 8'd81, 8'd51} }; // Instantiate UUT diff --git a/Top/Semafor_hw.tcl b/Top/Semafor_hw.tcl index 81f38ae..7e196e5 100644 --- a/Top/Semafor_hw.tcl +++ b/Top/Semafor_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Thu Dec 22 22:35:53 MSK 2022 +# Sat Dec 24 02:15:19 MSK 2022 # DO NOT MODIFY # # sem "Semafor" v1.1 -# 2022.12.22.22:35:53 +# 2022.12.24.02:15:19 # # diff --git a/Top/Semafor_hw.tcl~ b/Top/Semafor_hw.tcl~ index 6f9fa28..5899d01 100644 --- a/Top/Semafor_hw.tcl~ +++ b/Top/Semafor_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Wed Dec 21 21:00:10 MSK 2022 +# Sat Dec 24 01:52:10 MSK 2022 # DO NOT MODIFY # # sem "Semafor" v1.1 -# 2022.12.21.21:00:10 +# 2022.12.24.01:52:10 # # @@ -163,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES "" set_interface_property ram_slave SVD_ADDRESS_GROUP "" add_interface_port ram_slave ram_wr write Input 1 -add_interface_port ram_slave ram_addr address Input 2 +add_interface_port ram_slave ram_addr address Input 4 add_interface_port ram_slave ram_wrdata writedata Input 32 set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0 set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0 diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo index 08e5c97..0f955c5 100644 --- a/Top/niosII.sopcinfo +++ b/Top/niosII.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1671734311 + 1671833790 false true false diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html index 9411a31..b1d525b 100644 --- a/Top/niosII/niosII.html +++ b/Top/niosII/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.22.22:37:232022.12.24.02:16:30 Datasheet
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - - + +
generation took 0,01 secondsrendering took 0,08 secondsgeneration took 0,00 secondsrendering took 0,03 seconds
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml index 3ace025..73d6d07 100644 --- a/Top/niosII/niosII.xml +++ b/Top/niosII/niosII.xml @@ -1,6 +1,6 @@ - + @@ -607,36 +607,36 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.22 21:37:54 (*) Starting Nios II generation - # 2022.12.22 21:37:54 (*) Checking for plaintext license. - # 2022.12.22 21:37:55 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.22 21:37:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.22 21:37:55 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.22 21:37:55 (*) Plaintext license not found. - # 2022.12.22 21:37:55 (*) No license required to generate encrypted Nios II/e. - # 2022.12.22 21:37:55 (*) Elaborating CPU configuration settings - # 2022.12.22 21:37:55 (*) Creating all objects for CPU - # 2022.12.22 21:37:57 (*) Generating RTL from CPU objects - # 2022.12.22 21:37:57 (*) Creating plain-text RTL - # 2022.12.22 21:37:58 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 01:16:53 (*) Starting Nios II generation + # 2022.12.24 01:16:53 (*) Checking for plaintext license. + # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 01:16:54 (*) Plaintext license not found. + # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings + # 2022.12.24 01:16:54 (*) Creating all objects for CPU + # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects + # 2022.12.24 01:16:55 (*) Creating plain-text RTL + # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> queue size: 5 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" @@ -880,58 +880,58 @@ Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.000s - Timing: ELA:2/0.008s/0.016s - Timing: ELA:1/0.000s - Timing: COM:3/0.070s/0.093s + Timing: ELA:1/0.001s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.027s + Timing: COM:3/0.052s/0.076s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.031s/0.042s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.011s + Timing: COM:3/0.021s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.027s/0.034s + Timing: ELA:1/0.009s + Timing: COM:3/0.019s/0.025s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.018s - Timing: COM:3/0.028s/0.031s + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.011s + Timing: COM:3/0.021s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.008s/0.016s - Timing: ELA:1/0.000s - Timing: COM:3/0.025s/0.029s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.010s + Timing: COM:3/0.024s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.016s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.031s/0.042s + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.008s + Timing: COM:3/0.019s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.006s - Timing: COM:3/0.027s/0.035s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.011s + Timing: COM:3/0.022s/0.028s 61 modules, 199 connections]]> @@ -1334,19 +1334,19 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.22 21:37:54 (*) Starting Nios II generation - # 2022.12.22 21:37:54 (*) Checking for plaintext license. - # 2022.12.22 21:37:55 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.22 21:37:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.22 21:37:55 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.22 21:37:55 (*) Plaintext license not found. - # 2022.12.22 21:37:55 (*) No license required to generate encrypted Nios II/e. - # 2022.12.22 21:37:55 (*) Elaborating CPU configuration settings - # 2022.12.22 21:37:55 (*) Creating all objects for CPU - # 2022.12.22 21:37:57 (*) Generating RTL from CPU objects - # 2022.12.22 21:37:57 (*) Creating plain-text RTL - # 2022.12.22 21:37:58 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 01:16:53 (*) Starting Nios II generation + # 2022.12.24 01:16:53 (*) Checking for plaintext license. + # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 01:16:54 (*) Plaintext license not found. + # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings + # 2022.12.24 01:16:54 (*) Creating all objects for CPU + # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects + # 2022.12.24 01:16:55 (*) Creating plain-text RTL + # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> @@ -1390,7 +1390,7 @@ queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> @@ -1459,7 +1459,7 @@ queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> @@ -1533,7 +1533,7 @@ queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> @@ -2128,58 +2128,58 @@ Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.000s - Timing: ELA:2/0.008s/0.016s - Timing: ELA:1/0.000s - Timing: COM:3/0.070s/0.093s + Timing: ELA:1/0.001s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.027s + Timing: COM:3/0.052s/0.076s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.031s/0.042s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.011s + Timing: COM:3/0.021s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.027s/0.034s + Timing: ELA:1/0.009s + Timing: COM:3/0.019s/0.025s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.018s - Timing: COM:3/0.028s/0.031s + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.011s + Timing: COM:3/0.021s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s - Timing: ELA:2/0.008s/0.016s - Timing: ELA:1/0.000s - Timing: COM:3/0.025s/0.029s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.010s + Timing: COM:3/0.024s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.016s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.031s/0.042s + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.008s + Timing: COM:3/0.019s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.006s - Timing: COM:3/0.027s/0.035s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.011s + Timing: COM:3/0.022s/0.028s 61 modules, 199 connections]]> @@ -2605,19 +2605,19 @@ queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9348_4173096401569860192.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.22 21:37:54 (*) Starting Nios II generation - # 2022.12.22 21:37:54 (*) Checking for plaintext license. - # 2022.12.22 21:37:55 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.22 21:37:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.22 21:37:55 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.22 21:37:55 (*) Plaintext license not found. - # 2022.12.22 21:37:55 (*) No license required to generate encrypted Nios II/e. - # 2022.12.22 21:37:55 (*) Elaborating CPU configuration settings - # 2022.12.22 21:37:55 (*) Creating all objects for CPU - # 2022.12.22 21:37:57 (*) Generating RTL from CPU objects - # 2022.12.22 21:37:57 (*) Creating plain-text RTL - # 2022.12.22 21:37:58 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.24 01:16:53 (*) Starting Nios II generation + # 2022.12.24 01:16:53 (*) Checking for plaintext license. + # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.24 01:16:54 (*) Plaintext license not found. + # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. + # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings + # 2022.12.24 01:16:54 (*) Creating all objects for CPU + # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects + # 2022.12.24 01:16:55 (*) Creating plain-text RTL + # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> diff --git a/Top/niosII/synthesis/niosII.debuginfo b/Top/niosII/synthesis/niosII.debuginfo index a198dd4..0b4d440 100644 --- a/Top/niosII/synthesis/niosII.debuginfo +++ b/Top/niosII/synthesis/niosII.debuginfo @@ -1,7 +1,7 @@ - + com.altera.sopcmodel.ensemble.EClockAdapter @@ -53,7 +53,7 @@ int - 1671734242 + 1671833790 false true true @@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. --> 18.1 18.1 625 - 7A31C1D08890000001853B204A2B + 7A31C1D0889000000185410F37E7 diff --git a/Top/niosII/synthesis/niosII.qip b/Top/niosII/synthesis/niosII.qip index c5dc854..08a5253 100644 --- a/Top/niosII/synthesis/niosII.qip +++ b/Top/niosII/synthesis/niosII.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] -set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671734242" +set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790" set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] @@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTczNDI0Mg==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" diff --git a/Top/niosII/synthesis/submodules/dec.sv b/Top/niosII/synthesis/submodules/dec.sv index f9f5926..c80033a 100644 --- a/Top/niosII/synthesis/submodules/dec.sv +++ b/Top/niosII/synthesis/submodules/dec.sv @@ -1,132 +1,157 @@ module dec -#(m = 32) -( - //clock and reset - input logic clk, clrn, - //control slave - input logic ctl_wr, ctl_rd, - input logic ctl_addr, - input logic [31:0] ctl_wrdata, - output logic [31:0] ctl_rddata, - //memory slave - input logic ram_wr, - input logic [3:0] ram_addr, - input logic [31:0] ram_wrdata, - //external ports - input logic train, - output logic red, yellow, green -); - - logic run; - logic [1:0] divider; - - logic [m-1:0] divisor; - logic [1:0] contr; - logic [2:0] colors; - logic [m-1:0] cntdiv; - logic enacnt; + #(m = 32) + ( + //clock and reset + input logic clk, clrn, + //control slave + input logic ctl_wr, ctl_rd, + input logic ctl_addr, + input logic [31:0] ctl_wrdata, + output logic [31:0] ctl_rddata, + //memory slave + input logic ram_wr, + input logic [3:0] ram_addr, + input logic [31:0] ram_wrdata, + //external ports + input logic train, + output logic red, yellow, green + ); - //control slave logic - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) - begin - run <= 0; - divider <= 0; - end - else - begin - if (ctl_wr) - begin - case (ctl_addr) - 1'b0: run <= ctl_wrdata[0]; - 1'b1: divider <= ctl_wrdata[1:0]; - endcase - end - end - end - - always_comb - begin - case (ctl_addr) - 1'b0: ctl_rddata = {31'b0,run}; - 1'b1: ctl_rddata = {30'b0,divider}; - default: ctl_rddata = 'bx; - endcase - end - - //semaphore logic - - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) cntdiv<=0; - else - begin - if (train | ~run) cntdiv<=0; - else - begin - if (enacnt) cntdiv<=0; - else cntdiv<=cntdiv+1; - end - end - end - - always_comb - begin - enacnt=(cntdiv==divisor); - end - - always_ff @ (posedge clk or negedge clrn) - begin - if (!clrn) - begin - colors <= 3'b100; - end - else - begin - if (train | ~run) - begin - colors <= 3'b100; - end - else - begin - if (enacnt) - begin - case (colors) - 3'b100: colors <= 3'b010; - 3'b010: colors <= 3'b011; - 3'b011: colors <= 3'b001; - 3'b001: colors <= 3'b001; - default: colors <= 3'b100; - endcase - end - end - end - end - - always_comb - begin - case (colors) - 3'b100: contr = 2'b00; - 3'b010: contr = 2'b01; - 3'b011: contr = 2'b10; - 3'b001: contr = 2'b11; - default : contr = 2'b00; + typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates; + + logic run; + logic [1:0] divider; + logic [1:0] state; + logic [31:0] greenSaved; + logic [31:0] greenCount; + + logic [m-1:0] divisor; + logic [1:0] contr; + logic [2:0] colors; + logic [m-1:0] cntdiv; + logic enacnt; + + //control slave logic + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) begin + run <= 0; + divider <= 0; + end else begin + if (ctl_wr) begin + case (ctl_addr) + 1'b0: run <= ctl_wrdata[0]; + 1'b1: divider <= ctl_wrdata[1:0]; + endcase + end + end + end + + always_comb begin + case (ctl_addr) + 1'b0: ctl_rddata = {31'b0,run}; + 1'b1: ctl_rddata = {30'b0,divider}; + default: ctl_rddata = 'bx; endcase end - - assign red = colors[2]; - assign yellow = colors[1]; - assign green = colors[0]; - periodram b2v_inst3( - .clock(clk), - .data (ram_wrdata), - .wraddress (ram_addr), - .wren (ram_wr), - .rdaddress({divider,contr}), - .q(divisor) - ); + //semaphore logic + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) + cntdiv <= 0; + else begin + if (train | ~run) + cntdiv<=0; + else begin + if (enacnt) cntdiv<=0; + else cntdiv<=cntdiv+1; + end + end + end + + // we don't enable counters, if color is green + always_comb begin + enacnt = ((cntdiv == divisor) && !(colors == 3'b001)); + end + + always_ff @ (posedge clk or negedge clrn) begin + if (!clrn) begin + colors <= 3'b001; + state <= GREEN; + greenCount <= 32'd0; + end else begin + if (~run) begin + colors <= 3'b001; + state <= GREEN; + end + if (train) begin + colors <= 3'b100; + state <= RED; + greenSaved <= divisor; + greenCount <= divisor; + end else begin + case (state) + RED: begin + colors <= 3'b100; + if (enacnt) begin + state <= state + 1'b1; + greenSaved <= divisor; + end + end + YELLOW: begin + colors <= 3'b010; + if (enacnt) begin + state <= state + 1'b1; + end + end + BLINK: begin + if (enacnt) begin + state <= state + 1'b1; + end + if (greenSaved[0] == 0) begin + colors <= 3'b011; + end else begin + greenCount <= greenCount - 1'b1; + if (greenCount == 32'd0) begin + colors[1] <= ~colors[1]; + greenCount <= greenSaved; + end + end + end + GREEN: begin + if (enacnt) begin + state <= state + 1'b1; + end + colors <= 3'b001; + end + default: colors <= 3'b100; + endcase + end + end + end + assign contr = state; + // always_comb begin + // case (state) + // 2'b00: contr = 2'b00; + // 2'b01: contr = 2'b01; + // 2'b10: contr = 2'b10; + // 2'b11: contr = 2'b11; + // default : contr = 2'b00; + // endcase + // end + + assign red = colors[2]; + assign yellow = colors[1]; + assign green = colors[0]; + + periodram b2v_inst3 + ( + .clock(clk), + .data (ram_wrdata), + .wraddress (ram_addr), + .wren (ram_wr), + .rdaddress({divider,contr}), + .q(divisor) + ); endmodule diff --git a/Top/niosII/testbench/mentor/msim_setup.tcl b/Top/niosII/testbench/mentor/msim_setup.tcl index 8c23f8d..ab638d8 100644 --- a/Top/niosII/testbench/mentor/msim_setup.tcl +++ b/Top/niosII/testbench/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.22.22:39:16 +# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ---------------------------------------- # Initialize variables diff --git a/Top/niosII/testbench/niosII.html b/Top/niosII/testbench/niosII.html index 2395075..923458b 100644 --- a/Top/niosII/testbench/niosII.html +++ b/Top/niosII/testbench/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.22.22:38:312022.12.24.02:15:37 Datasheet
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - - + +
generation took 0,00 secondsrendering took 0,04 secondsgeneration took 0,01 secondsrendering took 0,07 seconds
diff --git a/Top/niosII/testbench/niosII_tb.html b/Top/niosII/testbench/niosII_tb.html index 565cdfd..dd5f5f1 100644 --- a/Top/niosII/testbench/niosII_tb.html +++ b/Top/niosII/testbench/niosII_tb.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.22.22:38:422022.12.24.02:15:47 Datasheet
@@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
AUTO_GENERATION_ID16717343221671833747
AUTO_UNIQUE_ID
- - + +
generation took 0,02 secondsrendering took 0,05 secondsgeneration took 0,01 secondsrendering took 0,06 seconds
diff --git a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v index 0ebbcef..8ce3bb0 100644 --- a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v +++ b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v @@ -1,35 +1,42 @@ `timescale 1 ps / 1 ps module niosII_tb ( -); + ); - wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk] - wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n + wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk] + wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n reg train; wire red, yellow, green; - niosII niosii_inst ( - .clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk - .reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n - .sem_export_train (train), // sem_export.train - .sem_export_red (red), // .red - .sem_export_yellow (yellow), // .yellow - .sem_export_green (green) // .green - ); + niosII niosii_inst + ( + .clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk + .reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n + .sem_export_train (train), // sem_export.train + .sem_export_red (red), // .red + .sem_export_yellow (yellow), // .yellow + .sem_export_green (green) // .green + ); - altera_avalon_clock_source #( - .CLOCK_RATE (50000000), - .CLOCK_UNIT (1) - ) niosii_inst_clk_bfm ( - .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk - ); + altera_avalon_clock_source + #( + .CLOCK_RATE (50000000), + .CLOCK_UNIT (1) + ) + niosii_inst_clk_bfm + ( + .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk + ); - altera_avalon_reset_source #( - .ASSERT_HIGH_RESET (0), - .INITIAL_RESET_CYCLES (50) - ) niosii_inst_reset_bfm ( - .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n - .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk - ); + altera_avalon_reset_source + #( + .ASSERT_HIGH_RESET (0), + .INITIAL_RESET_CYCLES (50) + ) + niosii_inst_reset_bfm + ( + .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n + .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk + ); initial begin train = 0; @@ -39,6 +46,18 @@ module niosII_tb ( train = 1; repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); train = 0; + repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 1; + repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 0; + repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 1; + repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 0; + repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 1; + repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); + train = 0; end end diff --git a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh index b2da50a..886dd6e 100644 --- a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh +++ b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.12.22.22:39:16 +# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.22.22:39:16 +# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh index 6682fd9..45ebdc7 100644 --- a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh +++ b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.12.22.22:39:16 +# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.22.22:39:16 +# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII_tb.csv b/Top/niosII_tb.csv index 53bce6a..97ad90c 100644 --- a/Top/niosII_tb.csv +++ b/Top/niosII_tb.csv @@ -1,12 +1,12 @@ -# system info niosII_tb on 2022.12.22.22:39:13 +# system info niosII_tb on 2022.12.24.02:16:19 system_info: name,value DEVICE,EP4CE115F29C7 DEVICE_FAMILY,Cyclone IV E -GENERATION_ID,1671734322 +GENERATION_ID,1671833747 # # -# Files generated for niosII_tb on 2022.12.22.22:39:13 +# Files generated for niosII_tb on 2022.12.24.02:16:19 files: filepath,kind,attributes,module,is_top niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true diff --git a/Top/semafor.qws b/Top/semafor.qws new file mode 100644 index 0000000000000000000000000000000000000000..045a66f76c7eeafeba764a56b7a06f33d5350a32 GIT binary patch literal 619 zcmbV}F;2rk5JkUDkSKEi3JQcQB%>q*i4q|M4Hcpf!FC`rU=xfe5NDzwx1gcrEQG+D ziBkn3!LDZi{PE1r-|=3g`C8SL`npr4o*qi;9dLHpZN5EyvFz^PnZvzLV-}i0IG%*&esDx+D$#a}!U}~6 zm^$XJc?i2eLsi#@V~Wn?EgA=s^9C`q6|+fA09l(2UYDV;(wg>l4_coa*eO^rp>x!a zEY+@c!RE7?I;1p1f~6$Ne@Zf8W|2-bMC;{$I{7@fWZgxTze^==LFy7AQ?bb#i~5b% ef4^occz=7H|0`=FEgvz*mznQvrwnOoJk&RO+-Zvd literal 0 HcmV?d00001 diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf index 44b6fe3bf8a41e931b84226e1e808f56c5167c3a..b9b3161903011fabde5db10b5359085e0f9a79b4 100644 GIT binary patch delta 96 zcmZ4WLw3~<*##N09~l@JU|0~yzKG0kmd$9F&0qv#rtPvB%pI;=CVB>jRwl+)CYICJ euVwCGvoJQaFtTiST*nN=EI`b<-Eke;%d-GV*BvJS delta 96 zcmZ4WLw3~<*##N09~c-IU|0ai{)NnMmd$9F&0qv#rtPvB%pI;=MtVj@R>l@q#)i|^ euVwCGGdDIdHZ*K^T*nN=EI`b<-Eke;%d-Gd+8sFn diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump index 8058ff9..0d308f7 100644 --- a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump +++ b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump @@ -751,8 +751,8 @@ alt_after_alt_main: 244: 003fff06 br 244 <__alt_data_end+0xfffe0244> 00000248
: - {0x000000f0, 0x000000f0, 0x000000f0, 0x00000010}, - {0x000000fa, 0x000000f0, 0x000000f0, 0x00000010} + {0x000000f1, 0x000000f1, 0x000000f1, 0x00000011}, + {0x000000d1, 0x000000f1, 0x000000f1, 0x00000011} }; int main() diff --git a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat index 4f38832..5a8a51d 100644 --- a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat +++ b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat @@ -5630,14 +5630,14 @@ @15FD 00000020 @15FE 00000010 @15FF 00000010 -@1600 000000F0 -@1601 000000F0 -@1602 000000F0 -@1603 00000010 -@1604 000000FA -@1605 000000F0 -@1606 000000F0 -@1607 00000010 +@1600 000000F1 +@1601 000000F1 +@1602 000000F1 +@1603 00000011 +@1604 000000D1 +@1605 000000F1 +@1606 000000F1 +@1607 00000011 @1608 64616552 @1609 00000079 @160A 0000000A diff --git a/Top/software/semafor/mem_init/niosII_mem.hex b/Top/software/semafor/mem_init/niosII_mem.hex index 851ad6c..e301f0d 100644 --- a/Top/software/semafor/mem_init/niosII_mem.hex +++ b/Top/software/semafor/mem_init/niosII_mem.hex @@ -703,7 +703,7 @@ :2015E800003FB6060005883A003FFB06DEFFFD04DF000215DF000204E13FFF150001883A31 :2015F000E0BFFF17E0BFFE15E0BFFE1710000226002AF07000000106002AF0B0003FFF06E9 :2015F80000000010000000100000000500000010000000100000002000000010000000104E -:20160000000000F0000000F0000000F000000010000000FA000000F0000000F00000001000 +:20160000000000F1000000F1000000F100000011000000D1000000F1000000F10000001122 :2016080064616552000000790000000A000000437665642F6C756E2F0000006C7665642FBA :2016100061746A2F61755F67000074727665642F61746A2F61755F6700007472000000006C :2016180000005B4800005BB000005C18000000000000000000000000000000000000000090 diff --git a/Top/software/semafor/sem.c b/Top/software/semafor/sem.c index 6cc5138..77c8c88 100644 --- a/Top/software/semafor/sem.c +++ b/Top/software/semafor/sem.c @@ -8,8 +8,8 @@ const alt_u32 divisors[TIME_SETS][TIME_STATES] = { {0x00000010, 0x00000010, 0x00000005, 0x00000010}, {0x00000010, 0x00000020, 0x00000010, 0x00000010}, - {0x000000f0, 0x000000f0, 0x000000f0, 0x00000010}, - {0x000000fa, 0x000000f0, 0x000000f0, 0x00000010} + {0x000000f1, 0x000000f1, 0x000000f1, 0x00000011}, + {0x000000d1, 0x000000f1, 0x000000f1, 0x00000011} }; int main() diff --git a/Top/software/semafor/transcript b/Top/software/semafor/transcript index 8672e2b..168b708 100644 --- a/Top/software/semafor/transcript +++ b/Top/software/semafor/transcript @@ -1 +1,8 @@ # Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl +# vsim -gui null_sim.mpf +# Start time: 01:19:59 on Dec 24,2022 +# ** Error (suppressible): (vsim-19) Failed to access library 'null_sim' at "null_sim". +# No such file or directory. (errno = ENOENT) +# Error loading design +# End time: 01:19:59 on Dec 24,2022, Elapsed time: 0:00:00 +# Errors: 1, Warnings: 0 diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp index 5ad0685..ac01443 100644 --- a/Top/software/semafor_bsp/settings.bsp +++ b/Top/software/semafor_bsp/settings.bsp @@ -2,8 +2,8 @@ hal default - 22.12.2022 22:44:16 - 1671734657095 + 24.12.2022 2:19:40 + 1671833980256 C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp settings.bsp ..\..\niosII.sopcinfo diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html index 2b757c5..6387456 100644 --- a/Top/software/semafor_bsp/summary.html +++ b/Top/software/semafor_bsp/summary.html @@ -22,10 +22,10 @@ BSP Version:default -BSP Generated On:22.12.2022 22:44:16 +BSP Generated On:24.12.2022 2:19:40 -BSP Generated Timestamp:1671734657095 +BSP Generated Timestamp:1671833980256 BSP Generated Location:C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp