diff --git a/.gitignore b/.gitignore
index 9823057..8bc9eed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,36 +1,36 @@
-*.pdf
-*.rpt
-*.bak
-.#*
-
-/db
-/incremental_db
-/output_files
-/simulation
-/.qsys*
-# /atom_netlists
-greybox_tmp/
-.qsys_edit/
-synthesis/
-*output_files/
-simulation/
-obj/
-drivers/
-HAL/
-Part_test/
-.metadata/
-RemoteSystemsTempFiles/
-aldec/
-cadence/
-synopsys/
-
-
-/testbenches/*.bak
-/common_uart/*.bak
-
-/build/*
-!/build/*.pdf
-!/build/tikz*.sty
-
-
+*.pdf
+*.rpt
+*.bak
+.#*
+
+/db
+/incremental_db
+/output_files
+/simulation
+/.qsys*
+# /atom_netlists
+greybox_tmp/
+.qsys_edit/
+synthesis/
+*output_files/
+simulation/
+obj/
+drivers/
+HAL/
+Part_test/
+.metadata/
+RemoteSystemsTempFiles/
+aldec/
+cadence/
+synopsys/
+
+
+/testbenches/*.bak
+/common_uart/*.bak
+
+/build/*
+!/build/*.pdf
+!/build/tikz*.sty
+
+
 !/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
\ No newline at end of file
diff --git a/HDL/IP/periodram.qip b/HDL/IP/periodram.qip
index 66f194e..fea5425 100644
--- a/HDL/IP/periodram.qip
+++ b/HDL/IP/periodram.qip
@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "18.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]
diff --git a/HDL/IP/periodram.v b/HDL/IP/periodram.v
index f7f7363..5587332 100644
--- a/HDL/IP/periodram.v
+++ b/HDL/IP/periodram.v
@@ -1,222 +1,222 @@
-// megafunction wizard: %RAM: 2-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram 
-
-// ============================================================
-// File Name: periodram.v
-// Megafunction Name(s):
-// 			altsyncram
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2018  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module periodram (
-	clock,
-	data,
-	rdaddress,
-	wraddress,
-	wren,
-	q);
-
-	input	  clock;
-	input	[31:0]  data;
-	input	[3:0]  rdaddress;
-	input	[3:0]  wraddress;
-	input	  wren;
-	output	[31:0]  q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri1	  clock;
-	tri0	  wren;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [31:0] sub_wire0;
-	wire [31:0] q = sub_wire0[31:0];
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.address_b (rdaddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.q_b (sub_wire0),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({32{1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-`ifdef NO_PLI
-		altsyncram_component.init_file = "periodram.rif"
-`else
-		altsyncram_component.init_file = "periodram.hex"
-`endif
-,
-		altsyncram_component.init_file_layout = "PORT_B",
-		altsyncram_component.intended_device_family = "Cyclone IV E",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 16,
-		altsyncram_component.numwords_b = 16,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = 4,
-		altsyncram_component.widthad_b = 4,
-		altsyncram_component.width_a = 32,
-		altsyncram_component.width_b = 32,
-		altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGrren NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
-// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
-// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
-// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: periodram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2018  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module periodram (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[3:0]  rdaddress;
+	input	[3:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "periodram.rif"
+`else
+		altsyncram_component.init_file = "periodram.hex"
+`endif
+,
+		altsyncram_component.init_file_layout = "PORT_B",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 16,
+		altsyncram_component.numwords_b = 16,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 4,
+		altsyncram_component.widthad_b = 4,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
+// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
+// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/HDL/IP/periodram_inst.v b/HDL/IP/periodram_inst.v
index 9fa36ba..46ab57b 100644
--- a/HDL/IP/periodram_inst.v
+++ b/HDL/IP/periodram_inst.v
@@ -1,8 +1,8 @@
-periodram	periodram_inst (
-	.clock ( clock_sig ),
-	.data ( data_sig ),
-	.rdaddress ( rdaddress_sig ),
-	.wraddress ( wraddress_sig ),
-	.wren ( wren_sig ),
-	.q ( q_sig )
-	);
+periodram	periodram_inst (
+	.clock ( clock_sig ),
+	.data ( data_sig ),
+	.rdaddress ( rdaddress_sig ),
+	.wraddress ( wraddress_sig ),
+	.wren ( wren_sig ),
+	.q ( q_sig )
+	);
diff --git a/HDL/dec.sv b/HDL/dec.sv
index c80033a..6b92f6b 100644
--- a/HDL/dec.sv
+++ b/HDL/dec.sv
@@ -93,19 +93,19 @@ module dec
                   RED: begin
                       colors <= 3'b100;
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= YELLOW;
                           greenSaved <= divisor;
                       end
                   end
                   YELLOW: begin
                       colors <= 3'b010;
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= BLINK;
                       end
                   end
                   BLINK: begin
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= GREEN;
                       end
                       if (greenSaved[0] == 0) begin
                           colors <= 3'b011;
@@ -118,9 +118,6 @@ module dec
                       end
                   end
                   GREEN: begin
-                      if (enacnt) begin
-                          state <= state + 1'b1;
-                      end
                       colors <= 3'b001;
                   end
                   default: colors <= 3'b100;
diff --git a/Testbench/dec/.gitignore b/Testbench/dec/.gitignore
index c394f5e..d108e33 100644
--- a/Testbench/dec/.gitignore
+++ b/Testbench/dec/.gitignore
@@ -1,19 +1,19 @@
-*.pdf
-*.rpt
-*.bak
-.#*
-
-/db
-/incremental_db
-/output_files
-/simulation
-/.qsys*
-# /atom_netlists
-
-
-/testbenches/*.bak
-/common_uart/*.bak
-
-/build/*
-!/build/*.pdf
-!/build/tikz*.sty
+*.pdf
+*.rpt
+*.bak
+.#*
+
+/db
+/incremental_db
+/output_files
+/simulation
+/.qsys*
+# /atom_netlists
+
+
+/testbenches/*.bak
+/common_uart/*.bak
+
+/build/*
+!/build/*.pdf
+!/build/tikz*.sty
diff --git a/Testbench/dec/dec.qsf b/Testbench/dec/dec.qsf
index ed09ddb..fcbda42 100644
--- a/Testbench/dec/dec.qsf
+++ b/Testbench/dec/dec.qsf
@@ -1,69 +1,69 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors.  Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 16:14:06  October 18, 2022
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		dec_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE6E22A7
-set_global_assignment -name TOP_LEVEL_ENTITY dec
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06  OCTOBER 18, 2022"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
-set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
-set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
-set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
-set_global_assignment -name HEX_FILE periodram.hex
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 16:14:06  October 18, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		dec_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22A7
+set_global_assignment -name TOP_LEVEL_ENTITY dec
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06  OCTOBER 18, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
+set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
+set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
+set_global_assignment -name HEX_FILE periodram.hex
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Testbench/dec/dec_tb.sv b/Testbench/dec/dec_tb.sv
index 7fe63df..67c04c3 100644
--- a/Testbench/dec/dec_tb.sv
+++ b/Testbench/dec/dec_tb.sv
@@ -1,128 +1,128 @@
-`timescale 1 ns/1 ns
-
-module dec_tb();
-
-	// Wires and variables to connect to UUT (unit under test)
-	logic clk, clrn, train;
-	logic r, y, g;
-    logic [1:0] div;
-	logic ctl_wr, ctl_rd;
-	logic ctl_addr;
-	logic [31:0] ctl_wrdata;
-	logic [31:0] ctl_rddata;
-	logic ram_wr;
-	logic [1:0] ram_addr;
-	logic [31:0] ram_wrdata;
-
-    logic [31:0] divisor[3:0] = {
-        {8'd11, 8'd71, 8'd51, 8'd21},
-        {8'd11, 8'd31, 8'd41, 8'd31},
-        {8'd11, 8'd31, 8'd11, 8'd101},
-        {8'd11, 8'd61, 8'd81, 8'd51}
-    };
-	
-	// Instantiate UUT
-	dec my_sem(
-        .clk(clk), .clrn(clrn),
-        .ctl_wr(ctl_wr), .ctl_rd(ctl_rd), 
-        .ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
-        .ram_wr(ram_wr),
-        .ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
-		.train(train), .red(r), .yellow(y), .green(g)
-    );
-
-	// Clock definition
-	initial begin
-		clk = 0;
-		forever #10 clk = ~clk;
-	end
-	
-	// Divisor and train definition
-	initial begin
-        //initial reset
-        clrn = 0;
-		div = 0;
-		train = 0;
-        //take reset off
-        @(negedge clk) clrn = 1;
-        //configure semaphore
-        for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]);        //write divisor RAM
-        write_reg_transaction(1,div);   //write initial divisor
-        write_reg_transaction(0,1);     //enable semaphore
-        //run trains
-		repeat (4)
-		begin
-            repeat (10) @(posedge clk);
-			train=1;
-            repeat (4) @(posedge clk);
-			train=0;
-			wait ({r,y,g}==3'b001);
-            repeat (10) @(posedge clk);
-            write_reg_transaction(1,div);
-            div=div+1;
-		end
-        //wait a little
-		repeat (10) @(posedge clk); 
-        $stop;
-	end
-	
-	//Single register write transaction task
-	task write_reg_transaction;
-		//input signals
-		input [1:0] offs;
-		input [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ctl_wr = 1;
-			ctl_addr = offs;
-			ctl_wrdata = val;
-			@(posedge clk);
-			//deassert signals
-			ctl_wr = 0;
-			ctl_addr = 'bx;
-			ctl_wrdata = 'bx;
-		end
-	endtask
-
-	//Single register read transaction task
-	task read_reg_transaction;
-		//input signals
-		input [1:0] offs;
-		output [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ctl_rd = 1;
-			ctl_addr = offs;
-			@(posedge clk);
-            val = ctl_rddata;
-			//deassert signals
-			ctl_rd = 0;
-			ctl_addr = 'bx;
-		end
-	endtask
-
-	//RAM write transaction task
-	task write_ram_transaction;
-		//input signals
-		input [1:0] offs;
-		input [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ram_wr = 1;
-			ram_addr = offs;
-			ram_wrdata = val;
-			@(posedge clk);
-			//deassert signals
-			ram_wr = 0;
-			ram_addr = 'bx;
-			ram_wrdata = 'bx;
-		end
-	endtask
-
-endmodule
+`timescale 1 ns/1 ns
+
+module dec_tb();
+
+	// Wires and variables to connect to UUT (unit under test)
+	logic clk, clrn, train;
+	logic r, y, g;
+    logic [1:0] div;
+	logic ctl_wr, ctl_rd;
+	logic ctl_addr;
+	logic [31:0] ctl_wrdata;
+	logic [31:0] ctl_rddata;
+	logic ram_wr;
+	logic [1:0] ram_addr;
+	logic [31:0] ram_wrdata;
+
+    logic [31:0] divisor[3:0] = {
+        {8'd11, 8'd71, 8'd51, 8'd21},
+        {8'd11, 8'd31, 8'd41, 8'd31},
+        {8'd11, 8'd31, 8'd11, 8'd101},
+        {8'd11, 8'd61, 8'd81, 8'd51}
+    };
+	
+	// Instantiate UUT
+	dec my_sem(
+        .clk(clk), .clrn(clrn),
+        .ctl_wr(ctl_wr), .ctl_rd(ctl_rd), 
+        .ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
+        .ram_wr(ram_wr),
+        .ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
+		.train(train), .red(r), .yellow(y), .green(g)
+    );
+
+	// Clock definition
+	initial begin
+		clk = 0;
+		forever #10 clk = ~clk;
+	end
+	
+	// Divisor and train definition
+	initial begin
+        //initial reset
+        clrn = 0;
+		div = 0;
+		train = 0;
+        //take reset off
+        @(negedge clk) clrn = 1;
+        //configure semaphore
+        for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]);        //write divisor RAM
+        write_reg_transaction(1,div);   //write initial divisor
+        write_reg_transaction(0,1);     //enable semaphore
+        //run trains
+		repeat (4)
+		begin
+            repeat (10) @(posedge clk);
+			train=1;
+            repeat (4) @(posedge clk);
+			train=0;
+			wait ({r,y,g}==3'b001);
+            repeat (10) @(posedge clk);
+            write_reg_transaction(1,div);
+            div=div+1;
+		end
+        //wait a little
+		repeat (10) @(posedge clk); 
+        $stop;
+	end
+	
+	//Single register write transaction task
+	task write_reg_transaction;
+		//input signals
+		input [1:0] offs;
+		input [31:0] val;
+		//transaction implementation
+		begin
+			@(posedge clk);
+			//assert signals for one clock cycle
+			ctl_wr = 1;
+			ctl_addr = offs;
+			ctl_wrdata = val;
+			@(posedge clk);
+			//deassert signals
+			ctl_wr = 0;
+			ctl_addr = 'bx;
+			ctl_wrdata = 'bx;
+		end
+	endtask
+
+	//Single register read transaction task
+	task read_reg_transaction;
+		//input signals
+		input [1:0] offs;
+		output [31:0] val;
+		//transaction implementation
+		begin
+			@(posedge clk);
+			//assert signals for one clock cycle
+			ctl_rd = 1;
+			ctl_addr = offs;
+			@(posedge clk);
+            val = ctl_rddata;
+			//deassert signals
+			ctl_rd = 0;
+			ctl_addr = 'bx;
+		end
+	endtask
+
+	//RAM write transaction task
+	task write_ram_transaction;
+		//input signals
+		input [1:0] offs;
+		input [31:0] val;
+		//transaction implementation
+		begin
+			@(posedge clk);
+			//assert signals for one clock cycle
+			ram_wr = 1;
+			ram_addr = offs;
+			ram_wrdata = val;
+			@(posedge clk);
+			//deassert signals
+			ram_wr = 0;
+			ram_addr = 'bx;
+			ram_wrdata = 'bx;
+		end
+	endtask
+
+endmodule
diff --git a/Testbench/dec/periodram.hex b/Testbench/dec/periodram.hex
index 229095d..3dfd9d2 100644
--- a/Testbench/dec/periodram.hex
+++ b/Testbench/dec/periodram.hex
@@ -1,17 +1,17 @@
-:040000000000006498
-:040001000000006497
-:0400020000000032C8
-:040003000000000AEF
-:040004000000006494
-:04000500000000C82F
-:040006000000006492
-:040007000000000AEB
-:04000800000000965E
-:04000900000000FAF9
-:04000A00000000C82A
-:04000B000000000AE7
-:04000C00000000FAF6
-:04000D00000000FAF5
-:04000E00000000FAF4
-:04000F000000000AE3
-:00000001FF
+:040000000000006498
+:040001000000006497
+:0400020000000032C8
+:040003000000000AEF
+:040004000000006494
+:04000500000000C82F
+:040006000000006492
+:040007000000000AEB
+:04000800000000965E
+:04000900000000FAF9
+:04000A00000000C82A
+:04000B000000000AE7
+:04000C00000000FAF6
+:04000D00000000FAF5
+:04000E00000000FAF4
+:04000F000000000AE3
+:00000001FF
diff --git a/Testbench/dec/semafor.qpf b/Testbench/dec/semafor.qpf
index 23f10ea..93229b9 100644
--- a/Testbench/dec/semafor.qpf
+++ b/Testbench/dec/semafor.qpf
@@ -1,30 +1,30 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors.  Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 16:14:06  October 18, 2022
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "18.1"
-DATE = "16:14:06  October 18, 2022"
-
-# Revisions
-
-PROJECT_REVISION = "dec"
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 16:14:06  October 18, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "16:14:06  October 18, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "dec"
diff --git a/Testbench/dec/wave.do b/Testbench/dec/wave.do
index d3f216b..ee78a29 100644
--- a/Testbench/dec/wave.do
+++ b/Testbench/dec/wave.do
@@ -1,35 +1,35 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /dec_tb/clk
-add wave -noupdate /dec_tb/clrn
-add wave -noupdate /dec_tb/train
-add wave -noupdate /dec_tb/r
-add wave -noupdate /dec_tb/y
-add wave -noupdate /dec_tb/g
-add wave -noupdate /dec_tb/div
-add wave -noupdate /dec_tb/ctl_wr
-add wave -noupdate /dec_tb/ctl_rd
-add wave -noupdate /dec_tb/ctl_addr
-add wave -noupdate /dec_tb/ctl_wrdata
-add wave -noupdate /dec_tb/ctl_rddata
-add wave -noupdate /dec_tb/ram_wr
-add wave -noupdate /dec_tb/ram_addr
-add wave -noupdate /dec_tb/ram_wrdata
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3346003 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {15928500 ps}
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /dec_tb/clk
+add wave -noupdate /dec_tb/clrn
+add wave -noupdate /dec_tb/train
+add wave -noupdate /dec_tb/r
+add wave -noupdate /dec_tb/y
+add wave -noupdate /dec_tb/g
+add wave -noupdate /dec_tb/div
+add wave -noupdate /dec_tb/ctl_wr
+add wave -noupdate /dec_tb/ctl_rd
+add wave -noupdate /dec_tb/ctl_addr
+add wave -noupdate /dec_tb/ctl_wrdata
+add wave -noupdate /dec_tb/ctl_rddata
+add wave -noupdate /dec_tb/ram_wr
+add wave -noupdate /dec_tb/ram_addr
+add wave -noupdate /dec_tb/ram_wrdata
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3346003 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {15928500 ps}
diff --git a/Top/.gitignore b/Top/.gitignore
index 916133b..7ee46fe 100644
--- a/Top/.gitignore
+++ b/Top/.gitignore
@@ -1,34 +1,34 @@
-*.pdf
-*.rpt
-*.bak
-.#*
-
-/db
-/incremental_db
-/output_files
-/simulation
-/.qsys*
-# /atom_netlists
-/greybox_tmp/
-/.qsys_edit/
-/synthesis/
-/*output_files/
-/simulation/
-/obj/
-/drivers/
-/HAL/
-/Part_test/
-/.metadata/
-/RemoteSystemsTempFiles/
-/aldec/
-/cadence/
-/synopsys/
-
-
-/testbenches/*.bak
-/common_uart/*.bak
-
-/build/*
-!/build/*.pdf
-!/build/tikz*.sty
-
+*.pdf
+*.rpt
+*.bak
+.#*
+
+/db
+/incremental_db
+/output_files
+/simulation
+/.qsys*
+# /atom_netlists
+/greybox_tmp/
+/.qsys_edit/
+/synthesis/
+/*output_files/
+/simulation/
+/obj/
+/drivers/
+/HAL/
+/Part_test/
+/.metadata/
+/RemoteSystemsTempFiles/
+/aldec/
+/cadence/
+/synopsys/
+
+
+/testbenches/*.bak
+/common_uart/*.bak
+
+/build/*
+!/build/*.pdf
+!/build/tikz*.sty
+
diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo
index 0f955c5..9bf8f16 100644
--- a/Top/niosII.sopcinfo
+++ b/Top/niosII.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
- <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2022.12.24.02:16:30 -->
+ <!-- Format version 20.1 720 (Future versions may contain additional information.) -->
+ <!-- 2023.01.24.11:09:13 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1671833790</value>
+  <value>1674547753</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -95,7 +95,7 @@
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
- <module name="clk" kind="clock_source" version="18.1" path="clk">
+ <module name="clk" kind="clock_source" version="20.1" path="clk">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
   <parameter name="clockFrequency">
@@ -148,7 +148,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk_in" kind="clock_sink" version="18.1">
+  <interface name="clk_in" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -213,7 +213,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="clk_in_reset" kind="reset_sink" version="18.1">
+  <interface name="clk_in_reset" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -262,7 +262,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="clk" kind="clock_source" version="18.1">
+  <interface name="clk" kind="clock_source" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -361,7 +361,7 @@ parameters are a RESULT of the module parameters. -->
     <name>sem.clock</name>
    </clockDomainMember>
   </interface>
-  <interface name="clk_reset" kind="reset_source" version="18.1">
+  <interface name="clk_reset" kind="reset_source" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -423,7 +423,7 @@ parameters are a RESULT of the module parameters. -->
    </port>
   </interface>
  </module>
- <module name="cpu" kind="altera_nios2_gen2" version="18.1" path="cpu">
+ <module name="cpu" kind="altera_nios2_gen2" version="20.1" path="cpu">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
   <assignment>
@@ -2213,7 +2213,7 @@ the requested settings for a module instance. -->
   </parameter>
   <parameter name="deviceFeaturesSystemInfo">
    <type>java.lang.String</type>
-   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <value>COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -2274,7 +2274,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="18.1">
+  <interface name="clk" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -2335,7 +2335,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="reset" kind="reset_sink" version="18.1">
+  <interface name="reset" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -2386,7 +2386,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset_req</role>
    </port>
   </interface>
-  <interface name="data_master" kind="avalon_master" version="18.1">
+  <interface name="data_master" kind="avalon_master" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -2749,7 +2749,7 @@ parameters are a RESULT of the module parameters. -->
     <span>131072</span>
    </memoryBlock>
   </interface>
-  <interface name="instruction_master" kind="avalon_master" version="18.1">
+  <interface name="instruction_master" kind="avalon_master" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3052,7 +3052,7 @@ parameters are a RESULT of the module parameters. -->
     <span>131072</span>
    </memoryBlock>
   </interface>
-  <interface name="irq" kind="interrupt_receiver" version="18.1">
+  <interface name="irq" kind="interrupt_receiver" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3135,7 +3135,7 @@ parameters are a RESULT of the module parameters. -->
     <interruptNumber>1</interruptNumber>
    </interrupt>
   </interface>
-  <interface name="debug_reset_request" kind="reset_source" version="18.1">
+  <interface name="debug_reset_request" kind="reset_source" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3196,7 +3196,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset</role>
    </port>
   </interface>
-  <interface name="debug_mem_slave" kind="avalon_slave" version="18.1">
+  <interface name="debug_mem_slave" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3574,7 +3574,7 @@ parameters are a RESULT of the module parameters. -->
   <interface
      name="custom_instruction_master"
      kind="nios_custom_instruction_master"
-     version="18.1">
+     version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3663,7 +3663,7 @@ parameters are a RESULT of the module parameters. -->
  <module
    name="jtag_uart"
    kind="altera_avalon_jtag_uart"
-   version="18.1"
+   version="20.1"
    path="jtag_uart">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -3846,7 +3846,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="18.1">
+  <interface name="clk" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3907,7 +3907,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="reset" kind="reset_sink" version="18.1">
+  <interface name="reset" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -3952,7 +3952,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="avalon_jtag_slave" kind="avalon_slave" version="18.1">
+  <interface name="avalon_jtag_slave" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -4329,7 +4329,7 @@ parameters are a RESULT of the module parameters. -->
     <role>waitrequest</role>
    </port>
   </interface>
-  <interface name="irq" kind="interrupt_sender" version="18.1">
+  <interface name="irq" kind="interrupt_sender" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -4410,7 +4410,7 @@ parameters are a RESULT of the module parameters. -->
  <module
    name="mem"
    kind="altera_avalon_onchip_memory2"
-   version="18.1"
+   version="20.1"
    path="mem">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -4730,7 +4730,7 @@ the requested settings for a module instance. -->
   </parameter>
   <parameter name="deviceFeatures">
    <type>java.lang.String</type>
-   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <value>COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
@@ -4801,7 +4801,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="s1" kind="avalon_slave" version="18.1">
+  <interface name="s1" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -5178,7 +5178,7 @@ parameters are a RESULT of the module parameters. -->
     <role>byteenable</role>
    </port>
   </interface>
-  <interface name="s2" kind="avalon_slave" version="18.1">
+  <interface name="s2" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -5555,7 +5555,7 @@ parameters are a RESULT of the module parameters. -->
     <role>byteenable</role>
    </port>
   </interface>
-  <interface name="clk1" kind="clock_sink" version="18.1">
+  <interface name="clk1" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -5600,7 +5600,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="reset1" kind="reset_sink" version="18.1">
+  <interface name="reset1" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -5679,7 +5679,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clock" kind="clock_sink" version="18.1">
+  <interface name="clock" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -5724,7 +5724,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="ctl_slave" kind="avalon_slave" version="18.1">
+  <interface name="ctl_slave" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6089,7 +6089,7 @@ parameters are a RESULT of the module parameters. -->
     <role>readdata</role>
    </port>
   </interface>
-  <interface name="reset_n" kind="reset_sink" version="18.1">
+  <interface name="reset_n" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6134,7 +6134,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="ram_slave" kind="avalon_slave" version="18.1">
+  <interface name="ram_slave" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6487,7 +6487,7 @@ parameters are a RESULT of the module parameters. -->
     <role>writedata</role>
    </port>
   </interface>
-  <interface name="sem" kind="conduit_end" version="18.1">
+  <interface name="sem" kind="conduit_end" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6554,7 +6554,7 @@ parameters are a RESULT of the module parameters. -->
  <module
    name="sys_clk_timer"
    kind="altera_avalon_timer"
-   version="18.1"
+   version="20.1"
    path="sys_clk_timer">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -6780,7 +6780,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="clk" kind="clock_sink" version="18.1">
+  <interface name="clk" kind="clock_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6841,7 +6841,7 @@ parameters are a RESULT of the module parameters. -->
     <role>clk</role>
    </port>
   </interface>
-  <interface name="reset" kind="reset_sink" version="18.1">
+  <interface name="reset" kind="reset_sink" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -6886,7 +6886,7 @@ parameters are a RESULT of the module parameters. -->
     <role>reset_n</role>
    </port>
   </interface>
-  <interface name="s1" kind="avalon_slave" version="18.1">
+  <interface name="s1" kind="avalon_slave" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -7255,7 +7255,7 @@ parameters are a RESULT of the module parameters. -->
     <role>write_n</role>
    </port>
   </interface>
-  <interface name="irq" kind="interrupt_sender" version="18.1">
+  <interface name="irq" kind="interrupt_sender" version="20.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -7336,7 +7336,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/jtag_uart.avalon_jtag_slave"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="jtag_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority">
@@ -7387,7 +7387,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/sem.ctl_slave"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="sem.ctl_slave">
   <parameter name="arbitrationPriority">
@@ -7438,7 +7438,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/cpu.debug_mem_slave"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="cpu.debug_mem_slave">
   <parameter name="arbitrationPriority">
@@ -7489,7 +7489,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/sem.ram_slave"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="sem.ram_slave">
   <parameter name="arbitrationPriority">
@@ -7540,7 +7540,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/sys_clk_timer.s1"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="sys_clk_timer.s1">
   <parameter name="arbitrationPriority">
@@ -7591,7 +7591,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.data_master/mem.s2"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.data_master"
    end="mem.s2">
   <parameter name="arbitrationPriority">
@@ -7642,7 +7642,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.instruction_master/cpu.debug_mem_slave"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.instruction_master"
    end="cpu.debug_mem_slave">
   <parameter name="arbitrationPriority">
@@ -7693,7 +7693,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.instruction_master/mem.s1"
    kind="avalon"
-   version="18.1"
+   version="20.1"
    start="cpu.instruction_master"
    end="mem.s1">
   <parameter name="arbitrationPriority">
@@ -7744,7 +7744,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk/cpu.clk"
    kind="clock"
-   version="18.1"
+   version="20.1"
    start="clk.clk"
    end="cpu.clk">
   <parameter name="deviceFamily">
@@ -7771,7 +7771,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk/jtag_uart.clk"
    kind="clock"
-   version="18.1"
+   version="20.1"
    start="clk.clk"
    end="jtag_uart.clk">
   <parameter name="deviceFamily">
@@ -7798,7 +7798,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk/sys_clk_timer.clk"
    kind="clock"
-   version="18.1"
+   version="20.1"
    start="clk.clk"
    end="sys_clk_timer.clk">
   <parameter name="deviceFamily">
@@ -7825,7 +7825,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk/mem.clk1"
    kind="clock"
-   version="18.1"
+   version="20.1"
    start="clk.clk"
    end="mem.clk1">
   <parameter name="deviceFamily">
@@ -7852,7 +7852,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk/sem.clock"
    kind="clock"
-   version="18.1"
+   version="20.1"
    start="clk.clk"
    end="sem.clock">
   <parameter name="deviceFamily">
@@ -7879,7 +7879,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.irq/sys_clk_timer.irq"
    kind="interrupt"
-   version="18.1"
+   version="20.1"
    start="cpu.irq"
    end="sys_clk_timer.irq">
   <parameter name="irqNumber">
@@ -7914,7 +7914,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.irq/jtag_uart.irq"
    kind="interrupt"
-   version="18.1"
+   version="20.1"
    start="cpu.irq"
    end="jtag_uart.irq">
   <parameter name="irqNumber">
@@ -7949,7 +7949,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk_reset/cpu.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="clk.clk_reset"
    end="cpu.reset">
   <parameter name="deviceFamily">
@@ -7976,7 +7976,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk_reset/jtag_uart.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="clk.clk_reset"
    end="jtag_uart.reset">
   <parameter name="deviceFamily">
@@ -8003,7 +8003,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk_reset/sys_clk_timer.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="clk.clk_reset"
    end="sys_clk_timer.reset">
   <parameter name="deviceFamily">
@@ -8030,7 +8030,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk_reset/mem.reset1"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="clk.clk_reset"
    end="mem.reset1">
   <parameter name="deviceFamily">
@@ -8057,7 +8057,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="clk.clk_reset/sem.reset_n"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="clk.clk_reset"
    end="sem.reset_n">
   <parameter name="deviceFamily">
@@ -8084,7 +8084,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.debug_reset_request/cpu.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="cpu.debug_reset_request"
    end="cpu.reset">
   <parameter name="deviceFamily">
@@ -8111,7 +8111,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.debug_reset_request/jtag_uart.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="cpu.debug_reset_request"
    end="jtag_uart.reset">
   <parameter name="deviceFamily">
@@ -8138,7 +8138,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.debug_reset_request/sys_clk_timer.reset"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="cpu.debug_reset_request"
    end="sys_clk_timer.reset">
   <parameter name="deviceFamily">
@@ -8165,7 +8165,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.debug_reset_request/mem.reset1"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="cpu.debug_reset_request"
    end="mem.reset1">
   <parameter name="deviceFamily">
@@ -8192,7 +8192,7 @@ parameters are a RESULT of the module parameters. -->
  <connection
    name="cpu.debug_reset_request/sem.reset_n"
    kind="reset"
-   version="18.1"
+   version="20.1"
    start="cpu.debug_reset_request"
    end="sem.reset_n">
   <parameter name="deviceFamily">
@@ -8222,7 +8222,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>Clock Source</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8230,7 +8230,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8238,7 +8238,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8246,7 +8246,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Output</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8254,7 +8254,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Output</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8262,7 +8262,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>Nios II Processor</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>5</instanceCount>
@@ -8270,7 +8270,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Input</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>5</instanceCount>
@@ -8278,7 +8278,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Input</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -8286,7 +8286,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Master</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8294,7 +8294,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Interrupt Receiver</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8302,7 +8302,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Reset Output</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>7</instanceCount>
@@ -8310,7 +8310,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Avalon Memory Mapped Slave</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8318,7 +8318,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Custom Instruction Master</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8326,7 +8326,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>JTAG UART Intel FPGA IP</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -8334,7 +8334,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Interrupt Sender</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8342,7 +8342,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8358,7 +8358,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Conduit</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -8366,7 +8366,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>Interval Timer Intel FPGA IP</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>8</instanceCount>
@@ -8374,7 +8374,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IConnection</subtype>
   <displayName>Avalon Memory Mapped Connection</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>5</instanceCount>
@@ -8382,7 +8382,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IConnection</subtype>
   <displayName>Clock Connection</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -8390,7 +8390,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IConnection</subtype>
   <displayName>Interrupt Connection</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
  <plugin>
   <instanceCount>10</instanceCount>
@@ -8398,8 +8398,8 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IConnection</subtype>
   <displayName>Reset Connection</displayName>
-  <version>18.1</version>
+  <version>20.1</version>
  </plugin>
- <reportVersion>18.1 625</reportVersion>
+ <reportVersion>20.1 720</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
diff --git a/Top/niosII/niosII.bsf b/Top/niosII/niosII.bsf
index c61f1b7..2a53fa4 100644
--- a/Top/niosII/niosII.bsf
+++ b/Top/niosII/niosII.bsf
@@ -1,94 +1,94 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 288 232)
-	(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 216 20 228)(font "Arial" ))
-	(port
-		(pt 0 72)
-		(input)
-		(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
-		(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 112 72)(line_width 1))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
-		(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 112 112)(line_width 1))
-	)
-	(port
-		(pt 0 152)
-		(input)
-		(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
-		(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 112 152)(line_width 1))
-	)
-	(port
-		(pt 0 168)
-		(output)
-		(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
-		(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 112 168)(line_width 1))
-	)
-	(port
-		(pt 0 184)
-		(output)
-		(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
-		(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
-		(line (pt 0 184)(pt 112 184)(line_width 1))
-	)
-	(port
-		(pt 0 200)
-		(output)
-		(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
-		(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
-		(line (pt 0 200)(pt 112 200)(line_width 1))
-	)
-	(drawing
-		(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
-		(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
-		(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
-		(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
-		(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
-		(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
-		(text " niosII " (rect 262 216 572 442)(font "Arial" ))
-		(line (pt 112 32)(pt 176 32)(line_width 1))
-		(line (pt 176 32)(pt 176 216)(line_width 1))
-		(line (pt 112 216)(pt 176 216)(line_width 1))
-		(line (pt 112 32)(pt 112 216)(line_width 1))
-		(line (pt 113 52)(pt 113 76)(line_width 1))
-		(line (pt 114 52)(pt 114 76)(line_width 1))
-		(line (pt 113 92)(pt 113 116)(line_width 1))
-		(line (pt 114 92)(pt 114 116)(line_width 1))
-		(line (pt 113 132)(pt 113 204)(line_width 1))
-		(line (pt 114 132)(pt 114 204)(line_width 1))
-		(line (pt 0 0)(pt 288 0)(line_width 1))
-		(line (pt 288 0)(pt 288 232)(line_width 1))
-		(line (pt 0 232)(pt 288 232)(line_width 1))
-		(line (pt 0 0)(pt 0 232)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 288 232)
+	(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 216 20 228)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
+		(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
+		(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 112 152)(line_width 1))
+	)
+	(port
+		(pt 0 168)
+		(output)
+		(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 112 168)(line_width 1))
+	)
+	(port
+		(pt 0 184)
+		(output)
+		(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
+		(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 112 184)(line_width 1))
+	)
+	(port
+		(pt 0 200)
+		(output)
+		(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
+		(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
+		(line (pt 0 200)(pt 112 200)(line_width 1))
+	)
+	(drawing
+		(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
+		(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
+		(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
+		(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
+		(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
+		(text " niosII " (rect 262 216 572 442)(font "Arial" ))
+		(line (pt 112 32)(pt 176 32)(line_width 1))
+		(line (pt 176 32)(pt 176 216)(line_width 1))
+		(line (pt 112 216)(pt 176 216)(line_width 1))
+		(line (pt 112 32)(pt 112 216)(line_width 1))
+		(line (pt 113 52)(pt 113 76)(line_width 1))
+		(line (pt 114 52)(pt 114 76)(line_width 1))
+		(line (pt 113 92)(pt 113 116)(line_width 1))
+		(line (pt 114 92)(pt 114 116)(line_width 1))
+		(line (pt 113 132)(pt 113 204)(line_width 1))
+		(line (pt 114 132)(pt 114 204)(line_width 1))
+		(line (pt 0 0)(pt 288 0)(line_width 1))
+		(line (pt 288 0)(pt 288 232)(line_width 1))
+		(line (pt 0 232)(pt 288 232)(line_width 1))
+		(line (pt 0 0)(pt 0 232)(line_width 1))
+	)
+)
diff --git a/Top/niosII/niosII.cmp b/Top/niosII/niosII.cmp
index ef3bdda..78674b7 100644
--- a/Top/niosII/niosII.cmp
+++ b/Top/niosII/niosII.cmp
@@ -1,4 +1,4 @@
-	component niosII is
+	component niosII is
 		port (
 			clk_clk           : in  std_logic := 'X'; -- clk
 			reset_reset_n     : in  std_logic := 'X'; -- reset_n
@@ -7,5 +7,5 @@
 			sem_export_yellow : out std_logic;        -- yellow
 			sem_export_green  : out std_logic         -- green
 		);
-	end component niosII;
-
+	end component niosII;
+
diff --git a/Top/niosII/niosII_inst.v b/Top/niosII/niosII_inst.v
index 77513fe..5b4ee5e 100644
--- a/Top/niosII/niosII_inst.v
+++ b/Top/niosII/niosII_inst.v
@@ -5,5 +5,5 @@
 		.sem_export_red    (<connected-to-sem_export_red>),    //           .red
 		.sem_export_yellow (<connected-to-sem_export_yellow>), //           .yellow
 		.sem_export_green  (<connected-to-sem_export_green>)   //           .green
-	);
-
+	);
+
diff --git a/Top/niosII/niosII_inst.vhd b/Top/niosII/niosII_inst.vhd
index a97848d..1e56e3e 100644
--- a/Top/niosII/niosII_inst.vhd
+++ b/Top/niosII/niosII_inst.vhd
@@ -1,4 +1,4 @@
-	component niosII is
+	component niosII is
 		port (
 			clk_clk           : in  std_logic := 'X'; -- clk
 			reset_reset_n     : in  std_logic := 'X'; -- reset_n
@@ -7,9 +7,9 @@
 			sem_export_yellow : out std_logic;        -- yellow
 			sem_export_green  : out std_logic         -- green
 		);
-	end component niosII;
-
-	u0 : component niosII
+	end component niosII;
+
+	u0 : component niosII
 		port map (
 			clk_clk           => CONNECTED_TO_clk_clk,           --        clk.clk
 			reset_reset_n     => CONNECTED_TO_reset_reset_n,     --      reset.reset_n
@@ -18,4 +18,4 @@
 			sem_export_yellow => CONNECTED_TO_sem_export_yellow, --           .yellow
 			sem_export_green  => CONNECTED_TO_sem_export_green   --           .green
 		);
-
+
diff --git a/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v b/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v
index cf8576a..0d57cc2 100644
--- a/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v
+++ b/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v
@@ -1,915 +1,915 @@
-// -----------------------------------------------------------
-// Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
-// use of Altera Corporation's design tools, logic functions and other
-// software and tools, and its AMPP partner logic functions, and any
-// output files any of the foregoing (including device programming or
-// simulation files), and any associated documentation or information are
-// expressly subject to the terms and conditions of the Altera Program
-// License Subscription Agreement or other applicable license agreement,
-// including, without limitation, that your use is for the sole purpose
-// of programming logic devices manufactured by Altera and sold by Altera
-// or its authorized distributors.  Please refer to the applicable
-// agreement for further details.
-//
-// Description: Single clock Avalon-ST FIFO.
-// -----------------------------------------------------------
-
-`timescale 1 ns / 1 ns
-
-
-//altera message_off 10036
-module altera_avalon_sc_fifo
-#(
-    // --------------------------------------------------
-    // Parameters
-    // --------------------------------------------------
-    parameter SYMBOLS_PER_BEAT  = 1,
-    parameter BITS_PER_SYMBOL   = 8,
-    parameter FIFO_DEPTH        = 16,
-    parameter CHANNEL_WIDTH     = 0,
-    parameter ERROR_WIDTH       = 0,
-    parameter USE_PACKETS       = 0,
-    parameter USE_FILL_LEVEL    = 0,
-    parameter USE_STORE_FORWARD = 0,
-    parameter USE_ALMOST_FULL_IF = 0,
-    parameter USE_ALMOST_EMPTY_IF = 0,
-
-    // --------------------------------------------------
-    // Empty latency is defined as the number of cycles
-    // required for a write to deassert the empty flag.
-    // For example, a latency of 1 means that the empty
-    // flag is deasserted on the cycle after a write.
-    //
-    // Another way to think of it is the latency for a
-    // write to propagate to the output. 
-    // 
-    // An empty latency of 0 implies lookahead, which is
-    // only implemented for the register-based FIFO.
-    // --------------------------------------------------
-    parameter EMPTY_LATENCY     = 3,
-    parameter USE_MEMORY_BLOCKS = 1,
-
-    // --------------------------------------------------
-    // Internal Parameters
-    // --------------------------------------------------
-    parameter DATA_WIDTH  = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
-    parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
-)
-(
-    // --------------------------------------------------
-    // Ports
-    // --------------------------------------------------
-    input                       clk,
-    input                       reset,
-
-    input [DATA_WIDTH-1: 0]     in_data,
-    input                       in_valid,
-    input                       in_startofpacket,
-    input                       in_endofpacket,
-    input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]     in_empty,
-    input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]     in_error,
-    input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0]  in_channel,
-    output                      in_ready,
-
-    output [DATA_WIDTH-1 : 0]   out_data,
-    output reg                  out_valid,
-    output                      out_startofpacket,
-    output                      out_endofpacket,
-    output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]    out_empty,
-    output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]    out_error,
-    output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
-    input                       out_ready,
-
-    input [(USE_STORE_FORWARD ? 2 : 1) : 0]   csr_address,
-    input                       csr_write,
-    input                       csr_read,
-    input [31 : 0]              csr_writedata,
-    output reg [31 : 0]         csr_readdata,
-
-    output  wire                almost_full_data,
-    output  wire                almost_empty_data
-);
-
-    // --------------------------------------------------
-    // Local Parameters
-    // --------------------------------------------------
-    localparam ADDR_WIDTH   = log2ceil(FIFO_DEPTH);
-    localparam DEPTH        = FIFO_DEPTH;
-    localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
-    localparam PAYLOAD_WIDTH     = (USE_PACKETS == 1) ? 
-                   2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
-                   DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
-
-    // --------------------------------------------------
-    // Internal Signals
-    // --------------------------------------------------
-    genvar i;
-
-    reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
-    reg [ADDR_WIDTH-1 : 0]  wr_ptr;
-    reg [ADDR_WIDTH-1 : 0]  rd_ptr;
-    reg [DEPTH-1      : 0]  mem_used;
-
-    wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
-    wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
-    wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
-    wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
-
-    wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
-
-    wire read;
-    wire write;
-
-    reg empty;
-    reg next_empty;
-    reg full;
-    reg next_full;
-
-    wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
-    wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
-    wire [PAYLOAD_WIDTH-1 : 0] in_payload;
-    reg  [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
-    reg  [PAYLOAD_WIDTH-1 : 0] out_payload;
-
-    reg  internal_out_valid;
-    wire internal_out_ready;
-
-    reg  [ADDR_WIDTH : 0] fifo_fill_level;
-    reg  [ADDR_WIDTH : 0] fill_level;
-
-    reg  [ADDR_WIDTH-1 : 0]   sop_ptr = 0;
-    wire [ADDR_WIDTH-1 : 0]   curr_sop_ptr;
-    reg  [23:0]   almost_full_threshold;
-    reg  [23:0]   almost_empty_threshold;
-    reg  [23:0]   cut_through_threshold;
-    reg  [15:0]   pkt_cnt;
-    reg           drop_on_error_en;
-    reg           error_in_pkt;
-    reg           pkt_has_started;
-    reg           sop_has_left_fifo;
-    reg           fifo_too_small_r;
-    reg           pkt_cnt_eq_zero;
-    reg           pkt_cnt_eq_one;
-
-    wire          wait_for_threshold;
-    reg           pkt_mode;
-    wire          wait_for_pkt;
-    wire          ok_to_forward;
-    wire          in_pkt_eop_arrive;
-    wire          out_pkt_leave;
-    wire          in_pkt_start;
-    wire          in_pkt_error;
-    wire          drop_on_error;
-    wire          fifo_too_small;
-    wire          out_pkt_sop_leave;
-    wire [31:0]   max_fifo_size;
-    reg           fifo_fill_level_lt_cut_through_threshold;
-
-    // --------------------------------------------------
-    // Define Payload
-    //
-    // Icky part where we decide which signals form the
-    // payload to the FIFO with generate blocks.
-    // --------------------------------------------------
-    generate
-        if (EMPTY_WIDTH > 0) begin : gen_blk1
-            assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
-            assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
-        end 
-        else begin : gen_blk1_else
-            assign out_empty = in_error;
-            assign in_packet_signals = {in_startofpacket, in_endofpacket};
-            assign {out_startofpacket, out_endofpacket} = out_packet_signals;
-        end
-    endgenerate
-
-    generate
-        if (USE_PACKETS) begin : gen_blk2
-            if (ERROR_WIDTH > 0) begin : gen_blk3
-                if (CHANNEL_WIDTH > 0) begin : gen_blk4
-                    assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
-                    assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
-                end
-                else begin : gen_blk4_else
-                    assign out_channel = in_channel;
-                    assign in_payload = {in_packet_signals, in_data, in_error};
-                    assign {out_packet_signals, out_data, out_error} = out_payload;
-                end
-            end
-            else begin : gen_blk3_else
-                assign out_error = in_error;
-                if (CHANNEL_WIDTH > 0) begin : gen_blk5
-                    assign in_payload = {in_packet_signals, in_data, in_channel};
-                    assign {out_packet_signals, out_data, out_channel} = out_payload;
-                end
-                else begin : gen_blk5_else
-                    assign out_channel = in_channel;
-                    assign in_payload = {in_packet_signals, in_data};
-                    assign {out_packet_signals, out_data} = out_payload;
-                end
-            end
-        end
-        else begin : gen_blk2_else
-            assign out_packet_signals = 0;
-            if (ERROR_WIDTH > 0) begin : gen_blk6
-                if (CHANNEL_WIDTH > 0) begin : gen_blk7
-                    assign in_payload = {in_data, in_error, in_channel};
-                    assign {out_data, out_error, out_channel} = out_payload;
-                end
-                else begin : gen_blk7_else
-                    assign out_channel = in_channel;
-                    assign in_payload = {in_data, in_error};
-                    assign {out_data, out_error} = out_payload;
-                end
-            end
-            else begin : gen_blk6_else
-                assign out_error = in_error;
-                if (CHANNEL_WIDTH > 0) begin : gen_blk8
-                    assign in_payload = {in_data, in_channel};
-                    assign {out_data, out_channel} = out_payload;
-                end
-                else begin : gen_blk8_else
-                    assign out_channel = in_channel;
-                    assign in_payload = in_data;
-                    assign out_data = out_payload;
-                end
-            end
-        end
-    endgenerate
-
-    // --------------------------------------------------
-    // Memory-based FIFO storage
-    //
-    // To allow a ready latency of 0, the read index is 
-    // obtained from the next read pointer and memory 
-    // outputs are unregistered.
-    //
-    // If the empty latency is 1, we infer bypass logic
-    // around the memory so writes propagate to the
-    // outputs on the next cycle.
-    //
-    // Do not change the way this is coded: Quartus needs
-    // a perfect match to the template, and any attempt to 
-    // refactor the two always blocks into one will break
-    // memory inference.
-    // --------------------------------------------------
-    generate if (USE_MEMORY_BLOCKS == 1) begin  : gen_blk9
-
-        if (EMPTY_LATENCY == 1) begin : gen_blk10
-
-            always @(posedge clk) begin
-                if (in_valid && in_ready)
-                    mem[wr_ptr] = in_payload;
-
-                internal_out_payload = mem[mem_rd_ptr];
-            end
-
-        end else begin : gen_blk10_else
-
-            always @(posedge clk) begin
-                if (in_valid && in_ready)
-                    mem[wr_ptr] <= in_payload;
-
-                internal_out_payload <= mem[mem_rd_ptr];
-            end
-
-        end
-
-        assign mem_rd_ptr = next_rd_ptr;
-    
-    end else begin : gen_blk9_else
-
-    // --------------------------------------------------
-    // Register-based FIFO storage
-    //
-    // Uses a shift register as the storage element. Each
-    // shift register slot has a bit which indicates if
-    // the slot is occupied (credit to Sam H for the idea).
-    // The occupancy bits are contiguous and start from the
-    // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
-    // FIFO.
-    // 
-    // Each slot is enabled during a read or when it
-    // is unoccupied. New data is always written to every
-    // going-to-be-empty slot (we keep track of which ones
-    // are actually useful with the occupancy bits). On a
-    // read we shift occupied slots.
-    // 
-    // The exception is the last slot, which always gets 
-    // new data when it is unoccupied.
-    // --------------------------------------------------
-        for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
-            always @(posedge clk or posedge reset) begin
-                if (reset) begin
-                    mem[i] <= 0;
-                end 
-                else if (read || !mem_used[i]) begin
-                    if (!mem_used[i+1])
-                        mem[i] <= in_payload;
-                    else
-                        mem[i] <= mem[i+1];
-                end
-            end
-        end
-
-        always @(posedge clk, posedge reset) begin
-            if (reset) begin
-                mem[DEPTH-1] <= 0;
-            end 
-            else begin
-                if (DEPTH == 1) begin
-                    if (write)
-                        mem[DEPTH-1] <= in_payload;
-                end
-                else if (!mem_used[DEPTH-1])
-                    mem[DEPTH-1] <= in_payload;    
-            end
-        end
-
-    end
-    endgenerate
-
-    assign read  = internal_out_ready && internal_out_valid  && ok_to_forward;
-    assign write = in_ready && in_valid;
-
-    // --------------------------------------------------
-    // Pointer Management
-    // --------------------------------------------------
-    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
-
-        assign incremented_wr_ptr = wr_ptr + 1'b1;
-        assign incremented_rd_ptr = rd_ptr + 1'b1;
-        assign next_wr_ptr =  drop_on_error ? curr_sop_ptr : write ?  incremented_wr_ptr : wr_ptr;
-        assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
-
-        always @(posedge clk or posedge reset) begin
-            if (reset) begin
-                wr_ptr <= 0;
-                rd_ptr <= 0;
-            end
-            else begin
-                wr_ptr <= next_wr_ptr;
-                rd_ptr <= next_rd_ptr;
-            end
-        end
-
-    end else begin : gen_blk11_else
-
-    // --------------------------------------------------
-    // Shift Register Occupancy Bits
-    //
-    // Consider a 4-deep FIFO with 2 entries: 0011
-    // On a read and write, do not modify the bits.
-    // On a write, left-shift the bits to get 0111.
-    // On a read, right-shift the bits to get 0001.
-    //
-    // Also, on a write we set bit0 (the head), while
-    // clearing the tail on a read.
-    // --------------------------------------------------
-        always @(posedge clk or posedge reset) begin
-            if (reset) begin
-                mem_used[0] <= 0;
-            end 
-            else begin
-                if (write ^ read) begin
-                    if (write)
-                        mem_used[0] <= 1;
-                    else if (read) begin
-                        if (DEPTH > 1)
-                            mem_used[0] <= mem_used[1];
-                        else
-                            mem_used[0] <= 0;
-                    end    
-                end
-            end
-        end
-
-        if (DEPTH > 1) begin : gen_blk12
-            always @(posedge clk or posedge reset) begin
-                if (reset) begin
-                    mem_used[DEPTH-1] <= 0;
-                end
-                else begin 
-                    if (write ^ read) begin            
-                        mem_used[DEPTH-1] <= 0;
-                        if (write)
-                            mem_used[DEPTH-1] <= mem_used[DEPTH-2];
-                    end
-                end
-            end
-          end
-     
-        for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
-            always @(posedge clk, posedge reset) begin
-                if (reset) begin
-                    mem_used[i] <= 0;
-                end 
-                else begin
-                    if (write ^ read) begin
-                        if (write)
-                            mem_used[i] <= mem_used[i-1];
-                        else if (read)
-                            mem_used[i] <= mem_used[i+1];     
-                    end
-                end
-            end
-        end
-     
-    end
-    endgenerate
-
-
-    // --------------------------------------------------
-    // Memory FIFO Status Management
-    //
-    // Generates the full and empty signals from the
-    // pointers. The FIFO is full when the next write 
-    // pointer will be equal to the read pointer after
-    // a write. Reading from a FIFO clears full.
-    //
-    // The FIFO is empty when the next read pointer will
-    // be equal to the write pointer after a read. Writing
-    // to a FIFO clears empty.
-    //
-    // A simultaneous read and write must not change any of 
-    // the empty or full flags unless there is a drop on error event.
-    // --------------------------------------------------
-    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
-
-        always @* begin
-            next_full = full;
-            next_empty = empty;
-     
-            if (read && !write) begin
-                next_full = 1'b0;
-     
-                if (incremented_rd_ptr == wr_ptr)
-                    next_empty = 1'b1;
-            end
-            
-            if (write && !read) begin
-                if (!drop_on_error)
-                  next_empty = 1'b0;
-                else if (curr_sop_ptr == rd_ptr)   // drop on error and only 1 pkt in fifo
-                  next_empty = 1'b1;
-     
-                if (incremented_wr_ptr == rd_ptr && !drop_on_error)
-                    next_full = 1'b1;
-            end
-
-            if (write && read && drop_on_error) begin
-                if (curr_sop_ptr == next_rd_ptr)
-                  next_empty = 1'b1;
-            end
-        end
-     
-        always @(posedge clk or posedge reset) begin
-            if (reset) begin
-                empty <= 1;
-                full  <= 0;
-            end
-            else begin 
-                empty <= next_empty;
-                full  <= next_full;
-            end
-        end
-
-    end else begin : gen_blk13_else
-    // --------------------------------------------------
-    // Register FIFO Status Management
-    //
-    // Full when the tail occupancy bit is 1. Empty when
-    // the head occupancy bit is 0.
-    // --------------------------------------------------
-        always @* begin
-            full  = mem_used[DEPTH-1];
-            empty = !mem_used[0];
-
-            // ------------------------------------------
-            // For a single slot FIFO, reading clears the
-            // full status immediately.
-            // ------------------------------------------
-            if (DEPTH == 1)
-                full = mem_used[0] && !read;
-
-            internal_out_payload = mem[0];
-
-            // ------------------------------------------
-            // Writes clear empty immediately for lookahead modes.
-            // Note that we use in_valid instead of write to avoid
-            // combinational loops (in lookahead mode, qualifying
-            // with in_ready is meaningless).
-            //
-            // In a 1-deep FIFO, a possible combinational loop runs
-            // from write -> out_valid -> out_ready -> write
-            // ------------------------------------------
-            if (EMPTY_LATENCY == 0) begin
-                empty = !mem_used[0] && !in_valid;
-
-                if (!mem_used[0] && in_valid)
-                    internal_out_payload = in_payload;
-            end
-        end
-
-    end
-    endgenerate
-
-    // --------------------------------------------------
-    // Avalon-ST Signals
-    //
-    // The in_ready signal is straightforward. 
-    //
-    // To match memory latency when empty latency > 1, 
-    // out_valid assertions must be delayed by one clock
-    // cycle.
-    //
-    // Note: out_valid deassertions must not be delayed or 
-    // the FIFO will underflow.
-    // --------------------------------------------------
-    assign in_ready = !full;
-    assign internal_out_ready = out_ready || !out_valid;
-
-    generate if (EMPTY_LATENCY > 1) begin : gen_blk14
-        always @(posedge clk or posedge reset) begin
-            if (reset)
-                internal_out_valid <= 0;
-            else begin
-                internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
-
-                if (read) begin
-                    if (incremented_rd_ptr == wr_ptr)
-                        internal_out_valid <= 1'b0;
-                end
-            end
-        end
-    end else begin : gen_blk14_else
-        always @* begin
-            internal_out_valid = !empty & ok_to_forward;
-        end
-    end
-    endgenerate
-
-    // --------------------------------------------------
-    // Single Output Pipeline Stage
-    //
-    // This output pipeline stage is enabled if the FIFO's 
-    // empty latency is set to 3 (default). It is disabled
-    // for all other allowed latencies.
-    //
-    // Reason: The memory outputs are unregistered, so we have to
-    // register the output or fmax will drop if combinatorial
-    // logic is present on the output datapath.
-    // 
-    // Q: The Avalon-ST spec says that I have to register my outputs
-    //    But isn't the memory counted as a register?
-    // A: The path from the address lookup to the memory output is
-    //    slow. Registering the memory outputs is a good idea. 
-    //
-    // The registers get packed into the memory by the fitter
-    // which means minimal resources are consumed (the result
-    // is a altsyncram with registered outputs, available on 
-    // all modern Altera devices). 
-    //
-    // This output stage acts as an extra slot in the FIFO, 
-    // and complicates the fill level.
-    // --------------------------------------------------
-    generate if (EMPTY_LATENCY == 3) begin : gen_blk15
-        always @(posedge clk or posedge reset) begin
-            if (reset) begin
-                out_valid   <= 0;
-                out_payload <= 0;
-            end
-            else begin
-                if (internal_out_ready) begin
-                    out_valid   <= internal_out_valid & ok_to_forward;
-                    out_payload <= internal_out_payload;
-                end
-            end
-        end
-    end
-    else begin : gen_blk15_else
-        always @* begin
-            out_valid   = internal_out_valid;
-            out_payload = internal_out_payload;
-        end
-    end
-    endgenerate
-
-    // --------------------------------------------------
-    // Fill Level
-    //
-    // The fill level is calculated from the next write
-    // and read pointers to avoid unnecessary latency
-    // and logic.
-    //
-    // However, if the store-and-forward mode of the FIFO
-    // is enabled, the fill level is an up-down counter
-    // for fmax optimization reasons.
-    //
-    // If the output pipeline is enabled, the fill level 
-    // must account for it, or we'll always be off by one.
-    // This may, or may not be important depending on the
-    // application.
-    //
-    // For now, we'll always calculate the exact fill level
-    // at the cost of an extra adder when the output stage
-    // is enabled.
-    // --------------------------------------------------
-    generate if (USE_FILL_LEVEL) begin : gen_blk16
-        wire [31:0] depth32;
-        assign depth32 = DEPTH;
-
-        if (USE_STORE_FORWARD) begin
-
-            reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
-            
-            // --------------------------------------------------
-            // We only drop on endofpacket. As long as we don't add to the fill
-            // level on the dropped endofpacket cycle, we can simply subtract
-            // (packet length - 1) from the fill level for dropped packets.
-            // --------------------------------------------------
-            always @(posedge clk or posedge reset) begin
-                if (reset) begin
-                    curr_packet_len_less_one <= 0;
-                end else begin
-                    if (write) begin
-                        curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
-                        if (in_endofpacket)
-                            curr_packet_len_less_one <= 0;
-                    end
-                end
-            end
-
-            always @(posedge clk or posedge reset) begin
-                if (reset) begin
-                    fifo_fill_level <= 0;
-                end else if (drop_on_error) begin
-                    fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
-                    if (read)
-                        fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
-                end else if (write && !read) begin
-                    fifo_fill_level <= fifo_fill_level + 1'b1;
-                end else if (read && !write) begin
-                    fifo_fill_level <= fifo_fill_level - 1'b1;
-                end
-            end
-
-        end else begin
-
-            always @(posedge clk or posedge reset) begin
-                if (reset) 
-                    fifo_fill_level <= 0;
-                else if (next_full & !drop_on_error)
-                    fifo_fill_level <= depth32[ADDR_WIDTH:0];
-                else begin
-                    fifo_fill_level[ADDR_WIDTH]     <= 1'b0;
-                    fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
-                end
-            end
-
-        end
-
-        always @* begin
-            fill_level = fifo_fill_level;
-
-            if (EMPTY_LATENCY == 3)
-                fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
-        end
-    end
-    else begin : gen_blk16_else
-        always @* begin
-            fill_level = 0;
-        end  
-    end
-    endgenerate
-
-    generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
-      assign almost_full_data = (fill_level >= almost_full_threshold);
-    end
-    else
-      assign almost_full_data = 0;
-    endgenerate
-
-    generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
-      assign almost_empty_data = (fill_level <= almost_empty_threshold);
-    end
-    else
-      assign almost_empty_data = 0;
-    endgenerate
-
-    // --------------------------------------------------
-    // Avalon-MM Status & Control Connection Point
-    //
-    // Register map:
-    //
-    // | Addr   | RW |     31 - 0      |
-    // |  0     | R  |   Fill level    |
-    //
-    // The registering of this connection point means
-    // that there is a cycle of latency between 
-    // reads/writes and the updating of the fill level.
-    // --------------------------------------------------
-    generate if (USE_STORE_FORWARD) begin : gen_blk19
-    assign max_fifo_size = FIFO_DEPTH - 1;
-      always @(posedge clk or posedge reset) begin
-          if (reset) begin
-              almost_full_threshold  <= max_fifo_size[23 : 0];
-              almost_empty_threshold <= 0;
-              cut_through_threshold  <= 0;
-              drop_on_error_en       <= 0;
-              csr_readdata           <= 0;
-              pkt_mode               <= 1'b1;
-          end
-          else begin
-              if (csr_read) begin
-                csr_readdata <= 32'b0;
-                if (csr_address == 5)
-                    csr_readdata <= {31'b0, drop_on_error_en};
-                else if (csr_address == 4)
-                    csr_readdata <= {8'b0, cut_through_threshold};
-                else if (csr_address == 3)
-                    csr_readdata <= {8'b0, almost_empty_threshold};
-                else if (csr_address == 2)
-                    csr_readdata <= {8'b0, almost_full_threshold};
-                else if (csr_address == 0)
-                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
-             end
-             else if (csr_write) begin
-               if(csr_address == 3'b101)
-                   drop_on_error_en       <= csr_writedata[0];
-               else if(csr_address == 3'b100) begin
-                   cut_through_threshold  <= csr_writedata[23:0];
-                   pkt_mode <= (csr_writedata[23:0] == 0);
-               end
-               else if(csr_address == 3'b011)
-                    almost_empty_threshold <= csr_writedata[23:0];
-               else if(csr_address == 3'b010)
-                  almost_full_threshold  <= csr_writedata[23:0];
-             end     
-          end
-      end
-    end
-    else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
-    assign max_fifo_size = FIFO_DEPTH - 1;
-      always @(posedge clk or posedge reset) begin
-          if (reset) begin
-              almost_full_threshold  <= max_fifo_size[23 : 0];
-              almost_empty_threshold <= 0;
-              csr_readdata           <= 0;
-          end
-          else begin
-             if (csr_read) begin
-                csr_readdata <= 32'b0;
-                if (csr_address == 3)
-                    csr_readdata <= {8'b0, almost_empty_threshold};
-                else if (csr_address == 2)
-                    csr_readdata <= {8'b0, almost_full_threshold};
-                else if (csr_address == 0)
-                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
-             end
-             else if (csr_write) begin
-               if(csr_address == 3'b011)
-                   almost_empty_threshold <= csr_writedata[23:0];
-               else if(csr_address == 3'b010)
-                  almost_full_threshold  <= csr_writedata[23:0];
-             end       
-          end
-      end
-    end
-    else begin : gen_blk19_else2
-      always @(posedge clk or posedge reset) begin
-          if (reset) begin
-              csr_readdata <= 0;
-          end
-          else if (csr_read) begin
-              csr_readdata <= 0;
-
-              if (csr_address == 0) 
-                  csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
-          end
-      end
-    end
-    endgenerate
-
-    // --------------------------------------------------
-    // Store and forward logic
-    // --------------------------------------------------
-    // if the fifo gets full before the entire packet or the
-    // cut-threshold condition is met then start sending out
-    // data in order to avoid dead-lock situation
-
-    generate if (USE_STORE_FORWARD) begin : gen_blk20
-      assign wait_for_threshold   = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
-      assign wait_for_pkt         = pkt_cnt_eq_zero  | (pkt_cnt_eq_one  & out_pkt_leave);
-      assign ok_to_forward        = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : 
-                                     ~wait_for_threshold) | fifo_too_small_r;
-      assign in_pkt_eop_arrive    = in_valid & in_ready & in_endofpacket;
-      assign in_pkt_start         = in_valid & in_ready & in_startofpacket;
-      assign in_pkt_error         = in_valid & in_ready & |in_error;
-      assign out_pkt_sop_leave    = out_valid & out_ready & out_startofpacket;
-      assign out_pkt_leave        = out_valid & out_ready & out_endofpacket;
-      assign fifo_too_small       = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
-
-      // count packets coming and going into the fifo
-      always @(posedge clk or posedge reset) begin
-        if (reset) begin
-          pkt_cnt           <= 0;
-          pkt_has_started   <= 0;
-          sop_has_left_fifo <= 0;
-          fifo_too_small_r  <= 0;
-          pkt_cnt_eq_zero   <= 1'b1;
-          pkt_cnt_eq_one    <= 1'b0;
-          fifo_fill_level_lt_cut_through_threshold <= 1'b1;
-        end
-        else begin
-          fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
-          fifo_too_small_r <= fifo_too_small;
-
-          if( in_pkt_eop_arrive )
-            sop_has_left_fifo <= 1'b0;
-          else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
-            sop_has_left_fifo <= 1'b1;
-
-          if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
-            pkt_cnt <= pkt_cnt + 1'b1;
-            pkt_cnt_eq_zero <= 0;
-            if (pkt_cnt == 0)
-              pkt_cnt_eq_one <= 1'b1;
-            else
-              pkt_cnt_eq_one <= 1'b0;
-          end
-          else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
-            pkt_cnt <= pkt_cnt - 1'b1;
-            if (pkt_cnt == 1) 
-              pkt_cnt_eq_zero <= 1'b1;
-            else
-              pkt_cnt_eq_zero <= 1'b0;
-            if (pkt_cnt == 2) 
-              pkt_cnt_eq_one <= 1'b1;
-            else
-              pkt_cnt_eq_one <= 1'b0;
-          end
-
-          if (in_pkt_start)
-            pkt_has_started <= 1'b1;
-          else if (in_pkt_eop_arrive)
-            pkt_has_started <= 1'b0;
-        end
-      end
-
-      // drop on error logic
-      always @(posedge clk or posedge reset) begin
-        if (reset) begin
-          sop_ptr <= 0;
-          error_in_pkt <= 0;
-        end
-        else begin
-          // save the location of the SOP
-          if ( in_pkt_start ) 
-            sop_ptr <= wr_ptr;
-
-          // remember if error in pkt
-          // log error only if packet has already started
-          if (in_pkt_eop_arrive)
-            error_in_pkt <= 1'b0;
-          else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
-            error_in_pkt <= 1'b1;
-        end
-      end
-
-      assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & 
-                            ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
-
-      assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
-
-    end
-    else begin : gen_blk20_else
-      assign ok_to_forward = 1'b1;
-      assign drop_on_error = 1'b0;
-      if (ADDR_WIDTH <= 1)
-        assign curr_sop_ptr = 1'b0;
-      else
-        assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
-    end
-    endgenerate
-
-
-    // --------------------------------------------------
-    // Calculates the log2ceil of the input value
-    // --------------------------------------------------
-    function integer log2ceil;
-        input integer val;
-        reg[31:0] i;
-
-        begin
-            i = 1;
-            log2ceil = 0;
-
-            while (i < val) begin
-                log2ceil = log2ceil + 1;
-                i = i[30:0] << 1;
-            end
-        end
-    endfunction
-
-endmodule
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+    // --------------------------------------------------
+    // Parameters
+    // --------------------------------------------------
+    parameter SYMBOLS_PER_BEAT  = 1,
+    parameter BITS_PER_SYMBOL   = 8,
+    parameter FIFO_DEPTH        = 16,
+    parameter CHANNEL_WIDTH     = 0,
+    parameter ERROR_WIDTH       = 0,
+    parameter USE_PACKETS       = 0,
+    parameter USE_FILL_LEVEL    = 0,
+    parameter USE_STORE_FORWARD = 0,
+    parameter USE_ALMOST_FULL_IF = 0,
+    parameter USE_ALMOST_EMPTY_IF = 0,
+
+    // --------------------------------------------------
+    // Empty latency is defined as the number of cycles
+    // required for a write to deassert the empty flag.
+    // For example, a latency of 1 means that the empty
+    // flag is deasserted on the cycle after a write.
+    //
+    // Another way to think of it is the latency for a
+    // write to propagate to the output. 
+    // 
+    // An empty latency of 0 implies lookahead, which is
+    // only implemented for the register-based FIFO.
+    // --------------------------------------------------
+    parameter EMPTY_LATENCY     = 3,
+    parameter USE_MEMORY_BLOCKS = 1,
+
+    // --------------------------------------------------
+    // Internal Parameters
+    // --------------------------------------------------
+    parameter DATA_WIDTH  = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+    parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+    // --------------------------------------------------
+    // Ports
+    // --------------------------------------------------
+    input                       clk,
+    input                       reset,
+
+    input [DATA_WIDTH-1: 0]     in_data,
+    input                       in_valid,
+    input                       in_startofpacket,
+    input                       in_endofpacket,
+    input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]     in_empty,
+    input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]     in_error,
+    input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0]  in_channel,
+    output                      in_ready,
+
+    output [DATA_WIDTH-1 : 0]   out_data,
+    output reg                  out_valid,
+    output                      out_startofpacket,
+    output                      out_endofpacket,
+    output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]    out_empty,
+    output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]    out_error,
+    output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+    input                       out_ready,
+
+    input [(USE_STORE_FORWARD ? 2 : 1) : 0]   csr_address,
+    input                       csr_write,
+    input                       csr_read,
+    input [31 : 0]              csr_writedata,
+    output reg [31 : 0]         csr_readdata,
+
+    output  wire                almost_full_data,
+    output  wire                almost_empty_data
+);
+
+    // --------------------------------------------------
+    // Local Parameters
+    // --------------------------------------------------
+    localparam ADDR_WIDTH   = log2ceil(FIFO_DEPTH);
+    localparam DEPTH        = FIFO_DEPTH;
+    localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+    localparam PAYLOAD_WIDTH     = (USE_PACKETS == 1) ? 
+                   2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+                   DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+    // --------------------------------------------------
+    // Internal Signals
+    // --------------------------------------------------
+    genvar i;
+
+    reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+    reg [ADDR_WIDTH-1 : 0]  wr_ptr;
+    reg [ADDR_WIDTH-1 : 0]  rd_ptr;
+    reg [DEPTH-1      : 0]  mem_used;
+
+    wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+    wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+    wire read;
+    wire write;
+
+    reg empty;
+    reg next_empty;
+    reg full;
+    reg next_full;
+
+    wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+    wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+    wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+    reg  internal_out_valid;
+    wire internal_out_ready;
+
+    reg  [ADDR_WIDTH : 0] fifo_fill_level;
+    reg  [ADDR_WIDTH : 0] fill_level;
+
+    reg  [ADDR_WIDTH-1 : 0]   sop_ptr = 0;
+    wire [ADDR_WIDTH-1 : 0]   curr_sop_ptr;
+    reg  [23:0]   almost_full_threshold;
+    reg  [23:0]   almost_empty_threshold;
+    reg  [23:0]   cut_through_threshold;
+    reg  [15:0]   pkt_cnt;
+    reg           drop_on_error_en;
+    reg           error_in_pkt;
+    reg           pkt_has_started;
+    reg           sop_has_left_fifo;
+    reg           fifo_too_small_r;
+    reg           pkt_cnt_eq_zero;
+    reg           pkt_cnt_eq_one;
+
+    wire          wait_for_threshold;
+    reg           pkt_mode;
+    wire          wait_for_pkt;
+    wire          ok_to_forward;
+    wire          in_pkt_eop_arrive;
+    wire          out_pkt_leave;
+    wire          in_pkt_start;
+    wire          in_pkt_error;
+    wire          drop_on_error;
+    wire          fifo_too_small;
+    wire          out_pkt_sop_leave;
+    wire [31:0]   max_fifo_size;
+    reg           fifo_fill_level_lt_cut_through_threshold;
+
+    // --------------------------------------------------
+    // Define Payload
+    //
+    // Icky part where we decide which signals form the
+    // payload to the FIFO with generate blocks.
+    // --------------------------------------------------
+    generate
+        if (EMPTY_WIDTH > 0) begin : gen_blk1
+            assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+            assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+        end 
+        else begin : gen_blk1_else
+            assign out_empty = in_error;
+            assign in_packet_signals = {in_startofpacket, in_endofpacket};
+            assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+        end
+    endgenerate
+
+    generate
+        if (USE_PACKETS) begin : gen_blk2
+            if (ERROR_WIDTH > 0) begin : gen_blk3
+                if (CHANNEL_WIDTH > 0) begin : gen_blk4
+                    assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+                    assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk4_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data, in_error};
+                    assign {out_packet_signals, out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk3_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk5
+                    assign in_payload = {in_packet_signals, in_data, in_channel};
+                    assign {out_packet_signals, out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk5_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data};
+                    assign {out_packet_signals, out_data} = out_payload;
+                end
+            end
+        end
+        else begin : gen_blk2_else
+            assign out_packet_signals = 0;
+            if (ERROR_WIDTH > 0) begin : gen_blk6
+                if (CHANNEL_WIDTH > 0) begin : gen_blk7
+                    assign in_payload = {in_data, in_error, in_channel};
+                    assign {out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk7_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_data, in_error};
+                    assign {out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk6_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk8
+                    assign in_payload = {in_data, in_channel};
+                    assign {out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk8_else
+                    assign out_channel = in_channel;
+                    assign in_payload = in_data;
+                    assign out_data = out_payload;
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Memory-based FIFO storage
+    //
+    // To allow a ready latency of 0, the read index is 
+    // obtained from the next read pointer and memory 
+    // outputs are unregistered.
+    //
+    // If the empty latency is 1, we infer bypass logic
+    // around the memory so writes propagate to the
+    // outputs on the next cycle.
+    //
+    // Do not change the way this is coded: Quartus needs
+    // a perfect match to the template, and any attempt to 
+    // refactor the two always blocks into one will break
+    // memory inference.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin  : gen_blk9
+
+        if (EMPTY_LATENCY == 1) begin : gen_blk10
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] = in_payload;
+
+                internal_out_payload = mem[mem_rd_ptr];
+            end
+
+        end else begin : gen_blk10_else
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] <= in_payload;
+
+                internal_out_payload <= mem[mem_rd_ptr];
+            end
+
+        end
+
+        assign mem_rd_ptr = next_rd_ptr;
+    
+    end else begin : gen_blk9_else
+
+    // --------------------------------------------------
+    // Register-based FIFO storage
+    //
+    // Uses a shift register as the storage element. Each
+    // shift register slot has a bit which indicates if
+    // the slot is occupied (credit to Sam H for the idea).
+    // The occupancy bits are contiguous and start from the
+    // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+    // FIFO.
+    // 
+    // Each slot is enabled during a read or when it
+    // is unoccupied. New data is always written to every
+    // going-to-be-empty slot (we keep track of which ones
+    // are actually useful with the occupancy bits). On a
+    // read we shift occupied slots.
+    // 
+    // The exception is the last slot, which always gets 
+    // new data when it is unoccupied.
+    // --------------------------------------------------
+        for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem[i] <= 0;
+                end 
+                else if (read || !mem_used[i]) begin
+                    if (!mem_used[i+1])
+                        mem[i] <= in_payload;
+                    else
+                        mem[i] <= mem[i+1];
+                end
+            end
+        end
+
+        always @(posedge clk, posedge reset) begin
+            if (reset) begin
+                mem[DEPTH-1] <= 0;
+            end 
+            else begin
+                if (DEPTH == 1) begin
+                    if (write)
+                        mem[DEPTH-1] <= in_payload;
+                end
+                else if (!mem_used[DEPTH-1])
+                    mem[DEPTH-1] <= in_payload;    
+            end
+        end
+
+    end
+    endgenerate
+
+    assign read  = internal_out_ready && internal_out_valid  && ok_to_forward;
+    assign write = in_ready && in_valid;
+
+    // --------------------------------------------------
+    // Pointer Management
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
+
+        assign incremented_wr_ptr = wr_ptr + 1'b1;
+        assign incremented_rd_ptr = rd_ptr + 1'b1;
+        assign next_wr_ptr =  drop_on_error ? curr_sop_ptr : write ?  incremented_wr_ptr : wr_ptr;
+        assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                wr_ptr <= 0;
+                rd_ptr <= 0;
+            end
+            else begin
+                wr_ptr <= next_wr_ptr;
+                rd_ptr <= next_rd_ptr;
+            end
+        end
+
+    end else begin : gen_blk11_else
+
+    // --------------------------------------------------
+    // Shift Register Occupancy Bits
+    //
+    // Consider a 4-deep FIFO with 2 entries: 0011
+    // On a read and write, do not modify the bits.
+    // On a write, left-shift the bits to get 0111.
+    // On a read, right-shift the bits to get 0001.
+    //
+    // Also, on a write we set bit0 (the head), while
+    // clearing the tail on a read.
+    // --------------------------------------------------
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                mem_used[0] <= 0;
+            end 
+            else begin
+                if (write ^ read) begin
+                    if (write)
+                        mem_used[0] <= 1;
+                    else if (read) begin
+                        if (DEPTH > 1)
+                            mem_used[0] <= mem_used[1];
+                        else
+                            mem_used[0] <= 0;
+                    end    
+                end
+            end
+        end
+
+        if (DEPTH > 1) begin : gen_blk12
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem_used[DEPTH-1] <= 0;
+                end
+                else begin 
+                    if (write ^ read) begin            
+                        mem_used[DEPTH-1] <= 0;
+                        if (write)
+                            mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+                    end
+                end
+            end
+          end
+     
+        for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+            always @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    mem_used[i] <= 0;
+                end 
+                else begin
+                    if (write ^ read) begin
+                        if (write)
+                            mem_used[i] <= mem_used[i-1];
+                        else if (read)
+                            mem_used[i] <= mem_used[i+1];     
+                    end
+                end
+            end
+        end
+     
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Memory FIFO Status Management
+    //
+    // Generates the full and empty signals from the
+    // pointers. The FIFO is full when the next write 
+    // pointer will be equal to the read pointer after
+    // a write. Reading from a FIFO clears full.
+    //
+    // The FIFO is empty when the next read pointer will
+    // be equal to the write pointer after a read. Writing
+    // to a FIFO clears empty.
+    //
+    // A simultaneous read and write must not change any of 
+    // the empty or full flags unless there is a drop on error event.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
+
+        always @* begin
+            next_full = full;
+            next_empty = empty;
+     
+            if (read && !write) begin
+                next_full = 1'b0;
+     
+                if (incremented_rd_ptr == wr_ptr)
+                    next_empty = 1'b1;
+            end
+            
+            if (write && !read) begin
+                if (!drop_on_error)
+                  next_empty = 1'b0;
+                else if (curr_sop_ptr == rd_ptr)   // drop on error and only 1 pkt in fifo
+                  next_empty = 1'b1;
+     
+                if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+                    next_full = 1'b1;
+            end
+
+            if (write && read && drop_on_error) begin
+                if (curr_sop_ptr == next_rd_ptr)
+                  next_empty = 1'b1;
+            end
+        end
+     
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                empty <= 1;
+                full  <= 0;
+            end
+            else begin 
+                empty <= next_empty;
+                full  <= next_full;
+            end
+        end
+
+    end else begin : gen_blk13_else
+    // --------------------------------------------------
+    // Register FIFO Status Management
+    //
+    // Full when the tail occupancy bit is 1. Empty when
+    // the head occupancy bit is 0.
+    // --------------------------------------------------
+        always @* begin
+            full  = mem_used[DEPTH-1];
+            empty = !mem_used[0];
+
+            // ------------------------------------------
+            // For a single slot FIFO, reading clears the
+            // full status immediately.
+            // ------------------------------------------
+            if (DEPTH == 1)
+                full = mem_used[0] && !read;
+
+            internal_out_payload = mem[0];
+
+            // ------------------------------------------
+            // Writes clear empty immediately for lookahead modes.
+            // Note that we use in_valid instead of write to avoid
+            // combinational loops (in lookahead mode, qualifying
+            // with in_ready is meaningless).
+            //
+            // In a 1-deep FIFO, a possible combinational loop runs
+            // from write -> out_valid -> out_ready -> write
+            // ------------------------------------------
+            if (EMPTY_LATENCY == 0) begin
+                empty = !mem_used[0] && !in_valid;
+
+                if (!mem_used[0] && in_valid)
+                    internal_out_payload = in_payload;
+            end
+        end
+
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-ST Signals
+    //
+    // The in_ready signal is straightforward. 
+    //
+    // To match memory latency when empty latency > 1, 
+    // out_valid assertions must be delayed by one clock
+    // cycle.
+    //
+    // Note: out_valid deassertions must not be delayed or 
+    // the FIFO will underflow.
+    // --------------------------------------------------
+    assign in_ready = !full;
+    assign internal_out_ready = out_ready || !out_valid;
+
+    generate if (EMPTY_LATENCY > 1) begin : gen_blk14
+        always @(posedge clk or posedge reset) begin
+            if (reset)
+                internal_out_valid <= 0;
+            else begin
+                internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+                if (read) begin
+                    if (incremented_rd_ptr == wr_ptr)
+                        internal_out_valid <= 1'b0;
+                end
+            end
+        end
+    end else begin : gen_blk14_else
+        always @* begin
+            internal_out_valid = !empty & ok_to_forward;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Single Output Pipeline Stage
+    //
+    // This output pipeline stage is enabled if the FIFO's 
+    // empty latency is set to 3 (default). It is disabled
+    // for all other allowed latencies.
+    //
+    // Reason: The memory outputs are unregistered, so we have to
+    // register the output or fmax will drop if combinatorial
+    // logic is present on the output datapath.
+    // 
+    // Q: The Avalon-ST spec says that I have to register my outputs
+    //    But isn't the memory counted as a register?
+    // A: The path from the address lookup to the memory output is
+    //    slow. Registering the memory outputs is a good idea. 
+    //
+    // The registers get packed into the memory by the fitter
+    // which means minimal resources are consumed (the result
+    // is a altsyncram with registered outputs, available on 
+    // all modern Altera devices). 
+    //
+    // This output stage acts as an extra slot in the FIFO, 
+    // and complicates the fill level.
+    // --------------------------------------------------
+    generate if (EMPTY_LATENCY == 3) begin : gen_blk15
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                out_valid   <= 0;
+                out_payload <= 0;
+            end
+            else begin
+                if (internal_out_ready) begin
+                    out_valid   <= internal_out_valid & ok_to_forward;
+                    out_payload <= internal_out_payload;
+                end
+            end
+        end
+    end
+    else begin : gen_blk15_else
+        always @* begin
+            out_valid   = internal_out_valid;
+            out_payload = internal_out_payload;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Fill Level
+    //
+    // The fill level is calculated from the next write
+    // and read pointers to avoid unnecessary latency
+    // and logic.
+    //
+    // However, if the store-and-forward mode of the FIFO
+    // is enabled, the fill level is an up-down counter
+    // for fmax optimization reasons.
+    //
+    // If the output pipeline is enabled, the fill level 
+    // must account for it, or we'll always be off by one.
+    // This may, or may not be important depending on the
+    // application.
+    //
+    // For now, we'll always calculate the exact fill level
+    // at the cost of an extra adder when the output stage
+    // is enabled.
+    // --------------------------------------------------
+    generate if (USE_FILL_LEVEL) begin : gen_blk16
+        wire [31:0] depth32;
+        assign depth32 = DEPTH;
+
+        if (USE_STORE_FORWARD) begin
+
+            reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
+            
+            // --------------------------------------------------
+            // We only drop on endofpacket. As long as we don't add to the fill
+            // level on the dropped endofpacket cycle, we can simply subtract
+            // (packet length - 1) from the fill level for dropped packets.
+            // --------------------------------------------------
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    curr_packet_len_less_one <= 0;
+                end else begin
+                    if (write) begin
+                        curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
+                        if (in_endofpacket)
+                            curr_packet_len_less_one <= 0;
+                    end
+                end
+            end
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    fifo_fill_level <= 0;
+                end else if (drop_on_error) begin
+                    fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
+                    if (read)
+                        fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
+                end else if (write && !read) begin
+                    fifo_fill_level <= fifo_fill_level + 1'b1;
+                end else if (read && !write) begin
+                    fifo_fill_level <= fifo_fill_level - 1'b1;
+                end
+            end
+
+        end else begin
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) 
+                    fifo_fill_level <= 0;
+                else if (next_full & !drop_on_error)
+                    fifo_fill_level <= depth32[ADDR_WIDTH:0];
+                else begin
+                    fifo_fill_level[ADDR_WIDTH]     <= 1'b0;
+                    fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+                end
+            end
+
+        end
+
+        always @* begin
+            fill_level = fifo_fill_level;
+
+            if (EMPTY_LATENCY == 3)
+                fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+        end
+    end
+    else begin : gen_blk16_else
+        always @* begin
+            fill_level = 0;
+        end  
+    end
+    endgenerate
+
+    generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
+      assign almost_full_data = (fill_level >= almost_full_threshold);
+    end
+    else
+      assign almost_full_data = 0;
+    endgenerate
+
+    generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
+      assign almost_empty_data = (fill_level <= almost_empty_threshold);
+    end
+    else
+      assign almost_empty_data = 0;
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-MM Status & Control Connection Point
+    //
+    // Register map:
+    //
+    // | Addr   | RW |     31 - 0      |
+    // |  0     | R  |   Fill level    |
+    //
+    // The registering of this connection point means
+    // that there is a cycle of latency between 
+    // reads/writes and the updating of the fill level.
+    // --------------------------------------------------
+    generate if (USE_STORE_FORWARD) begin : gen_blk19
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              cut_through_threshold  <= 0;
+              drop_on_error_en       <= 0;
+              csr_readdata           <= 0;
+              pkt_mode               <= 1'b1;
+          end
+          else begin
+              if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 5)
+                    csr_readdata <= {31'b0, drop_on_error_en};
+                else if (csr_address == 4)
+                    csr_readdata <= {8'b0, cut_through_threshold};
+                else if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b101)
+                   drop_on_error_en       <= csr_writedata[0];
+               else if(csr_address == 3'b100) begin
+                   cut_through_threshold  <= csr_writedata[23:0];
+                   pkt_mode <= (csr_writedata[23:0] == 0);
+               end
+               else if(csr_address == 3'b011)
+                    almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end     
+          end
+      end
+    end
+    else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              csr_readdata           <= 0;
+          end
+          else begin
+             if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b011)
+                   almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end       
+          end
+      end
+    end
+    else begin : gen_blk19_else2
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              csr_readdata <= 0;
+          end
+          else if (csr_read) begin
+              csr_readdata <= 0;
+
+              if (csr_address == 0) 
+                  csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+          end
+      end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Store and forward logic
+    // --------------------------------------------------
+    // if the fifo gets full before the entire packet or the
+    // cut-threshold condition is met then start sending out
+    // data in order to avoid dead-lock situation
+
+    generate if (USE_STORE_FORWARD) begin : gen_blk20
+      assign wait_for_threshold   = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+      assign wait_for_pkt         = pkt_cnt_eq_zero  | (pkt_cnt_eq_one  & out_pkt_leave);
+      assign ok_to_forward        = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : 
+                                     ~wait_for_threshold) | fifo_too_small_r;
+      assign in_pkt_eop_arrive    = in_valid & in_ready & in_endofpacket;
+      assign in_pkt_start         = in_valid & in_ready & in_startofpacket;
+      assign in_pkt_error         = in_valid & in_ready & |in_error;
+      assign out_pkt_sop_leave    = out_valid & out_ready & out_startofpacket;
+      assign out_pkt_leave        = out_valid & out_ready & out_endofpacket;
+      assign fifo_too_small       = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+      // count packets coming and going into the fifo
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          pkt_cnt           <= 0;
+          pkt_has_started   <= 0;
+          sop_has_left_fifo <= 0;
+          fifo_too_small_r  <= 0;
+          pkt_cnt_eq_zero   <= 1'b1;
+          pkt_cnt_eq_one    <= 1'b0;
+          fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+        end
+        else begin
+          fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+          fifo_too_small_r <= fifo_too_small;
+
+          if( in_pkt_eop_arrive )
+            sop_has_left_fifo <= 1'b0;
+          else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+            sop_has_left_fifo <= 1'b1;
+
+          if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+            pkt_cnt <= pkt_cnt + 1'b1;
+            pkt_cnt_eq_zero <= 0;
+            if (pkt_cnt == 0)
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+          else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+            pkt_cnt <= pkt_cnt - 1'b1;
+            if (pkt_cnt == 1) 
+              pkt_cnt_eq_zero <= 1'b1;
+            else
+              pkt_cnt_eq_zero <= 1'b0;
+            if (pkt_cnt == 2) 
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+
+          if (in_pkt_start)
+            pkt_has_started <= 1'b1;
+          else if (in_pkt_eop_arrive)
+            pkt_has_started <= 1'b0;
+        end
+      end
+
+      // drop on error logic
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          sop_ptr <= 0;
+          error_in_pkt <= 0;
+        end
+        else begin
+          // save the location of the SOP
+          if ( in_pkt_start ) 
+            sop_ptr <= wr_ptr;
+
+          // remember if error in pkt
+          // log error only if packet has already started
+          if (in_pkt_eop_arrive)
+            error_in_pkt <= 1'b0;
+          else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+            error_in_pkt <= 1'b1;
+        end
+      end
+
+      assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & 
+                            ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+      assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
+
+    end
+    else begin : gen_blk20_else
+      assign ok_to_forward = 1'b1;
+      assign drop_on_error = 1'b0;
+      if (ADDR_WIDTH <= 1)
+        assign curr_sop_ptr = 1'b0;
+      else
+        assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv b/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv
index 0ccebc0..7823aad 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv
@@ -11,262 +11,262 @@
 // agreement for further details.
 
 
-// (C) 2001-2010 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
-// $Revision: #3 $
-// $Date: 2010/07/07 $
-// $Author: jyeap $
-
-/* -----------------------------------------------------------------------
-Round-robin/fixed arbitration implementation.
-
-Q: how do you find the least-significant set-bit in an n-bit binary number, X?
-
-A: M = X & (~X + 1)
-
-Example: X = 101000100
- 101000100 & 
- 010111011 + 1 =
-
- 101000100 &
- 010111100 =
- -----------
- 000000100
-
-The method can be generalized to find the first set-bit
-at a bit index no lower than bit-index N, simply by adding
-2**N rather than 1.
-
-
-Q: how does this relate to round-robin arbitration?
-A:
-Let X be the concatenation of all request signals.
-Let the number to be added to X (hereafter called the
-top_priority) initialize to 1, and be assigned from the
-concatenation of the previous saved-grant, left-rotated
-by one position, each time arbitration occurs.  The
-concatenation of grants is then M.
-
-Problem: consider this case:
-
-top_priority            = 010000
-request                 = 001001
-~request + top_priority = 000110
-next_grant              = 000000 <- no one is granted!
-
-There was no "set bit at a bit index no lower than bit-index 4", so 
-the result was 0.
-
-We need to propagate the carry out from (~request + top_priority) to the LSB, so
-that the sum becomes 000111, and next_grant is 000001.  This operation could be
-called a "circular add". 
-
-A bit of experimentation on the circular add reveals a significant amount of 
-delay in exiting and re-entering the carry chain - this will vary with device
-family.  Quartus also reports a combinational loop warning.  Finally, 
-Modelsim 6.3g has trouble with the expression, evaluating it to 'X'.  But 
-Modelsim _doesn't_ report a combinational loop!)
-
-An alternate solution: concatenate the request vector with itself, and OR
-corresponding bits from the top and bottom halves to determine next_grant.
-
-Example:
-
-top_priority                        =        010000
-{request, request}                  = 001001 001001
-{~request, ~request} + top_priority = 110111 000110
-result of & operation               = 000001 000000
-next_grant                          =        000001
-
-Notice that if request = 0, the sum operation will overflow, but we can ignore
-this; the next_grant result is 0 (no one granted), as you might expect.
-In the implementation, the last-granted value must be maintained as
-a non-zero value - best probably simply not to update it when no requests
-occur.
-
------------------------------------------------------------------------ */ 
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_arbitrator
-#(
-    parameter NUM_REQUESTERS = 8,
-    // --------------------------------------
-    // Implemented schemes
-    // "round-robin"
-    // "fixed-priority"
-    // "no-arb"
-    // --------------------------------------
-    parameter SCHEME         = "round-robin",
-    parameter PIPELINE       = 0
-)
-(
-    input clk,
-    input reset,
-   
-    // --------------------------------------
-    // Requests
-    // --------------------------------------
-    input [NUM_REQUESTERS-1:0]  request,
-   
-    // --------------------------------------
-    // Grants
-    // --------------------------------------
-    output [NUM_REQUESTERS-1:0] grant,
-
-    // --------------------------------------
-    // Control Signals
-    // --------------------------------------
-    input                       increment_top_priority,
-    input                       save_top_priority
-);
-
-    // --------------------------------------
-    // Signals
-    // --------------------------------------
-    wire [NUM_REQUESTERS-1:0]   top_priority;
-    reg  [NUM_REQUESTERS-1:0]   top_priority_reg;
-    reg  [NUM_REQUESTERS-1:0]   last_grant;
-    wire [2*NUM_REQUESTERS-1:0] result;
-
-    // --------------------------------------
-    // Scheme Selection
-    // --------------------------------------
-    generate
-        if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
-            assign top_priority = top_priority_reg;
-        end
-        else begin
-            // Fixed arbitration (or single-requester corner case)
-            assign top_priority = 1'b1;
-        end
-    endgenerate
-
-    // --------------------------------------
-    // Decision Logic
-    // --------------------------------------
-    altera_merlin_arb_adder
-    #(
-        .WIDTH (2 * NUM_REQUESTERS)
-    ) 
-    adder
-    (
-        .a ({ ~request, ~request }),
-        .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
-        .sum (result)
-    );
-
-  
-    generate if (SCHEME == "no-arb") begin
-
-        // --------------------------------------
-        // No arbitration: just wire request directly to grant
-        // --------------------------------------
-        assign grant = request;
-
-    end else begin
-        // Do the math in double-vector domain
-        wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
-        assign grant_double_vector = {request, request} & result;
-
-        // --------------------------------------
-        // Extract grant from the top and bottom halves
-        // of the double vector.
-        // --------------------------------------
-        assign grant =
-            grant_double_vector[NUM_REQUESTERS - 1 : 0] |
-            grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
-
-    end
-    endgenerate
-
-    // --------------------------------------
-    // Left-rotate the last grant vector to create top_priority.
-    // --------------------------------------
-    always @(posedge clk or posedge reset) begin
-        if (reset) begin
-            top_priority_reg <= 1'b1;
-        end
-        else begin
-            if (PIPELINE) begin
-                if (increment_top_priority) begin
-                    top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
-                        grant[NUM_REQUESTERS-1]} : top_priority_reg;
-                end
-            end else begin
-                if (increment_top_priority) begin
-                    if (|request)
-                        top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
-                            grant[NUM_REQUESTERS-1] };
-                    else
-                        top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
-                end
-                else if (save_top_priority) begin
-                    top_priority_reg <= grant; 
-                end
-            end
-        end
-    end
-
-endmodule
-
-// ----------------------------------------------
-// Adder for the standard arbitrator
-// ----------------------------------------------
-module altera_merlin_arb_adder
-#(
-    parameter WIDTH = 8
-)
-(
-    input [WIDTH-1:0] a,
-    input [WIDTH-1:0] b,
-
-    output [WIDTH-1:0] sum
-);
-
-    wire [WIDTH:0] sum_lint;
-    // ----------------------------------------------
-    // Benchmarks indicate that for small widths, the full
-    // adder has higher fmax because synthesis can merge
-    // it with the mux, allowing partial decisions to be 
-    // made early.
-    //
-    // The magic number is 4 requesters, which means an
-    // 8 bit adder.
-    // ----------------------------------------------
-    genvar i;
-    generate if (WIDTH <= 8) begin : full_adder
-
-        wire cout[WIDTH-1:0];
-
-        assign sum[0]  = (a[0] ^ b[0]);
-        assign cout[0] = (a[0] & b[0]);
-
-        for (i = 1; i < WIDTH; i = i+1) begin : arb
-
-            assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
-            assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
-
-        end
-
-    end else begin : carry_chain
-
-        assign sum_lint = a + b;
-        assign sum = sum_lint[WIDTH-1:0];
-
-    end
-    endgenerate
-
-endmodule
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
+// $Revision: #3 $
+// $Date: 2010/07/07 $
+// $Author: jyeap $
+
+/* -----------------------------------------------------------------------
+Round-robin/fixed arbitration implementation.
+
+Q: how do you find the least-significant set-bit in an n-bit binary number, X?
+
+A: M = X & (~X + 1)
+
+Example: X = 101000100
+ 101000100 & 
+ 010111011 + 1 =
+
+ 101000100 &
+ 010111100 =
+ -----------
+ 000000100
+
+The method can be generalized to find the first set-bit
+at a bit index no lower than bit-index N, simply by adding
+2**N rather than 1.
+
+
+Q: how does this relate to round-robin arbitration?
+A:
+Let X be the concatenation of all request signals.
+Let the number to be added to X (hereafter called the
+top_priority) initialize to 1, and be assigned from the
+concatenation of the previous saved-grant, left-rotated
+by one position, each time arbitration occurs.  The
+concatenation of grants is then M.
+
+Problem: consider this case:
+
+top_priority            = 010000
+request                 = 001001
+~request + top_priority = 000110
+next_grant              = 000000 <- no one is granted!
+
+There was no "set bit at a bit index no lower than bit-index 4", so 
+the result was 0.
+
+We need to propagate the carry out from (~request + top_priority) to the LSB, so
+that the sum becomes 000111, and next_grant is 000001.  This operation could be
+called a "circular add". 
+
+A bit of experimentation on the circular add reveals a significant amount of 
+delay in exiting and re-entering the carry chain - this will vary with device
+family.  Quartus also reports a combinational loop warning.  Finally, 
+Modelsim 6.3g has trouble with the expression, evaluating it to 'X'.  But 
+Modelsim _doesn't_ report a combinational loop!)
+
+An alternate solution: concatenate the request vector with itself, and OR
+corresponding bits from the top and bottom halves to determine next_grant.
+
+Example:
+
+top_priority                        =        010000
+{request, request}                  = 001001 001001
+{~request, ~request} + top_priority = 110111 000110
+result of & operation               = 000001 000000
+next_grant                          =        000001
+
+Notice that if request = 0, the sum operation will overflow, but we can ignore
+this; the next_grant result is 0 (no one granted), as you might expect.
+In the implementation, the last-granted value must be maintained as
+a non-zero value - best probably simply not to update it when no requests
+occur.
+
+----------------------------------------------------------------------- */ 
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_arbitrator
+#(
+    parameter NUM_REQUESTERS = 8,
+    // --------------------------------------
+    // Implemented schemes
+    // "round-robin"
+    // "fixed-priority"
+    // "no-arb"
+    // --------------------------------------
+    parameter SCHEME         = "round-robin",
+    parameter PIPELINE       = 0
+)
+(
+    input clk,
+    input reset,
+   
+    // --------------------------------------
+    // Requests
+    // --------------------------------------
+    input [NUM_REQUESTERS-1:0]  request,
+   
+    // --------------------------------------
+    // Grants
+    // --------------------------------------
+    output [NUM_REQUESTERS-1:0] grant,
+
+    // --------------------------------------
+    // Control Signals
+    // --------------------------------------
+    input                       increment_top_priority,
+    input                       save_top_priority
+);
+
+    // --------------------------------------
+    // Signals
+    // --------------------------------------
+    wire [NUM_REQUESTERS-1:0]   top_priority;
+    reg  [NUM_REQUESTERS-1:0]   top_priority_reg;
+    reg  [NUM_REQUESTERS-1:0]   last_grant;
+    wire [2*NUM_REQUESTERS-1:0] result;
+
+    // --------------------------------------
+    // Scheme Selection
+    // --------------------------------------
+    generate
+        if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
+            assign top_priority = top_priority_reg;
+        end
+        else begin
+            // Fixed arbitration (or single-requester corner case)
+            assign top_priority = 1'b1;
+        end
+    endgenerate
+
+    // --------------------------------------
+    // Decision Logic
+    // --------------------------------------
+    altera_merlin_arb_adder
+    #(
+        .WIDTH (2 * NUM_REQUESTERS)
+    ) 
+    adder
+    (
+        .a ({ ~request, ~request }),
+        .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
+        .sum (result)
+    );
+
+  
+    generate if (SCHEME == "no-arb") begin
+
+        // --------------------------------------
+        // No arbitration: just wire request directly to grant
+        // --------------------------------------
+        assign grant = request;
+
+    end else begin
+        // Do the math in double-vector domain
+        wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
+        assign grant_double_vector = {request, request} & result;
+
+        // --------------------------------------
+        // Extract grant from the top and bottom halves
+        // of the double vector.
+        // --------------------------------------
+        assign grant =
+            grant_double_vector[NUM_REQUESTERS - 1 : 0] |
+            grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
+
+    end
+    endgenerate
+
+    // --------------------------------------
+    // Left-rotate the last grant vector to create top_priority.
+    // --------------------------------------
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            top_priority_reg <= 1'b1;
+        end
+        else begin
+            if (PIPELINE) begin
+                if (increment_top_priority) begin
+                    top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
+                        grant[NUM_REQUESTERS-1]} : top_priority_reg;
+                end
+            end else begin
+                if (increment_top_priority) begin
+                    if (|request)
+                        top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
+                            grant[NUM_REQUESTERS-1] };
+                    else
+                        top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
+                end
+                else if (save_top_priority) begin
+                    top_priority_reg <= grant; 
+                end
+            end
+        end
+    end
+
+endmodule
+
+// ----------------------------------------------
+// Adder for the standard arbitrator
+// ----------------------------------------------
+module altera_merlin_arb_adder
+#(
+    parameter WIDTH = 8
+)
+(
+    input [WIDTH-1:0] a,
+    input [WIDTH-1:0] b,
+
+    output [WIDTH-1:0] sum
+);
+
+    wire [WIDTH:0] sum_lint;
+    // ----------------------------------------------
+    // Benchmarks indicate that for small widths, the full
+    // adder has higher fmax because synthesis can merge
+    // it with the mux, allowing partial decisions to be 
+    // made early.
+    //
+    // The magic number is 4 requesters, which means an
+    // 8 bit adder.
+    // ----------------------------------------------
+    genvar i;
+    generate if (WIDTH <= 8) begin : full_adder
+
+        wire cout[WIDTH-1:0];
+
+        assign sum[0]  = (a[0] ^ b[0]);
+        assign cout[0] = (a[0] & b[0]);
+
+        for (i = 1; i < WIDTH; i = i+1) begin : arb
+
+            assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
+            assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
+
+        end
+
+    end else begin : carry_chain
+
+        assign sum_lint = a + b;
+        assign sum = sum_lint[WIDTH-1:0];
+
+    end
+    endgenerate
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv
index dfa5cac..fef7f2e 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv
@@ -11,286 +11,286 @@
 // agreement for further details.
 
 
-// (C) 2001-2012 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// ------------------------------------------
-// Merlin Burst Uncompressor
-//
-// Compressed read bursts -> uncompressed
-// ------------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_burst_uncompressor
-#(
-    parameter ADDR_W      = 16,
-    parameter BURSTWRAP_W = 3,
-    parameter BYTE_CNT_W  = 4,
-    parameter PKT_SYMBOLS = 4,
-    parameter BURST_SIZE_W = 3
-)
-(
-    input clk,
-    input reset,
-   
-    // sink ST signals
-    input sink_startofpacket,
-    input sink_endofpacket,
-    input sink_valid,
-    output sink_ready,
-   
-    // sink ST "data"
-    input [ADDR_W - 1: 0] sink_addr,
-    input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
-    input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
-    input sink_is_compressed,
-    input [BURST_SIZE_W-1 : 0] sink_burstsize,
-   
-    // source ST signals
-    output source_startofpacket,
-    output source_endofpacket,
-    output source_valid,
-    input source_ready,
-   
-    // source ST "data"
-    output [ADDR_W - 1: 0] source_addr,
-    output [BURSTWRAP_W - 1 : 0] source_burstwrap,
-    output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
-   
-    // Note: in the slave agent, the output should always be uncompressed.  In
-    // other applications, it may be required to leave-compressed or not. How to
-    // control?  Seems like a simple mux - pass-through if no uncompression is
-    // required.
-    output source_is_compressed,
-    output [BURST_SIZE_W-1 : 0] source_burstsize
-);
-
-//----------------------------------------------------
-// AXSIZE decoding
-//
-// Turns the axsize value into the actual number of bytes
-// being transferred.
-// ---------------------------------------------------
-function reg[63:0] bytes_in_transfer;
-    input [BURST_SIZE_W-1:0] axsize;
-    case (axsize)
-        4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
-        4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
-        4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
-        4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
-        4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
-        4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
-        4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
-        4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
-        4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
-        4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
-        default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
-    endcase
-
-endfunction  
-
-   // num_symbols is PKT_SYMBOLS, appropriately sized.
-   wire [31:0] int_num_symbols = PKT_SYMBOLS;
-   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
-  
-   // def: Burst Compression.  In a merlin network, a compressed burst is one 
-   // which is transmitted in a single beat.  Example: read burst.  In 
-   // constrast, an uncompressed burst (example: write burst) is transmitted in
-   // one beat per writedata item.
-   //
-   // For compressed bursts which require response packets, burst
-   // uncompression is required.  Concrete example: a read burst of size 8
-   // occupies one response-fifo position.  When that fifo position reaches the
-   // front of the FIFO, the slave starts providing the required 8 readdatavalid
-   // pulses.  The 8 return response beats must be provided in a single packet,
-   // with incrementing address and decrementing byte_cnt fields.  Upon receipt
-   // of the final readdata item of the burst, the response FIFO item is
-   // retired.
-   // Burst uncompression logic provides:
-   //   a) 2-state FSM (idle, busy)
-   //     reset to idle state
-   //     transition to busy state for 2nd and subsequent rdv pulses
-   //     - a single-cycle burst (aka non-burst read) causes no transition to
-   //     busy state.
-   //   b) response startofpacket/endofpacket logic.  The response FIFO item 
-   //   will have sop asserted, and may have eop asserted. (In the case of
-   //   multiple read bursts transmit in the command fabric in a single packet,
-   //   the eop assertion will come in a later FIFO item.)  To support packet
-   //   conservation, and emit a well-formed packet on the response fabric,
-   //     i) response fabric startofpacket is asserted only for the first resp.
-   //     beat;
-   //     ii) response fabric endofpacket is asserted only for the last resp.
-   //     beat.
-   //   c) response address field.  The response address field contains an
-   //   incrementing sequence, such that each readdata item is associated with
-   //   its slave-map location.  N.b. a) computing the address correctly requires
-   //   knowledge of burstwrap behavior b) there may be no clients of the address
-   //   field, which makes this field a good target for optimization.  See
-   //   burst_uncompress_address_counter below.
-   //   d) response byte_cnt field.  The response byte_cnt field contains a
-   //   decrementing sequence, such that each beat of the response contains the
-   //   count of bytes to follow.  In the case of sub-bursts in a single packet,
-   //   the byte_cnt field may decrement down to num_symbols, then back up to
-   //   some value, multiple times in the packet.
-  
-   reg burst_uncompress_busy;
-   reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
-   wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
-   wire first_packet_beat;
-   wire last_packet_beat;
-
-   assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
-   assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
-
-   // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
-   // the output.
-   assign source_byte_cnt =
-     first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
-   assign source_valid = sink_valid;
-  
-   // Last packet beat is set throughout receipt of an uncompressed read burst
-   // from the response FIFO - this forces all the burst uncompression machinery
-   // idle.
-   assign last_packet_beat = ~sink_is_compressed |
-     (
-     burst_uncompress_busy ?
-       (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
-         sink_valid & (sink_byte_cnt == num_symbols)
-     );
-  
-   always @(posedge clk or posedge reset) begin
-     if (reset) begin
-       burst_uncompress_busy <= '0;
-       burst_uncompress_byte_counter <= '0;
-     end
-     else begin
-       if (source_valid & source_ready & sink_valid) begin
-         // No matter what the current state, last_packet_beat leads to
-         // idle.
-         if (last_packet_beat) begin
-           burst_uncompress_busy <= '0;
-           burst_uncompress_byte_counter <= '0;
-         end
-         else begin
-           if (burst_uncompress_busy) begin
-             burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? 
-               (burst_uncompress_byte_counter_lint - num_symbols) :
-               (sink_byte_cnt - num_symbols);
-           end
-           else begin // not busy, at least one more beat to go
-             burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
-             // To do: should busy go true for numsymbols-size compressed
-             // bursts?
-             burst_uncompress_busy <= 1'b1;
-           end
-         end
-       end
-     end
-   end
-  
-   reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
-   reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
-
-   wire [63:0] decoded_burstsize_wire;
-   wire [ADDR_W-1:0] decoded_burstsize;
-
-
-   localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
-   wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
-   // The input burstwrap value can be used as a mask against address values,
-   // but with one caveat: the address width may be (probably is) wider than 
-   // the burstwrap width.  The spec says: extend the msb of the burstwrap 
-   // value out over the entire address width (but only if the address width
-   // actually is wider than the burstwrap width; otherwise it's a 0-width or
-   // negative range and concatenation multiplier). 
-   generate
-      if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
-         // Sign-extend, just wires:
-            assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
-                {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
-            assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
-      end
-      else begin
-            assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
-      end
-   endgenerate
-
-   always @(posedge clk or posedge reset) begin
-     if (reset) begin
-       burst_uncompress_address_base <= '0;
-     end
-     else if (first_packet_beat & source_ready) begin
-       burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
-     end
-   end
-
-   assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);  //expand it to 64 bits
-   assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];      //then take the width that is needed
-
-   wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
-   (
-     (first_packet_beat ?
-       sink_addr :
-       burst_uncompress_address_offset) + decoded_burstsize
-    ) &
-    addr_width_burstwrap[ADDR_W-1:0];
-    wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
-
-   always @(posedge clk or posedge reset) begin
-     if (reset) begin
-       burst_uncompress_address_offset <= '0;
-     end
-     else begin
-       if (source_ready & source_valid) begin
-         burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
-         // if (first_packet_beat) begin
-         //   burst_uncompress_address_offset <=
-         //     (sink_addr + num_symbols) & addr_width_burstwrap;
-         // end
-         // else begin
-         //   burst_uncompress_address_offset <=
-         //     (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
-         // end
-       end
-     end
-   end
-  
-   // On the first packet beat, send the input address out unchanged, 
-   // while values are computed/registered for 2nd and subsequent beats.
-   assign source_addr = first_packet_beat ? sink_addr :
-       burst_uncompress_address_base | burst_uncompress_address_offset;
-   assign source_burstwrap = sink_burstwrap;
-   assign source_burstsize = sink_burstsize;
-  
-   //-------------------------------------------------------------------
-   // A single (compressed) read burst will have sop/eop in the same beat.
-   // A sequence of read sub-bursts emitted by a burst adapter in response to a
-   // single read burst will have sop on the first sub-burst, eop on the last.
-   // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve 
-   // packet conservation.
-   assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
-   assign source_endofpacket   = sink_endofpacket & last_packet_beat;
-   assign sink_ready = source_valid & source_ready & last_packet_beat;
-  
-   // This is correct for the slave agent usage, but won't always be true in the
-   // width adapter.  To do: add an "please uncompress" input, and use it to
-   // pass-through or modify, and set source_is_compressed accordingly.
-   assign source_is_compressed = 1'b0;
-endmodule
-
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Burst Uncompressor
+//
+// Compressed read bursts -> uncompressed
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_burst_uncompressor
+#(
+    parameter ADDR_W      = 16,
+    parameter BURSTWRAP_W = 3,
+    parameter BYTE_CNT_W  = 4,
+    parameter PKT_SYMBOLS = 4,
+    parameter BURST_SIZE_W = 3
+)
+(
+    input clk,
+    input reset,
+   
+    // sink ST signals
+    input sink_startofpacket,
+    input sink_endofpacket,
+    input sink_valid,
+    output sink_ready,
+   
+    // sink ST "data"
+    input [ADDR_W - 1: 0] sink_addr,
+    input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
+    input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
+    input sink_is_compressed,
+    input [BURST_SIZE_W-1 : 0] sink_burstsize,
+   
+    // source ST signals
+    output source_startofpacket,
+    output source_endofpacket,
+    output source_valid,
+    input source_ready,
+   
+    // source ST "data"
+    output [ADDR_W - 1: 0] source_addr,
+    output [BURSTWRAP_W - 1 : 0] source_burstwrap,
+    output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
+   
+    // Note: in the slave agent, the output should always be uncompressed.  In
+    // other applications, it may be required to leave-compressed or not. How to
+    // control?  Seems like a simple mux - pass-through if no uncompression is
+    // required.
+    output source_is_compressed,
+    output [BURST_SIZE_W-1 : 0] source_burstsize
+);
+
+//----------------------------------------------------
+// AXSIZE decoding
+//
+// Turns the axsize value into the actual number of bytes
+// being transferred.
+// ---------------------------------------------------
+function reg[63:0] bytes_in_transfer;
+    input [BURST_SIZE_W-1:0] axsize;
+    case (axsize)
+        4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+        4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+        4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+        4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+        4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+        4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+        4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+        4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+        4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+        4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+        default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+    endcase
+
+endfunction  
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+  
+   // def: Burst Compression.  In a merlin network, a compressed burst is one 
+   // which is transmitted in a single beat.  Example: read burst.  In 
+   // constrast, an uncompressed burst (example: write burst) is transmitted in
+   // one beat per writedata item.
+   //
+   // For compressed bursts which require response packets, burst
+   // uncompression is required.  Concrete example: a read burst of size 8
+   // occupies one response-fifo position.  When that fifo position reaches the
+   // front of the FIFO, the slave starts providing the required 8 readdatavalid
+   // pulses.  The 8 return response beats must be provided in a single packet,
+   // with incrementing address and decrementing byte_cnt fields.  Upon receipt
+   // of the final readdata item of the burst, the response FIFO item is
+   // retired.
+   // Burst uncompression logic provides:
+   //   a) 2-state FSM (idle, busy)
+   //     reset to idle state
+   //     transition to busy state for 2nd and subsequent rdv pulses
+   //     - a single-cycle burst (aka non-burst read) causes no transition to
+   //     busy state.
+   //   b) response startofpacket/endofpacket logic.  The response FIFO item 
+   //   will have sop asserted, and may have eop asserted. (In the case of
+   //   multiple read bursts transmit in the command fabric in a single packet,
+   //   the eop assertion will come in a later FIFO item.)  To support packet
+   //   conservation, and emit a well-formed packet on the response fabric,
+   //     i) response fabric startofpacket is asserted only for the first resp.
+   //     beat;
+   //     ii) response fabric endofpacket is asserted only for the last resp.
+   //     beat.
+   //   c) response address field.  The response address field contains an
+   //   incrementing sequence, such that each readdata item is associated with
+   //   its slave-map location.  N.b. a) computing the address correctly requires
+   //   knowledge of burstwrap behavior b) there may be no clients of the address
+   //   field, which makes this field a good target for optimization.  See
+   //   burst_uncompress_address_counter below.
+   //   d) response byte_cnt field.  The response byte_cnt field contains a
+   //   decrementing sequence, such that each beat of the response contains the
+   //   count of bytes to follow.  In the case of sub-bursts in a single packet,
+   //   the byte_cnt field may decrement down to num_symbols, then back up to
+   //   some value, multiple times in the packet.
+  
+   reg burst_uncompress_busy;
+   reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
+   wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
+   wire first_packet_beat;
+   wire last_packet_beat;
+
+   assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
+   assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
+
+   // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
+   // the output.
+   assign source_byte_cnt =
+     first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
+   assign source_valid = sink_valid;
+  
+   // Last packet beat is set throughout receipt of an uncompressed read burst
+   // from the response FIFO - this forces all the burst uncompression machinery
+   // idle.
+   assign last_packet_beat = ~sink_is_compressed |
+     (
+     burst_uncompress_busy ?
+       (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
+         sink_valid & (sink_byte_cnt == num_symbols)
+     );
+  
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_busy <= '0;
+       burst_uncompress_byte_counter <= '0;
+     end
+     else begin
+       if (source_valid & source_ready & sink_valid) begin
+         // No matter what the current state, last_packet_beat leads to
+         // idle.
+         if (last_packet_beat) begin
+           burst_uncompress_busy <= '0;
+           burst_uncompress_byte_counter <= '0;
+         end
+         else begin
+           if (burst_uncompress_busy) begin
+             burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? 
+               (burst_uncompress_byte_counter_lint - num_symbols) :
+               (sink_byte_cnt - num_symbols);
+           end
+           else begin // not busy, at least one more beat to go
+             burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
+             // To do: should busy go true for numsymbols-size compressed
+             // bursts?
+             burst_uncompress_busy <= 1'b1;
+           end
+         end
+       end
+     end
+   end
+  
+   reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
+   reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
+
+   wire [63:0] decoded_burstsize_wire;
+   wire [ADDR_W-1:0] decoded_burstsize;
+
+
+   localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
+   wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
+   // The input burstwrap value can be used as a mask against address values,
+   // but with one caveat: the address width may be (probably is) wider than 
+   // the burstwrap width.  The spec says: extend the msb of the burstwrap 
+   // value out over the entire address width (but only if the address width
+   // actually is wider than the burstwrap width; otherwise it's a 0-width or
+   // negative range and concatenation multiplier). 
+   generate
+      if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
+         // Sign-extend, just wires:
+            assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
+                {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
+            assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
+      end
+      else begin
+            assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
+      end
+   endgenerate
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_base <= '0;
+     end
+     else if (first_packet_beat & source_ready) begin
+       burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
+     end
+   end
+
+   assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);  //expand it to 64 bits
+   assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];      //then take the width that is needed
+
+   wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
+   (
+     (first_packet_beat ?
+       sink_addr :
+       burst_uncompress_address_offset) + decoded_burstsize
+    ) &
+    addr_width_burstwrap[ADDR_W-1:0];
+    wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_offset <= '0;
+     end
+     else begin
+       if (source_ready & source_valid) begin
+         burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
+         // if (first_packet_beat) begin
+         //   burst_uncompress_address_offset <=
+         //     (sink_addr + num_symbols) & addr_width_burstwrap;
+         // end
+         // else begin
+         //   burst_uncompress_address_offset <=
+         //     (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
+         // end
+       end
+     end
+   end
+  
+   // On the first packet beat, send the input address out unchanged, 
+   // while values are computed/registered for 2nd and subsequent beats.
+   assign source_addr = first_packet_beat ? sink_addr :
+       burst_uncompress_address_base | burst_uncompress_address_offset;
+   assign source_burstwrap = sink_burstwrap;
+   assign source_burstsize = sink_burstsize;
+  
+   //-------------------------------------------------------------------
+   // A single (compressed) read burst will have sop/eop in the same beat.
+   // A sequence of read sub-bursts emitted by a burst adapter in response to a
+   // single read burst will have sop on the first sub-burst, eop on the last.
+   // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve 
+   // packet conservation.
+   assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
+   assign source_endofpacket   = sink_endofpacket & last_packet_beat;
+   assign sink_ready = source_valid & source_ready & last_packet_beat;
+  
+   // This is correct for the slave agent usage, but won't always be true in the
+   // width adapter.  To do: add an "please uncompress" input, and use it to
+   // pass-through or modify, and set source_is_compressed accordingly.
+   assign source_is_compressed = 1'b0;
+endmodule
+
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv b/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv
index 4cbc92b..424ec4e 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv
@@ -11,293 +11,293 @@
 // agreement for further details.
 
 
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// --------------------------------------
-// Merlin Master Agent
-//
-// Converts Avalon-MM transactions into
-// Merlin network packets.
-// --------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_master_agent
-#(
-   // -------------------
-   // Packet Format Parameters
-   // -------------------
-   parameter 
-   PKT_QOS_H                  = 109,
-   PKT_QOS_L                  = 106,
-   PKT_DATA_SIDEBAND_H        = 105,
-   PKT_DATA_SIDEBAND_L        = 98,
-   PKT_ADDR_SIDEBAND_H        = 97, 
-   PKT_ADDR_SIDEBAND_L        = 93,
-   PKT_CACHE_H                = 92,
-   PKT_CACHE_L                = 89,
-   PKT_THREAD_ID_H            = 88,
-   PKT_THREAD_ID_L            = 87,
-   PKT_BEGIN_BURST            = 81,
-   PKT_PROTECTION_H           = 80,
-   PKT_PROTECTION_L           = 80,
-   PKT_BURSTWRAP_H            = 79,
-   PKT_BURSTWRAP_L            = 77,
-   PKT_BYTE_CNT_H             = 76,
-   PKT_BYTE_CNT_L             = 74,
-   PKT_ADDR_H                 = 73,
-   PKT_ADDR_L                 = 42,
-   PKT_BURST_SIZE_H           = 86,
-   PKT_BURST_SIZE_L           = 84,
-   PKT_BURST_TYPE_H           = 94,
-   PKT_BURST_TYPE_L           = 93,
-   PKT_TRANS_EXCLUSIVE        = 83,
-   PKT_TRANS_LOCK             = 82,
-   PKT_TRANS_COMPRESSED_READ  = 41,
-   PKT_TRANS_POSTED           = 40,
-   PKT_TRANS_WRITE            = 39,
-   PKT_TRANS_READ             = 38,
-   PKT_DATA_H                 = 37,
-   PKT_DATA_L                 = 6,
-   PKT_BYTEEN_H               = 5,
-   PKT_BYTEEN_L               = 2,
-   PKT_SRC_ID_H               = 1,
-   PKT_SRC_ID_L               = 1,
-   PKT_DEST_ID_H              = 0,
-   PKT_DEST_ID_L              = 0,
-   PKT_RESPONSE_STATUS_L      = 110,
-   PKT_RESPONSE_STATUS_H      = 111,
-   PKT_ORI_BURST_SIZE_L       = 112,
-   PKT_ORI_BURST_SIZE_H       = 114,
-   ST_DATA_W                  = 115,
-   ST_CHANNEL_W               = 1,
-
-   // -------------------
-   // Agent Parameters
-   // -------------------
-   AV_BURSTCOUNT_W       = 3,
-   ID                    = 1,
-   SUPPRESS_0_BYTEEN_RSP = 1,
-   BURSTWRAP_VALUE       = 4,
-   CACHE_VALUE           = 0,
-   SECURE_ACCESS_BIT     = 1,
-   USE_READRESPONSE      = 0,
-   USE_WRITERESPONSE     = 0,
-
-   // -------------------
-   // Derived Parameters
-   // -------------------
-   PKT_BURSTWRAP_W   = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
-   PKT_BYTE_CNT_W    = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
-   PKT_PROTECTION_W  = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
-   PKT_ADDR_W        = PKT_ADDR_H - PKT_ADDR_L + 1,
-   PKT_DATA_W        = PKT_DATA_H - PKT_DATA_L + 1,
-   PKT_BYTEEN_W      = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
-   PKT_SRC_ID_W      = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
-   PKT_DEST_ID_W     = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
-   PKT_BURST_SIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
-) (
-   // -------------------
-   // Clock & Reset
-   // -------------------
-   input                         clk,
-   input                         reset,
-
-   // -------------------
-   // Avalon-MM Anti-Master
-   // -------------------
-   input [PKT_ADDR_W-1 : 0]      av_address,
-   input                         av_write,
-   input                         av_read,
-   input [PKT_DATA_W-1 : 0]      av_writedata,
-   output reg [PKT_DATA_W-1 : 0] av_readdata,
-   output reg                    av_waitrequest,
-   output reg                    av_readdatavalid,
-   input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
-   input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
-   input                         av_debugaccess,
-   input                         av_lock,
-   output reg [1 : 0]            av_response,
-   output reg                    av_writeresponsevalid,
-
-   // -------------------
-   // Command Source
-   // -------------------
-   output reg                    cp_valid,
-   output reg [ST_DATA_W-1 : 0]  cp_data,
-   output wire                   cp_startofpacket,
-   output wire                   cp_endofpacket,
-   input                         cp_ready,
-
-   // -------------------
-   // Response Sink
-   // -------------------
-   input                         rp_valid,
-   input [ST_DATA_W-1 : 0]       rp_data,
-   input [ST_CHANNEL_W-1 : 0]    rp_channel,
-   input                         rp_startofpacket,
-   input                         rp_endofpacket,
-   output reg                    rp_ready
-);
-    // ------------------------------------------------------------
-    // Utility Functions
-    // ------------------------------------------------------------
-   function integer clogb2;
-      input [31 : 0] value;
-      begin
-         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
-            value = value >> 1;
-         clogb2 = clogb2 - 1;
-      end
-   endfunction // clogb2
-
-   localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
-   localparam NUMSYMBOLS   = PKT_BYTEEN_W; 
-   localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
-   localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
-   localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
-
-   typedef enum bit  [1 : 0]
-   {
-      FIXED       = 2'b00,
-      INCR        = 2'b01,
-      WRAP        = 2'b10,
-      OTHER_WRAP  = 2'b11
-   } MerlinBurstType;
-
-   // --------------------------------------
-   // Potential optimization: compare in words to save bits?
-   // --------------------------------------
-   wire is_burst;
-   assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
-
-   wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
-   wire [31 : 0] id_int              = ID; 
-   wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
-   wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
-
-   // --------------------------------------
-   // Address alignment
-   //
-   // The packet format requires that addresses be aligned to
-   // the transaction size.
-   // --------------------------------------
-   wire [PKT_ADDR_W-1 : 0] av_address_aligned;
-   generate 
-      if (NUMSYMBOLS > 1) begin
-         assign av_address_aligned = 
-         {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
-      end
-      else begin
-         assign av_address_aligned = av_address;
-      end 
-   endgenerate
-
-   // --------------------------------------
-   // Command & Response Construction
-   // --------------------------------------
-   always_comb begin
-      cp_data                                              = '0;
-
-      cp_data[PKT_PROTECTION_L]                            = av_debugaccess;    
-      cp_data[PKT_PROTECTION_L+1]                          = SECURE_ACCESS_BIT[0];  // secure cache bit
-      cp_data[PKT_PROTECTION_L+2]                          = 1'b0;                  // instruction/data cache bit
-      cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]           = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
-      cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]             = av_burstcount;
-      cp_data[PKT_ADDR_H : PKT_ADDR_L]                     = av_address_aligned;
-      cp_data[PKT_TRANS_EXCLUSIVE]                         = 1'b0;
-      cp_data[PKT_TRANS_LOCK]                              = av_lock;
-      cp_data[PKT_TRANS_COMPRESSED_READ]                   = av_read & is_burst;
-      cp_data[PKT_TRANS_READ]                              = av_read;
-      cp_data[PKT_TRANS_WRITE]                             = av_write;
-      cp_data[PKT_TRANS_POSTED]                            = av_write & !USE_WRITERESPONSE;
-      cp_data[PKT_DATA_H : PKT_DATA_L]                     = av_writedata;
-      cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L]                 = av_byteenable;
-      cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]         = burstsize_sig;
-      cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
-      cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]         = bursttype_value;
-      cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L]                 = id_int[PKT_SRC_ID_W-1 : 0];
-      cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L]           = '0;
-      cp_data[PKT_CACHE_H : PKT_CACHE_L]                   = CACHE_VALUE[3 : 0];
-      cp_data[PKT_QOS_H : PKT_QOS_L]                       = '0;        
-      cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L]   = '0;
-      cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L]   = '0;
-
-      av_readdata                                          = rp_data[PKT_DATA_H : PKT_DATA_L];
-      if (USE_WRITERESPONSE || USE_READRESPONSE)
-         av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
-      else
-         av_response = '0;
-      end
-
-   // --------------------------------------
-   // Command Control
-   // --------------------------------------
-   reg hold_waitrequest;
-
-   always @ (posedge clk, posedge reset) begin
-      if (reset)
-         hold_waitrequest <= 1'b1;
-      else
-         hold_waitrequest <= 1'b0;
-   end  
-   
-   always_comb begin
-      cp_valid = 0;
-
-      if ((av_write || av_read) && ~hold_waitrequest)
-         cp_valid = 1;
-   end
-
-   generate if (BURSTING) begin
-      reg sop_enable;
-
-      always @(posedge clk, posedge reset) begin
-         if (reset) begin
-            sop_enable <= 1'b1;
-         end
-         else begin
-            if (cp_valid && cp_ready) begin
-               sop_enable <= 1'b0;
-               if (cp_endofpacket)
-                  sop_enable <= 1'b1;
-            end
-         end
-      end
-
-      assign cp_startofpacket = sop_enable;
-      assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
-
-   end 
-   else begin
-
-      assign cp_startofpacket = 1'b1;
-      assign cp_endofpacket   = 1'b1;
-
-   end
-   endgenerate
-
-   // --------------------------------------
-   // Backpressure & Readdatavalid
-   // --------------------------------------
-   always_comb begin
-      rp_ready              = 1;
-      av_readdatavalid      = 0;
-      av_writeresponsevalid = 0;
-      av_waitrequest = hold_waitrequest | !cp_ready;
-
-      if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
-         av_writeresponsevalid = rp_valid;
-      else
-         av_readdatavalid      = rp_valid;
-
-      if (SUPPRESS_0_BYTEEN_RSP) begin
-         if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
-            av_readdatavalid = 0;
-      end
-   end
-
-endmodule
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Agent
+//
+// Converts Avalon-MM transactions into
+// Merlin network packets.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_agent
+#(
+   // -------------------
+   // Packet Format Parameters
+   // -------------------
+   parameter 
+   PKT_QOS_H                  = 109,
+   PKT_QOS_L                  = 106,
+   PKT_DATA_SIDEBAND_H        = 105,
+   PKT_DATA_SIDEBAND_L        = 98,
+   PKT_ADDR_SIDEBAND_H        = 97, 
+   PKT_ADDR_SIDEBAND_L        = 93,
+   PKT_CACHE_H                = 92,
+   PKT_CACHE_L                = 89,
+   PKT_THREAD_ID_H            = 88,
+   PKT_THREAD_ID_L            = 87,
+   PKT_BEGIN_BURST            = 81,
+   PKT_PROTECTION_H           = 80,
+   PKT_PROTECTION_L           = 80,
+   PKT_BURSTWRAP_H            = 79,
+   PKT_BURSTWRAP_L            = 77,
+   PKT_BYTE_CNT_H             = 76,
+   PKT_BYTE_CNT_L             = 74,
+   PKT_ADDR_H                 = 73,
+   PKT_ADDR_L                 = 42,
+   PKT_BURST_SIZE_H           = 86,
+   PKT_BURST_SIZE_L           = 84,
+   PKT_BURST_TYPE_H           = 94,
+   PKT_BURST_TYPE_L           = 93,
+   PKT_TRANS_EXCLUSIVE        = 83,
+   PKT_TRANS_LOCK             = 82,
+   PKT_TRANS_COMPRESSED_READ  = 41,
+   PKT_TRANS_POSTED           = 40,
+   PKT_TRANS_WRITE            = 39,
+   PKT_TRANS_READ             = 38,
+   PKT_DATA_H                 = 37,
+   PKT_DATA_L                 = 6,
+   PKT_BYTEEN_H               = 5,
+   PKT_BYTEEN_L               = 2,
+   PKT_SRC_ID_H               = 1,
+   PKT_SRC_ID_L               = 1,
+   PKT_DEST_ID_H              = 0,
+   PKT_DEST_ID_L              = 0,
+   PKT_RESPONSE_STATUS_L      = 110,
+   PKT_RESPONSE_STATUS_H      = 111,
+   PKT_ORI_BURST_SIZE_L       = 112,
+   PKT_ORI_BURST_SIZE_H       = 114,
+   ST_DATA_W                  = 115,
+   ST_CHANNEL_W               = 1,
+
+   // -------------------
+   // Agent Parameters
+   // -------------------
+   AV_BURSTCOUNT_W       = 3,
+   ID                    = 1,
+   SUPPRESS_0_BYTEEN_RSP = 1,
+   BURSTWRAP_VALUE       = 4,
+   CACHE_VALUE           = 0,
+   SECURE_ACCESS_BIT     = 1,
+   USE_READRESPONSE      = 0,
+   USE_WRITERESPONSE     = 0,
+
+   // -------------------
+   // Derived Parameters
+   // -------------------
+   PKT_BURSTWRAP_W   = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+   PKT_BYTE_CNT_W    = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+   PKT_PROTECTION_W  = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
+   PKT_ADDR_W        = PKT_ADDR_H - PKT_ADDR_L + 1,
+   PKT_DATA_W        = PKT_DATA_H - PKT_DATA_L + 1,
+   PKT_BYTEEN_W      = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   PKT_SRC_ID_W      = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
+   PKT_DEST_ID_W     = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
+   PKT_BURST_SIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
+) (
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input                         clk,
+   input                         reset,
+
+   // -------------------
+   // Avalon-MM Anti-Master
+   // -------------------
+   input [PKT_ADDR_W-1 : 0]      av_address,
+   input                         av_write,
+   input                         av_read,
+   input [PKT_DATA_W-1 : 0]      av_writedata,
+   output reg [PKT_DATA_W-1 : 0] av_readdata,
+   output reg                    av_waitrequest,
+   output reg                    av_readdatavalid,
+   input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
+   input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
+   input                         av_debugaccess,
+   input                         av_lock,
+   output reg [1 : 0]            av_response,
+   output reg                    av_writeresponsevalid,
+
+   // -------------------
+   // Command Source
+   // -------------------
+   output reg                    cp_valid,
+   output reg [ST_DATA_W-1 : 0]  cp_data,
+   output wire                   cp_startofpacket,
+   output wire                   cp_endofpacket,
+   input                         cp_ready,
+
+   // -------------------
+   // Response Sink
+   // -------------------
+   input                         rp_valid,
+   input [ST_DATA_W-1 : 0]       rp_data,
+   input [ST_CHANNEL_W-1 : 0]    rp_channel,
+   input                         rp_startofpacket,
+   input                         rp_endofpacket,
+   output reg                    rp_ready
+);
+    // ------------------------------------------------------------
+    // Utility Functions
+    // ------------------------------------------------------------
+   function integer clogb2;
+      input [31 : 0] value;
+      begin
+         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+            value = value >> 1;
+         clogb2 = clogb2 - 1;
+      end
+   endfunction // clogb2
+
+   localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
+   localparam NUMSYMBOLS   = PKT_BYTEEN_W; 
+   localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
+   localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
+   localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
+
+   typedef enum bit  [1 : 0]
+   {
+      FIXED       = 2'b00,
+      INCR        = 2'b01,
+      WRAP        = 2'b10,
+      OTHER_WRAP  = 2'b11
+   } MerlinBurstType;
+
+   // --------------------------------------
+   // Potential optimization: compare in words to save bits?
+   // --------------------------------------
+   wire is_burst;
+   assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
+
+   wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
+   wire [31 : 0] id_int              = ID; 
+   wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
+   wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
+
+   // --------------------------------------
+   // Address alignment
+   //
+   // The packet format requires that addresses be aligned to
+   // the transaction size.
+   // --------------------------------------
+   wire [PKT_ADDR_W-1 : 0] av_address_aligned;
+   generate 
+      if (NUMSYMBOLS > 1) begin
+         assign av_address_aligned = 
+         {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
+      end
+      else begin
+         assign av_address_aligned = av_address;
+      end 
+   endgenerate
+
+   // --------------------------------------
+   // Command & Response Construction
+   // --------------------------------------
+   always_comb begin
+      cp_data                                              = '0;
+
+      cp_data[PKT_PROTECTION_L]                            = av_debugaccess;    
+      cp_data[PKT_PROTECTION_L+1]                          = SECURE_ACCESS_BIT[0];  // secure cache bit
+      cp_data[PKT_PROTECTION_L+2]                          = 1'b0;                  // instruction/data cache bit
+      cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]           = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
+      cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]             = av_burstcount;
+      cp_data[PKT_ADDR_H : PKT_ADDR_L]                     = av_address_aligned;
+      cp_data[PKT_TRANS_EXCLUSIVE]                         = 1'b0;
+      cp_data[PKT_TRANS_LOCK]                              = av_lock;
+      cp_data[PKT_TRANS_COMPRESSED_READ]                   = av_read & is_burst;
+      cp_data[PKT_TRANS_READ]                              = av_read;
+      cp_data[PKT_TRANS_WRITE]                             = av_write;
+      cp_data[PKT_TRANS_POSTED]                            = av_write & !USE_WRITERESPONSE;
+      cp_data[PKT_DATA_H : PKT_DATA_L]                     = av_writedata;
+      cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L]                 = av_byteenable;
+      cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]         = burstsize_sig;
+      cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
+      cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]         = bursttype_value;
+      cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L]                 = id_int[PKT_SRC_ID_W-1 : 0];
+      cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L]           = '0;
+      cp_data[PKT_CACHE_H : PKT_CACHE_L]                   = CACHE_VALUE[3 : 0];
+      cp_data[PKT_QOS_H : PKT_QOS_L]                       = '0;        
+      cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L]   = '0;
+      cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L]   = '0;
+
+      av_readdata                                          = rp_data[PKT_DATA_H : PKT_DATA_L];
+      if (USE_WRITERESPONSE || USE_READRESPONSE)
+         av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
+      else
+         av_response = '0;
+      end
+
+   // --------------------------------------
+   // Command Control
+   // --------------------------------------
+   reg hold_waitrequest;
+
+   always @ (posedge clk, posedge reset) begin
+      if (reset)
+         hold_waitrequest <= 1'b1;
+      else
+         hold_waitrequest <= 1'b0;
+   end  
+   
+   always_comb begin
+      cp_valid = 0;
+
+      if ((av_write || av_read) && ~hold_waitrequest)
+         cp_valid = 1;
+   end
+
+   generate if (BURSTING) begin
+      reg sop_enable;
+
+      always @(posedge clk, posedge reset) begin
+         if (reset) begin
+            sop_enable <= 1'b1;
+         end
+         else begin
+            if (cp_valid && cp_ready) begin
+               sop_enable <= 1'b0;
+               if (cp_endofpacket)
+                  sop_enable <= 1'b1;
+            end
+         end
+      end
+
+      assign cp_startofpacket = sop_enable;
+      assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
+
+   end 
+   else begin
+
+      assign cp_startofpacket = 1'b1;
+      assign cp_endofpacket   = 1'b1;
+
+   end
+   endgenerate
+
+   // --------------------------------------
+   // Backpressure & Readdatavalid
+   // --------------------------------------
+   always_comb begin
+      rp_ready              = 1;
+      av_readdatavalid      = 0;
+      av_writeresponsevalid = 0;
+      av_waitrequest = hold_waitrequest | !cp_ready;
+
+      if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
+         av_writeresponsevalid = rp_valid;
+      else
+         av_readdatavalid      = rp_valid;
+
+      if (SUPPRESS_0_BYTEEN_RSP) begin
+         if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
+            av_readdatavalid = 0;
+      end
+   end
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv b/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv
index 9bc1226..ec824fc 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv
@@ -11,546 +11,546 @@
 // agreement for further details.
 
 
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// --------------------------------------
-// Merlin Master Translator
-//
-// Converts an Avalon-MM master interface into an 
-// Avalon-MM "universal" master interface.
-//
-// The universal interface is defined as the superset of ports
-// and parameters that can represent any legal Avalon 
-// interface.
-// --------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_master_translator #(
-   parameter
-      // widths
-      AV_ADDRESS_W                = 32,
-      AV_DATA_W                   = 32,
-      AV_BURSTCOUNT_W             = 4,
-      AV_BYTEENABLE_W             = 4,
-
-      UAV_ADDRESS_W               = 38,
-      UAV_BURSTCOUNT_W            = 10,
-  
-      // optional ports
-      USE_BURSTCOUNT              = 1,
-      USE_BEGINBURSTTRANSFER      = 0,
-      USE_BEGINTRANSFER           = 0,
-      USE_CHIPSELECT              = 0,
-      USE_READ                    = 1,
-      USE_READDATAVALID           = 1,
-      USE_WRITE                   = 1,
-      USE_WAITREQUEST             = 1,
-      USE_WRITERESPONSE           = 0,
-      USE_READRESPONSE            = 0,
-   
-      AV_REGISTERINCOMINGSIGNALS  = 0,
-      AV_SYMBOLS_PER_WORD         = 4,
-      AV_ADDRESS_SYMBOLS          = 0,
-      // must be enabled for a bursting master
-      AV_CONSTANT_BURST_BEHAVIOR  = 1,
-      UAV_CONSTANT_BURST_BEHAVIOR = 0,
-      AV_BURSTCOUNT_SYMBOLS       = 0,
-      AV_LINEWRAPBURSTS           = 0
-)(
-   input wire                           clk,
-   input wire                           reset,
-
-   // Universal Avalon Master
-   output reg                           uav_write,
-   output reg                           uav_read,
-   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
-   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
-   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
-   output wire [AV_DATA_W -1 : 0]       uav_writedata,
-   output wire                          uav_lock,
-   output wire                          uav_debugaccess,
-   output wire                          uav_clken,
-
-   input wire [AV_DATA_W -1 : 0]        uav_readdata,
-   input wire                           uav_readdatavalid,
-   input wire                           uav_waitrequest,
-   input wire [1 : 0]                   uav_response,
-   input wire                           uav_writeresponsevalid,
-
-   // Avalon-MM Anti-master (slave)
-   input reg                            av_write,
-   input reg                            av_read,
-   input wire [AV_ADDRESS_W -1 : 0]     av_address,
-   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
-   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
-   input wire [AV_DATA_W -1 : 0]        av_writedata,
-   input wire                           av_begintransfer,
-   input wire                           av_beginbursttransfer,
-   input wire                           av_lock,
-   input wire                           av_chipselect,
-   input wire                           av_debugaccess,
-   input wire                           av_clken,
-
-   output wire [AV_DATA_W -1 : 0]       av_readdata,
-   output wire                          av_readdatavalid,
-   output reg                           av_waitrequest,
-   output reg [1 : 0]                   av_response,
-   output reg                           av_writeresponsevalid
-);
-
-   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
-   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
-   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
-   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
-   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
-
-   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
-   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
-
-   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
-   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
-
-   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
-   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
-
-   function integer flog2;
-      input [31:0]  depth;
-      integer       i;
-      begin
-         i = depth;
-         if ( i <= 0 ) flog2 = 0;
-         else begin
-            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
-               i = i >> 1;
-         end
-      end
-   endfunction // flog2
-
-    // ------------------------------------------------------------
-    // Calculates the ceil(log2()) of the input val.
-    //
-    // Limited to a positive 32-bit input value.
-    // ------------------------------------------------------------
-    function integer clog2;
-        input[31:0] val;
-        reg[31:0] i;
-
-        begin
-            i = 1;
-            clog2 = 0;
-
-            while (i < val) begin
-                clog2 = clog2 + 1;
-                i = i[30:0] << 1;
-            end
-        end
-    endfunction
-
-   function integer pow2;
-      input [31:0] toShift;
-      begin
-         pow2 = 1;
-         pow2 = pow2 << toShift;
-      end
-   endfunction // pow2
-
-   // -------------------------------------------------
-   // Assign some constants to appropriately-sized signals to
-   // avoid synthesis warnings. This also helps some simulators
-   // with their inferred sensitivity lists.
-   //
-   // The symbols per word calculation here rounds non-power of two
-   // symbols to the next highest power of two, which is what we want
-   // when calculating the decrementing byte count.
-   // -------------------------------------------------
-   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
-   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
-
-   reg                            internal_beginbursttransfer;
-   reg                            internal_begintransfer;
-   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
-   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
-
-   reg uav_read_pre;
-   reg uav_write_pre;
-   reg read_accepted;
-
-   // -------------------------------------------------
-   // Pass through signals that we don't touch
-   // -------------------------------------------------
-   assign uav_writedata    = av_writedata;
-   assign uav_byteenable   = av_byteenable;
-   assign uav_lock         = av_lock;
-   assign uav_debugaccess  = av_debugaccess;
-   assign uav_clken        = av_clken;
-
-   assign av_readdata      = uav_readdata;
-   assign av_readdatavalid = uav_readdatavalid;
-
-   // -------------------------------------------------
-   // Response signals
-   // -------------------------------------------------
-   always_comb begin
-      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
-         av_response = '0;
-      else
-         av_response = uav_response;
-
-      if (USE_WRITERESPONSE) begin
-         av_writeresponsevalid = uav_writeresponsevalid;
-      end else begin
-         av_writeresponsevalid = '0;
-      end
-   end
-
-   // -------------------------------------------------
-   // Convert byte and word addresses into byte addresses
-   // -------------------------------------------------
-   always_comb begin
-      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
-
-      if (AV_ADDRESS_SYMBOLS)
-         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
-      else begin
-         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
-      end
-   end
-
-   // -------------------------------------------------
-   // Convert burstcount into symbol units
-   // -------------------------------------------------
-   always_comb begin
-      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
-
-      if (USE_BURSTCOUNT) begin
-         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
-         if (AV_BURSTCOUNT_SYMBOLS)
-            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
-         else begin
-            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
-         end
-      end
-   end
-
-   // -------------------------------------------------
-   // This is where we perform the per-transfer address and burstcount 
-   // calculations that are required by downstream modules.
-   // -------------------------------------------------
-   reg [UAV_ADDRESS_W -1 : 0] address_register;
-   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
-   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
-
-   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
-
-   always_comb begin
-      uav_address = uav_address_pre;
-      uav_burstcount = uav_burstcount_pre;
-
-      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
-         uav_address = address_register;
-         uav_burstcount = burstcount_register;
-      end
-   end
-
-   reg first_burst_stalled;
-   reg burst_stalled;
-
-   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
-   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
-
-   generate
-      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
-         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
-            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
-            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
-         end
-         else begin
-            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
-            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
-         end
-      end
-      else begin
-         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
-         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
-      end
-   endgenerate
-
-   always @(posedge clk, posedge reset) begin
-      if (reset) begin
-         address_register <= '0;
-         burstcount_register_lint <= '0;
-      end else begin
-         address_register <= address_register;
-         burstcount_register_lint <= burstcount_register_lint;
-
-         if (internal_beginbursttransfer || first_burst_stalled) begin
-            if (av_waitrequest) begin
-               address_register <= uav_address_pre;
-               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
-            end else begin
-               address_register <= combi_burst_addr_reg;
-               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
-            end
-         end else if (internal_begintransfer || burst_stalled) begin
-            if (~av_waitrequest) begin
-               address_register <= combi_addr_reg;
-               burstcount_register_lint <= burstcount_register - symbols_per_word;
-            end
-         end
-      end
-   end
-
-   always @(posedge clk, posedge reset) begin
-      if (reset) begin
-         first_burst_stalled <= 1'b0;
-         burst_stalled <= 1'b0;
-      end else begin
-         if (internal_beginbursttransfer || first_burst_stalled) begin
-            if (av_waitrequest) begin
-               first_burst_stalled <= 1'b1;
-            end else begin
-               first_burst_stalled <= 1'b0;
-            end
-         end else if (internal_begintransfer || burst_stalled) begin
-            if (~av_waitrequest) begin
-               burst_stalled <= 1'b0;
-            end else begin
-               burst_stalled <= 1'b1;
-            end
-         end
-      end
-   end
-
-   // -------------------------------------------------
-   // Waitrequest translation
-   // -------------------------------------------------
-   always @(posedge clk, posedge reset) begin
-      if (reset)
-         read_accepted <= 1'b0;
-      else begin
-         read_accepted <= read_accepted;
-         if (read_accepted == 0)
-            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
-         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
-            read_accepted <= 1'b0;
-      end
-
-   end
-
-   reg write_accepted = 0;
-   generate if (AV_REGISTERINCOMINGSIGNALS) begin
-      always @(posedge clk, posedge reset) begin
-         if (reset)
-            write_accepted <= 1'b0;
-         else begin
-            write_accepted <=
-            ~av_waitrequest ? 1'b0 :
-            uav_write & ~uav_waitrequest? 1'b1 :
-            write_accepted;
-         end
-      end
-   end endgenerate
-
-   always_comb begin
-      av_waitrequest = uav_waitrequest;
-
-      if (USE_READDATAVALID == 0) begin
-         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
-      end
-
-      if (AV_REGISTERINCOMINGSIGNALS) begin
-         av_waitrequest =
-            uav_read_pre ? ~uav_readdatavalid :
-            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
-            1'b1;
-      end
-
-      if (USE_WAITREQUEST == 0) begin
-         av_waitrequest = 0;
-      end
-   end
-
-   // -------------------------------------------------
-   // Determine the output read and write signals from 
-   // the read/write/chipselect input signals.
-   // -------------------------------------------------
-   always_comb begin
-      uav_write      =  1'b0;
-      uav_write_pre  =  1'b0;
-      uav_read       =  1'b0;
-      uav_read_pre   =  1'b0;
-
-      if (!USE_CHIPSELECT) begin
-         if (USE_READ) begin
-            uav_read_pre = av_read;
-         end
-     
-         if (USE_WRITE) begin
-            uav_write_pre = av_write;
-         end
-      end else begin
-         if (!USE_WRITE && USE_READ) begin
-            uav_write_pre = av_chipselect & ~av_read;
-            uav_read_pre = av_read;
-         end else if (!USE_READ && USE_WRITE) begin
-            uav_write_pre = av_write;
-            uav_read_pre = av_chipselect & ~av_write;
-         end else if (USE_READ && USE_WRITE) begin
-            uav_write_pre = av_write;
-            uav_read_pre = av_read;
-         end
-      end
-
-      if (USE_READDATAVALID == 0)
-         uav_read = uav_read_pre & ~read_accepted;
-      else
-         uav_read = uav_read_pre;
-
-      if (AV_REGISTERINCOMINGSIGNALS == 0)
-         uav_write = uav_write_pre;
-      else
-         uav_write = uav_write_pre & ~write_accepted;
-   end
-
-   // -------------------------------------------------
-   // Begintransfer assignment
-   // -------------------------------------------------
-   reg end_begintransfer;
-
-   always_comb begin
-      if (USE_BEGINTRANSFER) begin
-         internal_begintransfer = av_begintransfer;
-      end else begin
-         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
-      end
-   end
-
-   always @(posedge clk or posedge reset) begin
-      if (reset) begin
-         end_begintransfer <= 1'b0;
-      end else begin
-         if (internal_begintransfer == 1 && uav_waitrequest)
-            end_begintransfer <= 1'b1;
-         else if (uav_waitrequest)
-            end_begintransfer <= end_begintransfer;
-         else
-            end_begintransfer <= 1'b0;
-      end
-   end
-
-   // -------------------------------------------------
-   // Beginbursttransfer assignment
-   // -------------------------------------------------
-   reg   end_beginbursttransfer;
-   wire  last_burst_transfer_pre;
-   wire  last_burst_transfer_reg;
-   wire  last_burst_transfer;
-
-   // compare values before the mux to shorten critical path; benchmark before changing
-   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
-   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
-   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
-
-   always_comb begin
-      if (USE_BEGINBURSTTRANSFER) begin
-         internal_beginbursttransfer = av_beginbursttransfer;
-      end else begin
-         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
-      end
-   end
-
-   always @(posedge clk or posedge reset) begin
-      if (reset) begin
-         end_beginbursttransfer <= 1'b0;
-      end else begin
-         end_beginbursttransfer <= end_beginbursttransfer;
-         if (last_burst_transfer && internal_begintransfer || uav_read) begin
-            end_beginbursttransfer <= 1'b0;
-         end
-         else if (uav_write && internal_begintransfer) begin
-            end_beginbursttransfer <= 1'b1;
-         end
-      end
-   end
-
-   // synthesis translate_off
-
-   // ------------------------------------------------
-   // check_1   : for waitrequest signal violation
-   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
-   // Exception : begintransfer / beginbursttransfer
-   //           : previously not in any transaction (idle)
-   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
-   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
-   // ------------------------------------------------
-
-   reg av_waitrequest_r;
-   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
-   reg [AV_ADDRESS_W-1:0]    av_address_r;
-   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
-   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
-   reg [AV_DATA_W-1:0]       av_writedata_r;
-
-   always @(posedge clk or posedge reset) begin
-      if (reset) begin
-         av_waitrequest_r           <= '0;
-         av_write_r                 <= '0;
-         av_read_r                  <= '0;
-         av_lock_r                  <= '0;
-         av_chipselect_r            <= '0;
-         av_debugaccess_r           <= '0;
-         av_address_r               <= '0;
-         av_byteenable_r            <= '0;
-         av_burstcount_r            <= '0;
-         av_writedata_r             <= '0;
-      end else begin
-         av_waitrequest_r           <= av_waitrequest;
-         av_write_r                 <= av_write;
-         av_read_r                  <= av_read;
-         av_lock_r                  <= av_lock;
-         av_chipselect_r            <= av_chipselect;
-         av_debugaccess_r           <= av_debugaccess;
-         av_address_r               <= av_address;
-         av_byteenable_r            <= av_byteenable;
-         av_burstcount_r            <= av_burstcount;
-         av_writedata_r             <= av_writedata;
-   
-         if (
-            av_waitrequest_r && // When waitrequest is asserted
-            (
-               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
-               (av_read                   != av_read_r)  ||
-               (av_lock                   != av_lock_r)  ||
-               (av_debugaccess            != av_debugaccess_r) ||
-               (av_address                != av_address_r) ||
-               (av_byteenable             != av_byteenable_r) ||
-               (av_burstcount             != av_burstcount_r)
-            )  &&
-            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
-            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
-         ) begin
-            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
-            $display("av_address                %x --> %x", av_address_r               , av_address               );
-            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
-            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
-            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
-            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
-            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
-            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
-            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
-            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
-         end
-      end
-   
-   // end check_1
-   
-   end
-
-  // synthesis translate_on
-
-
-endmodule
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts an Avalon-MM master interface into an 
+// Avalon-MM "universal" master interface.
+//
+// The universal interface is defined as the superset of ports
+// and parameters that can represent any legal Avalon 
+// interface.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_translator #(
+   parameter
+      // widths
+      AV_ADDRESS_W                = 32,
+      AV_DATA_W                   = 32,
+      AV_BURSTCOUNT_W             = 4,
+      AV_BYTEENABLE_W             = 4,
+
+      UAV_ADDRESS_W               = 38,
+      UAV_BURSTCOUNT_W            = 10,
+  
+      // optional ports
+      USE_BURSTCOUNT              = 1,
+      USE_BEGINBURSTTRANSFER      = 0,
+      USE_BEGINTRANSFER           = 0,
+      USE_CHIPSELECT              = 0,
+      USE_READ                    = 1,
+      USE_READDATAVALID           = 1,
+      USE_WRITE                   = 1,
+      USE_WAITREQUEST             = 1,
+      USE_WRITERESPONSE           = 0,
+      USE_READRESPONSE            = 0,
+   
+      AV_REGISTERINCOMINGSIGNALS  = 0,
+      AV_SYMBOLS_PER_WORD         = 4,
+      AV_ADDRESS_SYMBOLS          = 0,
+      // must be enabled for a bursting master
+      AV_CONSTANT_BURST_BEHAVIOR  = 1,
+      UAV_CONSTANT_BURST_BEHAVIOR = 0,
+      AV_BURSTCOUNT_SYMBOLS       = 0,
+      AV_LINEWRAPBURSTS           = 0
+)(
+   input wire                           clk,
+   input wire                           reset,
+
+   // Universal Avalon Master
+   output reg                           uav_write,
+   output reg                           uav_read,
+   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
+   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+   output wire [AV_DATA_W -1 : 0]       uav_writedata,
+   output wire                          uav_lock,
+   output wire                          uav_debugaccess,
+   output wire                          uav_clken,
+
+   input wire [AV_DATA_W -1 : 0]        uav_readdata,
+   input wire                           uav_readdatavalid,
+   input wire                           uav_waitrequest,
+   input wire [1 : 0]                   uav_response,
+   input wire                           uav_writeresponsevalid,
+
+   // Avalon-MM Anti-master (slave)
+   input reg                            av_write,
+   input reg                            av_read,
+   input wire [AV_ADDRESS_W -1 : 0]     av_address,
+   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
+   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
+   input wire [AV_DATA_W -1 : 0]        av_writedata,
+   input wire                           av_begintransfer,
+   input wire                           av_beginbursttransfer,
+   input wire                           av_lock,
+   input wire                           av_chipselect,
+   input wire                           av_debugaccess,
+   input wire                           av_clken,
+
+   output wire [AV_DATA_W -1 : 0]       av_readdata,
+   output wire                          av_readdatavalid,
+   output reg                           av_waitrequest,
+   output reg [1 : 0]                   av_response,
+   output reg                           av_writeresponsevalid
+);
+
+   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
+   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
+   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
+   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
+   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
+
+   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
+   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
+
+   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
+   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
+
+   function integer flog2;
+      input [31:0]  depth;
+      integer       i;
+      begin
+         i = depth;
+         if ( i <= 0 ) flog2 = 0;
+         else begin
+            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
+               i = i >> 1;
+         end
+      end
+   endfunction // flog2
+
+    // ------------------------------------------------------------
+    // Calculates the ceil(log2()) of the input val.
+    //
+    // Limited to a positive 32-bit input value.
+    // ------------------------------------------------------------
+    function integer clog2;
+        input[31:0] val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            clog2 = 0;
+
+            while (i < val) begin
+                clog2 = clog2 + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+   function integer pow2;
+      input [31:0] toShift;
+      begin
+         pow2 = 1;
+         pow2 = pow2 << toShift;
+      end
+   endfunction // pow2
+
+   // -------------------------------------------------
+   // Assign some constants to appropriately-sized signals to
+   // avoid synthesis warnings. This also helps some simulators
+   // with their inferred sensitivity lists.
+   //
+   // The symbols per word calculation here rounds non-power of two
+   // symbols to the next highest power of two, which is what we want
+   // when calculating the decrementing byte count.
+   // -------------------------------------------------
+   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
+   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
+
+   reg                            internal_beginbursttransfer;
+   reg                            internal_begintransfer;
+   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
+   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
+
+   reg uav_read_pre;
+   reg uav_write_pre;
+   reg read_accepted;
+
+   // -------------------------------------------------
+   // Pass through signals that we don't touch
+   // -------------------------------------------------
+   assign uav_writedata    = av_writedata;
+   assign uav_byteenable   = av_byteenable;
+   assign uav_lock         = av_lock;
+   assign uav_debugaccess  = av_debugaccess;
+   assign uav_clken        = av_clken;
+
+   assign av_readdata      = uav_readdata;
+   assign av_readdatavalid = uav_readdatavalid;
+
+   // -------------------------------------------------
+   // Response signals
+   // -------------------------------------------------
+   always_comb begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
+         av_response = '0;
+      else
+         av_response = uav_response;
+
+      if (USE_WRITERESPONSE) begin
+         av_writeresponsevalid = uav_writeresponsevalid;
+      end else begin
+         av_writeresponsevalid = '0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert byte and word addresses into byte addresses
+   // -------------------------------------------------
+   always_comb begin
+      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
+
+      if (AV_ADDRESS_SYMBOLS)
+         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      else begin
+         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert burstcount into symbol units
+   // -------------------------------------------------
+   always_comb begin
+      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
+
+      if (USE_BURSTCOUNT) begin
+         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
+         if (AV_BURSTCOUNT_SYMBOLS)
+            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         else begin
+            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // This is where we perform the per-transfer address and burstcount 
+   // calculations that are required by downstream modules.
+   // -------------------------------------------------
+   reg [UAV_ADDRESS_W -1 : 0] address_register;
+   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
+   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
+
+   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
+
+   always_comb begin
+      uav_address = uav_address_pre;
+      uav_burstcount = uav_burstcount_pre;
+
+      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+         uav_address = address_register;
+         uav_burstcount = burstcount_register;
+      end
+   end
+
+   reg first_burst_stalled;
+   reg burst_stalled;
+
+   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
+   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
+
+   generate
+      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
+         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+         end
+         else begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+         end
+      end
+      else begin
+         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         address_register <= '0;
+         burstcount_register_lint <= '0;
+      end else begin
+         address_register <= address_register;
+         burstcount_register_lint <= burstcount_register_lint;
+
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               address_register <= uav_address_pre;
+               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
+            end else begin
+               address_register <= combi_burst_addr_reg;
+               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               address_register <= combi_addr_reg;
+               burstcount_register_lint <= burstcount_register - symbols_per_word;
+            end
+         end
+      end
+   end
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         first_burst_stalled <= 1'b0;
+         burst_stalled <= 1'b0;
+      end else begin
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               first_burst_stalled <= 1'b1;
+            end else begin
+               first_burst_stalled <= 1'b0;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               burst_stalled <= 1'b0;
+            end else begin
+               burst_stalled <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // Waitrequest translation
+   // -------------------------------------------------
+   always @(posedge clk, posedge reset) begin
+      if (reset)
+         read_accepted <= 1'b0;
+      else begin
+         read_accepted <= read_accepted;
+         if (read_accepted == 0)
+            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
+            read_accepted <= 1'b0;
+      end
+
+   end
+
+   reg write_accepted = 0;
+   generate if (AV_REGISTERINCOMINGSIGNALS) begin
+      always @(posedge clk, posedge reset) begin
+         if (reset)
+            write_accepted <= 1'b0;
+         else begin
+            write_accepted <=
+            ~av_waitrequest ? 1'b0 :
+            uav_write & ~uav_waitrequest? 1'b1 :
+            write_accepted;
+         end
+      end
+   end endgenerate
+
+   always_comb begin
+      av_waitrequest = uav_waitrequest;
+
+      if (USE_READDATAVALID == 0) begin
+         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+      end
+
+      if (AV_REGISTERINCOMINGSIGNALS) begin
+         av_waitrequest =
+            uav_read_pre ? ~uav_readdatavalid :
+            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+            1'b1;
+      end
+
+      if (USE_WAITREQUEST == 0) begin
+         av_waitrequest = 0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Determine the output read and write signals from 
+   // the read/write/chipselect input signals.
+   // -------------------------------------------------
+   always_comb begin
+      uav_write      =  1'b0;
+      uav_write_pre  =  1'b0;
+      uav_read       =  1'b0;
+      uav_read_pre   =  1'b0;
+
+      if (!USE_CHIPSELECT) begin
+         if (USE_READ) begin
+            uav_read_pre = av_read;
+         end
+     
+         if (USE_WRITE) begin
+            uav_write_pre = av_write;
+         end
+      end else begin
+         if (!USE_WRITE && USE_READ) begin
+            uav_write_pre = av_chipselect & ~av_read;
+            uav_read_pre = av_read;
+         end else if (!USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_chipselect & ~av_write;
+         end else if (USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_read;
+         end
+      end
+
+      if (USE_READDATAVALID == 0)
+         uav_read = uav_read_pre & ~read_accepted;
+      else
+         uav_read = uav_read_pre;
+
+      if (AV_REGISTERINCOMINGSIGNALS == 0)
+         uav_write = uav_write_pre;
+      else
+         uav_write = uav_write_pre & ~write_accepted;
+   end
+
+   // -------------------------------------------------
+   // Begintransfer assignment
+   // -------------------------------------------------
+   reg end_begintransfer;
+
+   always_comb begin
+      if (USE_BEGINTRANSFER) begin
+         internal_begintransfer = av_begintransfer;
+      end else begin
+         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if (internal_begintransfer == 1 && uav_waitrequest)
+            end_begintransfer <= 1'b1;
+         else if (uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Beginbursttransfer assignment
+   // -------------------------------------------------
+   reg   end_beginbursttransfer;
+   wire  last_burst_transfer_pre;
+   wire  last_burst_transfer_reg;
+   wire  last_burst_transfer;
+
+   // compare values before the mux to shorten critical path; benchmark before changing
+   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+   always_comb begin
+      if (USE_BEGINBURSTTRANSFER) begin
+         internal_beginbursttransfer = av_beginbursttransfer;
+      end else begin
+         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_beginbursttransfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= end_beginbursttransfer;
+         if (last_burst_transfer && internal_begintransfer || uav_read) begin
+            end_beginbursttransfer <= 1'b0;
+         end
+         else if (uav_write && internal_begintransfer) begin
+            end_beginbursttransfer <= 1'b1;
+         end
+      end
+   end
+
+   // synthesis translate_off
+
+   // ------------------------------------------------
+   // check_1   : for waitrequest signal violation
+   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
+   // Exception : begintransfer / beginbursttransfer
+   //           : previously not in any transaction (idle)
+   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
+   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
+   // ------------------------------------------------
+
+   reg av_waitrequest_r;
+   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
+   reg [AV_ADDRESS_W-1:0]    av_address_r;
+   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
+   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
+   reg [AV_DATA_W-1:0]       av_writedata_r;
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         av_waitrequest_r           <= '0;
+         av_write_r                 <= '0;
+         av_read_r                  <= '0;
+         av_lock_r                  <= '0;
+         av_chipselect_r            <= '0;
+         av_debugaccess_r           <= '0;
+         av_address_r               <= '0;
+         av_byteenable_r            <= '0;
+         av_burstcount_r            <= '0;
+         av_writedata_r             <= '0;
+      end else begin
+         av_waitrequest_r           <= av_waitrequest;
+         av_write_r                 <= av_write;
+         av_read_r                  <= av_read;
+         av_lock_r                  <= av_lock;
+         av_chipselect_r            <= av_chipselect;
+         av_debugaccess_r           <= av_debugaccess;
+         av_address_r               <= av_address;
+         av_byteenable_r            <= av_byteenable;
+         av_burstcount_r            <= av_burstcount;
+         av_writedata_r             <= av_writedata;
+   
+         if (
+            av_waitrequest_r && // When waitrequest is asserted
+            (
+               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
+               (av_read                   != av_read_r)  ||
+               (av_lock                   != av_lock_r)  ||
+               (av_debugaccess            != av_debugaccess_r) ||
+               (av_address                != av_address_r) ||
+               (av_byteenable             != av_byteenable_r) ||
+               (av_burstcount             != av_burstcount_r)
+            )  &&
+            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
+            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
+         ) begin
+            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
+            $display("av_address                %x --> %x", av_address_r               , av_address               );
+            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
+            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
+            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
+            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
+            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
+            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
+            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
+            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
+         end
+      end
+   
+   // end check_1
+   
+   end
+
+  // synthesis translate_on
+
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv b/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv
index 48bb1b4..7c6929c 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv
@@ -11,612 +11,612 @@
 // agreement for further details.
 
 
-// (C) 2001-2011 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_slave_agent
-#(
-   // Packet parameters
-   parameter PKT_BEGIN_BURST           = 81,
-   parameter PKT_DATA_H                = 31,
-   parameter PKT_DATA_L                = 0,
-   parameter PKT_SYMBOL_W              = 8,
-   parameter PKT_BYTEEN_H              = 71,
-   parameter PKT_BYTEEN_L              = 68,
-   parameter PKT_ADDR_H                = 63,
-   parameter PKT_ADDR_L                = 32,
-   parameter PKT_TRANS_LOCK            = 87,
-   parameter PKT_TRANS_COMPRESSED_READ = 67,
-   parameter PKT_TRANS_POSTED          = 66, 
-   parameter PKT_TRANS_WRITE           = 65,
-   parameter PKT_TRANS_READ            = 64,
-   parameter PKT_SRC_ID_H              = 74,
-   parameter PKT_SRC_ID_L              = 72,
-   parameter PKT_DEST_ID_H             = 77,
-   parameter PKT_DEST_ID_L             = 75,
-   parameter PKT_BURSTWRAP_H           = 85,
-   parameter PKT_BURSTWRAP_L           = 82,
-   parameter PKT_BYTE_CNT_H            = 81,
-   parameter PKT_BYTE_CNT_L            = 78,
-   parameter PKT_PROTECTION_H          = 86,
-   parameter PKT_PROTECTION_L          = 86,
-   parameter PKT_RESPONSE_STATUS_H     = 89,
-   parameter PKT_RESPONSE_STATUS_L     = 88,
-   parameter PKT_BURST_SIZE_H          = 92,
-   parameter PKT_BURST_SIZE_L          = 90,
-   parameter PKT_ORI_BURST_SIZE_L      = 93,
-   parameter PKT_ORI_BURST_SIZE_H      = 95,
-   parameter ST_DATA_W                 = 96,
-   parameter ST_CHANNEL_W              = 32,
-
-   // Slave parameters
-   parameter ADDR_W           = PKT_ADDR_H - PKT_ADDR_L + 1,
-   parameter AVS_DATA_W       = PKT_DATA_H - PKT_DATA_L + 1,
-   parameter AVS_BURSTCOUNT_W = 4,
-   parameter PKT_SYMBOLS      = AVS_DATA_W / PKT_SYMBOL_W,
-
-   // Slave agent parameters
-   parameter PREVENT_FIFO_OVERFLOW = 0,
-   parameter SUPPRESS_0_BYTEEN_CMD = 1,
-   parameter USE_READRESPONSE      = 0,
-   parameter USE_WRITERESPONSE     = 0,
-
-   // Derived slave parameters
-   parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
-   parameter BURST_SIZE_W = 3,
-
-   // Derived FIFO width
-   parameter FIFO_DATA_W = ST_DATA_W + 1,
-   
-   // ECC parameter
-   parameter ECC_ENABLE = 0
-) (
-   input                         clk,
-   input                         reset,
-
-   // Universal-Avalon anti-slave
-   output [ADDR_W-1:0]           m0_address,
-   output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
-   output [AVS_BE_W-1:0]         m0_byteenable,
-   output                        m0_read,
-   input [AVS_DATA_W-1:0]        m0_readdata,
-   input                         m0_waitrequest,
-   output                        m0_write,
-   output [AVS_DATA_W-1:0]       m0_writedata,
-   input                         m0_readdatavalid,
-   output                        m0_debugaccess,
-   output                        m0_lock,
-   input [1:0]                   m0_response,
-   input                         m0_writeresponsevalid,
-
-   // Avalon-ST FIFO interfaces.
-   // Note: there's no need to include the "data" field here, at least for
-   // reads, since readdata is filled in from slave info.  To keep life
-   // simple, have a data field, but fill it with 0s.
-   // Av-st response fifo source interface
-   output reg [FIFO_DATA_W-1:0]  rf_source_data,
-   output                        rf_source_valid,
-   output                        rf_source_startofpacket,
-   output                        rf_source_endofpacket,
-   input                         rf_source_ready,
-
-   // Av-st response fifo sink interface
-   input [FIFO_DATA_W-1:0]       rf_sink_data,
-   input                         rf_sink_valid,
-   input                         rf_sink_startofpacket,
-   input                         rf_sink_endofpacket,
-   output                        rf_sink_ready,
-
-   // Av-st readdata fifo src interface, data and response
-   // extra 2 bits for storing RESPONSE STATUS
-   output [AVS_DATA_W+1:0]       rdata_fifo_src_data,
-   output                        rdata_fifo_src_valid,
-   input                         rdata_fifo_src_ready,
-
-   // Av-st readdata fifo sink interface
-   input [AVS_DATA_W+1:0]        rdata_fifo_sink_data,
-   input                         rdata_fifo_sink_valid,
-   output                        rdata_fifo_sink_ready,
-   input                         rdata_fifo_sink_error,
-
-   // Av-st sink command packet interface
-   output                        cp_ready,
-   input                         cp_valid,
-   input [ST_DATA_W-1:0]         cp_data,
-   input [ST_CHANNEL_W-1:0]      cp_channel,
-   input                         cp_startofpacket,
-   input                         cp_endofpacket,
-
-   // Av-st source response packet interface
-   input                         rp_ready,
-   output reg                    rp_valid,
-   output reg [ST_DATA_W-1:0]    rp_data,
-   output                        rp_startofpacket,
-   output                        rp_endofpacket
-);
-
-   // --------------------------------------------------
-   // Ceil(log2()) function log2ceil of 4 = 2
-   // --------------------------------------------------
-   function integer log2ceil;
-      input reg[63:0] val;
-      reg [63:0] i;
-   
-      begin
-         i = 1;
-         log2ceil = 0;
-
-         while (i < val) begin
-            log2ceil = log2ceil + 1;
-            i = i << 1;
-         end
-      end
-   endfunction     
-
-   // ------------------------------------------------
-   // Local Parameters
-   // ------------------------------------------------
-   localparam DATA_W       = PKT_DATA_H - PKT_DATA_L + 1;
-   localparam BE_W         = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
-   localparam MID_W        = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
-   localparam SID_W        = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
-   localparam BYTE_CNT_W   = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
-   localparam BURSTWRAP_W  = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
-   localparam BURSTSIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
-   localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
-   localparam MAX_BURST    = 1 << (AVS_BURSTCOUNT_W - 1);
-   localparam BURSTING     = (MAX_BURST > PKT_SYMBOLS);
-
-   // ------------------------------------------------
-   // Signals
-   // ------------------------------------------------
-   wire [DATA_W-1:0]      cmd_data;
-   wire [BE_W-1:0]        cmd_byteen;
-   wire [ADDR_W-1:0]      cmd_addr;
-   wire [MID_W-1:0]       cmd_mid;
-   wire [SID_W-1:0]       cmd_sid;
-   wire                   cmd_read;
-   wire                   cmd_write;
-   wire                   cmd_compressed;
-   wire                   cmd_posted;
-   wire [BYTE_CNT_W-1:0]  cmd_byte_cnt;
-   wire [BURSTWRAP_W-1:0] cmd_burstwrap;
-   wire [BURSTSIZE_W-1:0] cmd_burstsize;
-   wire                   cmd_debugaccess;
-
-   wire                   suppress_cmd;
-   wire                   byteen_asserted;
-   wire                   suppress_read;
-   wire                   suppress_write;
-   wire                   needs_response_synthesis;
-   wire                   generate_response;
-
-   // Assign command fields
-   assign cmd_data         = cp_data[PKT_DATA_H  :PKT_DATA_L  ];
-   assign cmd_byteen       = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
-   assign cmd_addr         = cp_data[PKT_ADDR_H  :PKT_ADDR_L  ];
-   assign cmd_compressed   = cp_data[PKT_TRANS_COMPRESSED_READ];
-   assign cmd_posted       = cp_data[PKT_TRANS_POSTED];
-   assign cmd_write        = cp_data[PKT_TRANS_WRITE];
-   assign cmd_read         = cp_data[PKT_TRANS_READ];
-   assign cmd_mid          = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
-   assign cmd_sid          = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
-   assign cmd_byte_cnt     = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
-   assign cmd_burstwrap    = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
-   assign cmd_burstsize    = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
-   assign cmd_debugaccess  = cp_data[PKT_PROTECTION_L];
-
-   // Local "ready_for_command" signal: deasserted when the agent is unable to accept
-   // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
-   // ~rp_ready), ...
-   // Say, this could depend on the type of command, for example, even if the
-   // rdv FIFO is full, a write request can be accepted.  For later.
-   wire ready_for_command;
-
-   wire local_lock  = cp_valid & cp_data[PKT_TRANS_LOCK];
-   wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
-   wire local_read  = cp_valid & cp_data[PKT_TRANS_READ];
-   wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
-   wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
-
-   // num_symbols is PKT_SYMBOLS, appropriately sized.
-   wire [31:0] int_num_symbols = PKT_SYMBOLS;
-   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
-
-   generate
-      if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
-         // ---------------------------------------------------
-         // Backpressure if the slave says to, or if FIFO overflow may occur.
-         // 
-         // All commands are backpressured once the FIFO is full
-         // even if they don't need storage. This breaks a long
-         // combinatorial path from the master read/write through
-         // this logic and back to the master via the backpressure
-         // path.
-         //
-         // To avoid a loss of throughput the FIFO will be parameterized 
-         // one slot deeper. The extra slot should never be used in normal
-         // operation, but should a slave misbehave and accept one more
-         // read than it should then backpressure will kick in.
-         //
-         // An example: assume a slave with MPRT = 2. It can accept a
-         // command sequence RRWW without backpressuring. If the FIFO is
-         // only 2 deep, we'd backpressure the writes leading to loss of
-         // throughput. If the FIFO is 3 deep, we'll only backpressure when
-         // RRR... which is an illegal condition anyway.
-         // ---------------------------------------------------
-
-         assign ready_for_command = rf_source_ready;
-         assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
-
-      end else begin : no_prevent_fifo_overflow_block
-
-         // Do not suppress the command or the slave will
-         // not be able to waitrequest
-         assign ready_for_command = 1'b1;
-         // Backpressure only if the slave says to.
-         assign cp_ready = ~m0_waitrequest | suppress_cmd;
-
-      end
-   endgenerate
-
-   generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
-      assign byteen_asserted  = |cmd_byteen;
-      assign suppress_read    = ~byteen_asserted;
-      assign suppress_write   = ~byteen_asserted;
-      assign suppress_cmd     = ~byteen_asserted;
-   end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
-      assign byteen_asserted  = |cmd_byteen;
-      assign suppress_read    = ~byteen_asserted;
-      assign suppress_write   = 1'b0;
-      assign suppress_cmd     = ~byteen_asserted && cmd_read;
-   end else begin : no_suppress_0_byteen_cmd
-      assign suppress_read    = 1'b0;
-      assign suppress_write   = 1'b0;
-      assign suppress_cmd     = 1'b0;
-   end
-   endgenerate
-
-   // -------------------------------------------------------------------
-   // Extract avalon signals from command packet.
-   // -------------------------------------------------------------------
-   // Mask off the lower bits of address.
-   // The burst adapter before this component will break narrow sized packets
-   // into sub-bursts of length 1. However, the packet addresses are preserved,
-   // which means this component may see size-aligned addresses.
-   //
-   // Masking ensures that the addresses seen by an Avalon slave are aligned to 
-   // the full data width instead of the size.
-   //
-   // Example:
-   // output from burst adapter (datawidth=4, size=2 bytes):
-   // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
-   // expected output from slave agent:
-   // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
-   generate 
-      if (BITS_TO_MASK > 0) begin : mask_address
-
-         assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
-
-      end else begin : no_mask_address
-
-         assign m0_address = cmd_addr;
-
-      end
-   endgenerate
-
-   assign m0_byteenable = cmd_byteen;
-   assign m0_writedata  = cmd_data;
-
-   // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
-   // this sort of burst exists only in merlin fabric ST packets. What to do
-   // if we see such a burst? All beats in that burst need to be transmitted
-   // to the slave so we have enough space-time for byteenable expression.
-   //
-   // There can be multiple bursts in a packet, but only one beat per burst
-   // in <most> cases. The exception is when we've decided not to insert a
-   // burst adapter for efficiency reasons, in which case this agent is also
-   // responsible for driving burstcount to 1 on each beat of an uncompressed
-   // read burst.
-
-   assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
-
-   generate 
-       // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal.  Assign m0_burstcount
-       // from a sub-range, or 0-pad, as appropriate.
-       if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
-          wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
-          assign m0_burstcount = (local_read & ~local_compressed_read) ?
-             {zero_pad, num_symbols} :
-             {zero_pad, cmd_byte_cnt};
-       end
-       else begin : m0_burstcount_no_pad
-          assign m0_burstcount = (local_read & ~local_compressed_read) ? 
-          num_symbols[AVS_BURSTCOUNT_W-1:0] : 
-          cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
-       end
-   endgenerate
-
-   assign m0_write = ready_for_command & local_write & !suppress_write;
-   assign m0_lock  = ready_for_command & local_lock & (m0_read | m0_write);
-   assign m0_debugaccess  = cmd_debugaccess;
-
-   // -------------------------------------------------------------------
-   // Indirection layer for response packet values.  Some may always wire
-   // directly from the slave translator; others will no doubt emerge from
-   // various FIFOs.
-   // What to put in resp_data when a write occured? Answer: it does not
-   // matter, because only response status is needed for non-posted writes,
-   // and the packet already has a field for that.
-   //
-   // We use the rdata_fifo to store write responses as well. This allows us
-   // to handle backpressure on the response path, and allows write response
-   // merging.
-   assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
-   assign rdata_fifo_src_data  = {m0_response, m0_readdata};
-
-   // ------------------------------------------------------------------
-   // Generate a token when read commands are suppressed. The token
-   // is stored in the response FIFO, and will be used to synthesize 
-   // a read response. The same token is used for non-posted write
-   // response synthesis.
-   //
-   // Note: this token is not generated for suppressed uncompressed read cycles;
-   // the burst uncompression logic at the read side of the response FIFO
-   // generates the correct number of responses.
-   //
-   // When the slave can return the response, let it do its job. Don't 
-   // synthesize a response in that case, unless we've suppressed the
-   // the last transfer in a write sub-burst.
-   // ------------------------------------------------------------------
-   wire write_end_of_subburst;
-   assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || 
-                                        (!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
-                                        (USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
-
-   // Avalon-ST interfaces to external response FIFO.
-   //
-   // For efficiency, when synthesizing a write response we only store a non-posted write 
-   // transaction at its endofpacket, even if it was split into multiple sub-bursts.
-   //
-   // When not synthesizing write responses, we store each sub-burst in the FIFO.
-   // Each sub-burst to the slave will return a response, which corresponds to one 
-   // entry in the FIFO. We merge all the sub-burst responses on the final
-   // sub-burst and send it on the response channel.
-
-   wire internal_cp_endofburst;
-   wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
-   wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
-
-   assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
-   assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
-   assign write_end_of_subburst = local_write & internal_cp_endofburst;
-
-   assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
-                             & ready_for_command & cp_ready;
-   assign rf_source_startofpacket = cp_startofpacket;
-   assign rf_source_endofpacket   = cp_endofpacket;
-   always @* begin
-      // default: assign every command packet field to the response FIFO...
-      rf_source_data                                  = {1'b0, cp_data};
-
-      // ... and override select fields as needed.
-      rf_source_data[FIFO_DATA_W-1]                      = needs_response_synthesis;
-      rf_source_data[PKT_DATA_H   :PKT_DATA_L]           = {DATA_W {1'b0}};
-      rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L]         = cmd_byteen;
-      rf_source_data[PKT_ADDR_H   :PKT_ADDR_L]           = cmd_addr;
-      rf_source_data[PKT_TRANS_COMPRESSED_READ]          = cmd_compressed;
-      rf_source_data[PKT_TRANS_POSTED]                   = cmd_posted;
-      rf_source_data[PKT_TRANS_WRITE]                    = cmd_write;
-      rf_source_data[PKT_TRANS_READ]                     = cmd_read;
-      rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L]         = cmd_mid;
-      rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L]        = cmd_sid;
-      rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]      = cmd_byte_cnt;
-      rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]    = cmd_burstwrap;
-      rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]  = cmd_burstsize;
-      rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L]  = '0;
-      rf_source_data[PKT_PROTECTION_L]                   = cmd_debugaccess;
-   end
-
-   wire uncompressor_source_valid;
-   wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
-   wire last_write_response;
-
-   // last_write_response indicates the last response of the broken-up write burst (sub-bursts).
-   // At this time, the final merged response is sent, and rp_valid is only asserted
-   // once for the whole burst.
-   generate
-      if (USE_WRITERESPONSE) begin
-         assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
-         always @* begin
-            if (rf_sink_data[PKT_TRANS_WRITE] == 1) 
-               rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
-            else
-               rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
-         end
-      end else begin
-         assign last_write_response = 1'b0;
-         always @* begin
-            rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
-         end
-      end
-   endgenerate
-
-   // ------------------------------------------------------------------
-   // Response merging
-   // ------------------------------------------------------------------
-   reg [1:0] current_response;
-   reg [1:0] response_merged;
-   generate
-     if (USE_WRITERESPONSE) begin : response_merging_all
-        reg first_write_response;
-        reg reset_merged_output;
-        reg [1:0] previous_response_in;
-        reg [1:0]  previous_response;
-
-        always_ff @(posedge clk, posedge reset) begin
-           if (reset) begin
-              first_write_response  <= 1'b1;
-           end 
-           else begin // Merging work for write response, for read: previous_response_in = current_response
-              if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
-                 first_write_response <= 1'b0;
-                 if (rf_sink_endofpacket)
-                    first_write_response <= 1'b1;
-              end
-           end
-        end
-
-        always_comb begin
-           current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
-           reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
-           previous_response_in = reset_merged_output ? current_response : previous_response;
-           response_merged = current_response >= previous_response ? current_response: previous_response_in;
-        end
-
-        always_ff @(posedge clk or posedge reset) begin
-           if (reset) begin 
-              previous_response <= 2'b00;
-           end
-           else begin
-              if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
-                 previous_response <= response_merged;
-              end
-           end
-        end
-     end else begin : response_merging_read_only
-        always @* begin
-           current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | 
-                                                         {2{rdata_fifo_sink_error}};
-           response_merged = current_response;
-        end
-     end
-   endgenerate
-
-   assign generate_response = rf_sink_data[FIFO_DATA_W-1];
-
-   wire [BYTE_CNT_W-1:0]  rf_sink_byte_cnt   = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
-   wire                   rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
-   wire [BURSTWRAP_W-1:0] rf_sink_burstwrap  = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
-   wire [BURSTSIZE_W-1:0] rf_sink_burstsize  = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
-   wire [ADDR_W-1:0]      rf_sink_addr       = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
-   // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
-   wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;    
-
-   wire [BYTE_CNT_W-1:0]   burst_byte_cnt;
-   wire [BURSTWRAP_W-1:0]  rp_burstwrap;
-   wire [ADDR_W-1:0]       rp_address;
-   wire                    rp_is_compressed;
-   wire                    ready_for_response;
-
-   // ------------------------------------------------------------------
-   // We're typically ready for a response if the network is ready. There
-   // is one exception:
-   //
-   // If the slave issues write responses, we only issue a merged response on 
-   // the final sub-burst. As a result, we only care about response channel 
-   // availability on the final burst when we send out the merged response.
-   // ------------------------------------------------------------------
-   assign ready_for_response = (USE_WRITERESPONSE) ? 
-                            rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: 
-                            rp_ready;
-
-   // ------------------------------------------------------------------
-   // Backpressure the readdata fifo if we're supposed to synthesize a response.
-   // This may be a read response (for suppressed reads) or a write response
-   // (for non-posted writes).
-   // ------------------------------------------------------------------
-   assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
-
-   always @* begin
-      // By default, return all fields...
-      rp_data                                               = rf_sink_data[ST_DATA_W - 1 : 0];
-
-      // ... and override specific fields.
-      rp_data[PKT_DATA_H   :PKT_DATA_L]                     = rdata_fifo_sink_data[AVS_DATA_W-1:0];
-      // Assignments directly from the response fifo.
-      rp_data[PKT_TRANS_POSTED]                             = rf_sink_data[PKT_TRANS_POSTED];
-      rp_data[PKT_TRANS_WRITE]                              = rf_sink_data[PKT_TRANS_WRITE];
-      rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]                   = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
-      rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]                  = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
-      rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L]                   = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
-      rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L]            = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
-
-      // Burst uncompressor assignments
-      rp_data[PKT_ADDR_H   :PKT_ADDR_L]                     = rp_address;
-      rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]              = rp_burstwrap;
-      rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]                = burst_byte_cnt;
-      rp_data[PKT_TRANS_READ]                               = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
-      rp_data[PKT_TRANS_COMPRESSED_READ]                    = rp_is_compressed;
-
-      rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L]  = response_merged;
-      rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]            = uncompressor_burstsize;
-      // bounce the original size back to the master untouched
-      rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]    = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
-   end
-
-   // ------------------------------------------------------------------
-   // Note: the burst uncompressor may be asked to generate responses for
-   // write packets; these are treated the same as single-cycle uncompressed 
-   // reads.
-   // ------------------------------------------------------------------
-   altera_merlin_burst_uncompressor #(
-      .ADDR_W               (ADDR_W),
-      .BURSTWRAP_W          (BURSTWRAP_W),
-      .BYTE_CNT_W           (BYTE_CNT_W),
-      .PKT_SYMBOLS          (PKT_SYMBOLS),
-      .BURST_SIZE_W         (BURSTSIZE_W)
-   ) uncompressor (
-      .clk                  (clk),
-      .reset                (reset),
-      .sink_startofpacket   (rf_sink_startofpacket_wire),
-      .sink_endofpacket     (rf_sink_endofpacket),
-      .sink_valid           (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
-      .sink_ready           (rf_sink_ready),
-      .sink_addr            (rf_sink_addr),
-      .sink_burstwrap       (rf_sink_burstwrap),
-      .sink_byte_cnt        (rf_sink_byte_cnt),
-      .sink_is_compressed   (rf_sink_compressed),
-      .sink_burstsize       (rf_sink_burstsize),
-
-      .source_startofpacket (rp_startofpacket),
-      .source_endofpacket   (rp_endofpacket),
-      .source_valid         (uncompressor_source_valid),
-      .source_ready         (ready_for_response),
-      .source_addr          (rp_address),
-      .source_burstwrap     (rp_burstwrap),
-      .source_byte_cnt      (burst_byte_cnt),
-      .source_is_compressed (rp_is_compressed),
-      .source_burstsize     (uncompressor_burstsize)
-   );
-
-   //--------------------------------------
-   // Assertion: In case slave support response. The slave needs return response in order
-   // Ex: non-posted write followed by a read: write response must complete before read data 
-   //--------------------------------------
-   // synthesis translate_off      
-   ERROR_write_response_and_read_response_cannot_happen_same_time:
-   assert property ( @(posedge clk)
-      disable iff (reset) !(m0_writeresponsevalid  && m0_readdatavalid)
-   );    
-
-   // synthesis translate_on
-endmodule
-
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_agent
+#(
+   // Packet parameters
+   parameter PKT_BEGIN_BURST           = 81,
+   parameter PKT_DATA_H                = 31,
+   parameter PKT_DATA_L                = 0,
+   parameter PKT_SYMBOL_W              = 8,
+   parameter PKT_BYTEEN_H              = 71,
+   parameter PKT_BYTEEN_L              = 68,
+   parameter PKT_ADDR_H                = 63,
+   parameter PKT_ADDR_L                = 32,
+   parameter PKT_TRANS_LOCK            = 87,
+   parameter PKT_TRANS_COMPRESSED_READ = 67,
+   parameter PKT_TRANS_POSTED          = 66, 
+   parameter PKT_TRANS_WRITE           = 65,
+   parameter PKT_TRANS_READ            = 64,
+   parameter PKT_SRC_ID_H              = 74,
+   parameter PKT_SRC_ID_L              = 72,
+   parameter PKT_DEST_ID_H             = 77,
+   parameter PKT_DEST_ID_L             = 75,
+   parameter PKT_BURSTWRAP_H           = 85,
+   parameter PKT_BURSTWRAP_L           = 82,
+   parameter PKT_BYTE_CNT_H            = 81,
+   parameter PKT_BYTE_CNT_L            = 78,
+   parameter PKT_PROTECTION_H          = 86,
+   parameter PKT_PROTECTION_L          = 86,
+   parameter PKT_RESPONSE_STATUS_H     = 89,
+   parameter PKT_RESPONSE_STATUS_L     = 88,
+   parameter PKT_BURST_SIZE_H          = 92,
+   parameter PKT_BURST_SIZE_L          = 90,
+   parameter PKT_ORI_BURST_SIZE_L      = 93,
+   parameter PKT_ORI_BURST_SIZE_H      = 95,
+   parameter ST_DATA_W                 = 96,
+   parameter ST_CHANNEL_W              = 32,
+
+   // Slave parameters
+   parameter ADDR_W           = PKT_ADDR_H - PKT_ADDR_L + 1,
+   parameter AVS_DATA_W       = PKT_DATA_H - PKT_DATA_L + 1,
+   parameter AVS_BURSTCOUNT_W = 4,
+   parameter PKT_SYMBOLS      = AVS_DATA_W / PKT_SYMBOL_W,
+
+   // Slave agent parameters
+   parameter PREVENT_FIFO_OVERFLOW = 0,
+   parameter SUPPRESS_0_BYTEEN_CMD = 1,
+   parameter USE_READRESPONSE      = 0,
+   parameter USE_WRITERESPONSE     = 0,
+
+   // Derived slave parameters
+   parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   parameter BURST_SIZE_W = 3,
+
+   // Derived FIFO width
+   parameter FIFO_DATA_W = ST_DATA_W + 1,
+   
+   // ECC parameter
+   parameter ECC_ENABLE = 0
+) (
+   input                         clk,
+   input                         reset,
+
+   // Universal-Avalon anti-slave
+   output [ADDR_W-1:0]           m0_address,
+   output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
+   output [AVS_BE_W-1:0]         m0_byteenable,
+   output                        m0_read,
+   input [AVS_DATA_W-1:0]        m0_readdata,
+   input                         m0_waitrequest,
+   output                        m0_write,
+   output [AVS_DATA_W-1:0]       m0_writedata,
+   input                         m0_readdatavalid,
+   output                        m0_debugaccess,
+   output                        m0_lock,
+   input [1:0]                   m0_response,
+   input                         m0_writeresponsevalid,
+
+   // Avalon-ST FIFO interfaces.
+   // Note: there's no need to include the "data" field here, at least for
+   // reads, since readdata is filled in from slave info.  To keep life
+   // simple, have a data field, but fill it with 0s.
+   // Av-st response fifo source interface
+   output reg [FIFO_DATA_W-1:0]  rf_source_data,
+   output                        rf_source_valid,
+   output                        rf_source_startofpacket,
+   output                        rf_source_endofpacket,
+   input                         rf_source_ready,
+
+   // Av-st response fifo sink interface
+   input [FIFO_DATA_W-1:0]       rf_sink_data,
+   input                         rf_sink_valid,
+   input                         rf_sink_startofpacket,
+   input                         rf_sink_endofpacket,
+   output                        rf_sink_ready,
+
+   // Av-st readdata fifo src interface, data and response
+   // extra 2 bits for storing RESPONSE STATUS
+   output [AVS_DATA_W+1:0]       rdata_fifo_src_data,
+   output                        rdata_fifo_src_valid,
+   input                         rdata_fifo_src_ready,
+
+   // Av-st readdata fifo sink interface
+   input [AVS_DATA_W+1:0]        rdata_fifo_sink_data,
+   input                         rdata_fifo_sink_valid,
+   output                        rdata_fifo_sink_ready,
+   input                         rdata_fifo_sink_error,
+
+   // Av-st sink command packet interface
+   output                        cp_ready,
+   input                         cp_valid,
+   input [ST_DATA_W-1:0]         cp_data,
+   input [ST_CHANNEL_W-1:0]      cp_channel,
+   input                         cp_startofpacket,
+   input                         cp_endofpacket,
+
+   // Av-st source response packet interface
+   input                         rp_ready,
+   output reg                    rp_valid,
+   output reg [ST_DATA_W-1:0]    rp_data,
+   output                        rp_startofpacket,
+   output                        rp_endofpacket
+);
+
+   // --------------------------------------------------
+   // Ceil(log2()) function log2ceil of 4 = 2
+   // --------------------------------------------------
+   function integer log2ceil;
+      input reg[63:0] val;
+      reg [63:0] i;
+   
+      begin
+         i = 1;
+         log2ceil = 0;
+
+         while (i < val) begin
+            log2ceil = log2ceil + 1;
+            i = i << 1;
+         end
+      end
+   endfunction     
+
+   // ------------------------------------------------
+   // Local Parameters
+   // ------------------------------------------------
+   localparam DATA_W       = PKT_DATA_H - PKT_DATA_L + 1;
+   localparam BE_W         = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+   localparam MID_W        = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
+   localparam SID_W        = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+   localparam BYTE_CNT_W   = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+   localparam BURSTWRAP_W  = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+   localparam BURSTSIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
+   localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
+   localparam MAX_BURST    = 1 << (AVS_BURSTCOUNT_W - 1);
+   localparam BURSTING     = (MAX_BURST > PKT_SYMBOLS);
+
+   // ------------------------------------------------
+   // Signals
+   // ------------------------------------------------
+   wire [DATA_W-1:0]      cmd_data;
+   wire [BE_W-1:0]        cmd_byteen;
+   wire [ADDR_W-1:0]      cmd_addr;
+   wire [MID_W-1:0]       cmd_mid;
+   wire [SID_W-1:0]       cmd_sid;
+   wire                   cmd_read;
+   wire                   cmd_write;
+   wire                   cmd_compressed;
+   wire                   cmd_posted;
+   wire [BYTE_CNT_W-1:0]  cmd_byte_cnt;
+   wire [BURSTWRAP_W-1:0] cmd_burstwrap;
+   wire [BURSTSIZE_W-1:0] cmd_burstsize;
+   wire                   cmd_debugaccess;
+
+   wire                   suppress_cmd;
+   wire                   byteen_asserted;
+   wire                   suppress_read;
+   wire                   suppress_write;
+   wire                   needs_response_synthesis;
+   wire                   generate_response;
+
+   // Assign command fields
+   assign cmd_data         = cp_data[PKT_DATA_H  :PKT_DATA_L  ];
+   assign cmd_byteen       = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
+   assign cmd_addr         = cp_data[PKT_ADDR_H  :PKT_ADDR_L  ];
+   assign cmd_compressed   = cp_data[PKT_TRANS_COMPRESSED_READ];
+   assign cmd_posted       = cp_data[PKT_TRANS_POSTED];
+   assign cmd_write        = cp_data[PKT_TRANS_WRITE];
+   assign cmd_read         = cp_data[PKT_TRANS_READ];
+   assign cmd_mid          = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
+   assign cmd_sid          = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+   assign cmd_byte_cnt     = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   assign cmd_burstwrap    = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   assign cmd_burstsize    = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   assign cmd_debugaccess  = cp_data[PKT_PROTECTION_L];
+
+   // Local "ready_for_command" signal: deasserted when the agent is unable to accept
+   // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
+   // ~rp_ready), ...
+   // Say, this could depend on the type of command, for example, even if the
+   // rdv FIFO is full, a write request can be accepted.  For later.
+   wire ready_for_command;
+
+   wire local_lock  = cp_valid & cp_data[PKT_TRANS_LOCK];
+   wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
+   wire local_read  = cp_valid & cp_data[PKT_TRANS_READ];
+   wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
+   wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+   generate
+      if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
+         // ---------------------------------------------------
+         // Backpressure if the slave says to, or if FIFO overflow may occur.
+         // 
+         // All commands are backpressured once the FIFO is full
+         // even if they don't need storage. This breaks a long
+         // combinatorial path from the master read/write through
+         // this logic and back to the master via the backpressure
+         // path.
+         //
+         // To avoid a loss of throughput the FIFO will be parameterized 
+         // one slot deeper. The extra slot should never be used in normal
+         // operation, but should a slave misbehave and accept one more
+         // read than it should then backpressure will kick in.
+         //
+         // An example: assume a slave with MPRT = 2. It can accept a
+         // command sequence RRWW without backpressuring. If the FIFO is
+         // only 2 deep, we'd backpressure the writes leading to loss of
+         // throughput. If the FIFO is 3 deep, we'll only backpressure when
+         // RRR... which is an illegal condition anyway.
+         // ---------------------------------------------------
+
+         assign ready_for_command = rf_source_ready;
+         assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
+
+      end else begin : no_prevent_fifo_overflow_block
+
+         // Do not suppress the command or the slave will
+         // not be able to waitrequest
+         assign ready_for_command = 1'b1;
+         // Backpressure only if the slave says to.
+         assign cp_ready = ~m0_waitrequest | suppress_cmd;
+
+      end
+   endgenerate
+
+   generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = ~byteen_asserted;
+      assign suppress_cmd     = ~byteen_asserted;
+   end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = ~byteen_asserted && cmd_read;
+   end else begin : no_suppress_0_byteen_cmd
+      assign suppress_read    = 1'b0;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = 1'b0;
+   end
+   endgenerate
+
+   // -------------------------------------------------------------------
+   // Extract avalon signals from command packet.
+   // -------------------------------------------------------------------
+   // Mask off the lower bits of address.
+   // The burst adapter before this component will break narrow sized packets
+   // into sub-bursts of length 1. However, the packet addresses are preserved,
+   // which means this component may see size-aligned addresses.
+   //
+   // Masking ensures that the addresses seen by an Avalon slave are aligned to 
+   // the full data width instead of the size.
+   //
+   // Example:
+   // output from burst adapter (datawidth=4, size=2 bytes):
+   // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
+   // expected output from slave agent:
+   // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
+   generate 
+      if (BITS_TO_MASK > 0) begin : mask_address
+
+         assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
+
+      end else begin : no_mask_address
+
+         assign m0_address = cmd_addr;
+
+      end
+   endgenerate
+
+   assign m0_byteenable = cmd_byteen;
+   assign m0_writedata  = cmd_data;
+
+   // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
+   // this sort of burst exists only in merlin fabric ST packets. What to do
+   // if we see such a burst? All beats in that burst need to be transmitted
+   // to the slave so we have enough space-time for byteenable expression.
+   //
+   // There can be multiple bursts in a packet, but only one beat per burst
+   // in <most> cases. The exception is when we've decided not to insert a
+   // burst adapter for efficiency reasons, in which case this agent is also
+   // responsible for driving burstcount to 1 on each beat of an uncompressed
+   // read burst.
+
+   assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
+
+   generate 
+       // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal.  Assign m0_burstcount
+       // from a sub-range, or 0-pad, as appropriate.
+       if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
+          wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
+          assign m0_burstcount = (local_read & ~local_compressed_read) ?
+             {zero_pad, num_symbols} :
+             {zero_pad, cmd_byte_cnt};
+       end
+       else begin : m0_burstcount_no_pad
+          assign m0_burstcount = (local_read & ~local_compressed_read) ? 
+          num_symbols[AVS_BURSTCOUNT_W-1:0] : 
+          cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
+       end
+   endgenerate
+
+   assign m0_write = ready_for_command & local_write & !suppress_write;
+   assign m0_lock  = ready_for_command & local_lock & (m0_read | m0_write);
+   assign m0_debugaccess  = cmd_debugaccess;
+
+   // -------------------------------------------------------------------
+   // Indirection layer for response packet values.  Some may always wire
+   // directly from the slave translator; others will no doubt emerge from
+   // various FIFOs.
+   // What to put in resp_data when a write occured? Answer: it does not
+   // matter, because only response status is needed for non-posted writes,
+   // and the packet already has a field for that.
+   //
+   // We use the rdata_fifo to store write responses as well. This allows us
+   // to handle backpressure on the response path, and allows write response
+   // merging.
+   assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
+   assign rdata_fifo_src_data  = {m0_response, m0_readdata};
+
+   // ------------------------------------------------------------------
+   // Generate a token when read commands are suppressed. The token
+   // is stored in the response FIFO, and will be used to synthesize 
+   // a read response. The same token is used for non-posted write
+   // response synthesis.
+   //
+   // Note: this token is not generated for suppressed uncompressed read cycles;
+   // the burst uncompression logic at the read side of the response FIFO
+   // generates the correct number of responses.
+   //
+   // When the slave can return the response, let it do its job. Don't 
+   // synthesize a response in that case, unless we've suppressed the
+   // the last transfer in a write sub-burst.
+   // ------------------------------------------------------------------
+   wire write_end_of_subburst;
+   assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || 
+                                        (!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
+                                        (USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
+
+   // Avalon-ST interfaces to external response FIFO.
+   //
+   // For efficiency, when synthesizing a write response we only store a non-posted write 
+   // transaction at its endofpacket, even if it was split into multiple sub-bursts.
+   //
+   // When not synthesizing write responses, we store each sub-burst in the FIFO.
+   // Each sub-burst to the slave will return a response, which corresponds to one 
+   // entry in the FIFO. We merge all the sub-burst responses on the final
+   // sub-burst and send it on the response channel.
+
+   wire internal_cp_endofburst;
+   wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
+   wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
+
+   assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
+   assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
+   assign write_end_of_subburst = local_write & internal_cp_endofburst;
+
+   assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
+                             & ready_for_command & cp_ready;
+   assign rf_source_startofpacket = cp_startofpacket;
+   assign rf_source_endofpacket   = cp_endofpacket;
+   always @* begin
+      // default: assign every command packet field to the response FIFO...
+      rf_source_data                                  = {1'b0, cp_data};
+
+      // ... and override select fields as needed.
+      rf_source_data[FIFO_DATA_W-1]                      = needs_response_synthesis;
+      rf_source_data[PKT_DATA_H   :PKT_DATA_L]           = {DATA_W {1'b0}};
+      rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L]         = cmd_byteen;
+      rf_source_data[PKT_ADDR_H   :PKT_ADDR_L]           = cmd_addr;
+      rf_source_data[PKT_TRANS_COMPRESSED_READ]          = cmd_compressed;
+      rf_source_data[PKT_TRANS_POSTED]                   = cmd_posted;
+      rf_source_data[PKT_TRANS_WRITE]                    = cmd_write;
+      rf_source_data[PKT_TRANS_READ]                     = cmd_read;
+      rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L]         = cmd_mid;
+      rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L]        = cmd_sid;
+      rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]      = cmd_byte_cnt;
+      rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]    = cmd_burstwrap;
+      rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]  = cmd_burstsize;
+      rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L]  = '0;
+      rf_source_data[PKT_PROTECTION_L]                   = cmd_debugaccess;
+   end
+
+   wire uncompressor_source_valid;
+   wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
+   wire last_write_response;
+
+   // last_write_response indicates the last response of the broken-up write burst (sub-bursts).
+   // At this time, the final merged response is sent, and rp_valid is only asserted
+   // once for the whole burst.
+   generate
+      if (USE_WRITERESPONSE) begin
+         assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
+         always @* begin
+            if (rf_sink_data[PKT_TRANS_WRITE] == 1) 
+               rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
+            else
+               rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end else begin
+         assign last_write_response = 1'b0;
+         always @* begin
+            rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end
+   endgenerate
+
+   // ------------------------------------------------------------------
+   // Response merging
+   // ------------------------------------------------------------------
+   reg [1:0] current_response;
+   reg [1:0] response_merged;
+   generate
+     if (USE_WRITERESPONSE) begin : response_merging_all
+        reg first_write_response;
+        reg reset_merged_output;
+        reg [1:0] previous_response_in;
+        reg [1:0]  previous_response;
+
+        always_ff @(posedge clk, posedge reset) begin
+           if (reset) begin
+              first_write_response  <= 1'b1;
+           end 
+           else begin // Merging work for write response, for read: previous_response_in = current_response
+              if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
+                 first_write_response <= 1'b0;
+                 if (rf_sink_endofpacket)
+                    first_write_response <= 1'b1;
+              end
+           end
+        end
+
+        always_comb begin
+           current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
+           reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
+           previous_response_in = reset_merged_output ? current_response : previous_response;
+           response_merged = current_response >= previous_response ? current_response: previous_response_in;
+        end
+
+        always_ff @(posedge clk or posedge reset) begin
+           if (reset) begin 
+              previous_response <= 2'b00;
+           end
+           else begin
+              if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
+                 previous_response <= response_merged;
+              end
+           end
+        end
+     end else begin : response_merging_read_only
+        always @* begin
+           current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | 
+                                                         {2{rdata_fifo_sink_error}};
+           response_merged = current_response;
+        end
+     end
+   endgenerate
+
+   assign generate_response = rf_sink_data[FIFO_DATA_W-1];
+
+   wire [BYTE_CNT_W-1:0]  rf_sink_byte_cnt   = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   wire                   rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+   wire [BURSTWRAP_W-1:0] rf_sink_burstwrap  = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   wire [BURSTSIZE_W-1:0] rf_sink_burstsize  = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   wire [ADDR_W-1:0]      rf_sink_addr       = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
+   // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
+   wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;    
+
+   wire [BYTE_CNT_W-1:0]   burst_byte_cnt;
+   wire [BURSTWRAP_W-1:0]  rp_burstwrap;
+   wire [ADDR_W-1:0]       rp_address;
+   wire                    rp_is_compressed;
+   wire                    ready_for_response;
+
+   // ------------------------------------------------------------------
+   // We're typically ready for a response if the network is ready. There
+   // is one exception:
+   //
+   // If the slave issues write responses, we only issue a merged response on 
+   // the final sub-burst. As a result, we only care about response channel 
+   // availability on the final burst when we send out the merged response.
+   // ------------------------------------------------------------------
+   assign ready_for_response = (USE_WRITERESPONSE) ? 
+                            rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: 
+                            rp_ready;
+
+   // ------------------------------------------------------------------
+   // Backpressure the readdata fifo if we're supposed to synthesize a response.
+   // This may be a read response (for suppressed reads) or a write response
+   // (for non-posted writes).
+   // ------------------------------------------------------------------
+   assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
+
+   always @* begin
+      // By default, return all fields...
+      rp_data                                               = rf_sink_data[ST_DATA_W - 1 : 0];
+
+      // ... and override specific fields.
+      rp_data[PKT_DATA_H   :PKT_DATA_L]                     = rdata_fifo_sink_data[AVS_DATA_W-1:0];
+      // Assignments directly from the response fifo.
+      rp_data[PKT_TRANS_POSTED]                             = rf_sink_data[PKT_TRANS_POSTED];
+      rp_data[PKT_TRANS_WRITE]                              = rf_sink_data[PKT_TRANS_WRITE];
+      rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]                   = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+      rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]                  = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+      rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L]                   = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+      rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L]            = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
+
+      // Burst uncompressor assignments
+      rp_data[PKT_ADDR_H   :PKT_ADDR_L]                     = rp_address;
+      rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]              = rp_burstwrap;
+      rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]                = burst_byte_cnt;
+      rp_data[PKT_TRANS_READ]                               = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+      rp_data[PKT_TRANS_COMPRESSED_READ]                    = rp_is_compressed;
+
+      rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L]  = response_merged;
+      rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]            = uncompressor_burstsize;
+      // bounce the original size back to the master untouched
+      rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]    = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
+   end
+
+   // ------------------------------------------------------------------
+   // Note: the burst uncompressor may be asked to generate responses for
+   // write packets; these are treated the same as single-cycle uncompressed 
+   // reads.
+   // ------------------------------------------------------------------
+   altera_merlin_burst_uncompressor #(
+      .ADDR_W               (ADDR_W),
+      .BURSTWRAP_W          (BURSTWRAP_W),
+      .BYTE_CNT_W           (BYTE_CNT_W),
+      .PKT_SYMBOLS          (PKT_SYMBOLS),
+      .BURST_SIZE_W         (BURSTSIZE_W)
+   ) uncompressor (
+      .clk                  (clk),
+      .reset                (reset),
+      .sink_startofpacket   (rf_sink_startofpacket_wire),
+      .sink_endofpacket     (rf_sink_endofpacket),
+      .sink_valid           (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
+      .sink_ready           (rf_sink_ready),
+      .sink_addr            (rf_sink_addr),
+      .sink_burstwrap       (rf_sink_burstwrap),
+      .sink_byte_cnt        (rf_sink_byte_cnt),
+      .sink_is_compressed   (rf_sink_compressed),
+      .sink_burstsize       (rf_sink_burstsize),
+
+      .source_startofpacket (rp_startofpacket),
+      .source_endofpacket   (rp_endofpacket),
+      .source_valid         (uncompressor_source_valid),
+      .source_ready         (ready_for_response),
+      .source_addr          (rp_address),
+      .source_burstwrap     (rp_burstwrap),
+      .source_byte_cnt      (burst_byte_cnt),
+      .source_is_compressed (rp_is_compressed),
+      .source_burstsize     (uncompressor_burstsize)
+   );
+
+   //--------------------------------------
+   // Assertion: In case slave support response. The slave needs return response in order
+   // Ex: non-posted write followed by a read: write response must complete before read data 
+   //--------------------------------------
+   // synthesis translate_off      
+   ERROR_write_response_and_read_response_cannot_happen_same_time:
+   assert property ( @(posedge clk)
+      disable iff (reset) !(m0_writeresponsevalid  && m0_readdatavalid)
+   );    
+
+   // synthesis translate_on
+endmodule
+
diff --git a/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv b/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv
index 206eed5..ae64b31 100644
--- a/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv
+++ b/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv
@@ -11,472 +11,472 @@
 // agreement for further details.
 
 
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// -------------------------------------
-// Merlin Slave Translator
-//
-// Translates Universal Avalon  MM Slave
-// to any Avalon MM Slave
-// -------------------------------------
-//
-//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
-//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
-//The key feature here is that no same cycle turnaround data is processed through the fabric.
-
-//import avalon_utilities_pkg::*;
-
-`timescale 1 ns / 1 ns
-
-module altera_merlin_slave_translator #(
-   parameter
-   //Widths
-   AV_ADDRESS_W           = 32,
-   AV_DATA_W              = 32,
-   AV_BURSTCOUNT_W        = 4,
-   AV_BYTEENABLE_W        = 4,
-   UAV_BYTEENABLE_W       = 4,
-
-   //Read Latency
-   AV_READLATENCY          = 1,
-
-   //Timing
-   AV_READ_WAIT_CYCLES     = 0,
-   AV_WRITE_WAIT_CYCLES    = 0,
-   AV_SETUP_WAIT_CYCLES    = 0,
-   AV_DATA_HOLD_CYCLES     = 0,
-
-   //Optional Port Declarations
-   USE_READDATAVALID       = 1,
-   USE_WAITREQUEST         = 1,
-   USE_READRESPONSE        = 0,
-   USE_WRITERESPONSE       = 0,
-
-   //Variable Addressing
-   AV_SYMBOLS_PER_WORD     = 4,
-   AV_ADDRESS_SYMBOLS      = 0,
-   AV_BURSTCOUNT_SYMBOLS   = 0,
-   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
-   UAV_ADDRESS_W           = 38,
-   UAV_BURSTCOUNT_W        = 10,
-   UAV_DATA_W              = 32,
-
-   AV_CONSTANT_BURST_BEHAVIOR       = 0,
-   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
-   CHIPSELECT_THROUGH_READLATENCY   = 0,
-
-   // Tightly-Coupled Options
-   USE_UAV_CLKEN           = 0,
-   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
-) (
-
-   // -------------------
-   // Clock & Reset
-   // -------------------
-   input wire                             clk,
-   input wire                             reset,
-
-   // -------------------
-   // Universal Avalon Slave
-   // -------------------
-
-   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
-   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
-   input wire                             uav_write,
-   input wire                             uav_read,
-   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
-   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
-   input wire                             uav_lock,
-   input wire                             uav_debugaccess,
-   input wire                             uav_clken,
-
-   output logic                           uav_readdatavalid,
-   output logic                           uav_waitrequest,
-   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
-   output logic [1:0]                     uav_response,
-   // input wire                             uav_writeresponserequest,
-   output logic                           uav_writeresponsevalid,
-
-   // -------------------
-   // Customizable Avalon Master
-   // -------------------
-   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
-   output logic [AV_DATA_W - 1 : 0]       av_writedata,
-   output logic                           av_write,
-   output logic                           av_read,
-   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
-   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
-   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
-   output logic                           av_begintransfer,
-   output wire                            av_chipselect,
-   output logic                           av_beginbursttransfer,
-   output logic                           av_lock,
-   output wire                            av_clken,
-   output wire                            av_debugaccess,
-   output wire                            av_outputenable,
-
-   input logic [AV_DATA_W - 1 : 0]        av_readdata,
-   input logic                            av_readdatavalid,
-   input logic                            av_waitrequest,
-
-   input logic [1:0]                      av_response,
-   // output logic                           av_writeresponserequest,
-   input wire                             av_writeresponsevalid
-
-);
-
-   function integer clog2_plusone;
-      input [31:0] Depth;
-      integer i;
-      begin
-         i = Depth;
-         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
-            i = i >> 1;
-      end
-   endfunction
-
-   function integer max;
-      //returns the larger of two passed arguments
-      input [31:0] one;
-      input [31:0] two;
-      if(one > two)
-         max=one;
-      else
-         max=two;
-   endfunction // int
-
-   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
-   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
-   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
-   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
-   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
-   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
-   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
-                                          AV_ADDRESS_W :
-                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
-   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
-                                          AV_BURSTCOUNT_W :
-                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
-   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
-
-
-   // Calculate the symbols per word as the power of 2 extended symbols per word
-   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
-   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
-
-   // +--------------------------------
-   // |Backwards Compatibility Signals
-   // +--------------------------------
-   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
-   assign av_debugaccess = uav_debugaccess;
-
-   // +-------------------
-   // |Passthru Signals
-   // +-------------------
-
-   reg [1 : 0] av_response_delayed;
-
-   always @(posedge clk, posedge reset) begin
-      if (reset) begin
-         av_response_delayed <= 2'b0;
-      end else begin
-         av_response_delayed <= av_response;
-      end
-   end
-
-   always_comb
-   begin
-      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
-         uav_response = '0;
-      end else begin
-         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
-            uav_response = av_response;
-         end else begin
-            uav_response = av_response_delayed;
-         end
-      end
-   end
-   // assign av_writeresponserequest = uav_writeresponserequest;
-   assign uav_writeresponsevalid = av_writeresponsevalid;
-
-   //-------------------------
-   //Writedata and Byteenable
-   //-------------------------
-
-   always@* begin
-      av_byteenable = '0;
-      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
-   end
-
-   always@* begin
-      av_writedata = '0;
-      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
-   end
-
-   // +-------------------
-   // |Calculated Signals
-   // +-------------------
-
-   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
-
-   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
-      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
-
-      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
-         if(byteenable[i] == 1) begin
-            return i;
-         end
-      end
-
-      return '0;
-
-   endfunction
-
-   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
-   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
-   always@(posedge clk, posedge reset) begin
-      if(reset) begin
-         burstcount_reg <= '0;
-         address_reg    <= '0;
-      end else begin
-         burstcount_reg <= burstcount_reg;
-         address_reg    <= address_reg;
-         if(av_beginbursttransfer) begin
-            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
-            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
-         end
-      end
-   end
-
-   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
-
-   always@* begin
-      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
-         temp_wire = decode_byteenable(uav_byteenable);
-         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
-      end else begin
-         real_uav_address = uav_address;
-      end
-
-      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
-      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
-         av_address = address_reg;
-   end
-
-   always@* begin
-      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
-      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
-         av_burstcount = burstcount_reg;
-   end
-
-   always@* begin
-      av_lock = uav_lock;
-   end
-
-   // -------------------
-   // Writebyteenable Assignment
-   // -------------------
-   always@* begin
-      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
-   end
-
-   // -------------------
-   // Waitrequest Assignment
-   // -------------------
-
-   reg av_waitrequest_generated;
-   reg av_waitrequest_generated_read;
-   reg av_waitrequest_generated_write;
-   reg waitrequest_reset_override;
-   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
-
-   always@(posedge reset, posedge clk) begin
-      if(reset) begin
-         wait_latency_counter <= '0;
-         waitrequest_reset_override <= 1'h1;
-      end else begin
-         waitrequest_reset_override <= 1'h0;
-         wait_latency_counter <= '0;
-         if( ~uav_waitrequest | waitrequest_reset_override )
-            wait_latency_counter <= '0;
-         else if( uav_read | uav_write )
-            wait_latency_counter <= wait_latency_counter + 1'h1;
-      end
-   end
-
-
-   always @* begin
-
-      av_read  = uav_read;
-      av_write = uav_write;
-      av_waitrequest_generated         = 1'h1;
-      av_waitrequest_generated_read    = 1'h1;
-      av_waitrequest_generated_write   = 1'h1;
-
-      if(LOG2_OF_LATENCY_SUM == 1)
-         av_waitrequest_generated = 0;
-
-      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
-         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
-         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
-         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
-         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
-
-         if(uav_write)
-            av_waitrequest_generated = av_waitrequest_generated_write;
-         else
-            av_waitrequest_generated = av_waitrequest_generated_read;
-
-      end
-
-      if(USE_WAITREQUEST) begin
-         uav_waitrequest = av_waitrequest;
-      end else begin
-         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
-      end
-
-   end
-
-   // --------------
-   // Readdata Assignment
-   // --------------
-
-   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
-
-   always@(posedge clk, posedge reset) begin
-      if(reset)
-         av_readdata_pre <= 'b0;
-      else
-         av_readdata_pre <= av_readdata;
-   end
-
-   always@* begin
-      uav_readdata = {UAV_DATA_W{1'b0}};
-      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
-         uav_readdata[AV_DATA_W-1:0] = av_readdata;
-      end else begin
-         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
-      end
-   end
-   
-   // -------------------
-   // Readdatavalid Assigment
-   // -------------------
-   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
-   reg top_read_latency_shift_reg;
-
-   always@* begin
-      uav_readdatavalid=top_read_latency_shift_reg;
-      if(USE_READDATAVALID) begin
-         uav_readdatavalid = av_readdatavalid;
-      end
-   end
-
-   always@* begin
-      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
-      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
-         top_read_latency_shift_reg=read_latency_shift_reg;
-      end
-      if (AV_READLATENCY > 1) begin
-         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
-      end
-   end
-
-   always@(posedge reset, posedge clk) begin
-      if (reset) begin
-         read_latency_shift_reg <= '0;
-      end else if (av_clken) begin
-         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
-         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
-            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
-         end
-      end
-   end
-
-   // ------------
-   // Chipselect and OutputEnable
-   // ------------
-   reg av_chipselect_pre;
-   wire cs_extension;
-   reg av_outputenable_pre;
-   
-   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
-   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
-   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
-
-   always@(posedge reset, posedge clk) begin
-      if(reset)
-         av_outputenable_pre <= 1'b0;
-      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
-         av_outputenable_pre <= 0;
-      else
-         av_outputenable_pre <= cs_extension | uav_read;
-   end
-
-   always@(posedge reset, posedge clk) begin
-      if(reset) begin
-         av_chipselect_pre  <= 1'b0;
-      end else begin
-         av_chipselect_pre  <= 1'b0;
-         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
-            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
-            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
-            if(uav_read) begin
-               av_chipselect_pre <= 1'b1;
-            end else if(cs_extension == 1) begin
-               av_chipselect_pre <= 1'b1;
-            end
-         end
-      end
-   end
-
-   // -------------------
-   // Begintransfer Assigment
-   // -------------------
-   reg end_begintransfer;
-
-   always@* begin
-      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
-   end
-
-   always@ ( posedge clk or posedge reset ) begin
-      if(reset) begin
-         end_begintransfer <= 1'b0;
-      end else begin
-         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
-            end_begintransfer <= 1'b1;
-         else if(uav_waitrequest)
-            end_begintransfer <= end_begintransfer;
-         else
-            end_begintransfer <= 1'b0;
-      end
-   end
-
-   // -------------------
-   // Beginbursttransfer Assigment
-   // -------------------
-   reg end_beginbursttransfer;
-   reg in_transfer;
-
-   always@* begin
-      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
-   end
-
-   always@ ( posedge clk or posedge reset ) begin
-      if(reset) begin
-         end_beginbursttransfer <= 1'b0;
-         in_transfer <= 1'b0;
-      end else begin
-         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
-         if(uav_write && uav_burstcount == symbols_per_word)
-            in_transfer <=1'b0;
-         else if(uav_write)
-            in_transfer <=1'b1;
-      end
-   end
-
-endmodule
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon  MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator #(
+   parameter
+   //Widths
+   AV_ADDRESS_W           = 32,
+   AV_DATA_W              = 32,
+   AV_BURSTCOUNT_W        = 4,
+   AV_BYTEENABLE_W        = 4,
+   UAV_BYTEENABLE_W       = 4,
+
+   //Read Latency
+   AV_READLATENCY          = 1,
+
+   //Timing
+   AV_READ_WAIT_CYCLES     = 0,
+   AV_WRITE_WAIT_CYCLES    = 0,
+   AV_SETUP_WAIT_CYCLES    = 0,
+   AV_DATA_HOLD_CYCLES     = 0,
+
+   //Optional Port Declarations
+   USE_READDATAVALID       = 1,
+   USE_WAITREQUEST         = 1,
+   USE_READRESPONSE        = 0,
+   USE_WRITERESPONSE       = 0,
+
+   //Variable Addressing
+   AV_SYMBOLS_PER_WORD     = 4,
+   AV_ADDRESS_SYMBOLS      = 0,
+   AV_BURSTCOUNT_SYMBOLS   = 0,
+   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
+   UAV_ADDRESS_W           = 38,
+   UAV_BURSTCOUNT_W        = 10,
+   UAV_DATA_W              = 32,
+
+   AV_CONSTANT_BURST_BEHAVIOR       = 0,
+   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
+   CHIPSELECT_THROUGH_READLATENCY   = 0,
+
+   // Tightly-Coupled Options
+   USE_UAV_CLKEN           = 0,
+   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+) (
+
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input wire                             clk,
+   input wire                             reset,
+
+   // -------------------
+   // Universal Avalon Slave
+   // -------------------
+
+   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
+   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
+   input wire                             uav_write,
+   input wire                             uav_read,
+   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
+   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
+   input wire                             uav_lock,
+   input wire                             uav_debugaccess,
+   input wire                             uav_clken,
+
+   output logic                           uav_readdatavalid,
+   output logic                           uav_waitrequest,
+   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
+   output logic [1:0]                     uav_response,
+   // input wire                             uav_writeresponserequest,
+   output logic                           uav_writeresponsevalid,
+
+   // -------------------
+   // Customizable Avalon Master
+   // -------------------
+   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
+   output logic [AV_DATA_W - 1 : 0]       av_writedata,
+   output logic                           av_write,
+   output logic                           av_read,
+   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+   output logic                           av_begintransfer,
+   output wire                            av_chipselect,
+   output logic                           av_beginbursttransfer,
+   output logic                           av_lock,
+   output wire                            av_clken,
+   output wire                            av_debugaccess,
+   output wire                            av_outputenable,
+
+   input logic [AV_DATA_W - 1 : 0]        av_readdata,
+   input logic                            av_readdatavalid,
+   input logic                            av_waitrequest,
+
+   input logic [1:0]                      av_response,
+   // output logic                           av_writeresponserequest,
+   input wire                             av_writeresponsevalid
+
+);
+
+   function integer clog2_plusone;
+      input [31:0] Depth;
+      integer i;
+      begin
+         i = Depth;
+         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
+            i = i >> 1;
+      end
+   endfunction
+
+   function integer max;
+      //returns the larger of two passed arguments
+      input [31:0] one;
+      input [31:0] two;
+      if(one > two)
+         max=one;
+      else
+         max=two;
+   endfunction // int
+
+   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
+   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+                                          AV_ADDRESS_W :
+                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+                                          AV_BURSTCOUNT_W :
+                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+   // Calculate the symbols per word as the power of 2 extended symbols per word
+   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
+
+   // +--------------------------------
+   // |Backwards Compatibility Signals
+   // +--------------------------------
+   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+   assign av_debugaccess = uav_debugaccess;
+
+   // +-------------------
+   // |Passthru Signals
+   // +-------------------
+
+   reg [1 : 0] av_response_delayed;
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         av_response_delayed <= 2'b0;
+      end else begin
+         av_response_delayed <= av_response;
+      end
+   end
+
+   always_comb
+   begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
+         uav_response = '0;
+      end else begin
+         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
+            uav_response = av_response;
+         end else begin
+            uav_response = av_response_delayed;
+         end
+      end
+   end
+   // assign av_writeresponserequest = uav_writeresponserequest;
+   assign uav_writeresponsevalid = av_writeresponsevalid;
+
+   //-------------------------
+   //Writedata and Byteenable
+   //-------------------------
+
+   always@* begin
+      av_byteenable = '0;
+      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   always@* begin
+      av_writedata = '0;
+      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+   end
+
+   // +-------------------
+   // |Calculated Signals
+   // +-------------------
+
+   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+         if(byteenable[i] == 1) begin
+            return i;
+         end
+      end
+
+      return '0;
+
+   endfunction
+
+   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
+   always@(posedge clk, posedge reset) begin
+      if(reset) begin
+         burstcount_reg <= '0;
+         address_reg    <= '0;
+      end else begin
+         burstcount_reg <= burstcount_reg;
+         address_reg    <= address_reg;
+         if(av_beginbursttransfer) begin
+            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+         end
+      end
+   end
+
+   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+   always@* begin
+      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+         temp_wire = decode_byteenable(uav_byteenable);
+         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+      end else begin
+         real_uav_address = uav_address;
+      end
+
+      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_address = address_reg;
+   end
+
+   always@* begin
+      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_burstcount = burstcount_reg;
+   end
+
+   always@* begin
+      av_lock = uav_lock;
+   end
+
+   // -------------------
+   // Writebyteenable Assignment
+   // -------------------
+   always@* begin
+      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   // -------------------
+   // Waitrequest Assignment
+   // -------------------
+
+   reg av_waitrequest_generated;
+   reg av_waitrequest_generated_read;
+   reg av_waitrequest_generated_write;
+   reg waitrequest_reset_override;
+   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         wait_latency_counter <= '0;
+         waitrequest_reset_override <= 1'h1;
+      end else begin
+         waitrequest_reset_override <= 1'h0;
+         wait_latency_counter <= '0;
+         if( ~uav_waitrequest | waitrequest_reset_override )
+            wait_latency_counter <= '0;
+         else if( uav_read | uav_write )
+            wait_latency_counter <= wait_latency_counter + 1'h1;
+      end
+   end
+
+
+   always @* begin
+
+      av_read  = uav_read;
+      av_write = uav_write;
+      av_waitrequest_generated         = 1'h1;
+      av_waitrequest_generated_read    = 1'h1;
+      av_waitrequest_generated_write   = 1'h1;
+
+      if(LOG2_OF_LATENCY_SUM == 1)
+         av_waitrequest_generated = 0;
+
+      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+         if(uav_write)
+            av_waitrequest_generated = av_waitrequest_generated_write;
+         else
+            av_waitrequest_generated = av_waitrequest_generated_read;
+
+      end
+
+      if(USE_WAITREQUEST) begin
+         uav_waitrequest = av_waitrequest;
+      end else begin
+         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+      end
+
+   end
+
+   // --------------
+   // Readdata Assignment
+   // --------------
+
+   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+   always@(posedge clk, posedge reset) begin
+      if(reset)
+         av_readdata_pre <= 'b0;
+      else
+         av_readdata_pre <= av_readdata;
+   end
+
+   always@* begin
+      uav_readdata = {UAV_DATA_W{1'b0}};
+      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata;
+      end else begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
+      end
+   end
+   
+   // -------------------
+   // Readdatavalid Assigment
+   // -------------------
+   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+   reg top_read_latency_shift_reg;
+
+   always@* begin
+      uav_readdatavalid=top_read_latency_shift_reg;
+      if(USE_READDATAVALID) begin
+         uav_readdatavalid = av_readdatavalid;
+      end
+   end
+
+   always@* begin
+      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+         top_read_latency_shift_reg=read_latency_shift_reg;
+      end
+      if (AV_READLATENCY > 1) begin
+         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+      end
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if (reset) begin
+         read_latency_shift_reg <= '0;
+      end else if (av_clken) begin
+         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+         end
+      end
+   end
+
+   // ------------
+   // Chipselect and OutputEnable
+   // ------------
+   reg av_chipselect_pre;
+   wire cs_extension;
+   reg av_outputenable_pre;
+   
+   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset)
+         av_outputenable_pre <= 1'b0;
+      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
+         av_outputenable_pre <= 0;
+      else
+         av_outputenable_pre <= cs_extension | uav_read;
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         av_chipselect_pre  <= 1'b0;
+      end else begin
+         av_chipselect_pre  <= 1'b0;
+         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+            if(uav_read) begin
+               av_chipselect_pre <= 1'b1;
+            end else if(cs_extension == 1) begin
+               av_chipselect_pre <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------
+   // Begintransfer Assigment
+   // -------------------
+   reg end_begintransfer;
+
+   always@* begin
+      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+            end_begintransfer <= 1'b1;
+         else if(uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------
+   // Beginbursttransfer Assigment
+   // -------------------
+   reg end_beginbursttransfer;
+   reg in_transfer;
+
+   always@* begin
+      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_beginbursttransfer <= 1'b0;
+         in_transfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+         if(uav_write && uav_burstcount == symbols_per_word)
+            in_transfer <=1'b0;
+         else if(uav_write)
+            in_transfer <=1'b1;
+      end
+   end
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_reset_controller.sdc b/Top/niosII/synthesis/submodules/altera_reset_controller.sdc
index 2217025..1d9ff12 100644
--- a/Top/niosII/synthesis/submodules/altera_reset_controller.sdc
+++ b/Top/niosII/synthesis/submodules/altera_reset_controller.sdc
@@ -11,20 +11,20 @@
 # agreement for further details.
 
 
-# +---------------------------------------------------
-# | Cut the async clear paths
-# +---------------------------------------------------
-set aclr_counter 0
-set clrn_counter 0
-set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
-set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
-set aclr_counter [get_collection_size $aclr_collection]
-set clrn_counter [get_collection_size $clrn_collection]
-
-if {$aclr_counter > 0} {
-    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
-}
-
-if {$clrn_counter > 0} {
-    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
-}
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set aclr_counter 0
+set clrn_counter 0
+set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+set aclr_counter [get_collection_size $aclr_collection]
+set clrn_counter [get_collection_size $clrn_collection]
+
+if {$aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+}
+
+if {$clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+}
diff --git a/Top/niosII/synthesis/submodules/altera_reset_controller.v b/Top/niosII/synthesis/submodules/altera_reset_controller.v
index 1e44e31..a7b0cc6 100644
--- a/Top/niosII/synthesis/submodules/altera_reset_controller.v
+++ b/Top/niosII/synthesis/submodules/altera_reset_controller.v
@@ -11,309 +11,309 @@
 // agreement for further details.
 
 
-// (C) 2001-2013 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// --------------------------------------
-// Reset controller
-//
-// Combines all the input resets and synchronizes
-// the result to the clk.
-// ACDS13.1 - Added reset request as part of reset sequencing
-// --------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module altera_reset_controller
-#(
-    parameter NUM_RESET_INPUTS              = 6,
-    parameter USE_RESET_REQUEST_IN0 = 0,
-    parameter USE_RESET_REQUEST_IN1 = 0,
-    parameter USE_RESET_REQUEST_IN2 = 0,
-    parameter USE_RESET_REQUEST_IN3 = 0,
-    parameter USE_RESET_REQUEST_IN4 = 0,
-    parameter USE_RESET_REQUEST_IN5 = 0,
-    parameter USE_RESET_REQUEST_IN6 = 0,
-    parameter USE_RESET_REQUEST_IN7 = 0,
-    parameter USE_RESET_REQUEST_IN8 = 0,
-    parameter USE_RESET_REQUEST_IN9 = 0,
-    parameter USE_RESET_REQUEST_IN10 = 0,
-    parameter USE_RESET_REQUEST_IN11 = 0,
-    parameter USE_RESET_REQUEST_IN12 = 0,
-    parameter USE_RESET_REQUEST_IN13 = 0,
-    parameter USE_RESET_REQUEST_IN14 = 0,
-    parameter USE_RESET_REQUEST_IN15 = 0,
-    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
-    parameter SYNC_DEPTH                    = 2,
-    parameter RESET_REQUEST_PRESENT         = 0,
-    parameter RESET_REQ_WAIT_TIME           = 3,
-    parameter MIN_RST_ASSERTION_TIME        = 11,
-    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
-    parameter ADAPT_RESET_REQUEST          = 0
-)
-(
-    // --------------------------------------
-    // We support up to 16 reset inputs, for now
-    // --------------------------------------
-    input reset_in0,
-    input reset_in1,
-    input reset_in2,
-    input reset_in3,
-    input reset_in4,
-    input reset_in5,
-    input reset_in6,
-    input reset_in7,
-    input reset_in8,
-    input reset_in9,
-    input reset_in10,
-    input reset_in11,
-    input reset_in12,
-    input reset_in13,
-    input reset_in14,
-    input reset_in15,
-    input reset_req_in0,
-    input reset_req_in1,
-    input reset_req_in2,
-    input reset_req_in3,
-    input reset_req_in4,
-    input reset_req_in5,
-    input reset_req_in6,
-    input reset_req_in7,
-    input reset_req_in8,
-    input reset_req_in9,
-    input reset_req_in10,
-    input reset_req_in11,
-    input reset_req_in12,
-    input reset_req_in13,
-    input reset_req_in14,
-    input reset_req_in15,
-
-
-    input  clk,
-    output reg reset_out,
-    output reg reset_req
-);
-
-   // Always use async reset synchronizer if reset_req is used
-   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
-
-   // --------------------------------------
-   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
-   // --------------------------------------
-   localparam MIN_METASTABLE = 3;
-   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
-
-   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
-
-   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
-                                            MIN_RST_ASSERTION_TIME + 1 :
-                                        (
-                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
-                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
-                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
-                                        );
-
-   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
-   // --------------------------------------
-
-   wire merged_reset;
-   wire merged_reset_req_in;
-   wire reset_out_pre;
-   wire reset_req_pre;
-
-   // Registers and Interconnect
-   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
-   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
-   reg                                          r_sync_rst;
-   reg                                          r_early_rst;
-
-    // --------------------------------------
-    // "Or" all the input resets together
-    // --------------------------------------
-    assign merged_reset = (  
-                              reset_in0 | 
-                              reset_in1 | 
-                              reset_in2 | 
-                              reset_in3 | 
-                              reset_in4 | 
-                              reset_in5 | 
-                              reset_in6 | 
-                              reset_in7 | 
-                              reset_in8 | 
-                              reset_in9 | 
-                              reset_in10 | 
-                              reset_in11 | 
-                              reset_in12 | 
-                              reset_in13 | 
-                              reset_in14 | 
-                              reset_in15
-                          );
-
-    assign merged_reset_req_in = (
-                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
-                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
-                            );
-
-
-    // --------------------------------------
-    // And if required, synchronize it to the required clock domain,
-    // with the correct synchronization type
-    // --------------------------------------
-    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
-
-        assign reset_out_pre = merged_reset;
-        assign reset_req_pre = merged_reset_req_in;
-
-    end else begin
-
-        altera_reset_synchronizer
-        #(
-            .DEPTH      (SYNC_DEPTH),
-            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
-        )
-        alt_rst_sync_uq1
-        (
-            .clk        (clk),
-            .reset_in   (merged_reset),
-            .reset_out  (reset_out_pre)
-        );
-
-        altera_reset_synchronizer
-        #(
-            .DEPTH      (SYNC_DEPTH),
-            .ASYNC_RESET(0)
-        )
-        alt_rst_req_sync_uq1
-        (
-            .clk        (clk),
-            .reset_in   (merged_reset_req_in),
-            .reset_out  (reset_req_pre)
-        );
-
-    end
-    endgenerate
-
-    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
-                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
-        always @* begin
-            reset_out = reset_out_pre;
-            reset_req = reset_req_pre;
-        end
-    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
-
-        wire reset_out_pre2;
-
-        altera_reset_synchronizer
-        #(
-            .DEPTH      (SYNC_DEPTH+1),
-            .ASYNC_RESET(0)
-        )
-        alt_rst_sync_uq2
-        (
-            .clk        (clk),
-            .reset_in   (reset_out_pre),
-            .reset_out  (reset_out_pre2)
-        );
-
-        always @* begin
-            reset_out = reset_out_pre2;
-            reset_req = reset_req_pre;
-        end
-
-    end
-    else begin
-
-    // 3-FF Metastability Synchronizer
-    initial
-    begin
-        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
-    end
-
-    always @(posedge clk)
-    begin
-        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
-            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
-    end
-
-    // Synchronous reset pipe
-    initial
-    begin
-        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
-    end
-
-    always @(posedge clk)
-    begin
-        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
-        begin
-            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
-    end
-    else
-    begin
-        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
-    end
-    end
-
-    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
-    // matches the early input.
-
-    always @(posedge clk)
-    begin
-        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
-            3'b000:   r_sync_rst <= 1'b0; // Not reset
-            3'b001:   r_sync_rst <= 1'b0;
-            3'b010:   r_sync_rst <= 1'b0;
-            3'b011:   r_sync_rst <= 1'b1;
-            3'b100:   r_sync_rst <= 1'b1; 
-            3'b101:   r_sync_rst <= 1'b1;
-            3'b110:   r_sync_rst <= 1'b1;
-            3'b111:   r_sync_rst <= 1'b1; // In Reset
-            default:  r_sync_rst <= 1'b1;
-        endcase
-
-        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
-            2'b00:   r_early_rst <= 1'b0; // Not reset
-            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
-            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
-            2'b11:   r_early_rst <= 1'b1; // Held in reset
-            default: r_early_rst <= 1'b1;
-        endcase
-    end
-
-    always @* begin
-        reset_out = r_sync_rst;
-        reset_req = r_early_rst;
-    end
-
-    end
-    endgenerate
-
-endmodule
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// ACDS13.1 - Added reset request as part of reset sequencing
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+    parameter NUM_RESET_INPUTS              = 6,
+    parameter USE_RESET_REQUEST_IN0 = 0,
+    parameter USE_RESET_REQUEST_IN1 = 0,
+    parameter USE_RESET_REQUEST_IN2 = 0,
+    parameter USE_RESET_REQUEST_IN3 = 0,
+    parameter USE_RESET_REQUEST_IN4 = 0,
+    parameter USE_RESET_REQUEST_IN5 = 0,
+    parameter USE_RESET_REQUEST_IN6 = 0,
+    parameter USE_RESET_REQUEST_IN7 = 0,
+    parameter USE_RESET_REQUEST_IN8 = 0,
+    parameter USE_RESET_REQUEST_IN9 = 0,
+    parameter USE_RESET_REQUEST_IN10 = 0,
+    parameter USE_RESET_REQUEST_IN11 = 0,
+    parameter USE_RESET_REQUEST_IN12 = 0,
+    parameter USE_RESET_REQUEST_IN13 = 0,
+    parameter USE_RESET_REQUEST_IN14 = 0,
+    parameter USE_RESET_REQUEST_IN15 = 0,
+    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
+    parameter SYNC_DEPTH                    = 2,
+    parameter RESET_REQUEST_PRESENT         = 0,
+    parameter RESET_REQ_WAIT_TIME           = 3,
+    parameter MIN_RST_ASSERTION_TIME        = 11,
+    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
+    parameter ADAPT_RESET_REQUEST          = 0
+)
+(
+    // --------------------------------------
+    // We support up to 16 reset inputs, for now
+    // --------------------------------------
+    input reset_in0,
+    input reset_in1,
+    input reset_in2,
+    input reset_in3,
+    input reset_in4,
+    input reset_in5,
+    input reset_in6,
+    input reset_in7,
+    input reset_in8,
+    input reset_in9,
+    input reset_in10,
+    input reset_in11,
+    input reset_in12,
+    input reset_in13,
+    input reset_in14,
+    input reset_in15,
+    input reset_req_in0,
+    input reset_req_in1,
+    input reset_req_in2,
+    input reset_req_in3,
+    input reset_req_in4,
+    input reset_req_in5,
+    input reset_req_in6,
+    input reset_req_in7,
+    input reset_req_in8,
+    input reset_req_in9,
+    input reset_req_in10,
+    input reset_req_in11,
+    input reset_req_in12,
+    input reset_req_in13,
+    input reset_req_in14,
+    input reset_req_in15,
+
+
+    input  clk,
+    output reg reset_out,
+    output reg reset_req
+);
+
+   // Always use async reset synchronizer if reset_req is used
+   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+   // --------------------------------------
+   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
+   // --------------------------------------
+   localparam MIN_METASTABLE = 3;
+   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
+
+   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
+
+   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
+                                            MIN_RST_ASSERTION_TIME + 1 :
+                                        (
+                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
+                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
+                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
+                                        );
+
+   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
+   // --------------------------------------
+
+   wire merged_reset;
+   wire merged_reset_req_in;
+   wire reset_out_pre;
+   wire reset_req_pre;
+
+   // Registers and Interconnect
+   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
+   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
+   reg                                          r_sync_rst;
+   reg                                          r_early_rst;
+
+    // --------------------------------------
+    // "Or" all the input resets together
+    // --------------------------------------
+    assign merged_reset = (  
+                              reset_in0 | 
+                              reset_in1 | 
+                              reset_in2 | 
+                              reset_in3 | 
+                              reset_in4 | 
+                              reset_in5 | 
+                              reset_in6 | 
+                              reset_in7 | 
+                              reset_in8 | 
+                              reset_in9 | 
+                              reset_in10 | 
+                              reset_in11 | 
+                              reset_in12 | 
+                              reset_in13 | 
+                              reset_in14 | 
+                              reset_in15
+                          );
+
+    assign merged_reset_req_in = (
+                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
+                            );
+
+
+    // --------------------------------------
+    // And if required, synchronize it to the required clock domain,
+    // with the correct synchronization type
+    // --------------------------------------
+    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
+
+        assign reset_out_pre = merged_reset;
+        assign reset_req_pre = merged_reset_req_in;
+
+    end else begin
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
+        )
+        alt_rst_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset),
+            .reset_out  (reset_out_pre)
+        );
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_req_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset_req_in),
+            .reset_out  (reset_req_pre)
+        );
+
+    end
+    endgenerate
+
+    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
+                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
+        always @* begin
+            reset_out = reset_out_pre;
+            reset_req = reset_req_pre;
+        end
+    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
+
+        wire reset_out_pre2;
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH+1),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_sync_uq2
+        (
+            .clk        (clk),
+            .reset_in   (reset_out_pre),
+            .reset_out  (reset_out_pre2)
+        );
+
+        always @* begin
+            reset_out = reset_out_pre2;
+            reset_req = reset_req_pre;
+        end
+
+    end
+    else begin
+
+    // 3-FF Metastability Synchronizer
+    initial
+    begin
+        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
+            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
+    end
+
+    // Synchronous reset pipe
+    initial
+    begin
+        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
+        begin
+            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+    else
+    begin
+        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
+    end
+    end
+
+    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
+    // matches the early input.
+
+    always @(posedge clk)
+    begin
+        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
+            3'b000:   r_sync_rst <= 1'b0; // Not reset
+            3'b001:   r_sync_rst <= 1'b0;
+            3'b010:   r_sync_rst <= 1'b0;
+            3'b011:   r_sync_rst <= 1'b1;
+            3'b100:   r_sync_rst <= 1'b1; 
+            3'b101:   r_sync_rst <= 1'b1;
+            3'b110:   r_sync_rst <= 1'b1;
+            3'b111:   r_sync_rst <= 1'b1; // In Reset
+            default:  r_sync_rst <= 1'b1;
+        endcase
+
+        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
+            2'b00:   r_early_rst <= 1'b0; // Not reset
+            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
+            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
+            2'b11:   r_early_rst <= 1'b1; // Held in reset
+            default: r_early_rst <= 1'b1;
+        endcase
+    end
+
+    always @* begin
+        reset_out = r_sync_rst;
+        reset_req = r_early_rst;
+    end
+
+    end
+    endgenerate
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v b/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v
index 5277a4d..4176d12 100644
--- a/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v
+++ b/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v
@@ -11,77 +11,77 @@
 // agreement for further details.
 
 
-// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// -----------------------------------------------
-// Reset Synchronizer
-// -----------------------------------------------
-`timescale 1 ns / 1 ns
-
-module altera_reset_synchronizer
-#(
-    parameter ASYNC_RESET = 1,
-    parameter DEPTH       = 2
-)
-(
-    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
-
-    input   clk,
-    output  reset_out
-);
-
-    // -----------------------------------------------
-    // Synchronizer register chain. We cannot reuse the
-    // standard synchronizer in this implementation 
-    // because our timing constraints are different.
-    //
-    // Instead of cutting the timing path to the d-input 
-    // on the first flop we need to cut the aclr input.
-    // 
-    // We omit the "preserve" attribute on the final
-    // output register, so that the synthesis tool can
-    // duplicate it where needed.
-    // -----------------------------------------------
-    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
-    reg altera_reset_synchronizer_int_chain_out;
-
-    generate if (ASYNC_RESET) begin
-
-        // -----------------------------------------------
-        // Assert asynchronously, deassert synchronously.
-        // -----------------------------------------------
-        always @(posedge clk or posedge reset_in) begin
-            if (reset_in) begin
-                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
-                altera_reset_synchronizer_int_chain_out <= 1'b1;
-            end
-            else begin
-                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
-                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
-                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
-            end
-        end
-
-        assign reset_out = altera_reset_synchronizer_int_chain_out;
-     
-    end else begin
-
-        // -----------------------------------------------
-        // Assert synchronously, deassert synchronously.
-        // -----------------------------------------------
-        always @(posedge clk) begin
-            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
-            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
-            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
-        end
-
-        assign reset_out = altera_reset_synchronizer_int_chain_out;
- 
-    end
-    endgenerate
-
-endmodule
-
+// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+    reg altera_reset_synchronizer_int_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+                altera_reset_synchronizer_int_chain_out <= 1'b1;
+            end
+            else begin
+                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+            end
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
+
diff --git a/Top/niosII/synthesis/submodules/dec.sv b/Top/niosII/synthesis/submodules/dec.sv
index c80033a..6b92f6b 100644
--- a/Top/niosII/synthesis/submodules/dec.sv
+++ b/Top/niosII/synthesis/submodules/dec.sv
@@ -93,19 +93,19 @@ module dec
                   RED: begin
                       colors <= 3'b100;
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= YELLOW;
                           greenSaved <= divisor;
                       end
                   end
                   YELLOW: begin
                       colors <= 3'b010;
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= BLINK;
                       end
                   end
                   BLINK: begin
                       if (enacnt) begin
-                          state <= state + 1'b1;
+                          state <= GREEN;
                       end
                       if (greenSaved[0] == 0) begin
                           colors <= 3'b011;
@@ -118,9 +118,6 @@ module dec
                       end
                   end
                   GREEN: begin
-                      if (enacnt) begin
-                          state <= state + 1'b1;
-                      end
                       colors <= 3'b001;
                   end
                   default: colors <= 3'b100;
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif
index 644013a..7969f10 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif
@@ -1,42 +1,42 @@
-WIDTH=32;
-DEPTH=32;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-
-00 : deadbeef;
-01 : deadbeef;
-02 : deadbeef;
-03 : deadbeef;
-04 : deadbeef;
-05 : deadbeef;
-06 : deadbeef;
-07 : deadbeef;
-08 : deadbeef;
-09 : deadbeef;
-0a : deadbeef;
-0b : deadbeef;
-0c : deadbeef;
-0d : deadbeef;
-0e : deadbeef;
-0f : deadbeef;
-10 : deadbeef;
-11 : deadbeef;
-12 : deadbeef;
-13 : deadbeef;
-14 : deadbeef;
-15 : deadbeef;
-16 : deadbeef;
-17 : deadbeef;
-18 : deadbeef;
-19 : deadbeef;
-1a : deadbeef;
-1b : deadbeef;
-1c : deadbeef;
-1d : deadbeef;
-1e : deadbeef;
-1f : deadbeef;
-
-END;
+WIDTH=32;
+DEPTH=32;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : deadbeef;
+01 : deadbeef;
+02 : deadbeef;
+03 : deadbeef;
+04 : deadbeef;
+05 : deadbeef;
+06 : deadbeef;
+07 : deadbeef;
+08 : deadbeef;
+09 : deadbeef;
+0a : deadbeef;
+0b : deadbeef;
+0c : deadbeef;
+0d : deadbeef;
+0e : deadbeef;
+0f : deadbeef;
+10 : deadbeef;
+11 : deadbeef;
+12 : deadbeef;
+13 : deadbeef;
+14 : deadbeef;
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+END;
diff --git a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif
index 644013a..7969f10 100644
--- a/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif
+++ b/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif
@@ -1,42 +1,42 @@
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+END;
diff --git a/Top/niosII/synthesis/submodules/niosII_mem.hex b/Top/niosII/synthesis/submodules/niosII_mem.hex
index 19e432c..627a9c9 100644
--- a/Top/niosII/synthesis/submodules/niosII_mem.hex
+++ b/Top/niosII/synthesis/submodules/niosII_mem.hex
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diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v
index e548fe7..2c53838 100644
--- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v
+++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v
@@ -1,12 +1,12 @@
-// niosII_mm_interconnect_0_avalon_st_adapter.v
-
+// niosII_mm_interconnect_0_avalon_st_adapter.v
+
 // This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
 // will probably be lost.
 // 
-// Generated using ACDS version 18.1 625
-
+// Generated using ACDS version 18.1 625
+
 `timescale 1 ps / 1 ps
-module niosII_mm_interconnect_0_avalon_st_adapter #(
+module niosII_mm_interconnect_0_avalon_st_adapter #(
 		parameter inBitsPerSymbol = 34,
 		parameter inUsePackets    = 0,
 		parameter inDataWidth     = 34,
@@ -23,7 +23,7 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
 		parameter outUseValid     = 1,
 		parameter outUseReady     = 1,
 		parameter outReadyLatency = 0
-	) (
+	) (
 		input  wire        in_clk_0_clk,   // in_clk_0.clk
 		input  wire        in_rst_0_reset, // in_rst_0.reset
 		input  wire [33:0] in_0_data,      //     in_0.data
@@ -33,14 +33,14 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
 		output wire        out_0_valid,    //         .valid
 		input  wire        out_0_ready,    //         .ready
 		output wire [0:0]  out_0_error     //         .error
-	);
-
-	generate
-		// If any of the display statements (or deliberately broken
-		// instantiations) within this generate block triggers then this module
-		// has been instantiated this module with a set of parameters different
-		// from those it was generated for.  This will usually result in a
-		// non-functioning system.
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
 		if (inBitsPerSymbol != 34)
 		begin
 			initial begin
@@ -185,8 +185,8 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
 			instantiated_with_wrong_parameters_error_see_comment_above
 					outreadylatency_check ( .error(1'b1) );
 		end
-	endgenerate
-
+	endgenerate
+
 	niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
 		.clk       (in_clk_0_clk),    //   clk.clk
 		.reset_n   (~in_rst_0_reset), // reset.reset_n
@@ -197,6 +197,6 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
 		.out_valid (out_0_valid),     //      .valid
 		.out_ready (out_0_ready),     //      .ready
 		.out_error (out_0_error)      //      .error
-	);
-
-endmodule
+	);
+
+endmodule
diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv
index 0f2308d..5a45b23 100644
--- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv
+++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv
@@ -1,224 +1,224 @@
-// (C) 2001-2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files from any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License Subscription 
-// Agreement, Intel FPGA IP License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Intel and sold by 
-// Intel or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// -------------------------------------------------------
-// Merlin Router
-//
-// Asserts the appropriate one-hot encoded channel based on 
-// either (a) the address or (b) the dest id. The DECODER_TYPE
-// parameter controls this behaviour. 0 means address decoder,
-// 1 means dest id decoder.
-//
-// In the case of (a), it also sets the destination id.
-// -------------------------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module niosII_mm_interconnect_0_router_004_default_decode
-  #(
-     parameter DEFAULT_CHANNEL = 0,
-               DEFAULT_WR_CHANNEL = -1,
-               DEFAULT_RD_CHANNEL = -1,
-               DEFAULT_DESTID = 0 
-   )
-  (output [80 - 78 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
-  );
-
-  assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
-
-  generate
-    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
-      assign default_src_channel = '0;
-    end
-    else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
-    end
-  endgenerate
-
-  generate
-    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
-      assign default_wr_channel = '0;
-      assign default_rd_channel = '0;
-    end
-    else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
-    end
-  endgenerate
-
-endmodule
-
-
-module niosII_mm_interconnect_0_router_004
-(
-    // -------------------
-    // Clock & Reset
-    // -------------------
-    input clk,
-    input reset,
-
-    // -------------------
-    // Command Sink (Input)
-    // -------------------
-    input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
-    input                       sink_startofpacket,
-    input                       sink_endofpacket,
-    output                      sink_ready,
-
-    // -------------------
-    // Command Source (Output)
-    // -------------------
-    output                          src_valid,
-    output reg [94-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
-    output                          src_startofpacket,
-    output                          src_endofpacket,
-    input                           src_ready
-);
-
-    // -------------------------------------------------------
-    // Local parameters and variables
-    // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
-    localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
-    localparam PKT_DEST_ID_L = 78;
-    localparam PKT_PROTECTION_H = 84;
-    localparam PKT_PROTECTION_L = 82;
-    localparam ST_DATA_W = 94;
-    localparam ST_CHANNEL_W = 7;
-    localparam DECODER_TYPE = 1;
-
-    localparam PKT_TRANS_WRITE = 56;
-    localparam PKT_TRANS_READ  = 57;
-
-    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
-    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
-
-
-
-    // -------------------------------------------------------
-    // Figure out the number of bits to mask off for each slave span
-    // during address decoding
-    // -------------------------------------------------------
-    // -------------------------------------------------------
-    // Work out which address bits are significant based on the
-    // address range of the slaves. If the required width is too
-    // large or too small, we use the address field width instead.
-    // -------------------------------------------------------
-    localparam ADDR_RANGE = 64'h0;
-    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
-    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
-                                  (RANGE_ADDR_WIDTH == 0) ?
-                                        PKT_ADDR_H :
-                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
-
-    localparam RG = RANGE_ADDR_WIDTH;
-    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
-
-    reg [PKT_DEST_ID_W-1 : 0] destid;
-
-    // -------------------------------------------------------
-    // Pass almost everything through, untouched
-    // -------------------------------------------------------
-    assign sink_ready        = src_ready;
-    assign src_valid         = sink_valid;
-    assign src_startofpacket = sink_startofpacket;
-    assign src_endofpacket   = sink_endofpacket;
-    wire [7-1 : 0] default_src_channel;
-
-
-
-
-    // -------------------------------------------------------
-    // Write and read transaction signals
-    // -------------------------------------------------------
-    wire read_transaction;
-    assign read_transaction  = sink_data[PKT_TRANS_READ];
-
-
-    niosII_mm_interconnect_0_router_004_default_decode the_default_decode(
-      .default_destination_id (),
-      .default_wr_channel   (),
-      .default_rd_channel   (),
-      .default_src_channel  (default_src_channel)
-    );
-
-    always @* begin
-        src_data    = sink_data;
-        src_channel = default_src_channel;
-
-        // --------------------------------------------------
-        // DestinationID Decoder
-        // Sets the channel based on the destination ID.
-        // --------------------------------------------------
-        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
-
-
-
-        if (destid == 0 ) begin
-            src_channel = 7'b01;
-        end
-
-        if (destid == 1  && read_transaction) begin
-            src_channel = 7'b10;
-        end
-
-
-end
-
-
-    // --------------------------------------------------
-    // Ceil(log2()) function
-    // --------------------------------------------------
-    function integer log2ceil;
-        input reg[65:0] val;
-        reg [65:0] i;
-
-        begin
-            i = 1;
-            log2ceil = 0;
-
-            while (i < val) begin
-                log2ceil = log2ceil + 1;
-                i = i << 1;
-            end
-        end
-    endfunction
-
-endmodule
-
-
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module niosII_mm_interconnect_0_router_004_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [80 - 78 : 0] default_destination_id,
+   output [7-1 : 0] default_wr_channel,
+   output [7-1 : 0] default_rd_channel,
+   output [7-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[80 - 78 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module niosII_mm_interconnect_0_router_004
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [94-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [94-1    : 0] src_data,
+    output reg [7-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_L = 82;
+    localparam ST_DATA_W = 94;
+    localparam ST_CHANNEL_W = 7;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_READ  = 57;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [7-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    niosII_mm_interconnect_0_router_004_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 7'b01;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 7'b10;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv
index ee03f6e..81d647f 100644
--- a/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv
+++ b/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv
@@ -1,220 +1,220 @@
-// (C) 2001-2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files from any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License Subscription 
-// Agreement, Intel FPGA IP License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Intel and sold by 
-// Intel or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
-// $Revision: #1 $
-// $Date: 2018/07/18 $
-// $Author: psgswbuild $
-
-// -------------------------------------------------------
-// Merlin Router
-//
-// Asserts the appropriate one-hot encoded channel based on 
-// either (a) the address or (b) the dest id. The DECODER_TYPE
-// parameter controls this behaviour. 0 means address decoder,
-// 1 means dest id decoder.
-//
-// In the case of (a), it also sets the destination id.
-// -------------------------------------------------------
-
-`timescale 1 ns / 1 ns
-
-module niosII_mm_interconnect_0_router_008_default_decode
-  #(
-     parameter DEFAULT_CHANNEL = 0,
-               DEFAULT_WR_CHANNEL = -1,
-               DEFAULT_RD_CHANNEL = -1,
-               DEFAULT_DESTID = 1 
-   )
-  (output [80 - 78 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
-  );
-
-  assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
-
-  generate
-    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
-      assign default_src_channel = '0;
-    end
-    else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
-    end
-  endgenerate
-
-  generate
-    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
-      assign default_wr_channel = '0;
-      assign default_rd_channel = '0;
-    end
-    else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
-    end
-  endgenerate
-
-endmodule
-
-
-module niosII_mm_interconnect_0_router_008
-(
-    // -------------------
-    // Clock & Reset
-    // -------------------
-    input clk,
-    input reset,
-
-    // -------------------
-    // Command Sink (Input)
-    // -------------------
-    input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
-    input                       sink_startofpacket,
-    input                       sink_endofpacket,
-    output                      sink_ready,
-
-    // -------------------
-    // Command Source (Output)
-    // -------------------
-    output                          src_valid,
-    output reg [94-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
-    output                          src_startofpacket,
-    output                          src_endofpacket,
-    input                           src_ready
-);
-
-    // -------------------------------------------------------
-    // Local parameters and variables
-    // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
-    localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
-    localparam PKT_DEST_ID_L = 78;
-    localparam PKT_PROTECTION_H = 84;
-    localparam PKT_PROTECTION_L = 82;
-    localparam ST_DATA_W = 94;
-    localparam ST_CHANNEL_W = 7;
-    localparam DECODER_TYPE = 1;
-
-    localparam PKT_TRANS_WRITE = 56;
-    localparam PKT_TRANS_READ  = 57;
-
-    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
-    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
-
-
-
-    // -------------------------------------------------------
-    // Figure out the number of bits to mask off for each slave span
-    // during address decoding
-    // -------------------------------------------------------
-    // -------------------------------------------------------
-    // Work out which address bits are significant based on the
-    // address range of the slaves. If the required width is too
-    // large or too small, we use the address field width instead.
-    // -------------------------------------------------------
-    localparam ADDR_RANGE = 64'h0;
-    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
-    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
-                                  (RANGE_ADDR_WIDTH == 0) ?
-                                        PKT_ADDR_H :
-                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
-
-    localparam RG = RANGE_ADDR_WIDTH;
-    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
-
-    reg [PKT_DEST_ID_W-1 : 0] destid;
-
-    // -------------------------------------------------------
-    // Pass almost everything through, untouched
-    // -------------------------------------------------------
-    assign sink_ready        = src_ready;
-    assign src_valid         = sink_valid;
-    assign src_startofpacket = sink_startofpacket;
-    assign src_endofpacket   = sink_endofpacket;
-    wire [7-1 : 0] default_src_channel;
-
-
-
-
-    // -------------------------------------------------------
-    // Write and read transaction signals
-    // -------------------------------------------------------
-    wire read_transaction;
-    assign read_transaction  = sink_data[PKT_TRANS_READ];
-
-
-    niosII_mm_interconnect_0_router_008_default_decode the_default_decode(
-      .default_destination_id (),
-      .default_wr_channel   (),
-      .default_rd_channel   (),
-      .default_src_channel  (default_src_channel)
-    );
-
-    always @* begin
-        src_data    = sink_data;
-        src_channel = default_src_channel;
-
-        // --------------------------------------------------
-        // DestinationID Decoder
-        // Sets the channel based on the destination ID.
-        // --------------------------------------------------
-        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
-
-
-
-        if (destid == 1  && read_transaction) begin
-            src_channel = 7'b1;
-        end
-
-
-end
-
-
-    // --------------------------------------------------
-    // Ceil(log2()) function
-    // --------------------------------------------------
-    function integer log2ceil;
-        input reg[65:0] val;
-        reg [65:0] i;
-
-        begin
-            i = 1;
-            log2ceil = 0;
-
-            while (i < val) begin
-                log2ceil = log2ceil + 1;
-                i = i << 1;
-            end
-        end
-    endfunction
-
-endmodule
-
-
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/07/18 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module niosII_mm_interconnect_0_router_008_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 1 
+   )
+  (output [80 - 78 : 0] default_destination_id,
+   output [7-1 : 0] default_wr_channel,
+   output [7-1 : 0] default_rd_channel,
+   output [7-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[80 - 78 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module niosII_mm_interconnect_0_router_008
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [94-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [94-1    : 0] src_data,
+    output reg [7-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_L = 82;
+    localparam ST_DATA_W = 94;
+    localparam ST_CHANNEL_W = 7;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_READ  = 57;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [7-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    niosII_mm_interconnect_0_router_008_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 7'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/Top/niosII/synthesis/submodules/periodram.v b/Top/niosII/synthesis/submodules/periodram.v
index f7f7363..5587332 100644
--- a/Top/niosII/synthesis/submodules/periodram.v
+++ b/Top/niosII/synthesis/submodules/periodram.v
@@ -1,222 +1,222 @@
-// megafunction wizard: %RAM: 2-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram 
-
-// ============================================================
-// File Name: periodram.v
-// Megafunction Name(s):
-// 			altsyncram
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2018  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module periodram (
-	clock,
-	data,
-	rdaddress,
-	wraddress,
-	wren,
-	q);
-
-	input	  clock;
-	input	[31:0]  data;
-	input	[3:0]  rdaddress;
-	input	[3:0]  wraddress;
-	input	  wren;
-	output	[31:0]  q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri1	  clock;
-	tri0	  wren;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [31:0] sub_wire0;
-	wire [31:0] q = sub_wire0[31:0];
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.address_b (rdaddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.q_b (sub_wire0),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({32{1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-`ifdef NO_PLI
-		altsyncram_component.init_file = "periodram.rif"
-`else
-		altsyncram_component.init_file = "periodram.hex"
-`endif
-,
-		altsyncram_component.init_file_layout = "PORT_B",
-		altsyncram_component.intended_device_family = "Cyclone IV E",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 16,
-		altsyncram_component.numwords_b = 16,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = 4,
-		altsyncram_component.widthad_b = 4,
-		altsyncram_component.width_a = 32,
-		altsyncram_component.width_b = 32,
-		altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGrren NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
-// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
-// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
-// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: periodram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2018  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module periodram (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[3:0]  rdaddress;
+	input	[3:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "periodram.rif"
+`else
+		altsyncram_component.init_file = "periodram.hex"
+`endif
+,
+		altsyncram_component.init_file_layout = "PORT_B",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 16,
+		altsyncram_component.numwords_b = 16,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 4,
+		altsyncram_component.widthad_b = 4,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
+// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
+// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/Top/niosII/testbench/niosII_tb.qsys b/Top/niosII/testbench/niosII_tb.qsys
index be0fc93..0813eaf 100644
--- a/Top/niosII/testbench/niosII_tb.qsys
+++ b/Top/niosII/testbench/niosII_tb.qsys
@@ -7,33 +7,33 @@
    description=""
    tags=""
    categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element niosII_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element niosII_inst_clk_bfm
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element niosII_inst_reset_bfm
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-}
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element niosII_inst
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element niosII_inst_clk_bfm
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element niosII_inst_reset_bfm
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+}
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
  <parameter name="device" value="EP4CE115F29C7" />
diff --git a/Top/semafor.qpf b/Top/semafor.qpf
index 7a87269..d8727c9 100644
--- a/Top/semafor.qpf
+++ b/Top/semafor.qpf
@@ -1,30 +1,30 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors.  Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 16:34:55  October 18, 2022
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "18.1"
-DATE = "16:34:55  October 18, 2022"
-
-# Revisions
-
-PROJECT_REVISION = "semafor"
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 16:34:55  October 18, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "16:34:55  October 18, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "semafor"
diff --git a/Top/semafor.qsf b/Top/semafor.qsf
index 49362a8..867ec06 100644
--- a/Top/semafor.qsf
+++ b/Top/semafor.qsf
@@ -1,47 +1,47 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors.  Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 16:34:55  October 18, 2022
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		semafor_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 16:34:55  October 18, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		semafor_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE115F29C7
-set_global_assignment -name TOP_LEVEL_ENTITY niosII
+set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55  OCTOBER 18, 2022"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -52,9 +52,16 @@ set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_Y2 -to clk
+set_location_assignment PIN_M23 -to train
+set_location_assignment PIN_G19 -to yellow
+set_location_assignment PIN_F19 -to red
+set_location_assignment PIN_G21 -to green
+
+set_global_assignment -name SYSTEMVERILOG_FILE top.sv
+set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SOURCE_FILE niosII/niosII.cmp
-set_global_assignment -name QSYS_FILE niosII.qsys
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Top/semafor.qws b/Top/semafor.qws
deleted file mode 100644
index 045a66f..0000000
Binary files a/Top/semafor.qws and /dev/null differ
diff --git a/Top/semafor_assignment_defaults.qdf b/Top/semafor_assignment_defaults.qdf
new file mode 100644
index 0000000..f57442e
--- /dev/null
+++ b/Top/semafor_assignment_defaults.qdf
@@ -0,0 +1,808 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 11:08:42  January 24, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/Top/software/semafor/.cproject b/Top/software/semafor/.cproject
index 7d41614..8dab44a 100644
--- a/Top/software/semafor/.cproject
+++ b/Top/software/semafor/.cproject
@@ -1,83 +1,83 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
-			<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings"/>
-		</buildSystem>
-		<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
-					<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672." name="/" resourcePath="">
-						<toolChain id="altera.nios2.mingw.gcc4.1451739338" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
-							<targetPlatform id="altera.nios2.mingw.gcc4.1894897402" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
-							<builder buildPath="${workspace_loc://semafor}" id="altera.tool.gnu.builder.mingw.1910544022" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
-							<tool id="altera.tool.gnu.c.compiler.mingw.2112423510" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.181439709" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
-							</tool>
-							<tool id="altera.tool.gnu.cpp.compiler.mingw.1092618596" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
-							</tool>
-							<tool id="altera.tool.gnu.archiver.mingw.1773720286" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
-							<tool id="altera.tool.gnu.c.linker.mingw.544112231" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
-							<tool id="altera.tool.gnu.assembler.mingw.273557530" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.327317275" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
-							</tool>
-						</toolChain>
-					</folderInfo>
-				</configuration>
-			</storageModule>
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="semafor.null.1915366667" name="semafor"/>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="scannerConfiguration">
-		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.c.compiler.mingw.2112423510;cdt.managedbuild.tool.gnu.c.compiler.input.181439709">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.cpp.compiler.mingw.1092618596;cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
-		<buildTargets>
-			<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
-				<buildCommand>make</buildCommand>
-				<buildArguments/>
-				<buildTarget>mem_init_install</buildTarget>
-				<stopOnError>true</stopOnError>
-				<useDefaultCommand>false</useDefaultCommand>
-				<runAllBuilders>false</runAllBuilders>
-			</target>
-			<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
-				<buildCommand>make</buildCommand>
-				<buildArguments/>
-				<buildTarget>mem_init_generate</buildTarget>
-				<stopOnError>true</stopOnError>
-				<useDefaultCommand>false</useDefaultCommand>
-				<runAllBuilders>false</runAllBuilders>
-			</target>
-			<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
-				<buildCommand>make</buildCommand>
-				<buildArguments/>
-				<buildTarget>help</buildTarget>
-				<stopOnError>true</stopOnError>
-				<useDefaultCommand>false</useDefaultCommand>
-				<runAllBuilders>false</runAllBuilders>
-			</target>
-		</buildTargets>
-	</storageModule>
-</cproject>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
+			<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings"/>
+		</buildSystem>
+		<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672." name="/" resourcePath="">
+						<toolChain id="altera.nios2.mingw.gcc4.1451739338" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+							<targetPlatform id="altera.nios2.mingw.gcc4.1894897402" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+							<builder buildPath="${workspace_loc://semafor}" id="altera.tool.gnu.builder.mingw.1910544022" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+							<tool id="altera.tool.gnu.c.compiler.mingw.2112423510" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.181439709" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.cpp.compiler.mingw.1092618596" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.archiver.mingw.1773720286" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+							<tool id="altera.tool.gnu.c.linker.mingw.544112231" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+							<tool id="altera.tool.gnu.assembler.mingw.273557530" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.327317275" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="semafor.null.1915366667" name="semafor"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.c.compiler.mingw.2112423510;cdt.managedbuild.tool.gnu.c.compiler.input.181439709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.cpp.compiler.mingw.1092618596;cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+		<buildTargets>
+			<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>mem_init_install</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+			<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>mem_init_generate</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+			<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>help</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+		</buildTargets>
+	</storageModule>
+</cproject>
diff --git a/Top/software/semafor/.project b/Top/software/semafor/.project
index e855644..b8d97e7 100644
--- a/Top/software/semafor/.project
+++ b/Top/software/semafor/.project
@@ -1,40 +1,40 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>semafor</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>com.altera.sbtgui.project.makefileBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>com.altera.sbtgui.project.makefileBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.cdt.core.ccnature</nature>
-		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
-		<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
-		<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
-	</natures>
-</projectDescription>
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>semafor</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+	</natures>
+</projectDescription>
diff --git a/Top/software/semafor/.settings/language.settings.xml b/Top/software/semafor/.settings/language.settings.xml
index f9a6a5e..a4154b5 100644
--- a/Top/software/semafor/.settings/language.settings.xml
+++ b/Top/software/semafor/.settings/language.settings.xml
@@ -2,7 +2,7 @@
 <project>
 	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1220411458136844691" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
diff --git a/Top/software/semafor/Makefile b/Top/software/semafor/Makefile
index c1f1602..17e7010 100644
--- a/Top/software/semafor/Makefile
+++ b/Top/software/semafor/Makefile
@@ -1,1082 +1,1082 @@
-#------------------------------------------------------------------------------
-#              VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS
-#------------------------------------------------------------------------------
-
-# List of include directories for -I compiler option (-I added when used).
-# Includes the BSP.
-ALT_INCLUDE_DIRS :=
-
-# List of library directories for -L linker option (-L added when used).
-# Includes the BSP.
-ALT_LIBRARY_DIRS :=
-
-# List of library names for -l linker option (-l added when used).
-# Includes the BSP.
-ALT_LIBRARY_NAMES :=
-
-# List of library names for -msys-lib linker option (-msys-lib added when used).
-# These are libraries that might be located in the BSP and depend on the BSP
-# library, or vice versa
-ALT_BSP_DEP_LIBRARY_NAMES :=
-
-# List of dependencies for the linker.  This is usually the full pathname
-# of each library (*.a) file.
-# Includes the BSP.
-ALT_LDDEPS :=
-
-# List of root library directories that support running make to build them.
-# Includes the BSP and any ALT libraries.
-MAKEABLE_LIBRARY_ROOT_DIRS :=
-
-# Generic flags passed to the compiler for different types of input files.
-ALT_CFLAGS :=
-ALT_CXXFLAGS :=
-ALT_CPPFLAGS :=
-ALT_ASFLAGS :=
-ALT_LDFLAGS :=
-
-
-#------------------------------------------------------------------------------
-#                         The adjust-path macro
-# 
-# If COMSPEC/ComSpec is defined, Make is launched from Windows through
-# Cygwin.  The adjust-path macro converts absolute windows paths into
-# unix style paths (Example: c:/dir -> /c/dir). This will ensture
-# paths are readable by GNU Make.
-#
-# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no 
-# adjustment is necessary
-#
-#------------------------------------------------------------------------------
-
-ifndef COMSPEC
-ifdef ComSpec
-COMSPEC = $(ComSpec)
-endif # ComSpec
-endif # COMSPEC
-
-ifdef COMSPEC # if Windows OS
-
-ifeq ($(MAKE_VERSION),3.81) 
-#
-# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows
-#
-# Example Usage:
-# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb
-# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb
-# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb
-#
-
-#
-# adjust-path
-#  - converts back slash characters into forward slashes 
-#  - if input arg ($1) is an empty string then return the empty string
-#  - if input arg ($1) does not contain the string ":/", then return input arg
-#  - using sed, convert mixed path [c:/...] into mingw path [/c/...] 
-define adjust-path
-$(strip \
-$(if $1,\
-$(if $(findstring :/,$(subst \,/,$1)),\
-$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\
-$(subst \,/,$1))))
-endef
-
-#
-# adjust-path-mixed
-#  - converts back slash characters into forward slashes 
-#  - if input arg ($1) is an empty string then return the empty string
-#  - if input arg ($1) does not begin with a forward slash '/' char, then 
-#    return input arg
-#  - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] 
-#    into a mixed path [c:/...] 
-define adjust-path-mixed 
-$(strip \
-$(if $1,\
-$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\
-$(subst \,/,$1),\
-$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,'))))
-endef
-
-else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) 
-#
-#  adjust-path for Cygwin Gnu Make
-# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb
-# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb
-#
-adjust-path = $(if $1,$(shell cygpath -u "$1"),)
-adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),)
-endif
-
-else # !COMSPEC
-
-adjust-path = $1
-adjust-path-mixed = $1
-
-endif # COMSPEC
-
-
-#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
-#                           GENERATED SETTINGS START                         v
-#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
-
-#START GENERATED
+#------------------------------------------------------------------------------
+#              VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS
+#------------------------------------------------------------------------------
+
+# List of include directories for -I compiler option (-I added when used).
+# Includes the BSP.
+ALT_INCLUDE_DIRS :=
+
+# List of library directories for -L linker option (-L added when used).
+# Includes the BSP.
+ALT_LIBRARY_DIRS :=
+
+# List of library names for -l linker option (-l added when used).
+# Includes the BSP.
+ALT_LIBRARY_NAMES :=
+
+# List of library names for -msys-lib linker option (-msys-lib added when used).
+# These are libraries that might be located in the BSP and depend on the BSP
+# library, or vice versa
+ALT_BSP_DEP_LIBRARY_NAMES :=
+
+# List of dependencies for the linker.  This is usually the full pathname
+# of each library (*.a) file.
+# Includes the BSP.
+ALT_LDDEPS :=
+
+# List of root library directories that support running make to build them.
+# Includes the BSP and any ALT libraries.
+MAKEABLE_LIBRARY_ROOT_DIRS :=
+
+# Generic flags passed to the compiler for different types of input files.
+ALT_CFLAGS :=
+ALT_CXXFLAGS :=
+ALT_CPPFLAGS :=
+ALT_ASFLAGS :=
+ALT_LDFLAGS :=
+
+
+#------------------------------------------------------------------------------
+#                         The adjust-path macro
+# 
+# If COMSPEC/ComSpec is defined, Make is launched from Windows through
+# Cygwin.  The adjust-path macro converts absolute windows paths into
+# unix style paths (Example: c:/dir -> /c/dir). This will ensture
+# paths are readable by GNU Make.
+#
+# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no 
+# adjustment is necessary
+#
+#------------------------------------------------------------------------------
+
+ifndef COMSPEC
+ifdef ComSpec
+COMSPEC = $(ComSpec)
+endif # ComSpec
+endif # COMSPEC
+
+ifdef COMSPEC # if Windows OS
+
+ifeq ($(MAKE_VERSION),3.81) 
+#
+# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows
+#
+# Example Usage:
+# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb
+# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb
+#
+
+#
+# adjust-path
+#  - converts back slash characters into forward slashes 
+#  - if input arg ($1) is an empty string then return the empty string
+#  - if input arg ($1) does not contain the string ":/", then return input arg
+#  - using sed, convert mixed path [c:/...] into mingw path [/c/...] 
+define adjust-path
+$(strip \
+$(if $1,\
+$(if $(findstring :/,$(subst \,/,$1)),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\
+$(subst \,/,$1))))
+endef
+
+#
+# adjust-path-mixed
+#  - converts back slash characters into forward slashes 
+#  - if input arg ($1) is an empty string then return the empty string
+#  - if input arg ($1) does not begin with a forward slash '/' char, then 
+#    return input arg
+#  - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] 
+#    into a mixed path [c:/...] 
+define adjust-path-mixed 
+$(strip \
+$(if $1,\
+$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\
+$(subst \,/,$1),\
+$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,'))))
+endef
+
+else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) 
+#
+#  adjust-path for Cygwin Gnu Make
+# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb
+# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb
+#
+adjust-path = $(if $1,$(shell cygpath -u "$1"),)
+adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),)
+endif
+
+else # !COMSPEC
+
+adjust-path = $1
+adjust-path-mixed = $1
+
+endif # COMSPEC
+
+
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+#                           GENERATED SETTINGS START                         v
+#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
+
+#START GENERATED
 ACTIVE_BUILD_CONFIG := default
 BUILD_CONFIGS := default
-
-# The following TYPE comment allows tools to identify the 'type' of target this 
-# makefile is associated with. 
-# TYPE: APP_MAKEFILE
-
-# This following VERSION comment indicates the version of the tool used to 
-# generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 18.1
+
+# The following TYPE comment allows tools to identify the 'type' of target this 
+# makefile is associated with. 
+# TYPE: APP_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to 
+# generate this makefile. A makefile variable is provided for VERSION as well. 
+# ACDS_VERSION: 18.1
 ACDS_VERSION := 18.1
-
-# This following BUILD_NUMBER comment indicates the build number of the tool 
-# used to generate this makefile. 
-# BUILD_NUMBER: 625
-
+
+# This following BUILD_NUMBER comment indicates the build number of the tool 
+# used to generate this makefile. 
+# BUILD_NUMBER: 625
+
 # Define path to the application ELF. 
 # It may be used by the makefile fragments so is defined before including them. 
-# 
+# 
 ELF := semafor.elf
-
-# Paths to C, C++, and assembly source files.
+
+# Paths to C, C++, and assembly source files.
 C_SRCS := sem.c
 CXX_SRCS :=
 ASM_SRCS :=
-
-
+
+
 # Path to root of object file tree.
 OBJ_ROOT_DIR := obj
-
+
 # Options to control objdump.
 CREATE_OBJDUMP := 1
 OBJDUMP_INCLUDE_SOURCE := 1
 OBJDUMP_FULL_CONTENTS := 0
-
+
 # Options to enable/disable optional files.
 CREATE_ELF_DERIVED_FILES := 0
 CREATE_LINKER_MAP := 1
-
-# Common arguments for ALT_CFLAGSs
+
+# Common arguments for ALT_CFLAGSs
 APP_CFLAGS_DEFINED_SYMBOLS :=
 APP_CFLAGS_UNDEFINED_SYMBOLS :=
 APP_CFLAGS_OPTIMIZATION := -O0
 APP_CFLAGS_DEBUG_LEVEL := -g
 APP_CFLAGS_WARNINGS := -Wall
 APP_CFLAGS_USER_FLAGS :=
-
+
 APP_ASFLAGS_USER :=
 APP_LDFLAGS_USER :=
-
+
 # Linker options that have default values assigned later if not
 # assigned here.
 LINKER_SCRIPT :=
 CRT0 :=
 SYS_LIB :=
-
-# Define path to the root of the BSP.
+
+# Define path to the root of the BSP.
 BSP_ROOT_DIR := ../semafor_bsp/
-
-# List of application specific include directories, library directories and library names
+
+# List of application specific include directories, library directories and library names
 APP_INCLUDE_DIRS :=
 APP_LIBRARY_DIRS :=
 APP_LIBRARY_NAMES :=
-
-# Pre- and post- processor settings.
+
+# Pre- and post- processor settings.
 BUILD_PRE_PROCESS :=
 BUILD_POST_PROCESS :=
-
+
 QUARTUS_PROJECT_DIR := ../../
-
-
-#END GENERATED
-
-#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-#                            GENERATED SETTINGS END                           ^
-#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-
-#------------------------------------------------------------------------------
-#                           DEFAULT TARGET
-#------------------------------------------------------------------------------
-
-# Define the variable used to echo output if not already defined.
-ifeq ($(ECHO),)
-ECHO := echo
-endif
-
-# Put "all" rule before included makefile fragments because they may
-# define rules and we don't want one of those to become the default rule.
-.PHONY : all
-
-all:
-	@$(ECHO) [$(APP_NAME) build complete]
-
-all : build_pre_process libs app build_post_process 
-
-
-#------------------------------------------------------------------------------
-#                 VARIABLES DEPENDENT ON GENERATED CONTENT
-#------------------------------------------------------------------------------
-
-# Define object file directory per build configuration
-CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG)
-
-ifeq ($(BSP_ROOT_DIR),)
-$(error Edit Makefile and provide a value for BSP_ROOT_DIR)
-endif
-
-ifeq ($(wildcard $(BSP_ROOT_DIR)),)
-$(error BSP directory does not exist: $(BSP_ROOT_DIR))
-endif
-
-# Define absolute path to the root of the BSP.
-ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd))
-
-# Include makefile fragments.  Define variable ALT_LIBRARY_ROOT_DIR before
-# including each makefile fragment so that it knows the path to itself.
-BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk
-ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR)
-include $(BSP_INCLUDE_FILE)
-# C2H will need this to touch the BSP public.mk and avoid the sopc file 
-# out-of-date error during a BSP make
-ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk
-
-
-ifneq ($(WARNING.SMALL_STACK_SIZE),)
-# This WARNING is here to protect you from unknowingly using a very small stack
-# If the warning is set, increase your stack size or enable the BSP small stack 
-# setting to eliminate the warning
-$(warning WARNING: $(WARNING.SMALL_STACK_SIZE))
-endif
-
-# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF 
-# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_.  
-ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),)
-ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF)
-endif
-
-# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to 
-# download_elf target
-ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),)
-GMON_OUT_FILENAME := gmon.out
-WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME)
-endif
-
-# Name of ELF application.
-APP_NAME := $(basename $(ELF))
-
-# Set to defaults if variables not already defined in settings.
-ifeq ($(LINKER_SCRIPT),)
-LINKER_SCRIPT := $(BSP_LINKER_SCRIPT)
-endif
-ifeq ($(CRT0),)
-CRT0 := $(BSP_CRT0)
-endif
-ifeq ($(SYS_LIB),)
-SYS_LIB := $(BSP_SYS_LIB)
-endif
-
-OBJDUMP_NAME := $(APP_NAME).objdump
-OBJDUMP_FLAGS := --disassemble --syms --all-header
-ifeq ($(OBJDUMP_INCLUDE_SOURCE),1)
-OBJDUMP_FLAGS += --source
-endif
-ifeq ($(OBJDUMP_FULL_CONTENTS),1)
-OBJDUMP_FLAGS += --full-contents
-endif
-
-# Create list of linker dependencies (*.a files).
-APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS)
-
-# Take lists and add required prefixes.
-APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
-ASM_INC_PREFIX := -Wa,-I
-APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
-APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS))
-APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS))
-
-ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
-
-#
-# Avoid Nios II GCC 3.X options.
-#
-
-# Detect if small newlib C library is requested.
-# If yes, remove the -msmallc option because it is
-# now handled by other means.
-ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
-	ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
-	ALT_C_LIBRARY := smallc
-else
-	ALT_C_LIBRARY := c
-endif
-
-# Put each BSP dependent library in a group to avoid circular dependencies.
-APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -lm -l$(l) -Wl,--end-group)
-
-else # !AVOID_NIOS2_GCC3_OPTIONS
-
-#
-# Use Nios II GCC 3.X options.
-#
-ALT_BSP_DEP_LIBRARY_NAMES += $(ALT_BSP_DEP_LIBRARY_NAMES) m
-APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
-
-endif # !AVOID_NIOS2_GCC3_OPTIONS
-
-# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker.
-APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \
-              $(APP_CFLAGS_UNDEFINED_SYMBOLS) \
-              $(APP_CFLAGS_OPTIMIZATION) \
-              $(APP_CFLAGS_DEBUG_LEVEL) \
-              $(APP_CFLAGS_WARNINGS) \
-              $(APP_CFLAGS_USER_FLAGS) \
-              $(ALT_CFLAGS) \
-              $(CFLAGS)
-
-# Arguments only for the C++ compiler.
-APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS)
-
-# Arguments only for the C preprocessor.
-# Prefix each include directory with -I.
-APP_CPPFLAGS := $(APP_INC_DIRS) \
-                $(ALT_CPPFLAGS) \
-                $(CPPFLAGS)
-
-# Arguments only for the assembler.
-APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
-               $(ALT_ASFLAGS) \
-               $(APP_ASFLAGS_USER) \
-               $(ASFLAGS)
-
-# Arguments only for the linker.
-APP_LDFLAGS := $(APP_LDFLAGS_USER)
-
-ifneq ($(LINKER_SCRIPT),)
-APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
-endif
-
-ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
-
-# Avoid Nios II GCC 3.x options.
-ifneq ($(CRT0),)
-APP_LDFLAGS += $(CRT0)
-endif
-
-# The equivalent of the -msys-lib option is provided
-# by the GROUP() command in the linker script.
-# Note this means the SYS_LIB variable is now ignored.
-
-else # !AVOID_NIOS2_GCC3_OPTIONS
-
-# Use Nios II GCC 3.x options.
-ifneq ($(CRT0),)
-APP_LDFLAGS += -msys-crt0='$(CRT0)'
-endif
-ifneq ($(SYS_LIB),)
-APP_LDFLAGS += -msys-lib=$(SYS_LIB)
-endif
-
-endif # !AVOID_NIOS2_GCC3_OPTIONS
-
-APP_LDFLAGS += \
-           $(APP_LIB_DIRS) \
-           $(ALT_LDFLAGS) \
-           $(LDFLAGS)
-
-LINKER_MAP_NAME := $(APP_NAME).map
-ifeq ($(CREATE_LINKER_MAP), 1)
-APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME)
-endif
-
-# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the 
-# mem_init_install target of the mem_init.mk (located in the associated BSP) 
-# to know how to copy memory initialization files (e.g. .dat, .hex) into 
-# directories required for Quartus compilation or RTL simulation.
-
-# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory 
-# initialization files into your Quartus project directory. This is required 
-# to provide the initial memory contents of FPGA memories that can be 
-# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used 
-# for VHDL simulation of on-chip memories.
-
-# Defining SOPC_NAME causes the mem_init_install target to copy memory 
-# initialization files into your RTL simulation directory.  This is required 
-# to provide the initial memory contents of all memories that can be 
-# initialized by RTL simulation. This variable should be set to the same name 
-# as your SOPC Builder system name. For example, if you have a system called 
-# "foo.sopc", this variable should be set to "foo".
-
-# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME.
-ifeq ($(SOPC_NAME),)
-ifneq ($(QUARTUS_PROJECT_DIR),)
-SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo)))
-endif
-endif
-
-# Defining JDI_FILE is required to specify the JTAG Debug Information File 
-# path. This file is generated by Quartus, and is needed along with the 
-# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU 
-# systems. For multi-CPU systems, the processor instance ID is used to select 
-# from multiple CPU's during ELF download.
-
-# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during 
-# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then 
-# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be 
-# multiple .sopcinfo files in a Quartus project. 
-ifeq ($(JDI_FILE),)
-ifneq ($(QUARTUS_PROJECT_DIR),)
-JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi))
-endif
-endif
-
-# Path to root runtime directory used for hdl simulation 
-RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime
-
-
-
-#------------------------------------------------------------------------------
-#           MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT
-#------------------------------------------------------------------------------
-# mem_init.mk is a generated makefile fragment. This file defines all targets
-# used to generate HDL initialization simulation files and pre-initialized
-# onchip memory files.
-MEM_INIT_FILE :=  $(BSP_ROOT_DIR)/mem_init.mk
-include $(MEM_INIT_FILE)
-
-# Create list of object files to be built using the list of source files.
-# The source file hierarchy is preserved in the object tree.
-# The supported file extensions are:
-#
-# .c            - for C files
-# .cxx .cc .cpp - for C++ files
-# .S .s         - for assembler files
-#
-# Handle source files specified by --src-dir & --src-rdir differently, to
-# save some processing time in calling the adjust-path macro.
-
-OBJ_LIST_C 		:= $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS)))
-OBJ_LIST_CPP	:= $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS)))
-OBJ_LIST_CXX 	:= $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS)))
-OBJ_LIST_CC 	:= $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS)))
-OBJ_LIST_S 		:= $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS)))
-OBJ_LIST_SS		:= $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS)))
-
-OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \
-				$(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS))
-
-SDIR_OBJ_LIST_C		:= $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS)))
-SDIR_OBJ_LIST_CPP	:= $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS)))
-SDIR_OBJ_LIST_CXX 	:= $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS)))
-SDIR_OBJ_LIST_CC 	:= $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS)))
-SDIR_OBJ_LIST_S		:= $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS)))
-SDIR_OBJ_LIST_SS	:= $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS)))
-
-SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \
-				$(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \
-				$(SDIR_OBJ_LIST_SS))
-
-# Relative-pathed objects that being with "../" are handled differently.
-#
-# Regular objects are created as 
-#   $(CONFIG_OBJ_DIR)/<path>/<filename>.o
-# where the path structure is maintained under the obj directory.  This
-# applies for both absolute and relative paths; in the absolute path
-# case this means the entire source path will be recreated under the obj
-# directory.  This is done to allow two source files with the same name
-# to be included as part of the project.
-#
-# Note: On Cygwin, the path recreated under the obj directory will be 
-# the cygpath -u output path.
-#
-# Relative-path objects that begin with "../" cause problems under this 
-# scheme, as $(CONFIG_OBJ_DIR)/../<rest of path>/ can potentially put the object
-# files anywhere in the system, creating clutter and polluting the source tree.
-# As such, their paths are flattened - the object file created will be 
-# $(CONFIG_OBJ_DIR)/<filename>.o.  Due to this, two files specified with 
-# "../" in the beginning cannot have the same name in the project.  VPATH 
-# will be set for these sources to allow make to relocate the source file 
-# via %.o rules.
-#
-# The following lines separate the object list into the flatten and regular
-# lists, and then handles them as appropriate.
-
-FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST))
-FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST)))
-
-REGULAR_OBJ_LIST 		:= $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST))
-REGULAR_OBJ_LIST_C 		:= $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST))
-REGULAR_OBJ_LIST_CPP	:= $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST))
-REGULAR_OBJ_LIST_CXX 	:= $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST))
-REGULAR_OBJ_LIST_CC 	:= $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST))
-REGULAR_OBJ_LIST_S 		:= $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST))
-REGULAR_OBJ_LIST_SS		:= $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST))
-
-FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST))
-FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST)))
-
-REGULAR_SDIR_OBJ_LIST 		:= $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_C 	:= $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_CPP	:= $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_CXX 	:= $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_CC 	:= $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_S 	:= $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST))
-REGULAR_SDIR_OBJ_LIST_SS	:= $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST))
-
-VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST)))
-
-APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_C) \
-	$(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s)))
-
-APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_CPP) \
-	$(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s)))
-
-APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_CXX) \
-	$(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s)))
-
-APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_CC) \
-	$(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s)))
-
-APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_S) \
-	$(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s)))
-
-APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\
-	$(REGULAR_SDIR_OBJ_LIST_SS) \
-	$(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s)))
-
-APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \
-	$(APP_OBJS_S) $(APP_OBJS_SS) \
-	$(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS)
-
-# Add any extra user-provided object files.
-APP_OBJS += $(OBJS)
-
-# Create list of dependancy files for each object file.
-APP_DEPS := $(APP_OBJS:.o=.d)
-
-# Patch the Elf file with system specific information
-
-# Patch the Elf with the name of the sopc system
-ifneq ($(SOPC_NAME),)
-ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME)
-endif
-
-# Patch the Elf with the absolute path to the Quartus Project Directory
-ifneq ($(QUARTUS_PROJECT_DIR),)
-ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd))
-ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)"
-endif
-
-# Patch the Elf and download args with the JDI_FILE if specified
-ifneq ($(wildcard $(JDI_FILE)),)
-ELF_PATCH_FLAG += --jdi $(JDI_FILE)
-DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE)
-endif
-
-# Patch the Elf with the SOPCINFO_FILE if specified
-ifneq ($(wildcard $(SOPCINFO_FILE)),)
-ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE)
-endif
-
-# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. 
-# This is not needed if you only have one cable.
-ifneq ($(DOWNLOAD_CABLE),)
-DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)'
-endif
-
-
-#------------------------------------------------------------------------------
-#                           BUILD PRE/POST PROCESS
-#------------------------------------------------------------------------------
-build_pre_process :
-	$(BUILD_PRE_PROCESS)
-
-build_post_process :
-	$(BUILD_POST_PROCESS)
-
-.PHONY: build_pre_process build_post_process
-
-
-#------------------------------------------------------------------------------
-#                                 TOOLS
-#------------------------------------------------------------------------------
-
-#
-# Set tool default variables if not already defined.
-# If these are defined, they would typically be defined in an
-# included makefile fragment.
-#
-ifeq ($(DEFAULT_CROSS_COMPILE),)
-DEFAULT_CROSS_COMPILE := nios2-elf-
-endif
-
-ifeq ($(DEFAULT_STACKREPORT),)
-DEFAULT_STACKREPORT := nios2-stackreport
-endif
-
-ifeq ($(DEFAULT_DOWNLOAD),)
-DEFAULT_DOWNLOAD := nios2-download
-endif
-
-ifeq ($(DEFAULT_FLASHPROG),)
-DEFAULT_FLASHPROG := nios2-flash-programmer
-endif
-
-ifeq ($(DEFAULT_ELFPATCH),)
-DEFAULT_ELFPATCH := nios2-elf-insert
-endif
-
-ifeq ($(DEFAULT_RM),)
-DEFAULT_RM := rm -f
-endif
-
-ifeq ($(DEFAULT_CP),)
-DEFAULT_CP := cp -f
-endif
-
-ifeq ($(DEFAULT_MKDIR),)
-DEFAULT_MKDIR := mkdir -p
-endif
-
-#
-# Set tool variables to defaults if not already defined.
-# If these are defined, they would typically be defined by a
-# setting in the generated portion of this makefile.
-#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE)
-endif
-
-ifeq ($(origin CC),default)
-CC := $(CROSS_COMPILE)gcc -xc
-endif
-
-ifeq ($(origin CXX),default)
-CXX := $(CROSS_COMPILE)gcc -xc++
-endif
-
-ifeq ($(origin AS),default)
-AS := $(CROSS_COMPILE)gcc
-endif
-
-ifeq ($(origin AR),default)
-AR := $(CROSS_COMPILE)ar
-endif
-
-ifeq ($(origin LD),default)
-LD := $(CROSS_COMPILE)g++
-endif
-
-ifeq ($(origin RM),default)
-RM := $(DEFAULT_RM)
-endif
-
-ifeq ($(NM),)
-NM := $(CROSS_COMPILE)nm
-endif
-
-ifeq ($(CP),)
-CP := $(DEFAULT_CP)
-endif
-
-ifeq ($(OBJDUMP),)
-OBJDUMP := $(CROSS_COMPILE)objdump
-endif
-
-ifeq ($(OBJCOPY),)
-OBJCOPY := $(CROSS_COMPILE)objcopy
-endif
-
-ifeq ($(STACKREPORT),)
-STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
-else
-DISABLE_STACKREPORT := 1
-endif
-
-ifeq ($(DOWNLOAD),)
-DOWNLOAD := $(DEFAULT_DOWNLOAD)
-endif
-
-ifeq ($(FLASHPROG),)
-FLASHPROG := $(DEFAULT_FLASHPROG)
-endif
-
-ifeq ($(ELFPATCH),)
-ELFPATCH := $(DEFAULT_ELFPATCH)
-endif
-
-ifeq ($(MKDIR),)
-MKDIR := $(DEFAULT_MKDIR)
-endif
-
-#------------------------------------------------------------------------------
-#                     PATTERN RULES TO BUILD OBJECTS
-#------------------------------------------------------------------------------
-
-define compile.c
-@$(ECHO) Info: Compiling $< to $@
-@$(MKDIR) $(@D)
-$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
-$(CC_POST_PROCESS)
-endef
-
-define compile.cpp
-@$(ECHO) Info: Compiling $< to $@
-@$(MKDIR) $(@D)
-$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-$(CXX_POST_PROCESS)
-endef
-
-# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS
-ifeq ($(AS),$(patsubst %as,%,$(AS)))
-COMMA := ,
-APP_ASFLAGS :=  $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS))))
-endif
-
-define compile.s
-@$(ECHO) Info: Assembling $< to $@
-@$(MKDIR) $(@D)
-$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $<
-$(AS_POST_PROCESS)
-endef
-
-ifeq ($(MAKE_VERSION),3.81) 
-.SECONDEXPANSION:
-
-$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c)
-	$(compile.c)
-
-$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp)
-	$(compile.cpp)
-
-$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc)
-	$(compile.cpp)
-
-$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx)
-	$(compile.cpp)
-
-$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S)
-	$(compile.s)
-
-$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s)
-	$(compile.s)
-
-endif # MAKE_VERSION != 3.81
-
-$(CONFIG_OBJ_DIR)/%.o: %.c
-	$(compile.c)
-
-$(CONFIG_OBJ_DIR)/%.o: %.cpp
-	$(compile.cpp)
-
-$(CONFIG_OBJ_DIR)/%.o: %.cc
-	$(compile.cpp)
-
-$(CONFIG_OBJ_DIR)/%.o: %.cxx
-	$(compile.cpp)
-
-$(CONFIG_OBJ_DIR)/%.o: %.S
-	$(compile.s)
-
-$(CONFIG_OBJ_DIR)/%.o: %.s
-	$(compile.s)
-
-
-#------------------------------------------------------------------------------
-#                     PATTERN RULES TO INTERMEDIATE FILES
-#------------------------------------------------------------------------------
-
-$(CONFIG_OBJ_DIR)/%.s: %.c
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.s: %.cpp
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.s: %.cc
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.s: %.cxx
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.i: %.c
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.i: %.cpp
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.i: %.cc
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-$(CONFIG_OBJ_DIR)/%.i: %.cxx
-	@$(ECHO) Info: Compiling $< to $@
-	@$(MKDIR) $(@D)
-	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
-
-
-#------------------------------------------------------------------------------
-#                        TARGET RULES
-#------------------------------------------------------------------------------
-
-.PHONY : help
-help :
-	@$(ECHO) "Summary of Makefile targets"
-	@$(ECHO) "  Build targets:"
-	@$(ECHO) "    all (default)     - Application and all libraries (including BSP)"
-	@$(ECHO) "    bsp               - Just the BSP"
-	@$(ECHO) "    libs              - All libraries (including BSP)"
-	@$(ECHO) "    flash             - All flash files"
-	@$(ECHO) "    mem_init_generate - All memory initialization files"
-	@$(ECHO)
-	@$(ECHO) "  Clean targets:"
-	@$(ECHO) "    clean_all         - Application and all libraries (including BSP)"
-	@$(ECHO) "    clean             - Just the application"
-	@$(ECHO) "    clean_bsp         - Just the BSP"
-	@$(ECHO) "    clean_libs        - All libraries (including BSP)"
-	@$(ECHO)
-	@$(ECHO) "  Run targets:"
-	@$(ECHO) "    download-elf      - Download and run your elf executable"
-	@$(ECHO) "    program-flash     - Program flash contents to the board"
-
-# Handy rule to skip making libraries and just make application.
-.PHONY : app
-app : $(ELF)
-
-ifeq ($(CREATE_OBJDUMP), 1)
-app : $(OBJDUMP_NAME)
-endif
-
-ifeq ($(CREATE_ELF_DERIVED_FILES),1)
-app : elf_derived_files
-endif
-
-.PHONY: elf_derived_files
-elf_derived_files: default_mem_init
-
-# Handy rule for making just the BSP.
-.PHONY : bsp
-bsp :
-	@$(ECHO) Info: Building $(BSP_ROOT_DIR)
-	@$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR)
-
-
-# Make sure all makeable libraries (including the BSP) are up-to-date.
-LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
-
-.PHONY : libs
-libs : $(LIB_TARGETS)
-
-ifneq ($(strip $(LIB_TARGETS)),)
-$(LIB_TARGETS): %-recurs-make-lib:
-	@$(ECHO) Info: Building $*
-	$(MAKE) --no-print-directory -C $*
-endif
-
-ifneq ($(strip $(APP_LDDEPS)),)
-$(APP_LDDEPS): libs
-	@true
-endif
-
-# Rules to force your project to rebuild or relink
-# .force_relink file will cause any application that depends on this project to relink
-# .force_rebuild file will cause this project to rebuild object files
-# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
-
-FORCE_RELINK_DEP  := .force_relink
-FORCE_REBUILD_DEP := .force_rebuild
-FORCE_REBUILD_ALL_DEP := .force_rebuild_all
-FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
-
-$(FORCE_REBUILD_DEP_LIST):
-
-$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS)))
-
-$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS)))
-
-
-# Clean just the application.
-.PHONY : clean
-ifeq ($(CREATE_ELF_DERIVED_FILES),1)
-clean : clean_elf_derived_files
-endif
-
-clean :
-	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST)
-	@$(ECHO) [$(APP_NAME) clean complete]
-
-# Clean just the BSP.
-.PHONY : clean_bsp
-clean_bsp :
-	@$(ECHO) Info: Cleaning $(BSP_ROOT_DIR)
-	@$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean
-
-# Clean all makeable libraries including the BSP.
-LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
-
-.PHONY : clean_libs
-clean_libs : $(LIB_CLEAN_TARGETS)
-
-ifneq ($(strip $(LIB_CLEAN_TARGETS)),)
-$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib:
-	@$(ECHO) Info: Cleaning $*
-	$(MAKE) --no-print-directory -C $* clean
-endif
-
-.PHONY: clean_elf_derived_files
-clean_elf_derived_files: mem_init_clean
-
-# Clean application and all makeable libraries including the BSP.
-.PHONY : clean_all
-clean_all : clean mem_init_clean clean_libs
-
-# Include the dependency files unless the make goal is performing a clean
-# of the application.
-ifneq ($(firstword $(MAKECMDGOALS)),clean)
-ifneq ($(firstword $(MAKECMDGOALS)),clean_all)
--include $(APP_DEPS)
-endif
-endif
-
-.PHONY : download-elf
-download-elf : $(ELF)
-	@if [ "$(DOWNLOAD)" = "none" ]; \
-	then \
-		$(ECHO) Downloading $(ELF) not supported; \
-	else \
-		$(ECHO) Info: Downloading $(ELF); \
-		$(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \
-	fi
-
-# Delete the target of a rule if it has changed and its commands exit
-# with a nonzero exit status.
-.DELETE_ON_ERROR:
-
-# Rules for flash programming commands
-PROGRAM_FLASH_SUFFIX := -program
-PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES))
-
-.PHONY : program-flash
-program-flash : $(PROGRAM_FLASH_TARGET)
-
-.PHONY : $(PROGRAM_FLASH_TARGET)
-$(PROGRAM_FLASH_TARGET) : flash
-	@if [ "$(FLASHPROG)" = "none" ]; \
-	then \
-		$(ECHO) Programming flash not supported; \
-	else \
-		$(ECHO) Info: Programming $(basename $@).flash; \
-		if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \
-		then \
-			$(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
-			$(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
-		else \
-			$(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
-			$(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
-		fi \
-	fi
-
-
-# Rules for simulating with an HDL Simulator [QSYS only]
-ifeq ($(QSYS),1)
-#Create a top level modelsim script load_sim.tcl to source generate msim_setup.tcl and copy mem initialization files
-CREATE_TOP_SIM_SCRIPT := alt-create-top-sim-script
-
-ifeq ($(VSIM),)
-VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim"
-ifeq ($(ENABLE_VSIM_GUI),1)
-VSIM := $(VSIM_EXE) -gui
-else
-VSIM := $(VSIM_EXE) -c
-endif # ENABLE_VSIM_GUI == 1
-endif # VSIM not set
-
-ifeq ($(SPD),)
-ifneq ($(ABS_QUARTUS_PROJECT_DIR),)
-ifneq ($(SOPC_NAME),)
-SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb.spd
-LEGACY_SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd
-SPD = $(if $(wildcard $(SPD_LOCATION)),$(SPD_LOCATION),$(LEGACY_SPD_LOCATION))
-endif # SOPC_NAME set
-endif # ABS_QUARTUS_PROJECT_DIR set
-endif # SPD == empty string
-
-
-ifeq ($(LOAD_SIM_SCRIPT),)
-SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim
-LOAD_SIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/load_sim.tcl
-endif # LOAD_SIM_SCRIPT == empty string
-
-ifeq ($(MAKE_VERSION),3.81)
-ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE))
-else
-ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE)
-endif
-
-$(LOAD_SIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE)
-ifeq ($(SPD),)
-	$(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set)
-endif
-	@$(MKDIR) $(SIM_SCRIPT_DIR)
-	$(CREATE_TOP_SIM_SCRIPT) --spd=$(SPD) --mem-init-spd=$(abspath $(MEM_INIT_DESCRIPTOR_FILE)) --output-directory=$(SIM_SCRIPT_DIR)
-
-VSIM_COMMAND = \
-	cd $(dir $(LOAD_SIM_SCRIPT)) && \
-	$(VSIM) -do "do $(notdir $(LOAD_SIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)"
-
-.PHONY: sim
-sim: $(LOAD_SIM_SCRIPT) mem_init_generate
-ifeq ($(LOAD_SIM_SCRIPT),)
-	$(error LOAD_SIM_SCRIPT not set)
-endif
-	$(VSIM_COMMAND)
-
-endif # QSYS == 1
-
-
-
-
-#------------------------------------------------------------------------------
-#                         ELF TARGET RULE
-#------------------------------------------------------------------------------
-# Rule for constructing the executable elf file.
-$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS)
-	@$(ECHO) Info: Linking $@
-	$(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS)
-ifneq ($(DISABLE_ELFPATCH),1)
-	$(ELFPATCH) $@ $(ELF_PATCH_FLAG)
-endif
-ifneq ($(DISABLE_STACKREPORT),1)
-	@bash -c "$(STACKREPORT) $@"
-endif
-
-$(OBJDUMP_NAME) : $(ELF)
-	@$(ECHO) Info: Creating $@
-	$(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@
-
-# Rule for printing the name of the elf file
-.PHONY: print-elf-name
-print-elf-name:
-	@$(ECHO) $(ELF)
-
-
+
+
+#END GENERATED
+
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+#                            GENERATED SETTINGS END                           ^
+#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+#------------------------------------------------------------------------------
+#                           DEFAULT TARGET
+#------------------------------------------------------------------------------
+
+# Define the variable used to echo output if not already defined.
+ifeq ($(ECHO),)
+ECHO := echo
+endif
+
+# Put "all" rule before included makefile fragments because they may
+# define rules and we don't want one of those to become the default rule.
+.PHONY : all
+
+all:
+	@$(ECHO) [$(APP_NAME) build complete]
+
+all : build_pre_process libs app build_post_process 
+
+
+#------------------------------------------------------------------------------
+#                 VARIABLES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+
+# Define object file directory per build configuration
+CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG)
+
+ifeq ($(BSP_ROOT_DIR),)
+$(error Edit Makefile and provide a value for BSP_ROOT_DIR)
+endif
+
+ifeq ($(wildcard $(BSP_ROOT_DIR)),)
+$(error BSP directory does not exist: $(BSP_ROOT_DIR))
+endif
+
+# Define absolute path to the root of the BSP.
+ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd))
+
+# Include makefile fragments.  Define variable ALT_LIBRARY_ROOT_DIR before
+# including each makefile fragment so that it knows the path to itself.
+BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk
+ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR)
+include $(BSP_INCLUDE_FILE)
+# C2H will need this to touch the BSP public.mk and avoid the sopc file 
+# out-of-date error during a BSP make
+ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk
+
+
+ifneq ($(WARNING.SMALL_STACK_SIZE),)
+# This WARNING is here to protect you from unknowingly using a very small stack
+# If the warning is set, increase your stack size or enable the BSP small stack 
+# setting to eliminate the warning
+$(warning WARNING: $(WARNING.SMALL_STACK_SIZE))
+endif
+
+# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF 
+# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_.  
+ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),)
+ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF)
+endif
+
+# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to 
+# download_elf target
+ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),)
+GMON_OUT_FILENAME := gmon.out
+WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME)
+endif
+
+# Name of ELF application.
+APP_NAME := $(basename $(ELF))
+
+# Set to defaults if variables not already defined in settings.
+ifeq ($(LINKER_SCRIPT),)
+LINKER_SCRIPT := $(BSP_LINKER_SCRIPT)
+endif
+ifeq ($(CRT0),)
+CRT0 := $(BSP_CRT0)
+endif
+ifeq ($(SYS_LIB),)
+SYS_LIB := $(BSP_SYS_LIB)
+endif
+
+OBJDUMP_NAME := $(APP_NAME).objdump
+OBJDUMP_FLAGS := --disassemble --syms --all-header
+ifeq ($(OBJDUMP_INCLUDE_SOURCE),1)
+OBJDUMP_FLAGS += --source
+endif
+ifeq ($(OBJDUMP_FULL_CONTENTS),1)
+OBJDUMP_FLAGS += --full-contents
+endif
+
+# Create list of linker dependencies (*.a files).
+APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS)
+
+# Take lists and add required prefixes.
+APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+ASM_INC_PREFIX := -Wa,-I
+APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS))
+APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS))
+APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS))
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+#
+# Avoid Nios II GCC 3.X options.
+#
+
+# Detect if small newlib C library is requested.
+# If yes, remove the -msmallc option because it is
+# now handled by other means.
+ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
+	ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
+	ALT_C_LIBRARY := smallc
+else
+	ALT_C_LIBRARY := c
+endif
+
+# Put each BSP dependent library in a group to avoid circular dependencies.
+APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -lm -l$(l) -Wl,--end-group)
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+#
+# Use Nios II GCC 3.X options.
+#
+ALT_BSP_DEP_LIBRARY_NAMES += $(ALT_BSP_DEP_LIBRARY_NAMES) m
+APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker.
+APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \
+              $(APP_CFLAGS_UNDEFINED_SYMBOLS) \
+              $(APP_CFLAGS_OPTIMIZATION) \
+              $(APP_CFLAGS_DEBUG_LEVEL) \
+              $(APP_CFLAGS_WARNINGS) \
+              $(APP_CFLAGS_USER_FLAGS) \
+              $(ALT_CFLAGS) \
+              $(CFLAGS)
+
+# Arguments only for the C++ compiler.
+APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS)
+
+# Arguments only for the C preprocessor.
+# Prefix each include directory with -I.
+APP_CPPFLAGS := $(APP_INC_DIRS) \
+                $(ALT_CPPFLAGS) \
+                $(CPPFLAGS)
+
+# Arguments only for the assembler.
+APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
+               $(ALT_ASFLAGS) \
+               $(APP_ASFLAGS_USER) \
+               $(ASFLAGS)
+
+# Arguments only for the linker.
+APP_LDFLAGS := $(APP_LDFLAGS_USER)
+
+ifneq ($(LINKER_SCRIPT),)
+APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
+endif
+
+ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
+
+# Avoid Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += $(CRT0)
+endif
+
+# The equivalent of the -msys-lib option is provided
+# by the GROUP() command in the linker script.
+# Note this means the SYS_LIB variable is now ignored.
+
+else # !AVOID_NIOS2_GCC3_OPTIONS
+
+# Use Nios II GCC 3.x options.
+ifneq ($(CRT0),)
+APP_LDFLAGS += -msys-crt0='$(CRT0)'
+endif
+ifneq ($(SYS_LIB),)
+APP_LDFLAGS += -msys-lib=$(SYS_LIB)
+endif
+
+endif # !AVOID_NIOS2_GCC3_OPTIONS
+
+APP_LDFLAGS += \
+           $(APP_LIB_DIRS) \
+           $(ALT_LDFLAGS) \
+           $(LDFLAGS)
+
+LINKER_MAP_NAME := $(APP_NAME).map
+ifeq ($(CREATE_LINKER_MAP), 1)
+APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME)
+endif
+
+# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the 
+# mem_init_install target of the mem_init.mk (located in the associated BSP) 
+# to know how to copy memory initialization files (e.g. .dat, .hex) into 
+# directories required for Quartus compilation or RTL simulation.
+
+# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory 
+# initialization files into your Quartus project directory. This is required 
+# to provide the initial memory contents of FPGA memories that can be 
+# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used 
+# for VHDL simulation of on-chip memories.
+
+# Defining SOPC_NAME causes the mem_init_install target to copy memory 
+# initialization files into your RTL simulation directory.  This is required 
+# to provide the initial memory contents of all memories that can be 
+# initialized by RTL simulation. This variable should be set to the same name 
+# as your SOPC Builder system name. For example, if you have a system called 
+# "foo.sopc", this variable should be set to "foo".
+
+# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME.
+ifeq ($(SOPC_NAME),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo)))
+endif
+endif
+
+# Defining JDI_FILE is required to specify the JTAG Debug Information File 
+# path. This file is generated by Quartus, and is needed along with the 
+# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU 
+# systems. For multi-CPU systems, the processor instance ID is used to select 
+# from multiple CPU's during ELF download.
+
+# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during 
+# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then 
+# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be 
+# multiple .sopcinfo files in a Quartus project. 
+ifeq ($(JDI_FILE),)
+ifneq ($(QUARTUS_PROJECT_DIR),)
+JDI_FILE := $(firstword $(wildcard $(QUARTUS_PROJECT_DIR)/output_files/*.jdi) $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi))
+endif
+endif
+
+# Path to root runtime directory used for hdl simulation 
+RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime
+
+
+
+#------------------------------------------------------------------------------
+#           MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT
+#------------------------------------------------------------------------------
+# mem_init.mk is a generated makefile fragment. This file defines all targets
+# used to generate HDL initialization simulation files and pre-initialized
+# onchip memory files.
+MEM_INIT_FILE :=  $(BSP_ROOT_DIR)/mem_init.mk
+include $(MEM_INIT_FILE)
+
+# Create list of object files to be built using the list of source files.
+# The source file hierarchy is preserved in the object tree.
+# The supported file extensions are:
+#
+# .c            - for C files
+# .cxx .cc .cpp - for C++ files
+# .S .s         - for assembler files
+#
+# Handle source files specified by --src-dir & --src-rdir differently, to
+# save some processing time in calling the adjust-path macro.
+
+OBJ_LIST_C 		:= $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS)))
+OBJ_LIST_CPP	:= $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS)))
+OBJ_LIST_CXX 	:= $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS)))
+OBJ_LIST_CC 	:= $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS)))
+OBJ_LIST_S 		:= $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS)))
+OBJ_LIST_SS		:= $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS)))
+
+OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \
+				$(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS))
+
+SDIR_OBJ_LIST_C		:= $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS)))
+SDIR_OBJ_LIST_CPP	:= $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CXX 	:= $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_CC 	:= $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS)))
+SDIR_OBJ_LIST_S		:= $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS)))
+SDIR_OBJ_LIST_SS	:= $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS)))
+
+SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \
+				$(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \
+				$(SDIR_OBJ_LIST_SS))
+
+# Relative-pathed objects that being with "../" are handled differently.
+#
+# Regular objects are created as 
+#   $(CONFIG_OBJ_DIR)/<path>/<filename>.o
+# where the path structure is maintained under the obj directory.  This
+# applies for both absolute and relative paths; in the absolute path
+# case this means the entire source path will be recreated under the obj
+# directory.  This is done to allow two source files with the same name
+# to be included as part of the project.
+#
+# Note: On Cygwin, the path recreated under the obj directory will be 
+# the cygpath -u output path.
+#
+# Relative-path objects that begin with "../" cause problems under this 
+# scheme, as $(CONFIG_OBJ_DIR)/../<rest of path>/ can potentially put the object
+# files anywhere in the system, creating clutter and polluting the source tree.
+# As such, their paths are flattened - the object file created will be 
+# $(CONFIG_OBJ_DIR)/<filename>.o.  Due to this, two files specified with 
+# "../" in the beginning cannot have the same name in the project.  VPATH 
+# will be set for these sources to allow make to relocate the source file 
+# via %.o rules.
+#
+# The following lines separate the object list into the flatten and regular
+# lists, and then handles them as appropriate.
+
+FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST))
+FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST)))
+
+REGULAR_OBJ_LIST 		:= $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST))
+REGULAR_OBJ_LIST_C 		:= $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CPP	:= $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CXX 	:= $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_CC 	:= $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_S 		:= $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST))
+REGULAR_OBJ_LIST_SS		:= $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST))
+
+FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST))
+FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST)))
+
+REGULAR_SDIR_OBJ_LIST 		:= $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_C 	:= $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CPP	:= $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CXX 	:= $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_CC 	:= $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_S 	:= $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST))
+REGULAR_SDIR_OBJ_LIST_SS	:= $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST))
+
+VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST)))
+
+APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_C) \
+	$(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s)))
+
+APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_CPP) \
+	$(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s)))
+
+APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_CXX) \
+	$(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s)))
+
+APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_CC) \
+	$(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s)))
+
+APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_S) \
+	$(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s)))
+
+APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\
+	$(REGULAR_SDIR_OBJ_LIST_SS) \
+	$(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s)))
+
+APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \
+	$(APP_OBJS_S) $(APP_OBJS_SS) \
+	$(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS)
+
+# Add any extra user-provided object files.
+APP_OBJS += $(OBJS)
+
+# Create list of dependancy files for each object file.
+APP_DEPS := $(APP_OBJS:.o=.d)
+
+# Patch the Elf file with system specific information
+
+# Patch the Elf with the name of the sopc system
+ifneq ($(SOPC_NAME),)
+ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME)
+endif
+
+# Patch the Elf with the absolute path to the Quartus Project Directory
+ifneq ($(QUARTUS_PROJECT_DIR),)
+ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd))
+ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)"
+endif
+
+# Patch the Elf and download args with the JDI_FILE if specified
+ifneq ($(wildcard $(JDI_FILE)),)
+ELF_PATCH_FLAG += --jdi $(JDI_FILE)
+DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE)
+endif
+
+# Patch the Elf with the SOPCINFO_FILE if specified
+ifneq ($(wildcard $(SOPCINFO_FILE)),)
+ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE)
+endif
+
+# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. 
+# This is not needed if you only have one cable.
+ifneq ($(DOWNLOAD_CABLE),)
+DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)'
+endif
+
+
+#------------------------------------------------------------------------------
+#                           BUILD PRE/POST PROCESS
+#------------------------------------------------------------------------------
+build_pre_process :
+	$(BUILD_PRE_PROCESS)
+
+build_post_process :
+	$(BUILD_POST_PROCESS)
+
+.PHONY: build_pre_process build_post_process
+
+
+#------------------------------------------------------------------------------
+#                                 TOOLS
+#------------------------------------------------------------------------------
+
+#
+# Set tool default variables if not already defined.
+# If these are defined, they would typically be defined in an
+# included makefile fragment.
+#
+ifeq ($(DEFAULT_CROSS_COMPILE),)
+DEFAULT_CROSS_COMPILE := nios2-elf-
+endif
+
+ifeq ($(DEFAULT_STACKREPORT),)
+DEFAULT_STACKREPORT := nios2-stackreport
+endif
+
+ifeq ($(DEFAULT_DOWNLOAD),)
+DEFAULT_DOWNLOAD := nios2-download
+endif
+
+ifeq ($(DEFAULT_FLASHPROG),)
+DEFAULT_FLASHPROG := nios2-flash-programmer
+endif
+
+ifeq ($(DEFAULT_ELFPATCH),)
+DEFAULT_ELFPATCH := nios2-elf-insert
+endif
+
+ifeq ($(DEFAULT_RM),)
+DEFAULT_RM := rm -f
+endif
+
+ifeq ($(DEFAULT_CP),)
+DEFAULT_CP := cp -f
+endif
+
+ifeq ($(DEFAULT_MKDIR),)
+DEFAULT_MKDIR := mkdir -p
+endif
+
+#
+# Set tool variables to defaults if not already defined.
+# If these are defined, they would typically be defined by a
+# setting in the generated portion of this makefile.
+#
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE)
+endif
+
+ifeq ($(origin CC),default)
+CC := $(CROSS_COMPILE)gcc -xc
+endif
+
+ifeq ($(origin CXX),default)
+CXX := $(CROSS_COMPILE)gcc -xc++
+endif
+
+ifeq ($(origin AS),default)
+AS := $(CROSS_COMPILE)gcc
+endif
+
+ifeq ($(origin AR),default)
+AR := $(CROSS_COMPILE)ar
+endif
+
+ifeq ($(origin LD),default)
+LD := $(CROSS_COMPILE)g++
+endif
+
+ifeq ($(origin RM),default)
+RM := $(DEFAULT_RM)
+endif
+
+ifeq ($(NM),)
+NM := $(CROSS_COMPILE)nm
+endif
+
+ifeq ($(CP),)
+CP := $(DEFAULT_CP)
+endif
+
+ifeq ($(OBJDUMP),)
+OBJDUMP := $(CROSS_COMPILE)objdump
+endif
+
+ifeq ($(OBJCOPY),)
+OBJCOPY := $(CROSS_COMPILE)objcopy
+endif
+
+ifeq ($(STACKREPORT),)
+STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
+else
+DISABLE_STACKREPORT := 1
+endif
+
+ifeq ($(DOWNLOAD),)
+DOWNLOAD := $(DEFAULT_DOWNLOAD)
+endif
+
+ifeq ($(FLASHPROG),)
+FLASHPROG := $(DEFAULT_FLASHPROG)
+endif
+
+ifeq ($(ELFPATCH),)
+ELFPATCH := $(DEFAULT_ELFPATCH)
+endif
+
+ifeq ($(MKDIR),)
+MKDIR := $(DEFAULT_MKDIR)
+endif
+
+#------------------------------------------------------------------------------
+#                     PATTERN RULES TO BUILD OBJECTS
+#------------------------------------------------------------------------------
+
+define compile.c
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CC_POST_PROCESS)
+endef
+
+define compile.cpp
+@$(ECHO) Info: Compiling $< to $@
+@$(MKDIR) $(@D)
+$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+$(CXX_POST_PROCESS)
+endef
+
+# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS
+ifeq ($(AS),$(patsubst %as,%,$(AS)))
+COMMA := ,
+APP_ASFLAGS :=  $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS))))
+endif
+
+define compile.s
+@$(ECHO) Info: Assembling $< to $@
+@$(MKDIR) $(@D)
+$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $<
+$(AS_POST_PROCESS)
+endef
+
+ifeq ($(MAKE_VERSION),3.81) 
+.SECONDEXPANSION:
+
+$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c)
+	$(compile.c)
+
+$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp)
+	$(compile.cpp)
+
+$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc)
+	$(compile.cpp)
+
+$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx)
+	$(compile.cpp)
+
+$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S)
+	$(compile.s)
+
+$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s)
+	$(compile.s)
+
+endif # MAKE_VERSION != 3.81
+
+$(CONFIG_OBJ_DIR)/%.o: %.c
+	$(compile.c)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cpp
+	$(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cc
+	$(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.cxx
+	$(compile.cpp)
+
+$(CONFIG_OBJ_DIR)/%.o: %.S
+	$(compile.s)
+
+$(CONFIG_OBJ_DIR)/%.o: %.s
+	$(compile.s)
+
+
+#------------------------------------------------------------------------------
+#                     PATTERN RULES TO INTERMEDIATE FILES
+#------------------------------------------------------------------------------
+
+$(CONFIG_OBJ_DIR)/%.s: %.c
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cpp
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cc
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.s: %.cxx
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.c
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cpp
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cc
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+$(CONFIG_OBJ_DIR)/%.i: %.cxx
+	@$(ECHO) Info: Compiling $< to $@
+	@$(MKDIR) $(@D)
+	$(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $<
+
+
+#------------------------------------------------------------------------------
+#                        TARGET RULES
+#------------------------------------------------------------------------------
+
+.PHONY : help
+help :
+	@$(ECHO) "Summary of Makefile targets"
+	@$(ECHO) "  Build targets:"
+	@$(ECHO) "    all (default)     - Application and all libraries (including BSP)"
+	@$(ECHO) "    bsp               - Just the BSP"
+	@$(ECHO) "    libs              - All libraries (including BSP)"
+	@$(ECHO) "    flash             - All flash files"
+	@$(ECHO) "    mem_init_generate - All memory initialization files"
+	@$(ECHO)
+	@$(ECHO) "  Clean targets:"
+	@$(ECHO) "    clean_all         - Application and all libraries (including BSP)"
+	@$(ECHO) "    clean             - Just the application"
+	@$(ECHO) "    clean_bsp         - Just the BSP"
+	@$(ECHO) "    clean_libs        - All libraries (including BSP)"
+	@$(ECHO)
+	@$(ECHO) "  Run targets:"
+	@$(ECHO) "    download-elf      - Download and run your elf executable"
+	@$(ECHO) "    program-flash     - Program flash contents to the board"
+
+# Handy rule to skip making libraries and just make application.
+.PHONY : app
+app : $(ELF)
+
+ifeq ($(CREATE_OBJDUMP), 1)
+app : $(OBJDUMP_NAME)
+endif
+
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+app : elf_derived_files
+endif
+
+.PHONY: elf_derived_files
+elf_derived_files: default_mem_init
+
+# Handy rule for making just the BSP.
+.PHONY : bsp
+bsp :
+	@$(ECHO) Info: Building $(BSP_ROOT_DIR)
+	@$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR)
+
+
+# Make sure all makeable libraries (including the BSP) are up-to-date.
+LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : libs
+libs : $(LIB_TARGETS)
+
+ifneq ($(strip $(LIB_TARGETS)),)
+$(LIB_TARGETS): %-recurs-make-lib:
+	@$(ECHO) Info: Building $*
+	$(MAKE) --no-print-directory -C $*
+endif
+
+ifneq ($(strip $(APP_LDDEPS)),)
+$(APP_LDDEPS): libs
+	@true
+endif
+
+# Rules to force your project to rebuild or relink
+# .force_relink file will cause any application that depends on this project to relink
+# .force_rebuild file will cause this project to rebuild object files
+# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
+
+FORCE_RELINK_DEP  := .force_relink
+FORCE_REBUILD_DEP := .force_rebuild
+FORCE_REBUILD_ALL_DEP := .force_rebuild_all
+FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
+
+$(FORCE_REBUILD_DEP_LIST):
+
+$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS)))
+
+$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS)))
+
+
+# Clean just the application.
+.PHONY : clean
+ifeq ($(CREATE_ELF_DERIVED_FILES),1)
+clean : clean_elf_derived_files
+endif
+
+clean :
+	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST)
+	@$(ECHO) [$(APP_NAME) clean complete]
+
+# Clean just the BSP.
+.PHONY : clean_bsp
+clean_bsp :
+	@$(ECHO) Info: Cleaning $(BSP_ROOT_DIR)
+	@$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean
+
+# Clean all makeable libraries including the BSP.
+LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS))
+
+.PHONY : clean_libs
+clean_libs : $(LIB_CLEAN_TARGETS)
+
+ifneq ($(strip $(LIB_CLEAN_TARGETS)),)
+$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib:
+	@$(ECHO) Info: Cleaning $*
+	$(MAKE) --no-print-directory -C $* clean
+endif
+
+.PHONY: clean_elf_derived_files
+clean_elf_derived_files: mem_init_clean
+
+# Clean application and all makeable libraries including the BSP.
+.PHONY : clean_all
+clean_all : clean mem_init_clean clean_libs
+
+# Include the dependency files unless the make goal is performing a clean
+# of the application.
+ifneq ($(firstword $(MAKECMDGOALS)),clean)
+ifneq ($(firstword $(MAKECMDGOALS)),clean_all)
+-include $(APP_DEPS)
+endif
+endif
+
+.PHONY : download-elf
+download-elf : $(ELF)
+	@if [ "$(DOWNLOAD)" = "none" ]; \
+	then \
+		$(ECHO) Downloading $(ELF) not supported; \
+	else \
+		$(ECHO) Info: Downloading $(ELF); \
+		$(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \
+	fi
+
+# Delete the target of a rule if it has changed and its commands exit
+# with a nonzero exit status.
+.DELETE_ON_ERROR:
+
+# Rules for flash programming commands
+PROGRAM_FLASH_SUFFIX := -program
+PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES))
+
+.PHONY : program-flash
+program-flash : $(PROGRAM_FLASH_TARGET)
+
+.PHONY : $(PROGRAM_FLASH_TARGET)
+$(PROGRAM_FLASH_TARGET) : flash
+	@if [ "$(FLASHPROG)" = "none" ]; \
+	then \
+		$(ECHO) Programming flash not supported; \
+	else \
+		$(ECHO) Info: Programming $(basename $@).flash; \
+		if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \
+		then \
+			$(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+			$(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \
+		else \
+			$(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+			$(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \
+		fi \
+	fi
+
+
+# Rules for simulating with an HDL Simulator [QSYS only]
+ifeq ($(QSYS),1)
+#Create a top level modelsim script load_sim.tcl to source generate msim_setup.tcl and copy mem initialization files
+CREATE_TOP_SIM_SCRIPT := alt-create-top-sim-script
+
+ifeq ($(VSIM),)
+VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim"
+ifeq ($(ENABLE_VSIM_GUI),1)
+VSIM := $(VSIM_EXE) -gui
+else
+VSIM := $(VSIM_EXE) -c
+endif # ENABLE_VSIM_GUI == 1
+endif # VSIM not set
+
+ifeq ($(SPD),)
+ifneq ($(ABS_QUARTUS_PROJECT_DIR),)
+ifneq ($(SOPC_NAME),)
+SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb/$(SOPC_NAME)_tb.spd
+LEGACY_SPD_LOCATION = $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd
+SPD = $(if $(wildcard $(SPD_LOCATION)),$(SPD_LOCATION),$(LEGACY_SPD_LOCATION))
+endif # SOPC_NAME set
+endif # ABS_QUARTUS_PROJECT_DIR set
+endif # SPD == empty string
+
+
+ifeq ($(LOAD_SIM_SCRIPT),)
+SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim
+LOAD_SIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/load_sim.tcl
+endif # LOAD_SIM_SCRIPT == empty string
+
+ifeq ($(MAKE_VERSION),3.81)
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE))
+else
+ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE)
+endif
+
+$(LOAD_SIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE)
+ifeq ($(SPD),)
+	$(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set)
+endif
+	@$(MKDIR) $(SIM_SCRIPT_DIR)
+	$(CREATE_TOP_SIM_SCRIPT) --spd=$(SPD) --mem-init-spd=$(abspath $(MEM_INIT_DESCRIPTOR_FILE)) --output-directory=$(SIM_SCRIPT_DIR)
+
+VSIM_COMMAND = \
+	cd $(dir $(LOAD_SIM_SCRIPT)) && \
+	$(VSIM) -do "do $(notdir $(LOAD_SIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)"
+
+.PHONY: sim
+sim: $(LOAD_SIM_SCRIPT) mem_init_generate
+ifeq ($(LOAD_SIM_SCRIPT),)
+	$(error LOAD_SIM_SCRIPT not set)
+endif
+	$(VSIM_COMMAND)
+
+endif # QSYS == 1
+
+
+
+
+#------------------------------------------------------------------------------
+#                         ELF TARGET RULE
+#------------------------------------------------------------------------------
+# Rule for constructing the executable elf file.
+$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS)
+	@$(ECHO) Info: Linking $@
+	$(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS)
+ifneq ($(DISABLE_ELFPATCH),1)
+	$(ELFPATCH) $@ $(ELF_PATCH_FLAG)
+endif
+ifneq ($(DISABLE_STACKREPORT),1)
+	@bash -c "$(STACKREPORT) $@"
+endif
+
+$(OBJDUMP_NAME) : $(ELF)
+	@$(ECHO) Info: Creating $@
+	$(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@
+
+# Rule for printing the name of the elf file
+.PHONY: print-elf-name
+print-elf-name:
+	@$(ECHO) $(ELF)
+
+
diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
index b9b3161..a8dc3e0 100644
Binary files a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf and b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf differ
diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
index 05ba38a..a192421 100644
--- a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
+++ b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
@@ -1,155 +1,149 @@
 Archive member included to satisfy reference by file (symbol)
 
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
                               obj/default/sem.o (puts)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (strlen)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (__sinit)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (__sfvwrite_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_fwalk)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-impure.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_global_impure_ptr)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_malloc_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memchr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memchr)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcpy.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memcpy)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memmove.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memmove)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memset.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (memset)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (_realloc_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) (_sbrk_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (__sread)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_write_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (__swsetup_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_close_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_fclose_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o) (__sflush_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (_free_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (errno)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_lseek_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) (__smakebuf_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_read_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) (_fstat_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) (_isatty_r)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (__divsi3)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (__mulsi3)
-../semafor_bsp/\libhal_bsp.a(alt_close.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o) (close)
-../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (strlen)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (__sinit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (__sfvwrite_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_fwalk)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-impure.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_global_impure_ptr)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_malloc_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memchr)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memcpy)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memmove)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (memset)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (_realloc_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o) (_sbrk_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (__sread)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_write_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (__swsetup_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_close_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_fclose_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o) (__sflush_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (_free_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-int_errno.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o) (errno)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_lseek_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o) (__smakebuf_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_read_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o) (_fstat_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o) (_isatty_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (__divsi3)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (__mulsi3)
+../semafor_bsp//libhal_bsp.a(alt_close.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o) (close)
+../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
                               obj/default/sem.o (alt_dcache_flush)
-../semafor_bsp/\libhal_bsp.a(alt_dev.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_fd_list)
-../semafor_bsp/\libhal_bsp.a(alt_errno.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_errno)
-../semafor_bsp/\libhal_bsp.a(alt_fstat.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) (fstat)
-../semafor_bsp/\libhal_bsp.a(alt_isatty.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) (isatty)
-../semafor_bsp/\libhal_bsp.a(alt_lseek.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) (lseek)
-../semafor_bsp/\libhal_bsp.a(alt_main.o)
+../semafor_bsp//libhal_bsp.a(alt_dev.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_fd_list)
+../semafor_bsp//libhal_bsp.a(alt_errno.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_errno)
+../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o) (fstat)
+../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o) (isatty)
+../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o) (lseek)
+../semafor_bsp//libhal_bsp.a(alt_main.o)
                               ../semafor_bsp//obj/HAL/src/crt0.o (alt_main)
-../semafor_bsp/\libhal_bsp.a(alt_malloc_lock.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) (__malloc_lock)
-../semafor_bsp/\libhal_bsp.a(alt_read.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) (read)
-../semafor_bsp/\libhal_bsp.a(alt_release_fd.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_release_fd)
-../semafor_bsp/\libhal_bsp.a(alt_sbrk.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (sbrk)
-../semafor_bsp/\libhal_bsp.a(alt_write.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) (write)
-../semafor_bsp/\libhal_bsp.a(alt_sys_init.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (alt_irq_init)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write)
-../semafor_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init)
-../semafor_bsp/\libhal_bsp.a(alt_alarm_start.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start)
-../semafor_bsp/\libhal_bsp.a(alt_dev_llist_insert.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert)
-../semafor_bsp/\libhal_bsp.a(alt_do_ctors.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (_do_ctors)
-../semafor_bsp/\libhal_bsp.a(alt_do_dtors.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (_do_dtors)
-../semafor_bsp/\libhal_bsp.a(alt_iic.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register)
-../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_iic.o) (alt_iic_isr_register)
-../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (alt_io_redirect)
-../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry)
-../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq)
-../semafor_bsp/\libhal_bsp.a(alt_irq_vars.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_iic.o) (alt_irq_active)
-../semafor_bsp/\libhal_bsp.a(alt_open.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o) (open)
-../semafor_bsp/\libhal_bsp.a(alt_tick.o)
-                              ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate)
-../semafor_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_nios2_gen2_irq_init)
-../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) (alt_exception)
-../semafor_bsp/\libhal_bsp.a(alt_find_dev.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_find_dev)
-../semafor_bsp/\libhal_bsp.a(alt_find_file.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_find_file)
-../semafor_bsp/\libhal_bsp.a(alt_get_fd.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_get_fd)
-../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) (alt_instruction_exception_entry)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (atexit)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_main.o) (exit)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
-                              ../semafor_bsp/\libhal_bsp.a(alt_find_dev.o) (memcmp)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) (__register_exitproc)
-c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (__call_exitprocs)
-../semafor_bsp/\libhal_bsp.a(alt_exit.o)
-                              c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (_exit)
-
-Allocating common symbols
-Common symbol       size              file
-
-alt_irq             0x100             ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
-errno               0x4               c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o)
+../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o) (__malloc_lock)
+../semafor_bsp//libhal_bsp.a(alt_read.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o) (read)
+../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_release_fd)
+../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o) (sbrk)
+../semafor_bsp//libhal_bsp.a(alt_write.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o) (write)
+../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (alt_irq_init)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write)
+../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init)
+../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start)
+../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert)
+../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (_do_ctors)
+../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (_do_dtors)
+../semafor_bsp//libhal_bsp.a(alt_iic.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register)
+../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic.o) (alt_iic_isr_register)
+../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (alt_io_redirect)
+../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry)
+../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o) (alt_irq)
+../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic.o) (alt_irq_active)
+../semafor_bsp//libhal_bsp.a(alt_open.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o) (open)
+../semafor_bsp//libhal_bsp.a(alt_tick.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate)
+../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_nios2_gen2_irq_init)
+../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o) (alt_exception)
+../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_find_dev)
+../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_find_file)
+../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_get_fd)
+../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o) (alt_instruction_exception_entry)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (atexit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (exit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_find_dev.o) (memcmp)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o) (__register_exitproc)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o) (__call_exitprocs)
+../semafor_bsp//libhal_bsp.a(alt_exit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o) (_exit)
 
 Memory Configuration
 
@@ -162,16 +156,16 @@ Linker script and memory map
 
 LOAD ../semafor_bsp//obj/HAL/src/crt0.o
 LOAD obj/default/sem.o
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libstdc++.a
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libm.a
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libstdc++.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libm.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
 START GROUP
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a
-LOAD ../semafor_bsp/\libhal_bsp.a
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libm.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
+LOAD ../semafor_bsp//libhal_bsp.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libm.a
 END GROUP
-LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
                 0x0000000000000000                __alt_mem_mem = 0x0
 
 .entry          0x0000000000000000       0x20
@@ -179,66 +173,66 @@ LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../li
  .entry         0x0000000000000000       0x20 ../semafor_bsp//obj/HAL/src/crt0.o
                 0x0000000000000000                __reset
 
-.exceptions     0x0000000000000020      0x210
-                [!provide]                        PROVIDE (__ram_exceptions_start, ABSOLUTE (.))
+.exceptions     0x0000000000000020      0x204
+                [!provide]                        PROVIDE (__ram_exceptions_start = ABSOLUTE (.))
                 0x0000000000000020                . = ALIGN (0x20)
  *(.irq)
  *(.exceptions.entry.label)
  .exceptions.entry.label
-                0x0000000000000020        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x0000000000000020        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
                 0x0000000000000020                alt_irq_entry
  .exceptions.entry.label
-                0x0000000000000020        0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x0000000000000020        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
                 0x0000000000000020                alt_exception
  *(.exceptions.entry.user)
  *(.exceptions.entry.ecc_fatal)
  *(.exceptions.entry)
  .exceptions.entry
-                0x0000000000000020       0x54 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x0000000000000020       0x54 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
  *(.exceptions.irqtest.user)
  *(.exceptions.irqtest)
  .exceptions.irqtest
-                0x0000000000000074       0x10 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x0000000000000074       0x10 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
  *(.exceptions.irqhandler.user)
  *(.exceptions.irqhandler)
  .exceptions.irqhandler
-                0x0000000000000084        0x4 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x0000000000000084        0x4 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
  *(.exceptions.irqreturn.user)
  *(.exceptions.irqreturn)
  .exceptions.irqreturn
-                0x0000000000000088        0x4 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x0000000000000088        0x4 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
  *(.exceptions.notirq.label)
  .exceptions.notirq.label
-                0x000000000000008c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x000000000000008c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
  *(.exceptions.notirq.user)
  *(.exceptions.notirq)
  .exceptions.notirq
-                0x000000000000008c        0x8 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x000000000000008c        0x8 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
  *(.exceptions.soft.user)
  *(.exceptions.soft)
  *(.exceptions.unknown.user)
  *(.exceptions.unknown)
  .exceptions.unknown
-                0x0000000000000094       0x14 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x0000000000000094       0x14 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
  *(.exceptions.exit.label)
  .exceptions.exit.label
-                0x00000000000000a8        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
+                0x00000000000000a8        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
  .exceptions.exit.label
-                0x00000000000000a8        0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x00000000000000a8        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
  *(.exceptions.exit.user)
  *(.exceptions.exit)
  .exceptions.exit
-                0x00000000000000a8       0x54 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
+                0x00000000000000a8       0x54 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
  *(.exceptions)
- .exceptions    0x00000000000000fc       0xd4 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
+ .exceptions    0x00000000000000fc       0xc8 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
                 0x00000000000000fc                alt_irq_handler
- .exceptions    0x00000000000001d0       0x60 ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o)
-                0x00000000000001d0                alt_instruction_exception_entry
-                [!provide]                        PROVIDE (__ram_exceptions_end, ABSOLUTE (.))
-                [!provide]                        PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions))
+ .exceptions    0x00000000000001c4       0x60 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                0x00000000000001c4                alt_instruction_exception_entry
+                [!provide]                        PROVIDE (__ram_exceptions_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_exceptions_start = LOADADDR (.exceptions))
 
-.text           0x0000000000000230     0x55b0
-                [!provide]                        PROVIDE (stext, ABSOLUTE (.))
+.text           0x0000000000000224     0x5510
+                [!provide]                        PROVIDE (stext = ABSOLUTE (.))
  *(.interp)
  *(.hash)
  *(.dynsym)
@@ -282,565 +276,566 @@ LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../li
  *(.init)
  *(.plt)
  *(.text .stub .text.* .gnu.linkonce.t.*)
- .text          0x0000000000000230       0x18 ../semafor_bsp//obj/HAL/src/crt0.o
-                0x0000000000000230                _start
- .text          0x0000000000000248       0xf0 obj/default/sem.o
-                0x0000000000000248                main
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+ .text          0x0000000000002bd0        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-int_errno.o)
+ .text          0x0000000000002bd0        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
  .text._lseek_r
-                0x0000000000002c3c       0x60 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o)
-                0x0000000000002c3c                _lseek_r
- .text          0x0000000000002c9c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o)
+                0x0000000000002bd0       0x64 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+                0x0000000000002bd0                _lseek_r
+ .text          0x0000000000002c34        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
  .text.__smakebuf_r
-                0x0000000000002c9c      0x1bc c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o)
-                0x0000000000002c9c                __smakebuf_r
- .text          0x0000000000002e58        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o)
- .text._read_r  0x0000000000002e58       0x60 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o)
-                0x0000000000002e58                _read_r
- .text          0x0000000000002eb8        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
+                0x0000000000002c34      0x1b0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+                0x0000000000002c34                __smakebuf_r
+ .text.__swhatbuf_r
+                0x0000000000002de4       0x98 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+                0x0000000000002de4                __swhatbuf_r
+ .text          0x0000000000002e7c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .text._read_r  0x0000000000002e7c       0x64 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+                0x0000000000002e7c                _read_r
+ .text          0x0000000000002ee0        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
  .text._fstat_r
-                0x0000000000002eb8       0x5c c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
-                0x0000000000002eb8                _fstat_r
- .text          0x0000000000002f14        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
+                0x0000000000002ee0       0x60 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+                0x0000000000002ee0                _fstat_r
+ .text          0x0000000000002f40        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
  .text._isatty_r
-                0x0000000000002f14       0x54 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
-                0x0000000000002f14                _isatty_r
- .text          0x0000000000002f68      0x1b4 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o)
-                0x0000000000002f68                __divsi3
-                0x0000000000002fec                __modsi3
-                0x0000000000003060                __udivsi3
-                0x00000000000030c4                __umodsi3
- .text          0x000000000000311c       0x28 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o)
-                0x000000000000311c                __mulsi3
- .text          0x0000000000003144      0x114 ../semafor_bsp/\libhal_bsp.a(alt_close.o)
-                0x0000000000003180                close
- .text          0x0000000000003258       0x28 ../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o)
-                0x0000000000003258                alt_dcache_flush
- .text          0x0000000000003280       0x2c ../semafor_bsp/\libhal_bsp.a(alt_dev.o)
- .text          0x00000000000032ac        0x0 ../semafor_bsp/\libhal_bsp.a(alt_errno.o)
- .text          0x00000000000032ac       0xf4 ../semafor_bsp/\libhal_bsp.a(alt_fstat.o)
-                0x00000000000032e8                fstat
- .text          0x00000000000033a0       0xe8 ../semafor_bsp/\libhal_bsp.a(alt_isatty.o)
-                0x00000000000033dc                isatty
- .text          0x0000000000003488      0x118 ../semafor_bsp/\libhal_bsp.a(alt_lseek.o)
-                0x00000000000034c4                lseek
- .text          0x00000000000035a0       0x7c ../semafor_bsp/\libhal_bsp.a(alt_main.o)
-                0x00000000000035a0                alt_main
- .text          0x000000000000361c       0x48 ../semafor_bsp/\libhal_bsp.a(alt_malloc_lock.o)
-                0x000000000000361c                __malloc_lock
-                0x0000000000003640                __malloc_unlock
- .text          0x0000000000003664      0x140 ../semafor_bsp/\libhal_bsp.a(alt_read.o)
-                0x00000000000036a0                read
- .text          0x00000000000037a4       0x84 ../semafor_bsp/\libhal_bsp.a(alt_release_fd.o)
-                0x00000000000037a4                alt_release_fd
- .text          0x0000000000003828       0xb0 ../semafor_bsp/\libhal_bsp.a(alt_sbrk.o)
-                0x0000000000003828                sbrk
- .text          0x00000000000038d8      0x13c ../semafor_bsp/\libhal_bsp.a(alt_write.o)
-                0x0000000000003914                write
- .text          0x0000000000003a14       0xcc ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o)
-                0x0000000000003a48                alt_irq_init
-                0x0000000000003a80                alt_sys_init
- .text          0x0000000000003ae0      0x164 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
-                0x0000000000003ae0                altera_avalon_jtag_uart_read_fd
-                0x0000000000003b40                altera_avalon_jtag_uart_write_fd
-                0x0000000000003ba0                altera_avalon_jtag_uart_close_fd
-                0x0000000000003bf0                altera_avalon_jtag_uart_ioctl_fd
- .text          0x0000000000003c44      0x3d4 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o)
-                0x0000000000003c44                altera_avalon_jtag_uart_init
-                0x0000000000003fb0                altera_avalon_jtag_uart_close
- .text          0x0000000000004018       0xf0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
-                0x0000000000004018                altera_avalon_jtag_uart_ioctl
- .text          0x0000000000004108      0x21c ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o)
-                0x0000000000004108                altera_avalon_jtag_uart_read
- .text          0x0000000000004324      0x224 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o)
-                0x0000000000004324                altera_avalon_jtag_uart_write
- .text          0x0000000000004548       0xf4 ../semafor_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o)
-                0x00000000000045c0                alt_avalon_timer_sc_init
- .text          0x000000000000463c      0x12c ../semafor_bsp/\libhal_bsp.a(alt_alarm_start.o)
-                0x000000000000463c                alt_alarm_start
- .text          0x0000000000004768       0xe0 ../semafor_bsp/\libhal_bsp.a(alt_dev_llist_insert.o)
-                0x00000000000047a4                alt_dev_llist_insert
- .text          0x0000000000004848       0x60 ../semafor_bsp/\libhal_bsp.a(alt_do_ctors.o)
-                0x0000000000004848                _do_ctors
- .text          0x00000000000048a8       0x60 ../semafor_bsp/\libhal_bsp.a(alt_do_dtors.o)
-                0x00000000000048a8                _do_dtors
- .text          0x0000000000004908      0x1b0 ../semafor_bsp/\libhal_bsp.a(alt_iic.o)
-                0x0000000000004908                alt_ic_isr_register
-                0x0000000000004958                alt_ic_irq_enable
-                0x00000000000049e0                alt_ic_irq_disable
-                0x0000000000004a6c                alt_ic_irq_enabled
- .text          0x0000000000004ab8       0xf0 ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o)
-                0x0000000000004ab8                alt_iic_isr_register
- .text          0x0000000000004ba8      0x160 ../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o)
-                0x0000000000004c8c                alt_io_redirect
- .text          0x0000000000004d08        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
- .text          0x0000000000004d08        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
- .text          0x0000000000004d08        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_vars.o)
- .text          0x0000000000004d08      0x284 ../semafor_bsp/\libhal_bsp.a(alt_open.o)
-                0x0000000000004e30                open
- .text          0x0000000000004f8c      0x1a4 ../semafor_bsp/\libhal_bsp.a(alt_tick.o)
-                0x0000000000004f8c                alt_alarm_stop
-                0x0000000000005028                alt_tick
- .text          0x0000000000005130       0x24 ../semafor_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o)
-                0x0000000000005130                altera_nios2_gen2_irq_init
- .text          0x0000000000005154        0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
- .text          0x0000000000005154       0x90 ../semafor_bsp/\libhal_bsp.a(alt_find_dev.o)
-                0x0000000000005154                alt_find_dev
- .text          0x00000000000051e4      0x108 ../semafor_bsp/\libhal_bsp.a(alt_find_file.o)
-                0x00000000000051e4                alt_find_file
- .text          0x00000000000052ec       0xc4 ../semafor_bsp/\libhal_bsp.a(alt_get_fd.o)
-                0x00000000000052ec                alt_get_fd
- .text          0x00000000000053b0       0x9c ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o)
-                0x00000000000053b0                alt_exception_cause_generated_bad_addr
- .text          0x000000000000544c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
- .text.atexit   0x000000000000544c       0x14 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
-                0x000000000000544c                atexit
- .text          0x0000000000005460        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
- .text.exit     0x0000000000005460       0x38 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
-                0x0000000000005460                exit
- .text          0x0000000000005498        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
- .text.memcmp   0x0000000000005498       0x7c c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
-                0x0000000000005498                memcmp
- .text          0x0000000000005514        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o)
+                0x0000000000002f40       0x58 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+                0x0000000000002f40                _isatty_r
+ .text          0x0000000000002f98      0x1b4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+                0x0000000000002f98                __divsi3
+                0x0000000000003018                __modsi3
+                0x000000000000308c                __udivsi3
+                0x00000000000030f0                __umodsi3
+ .text          0x000000000000314c       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+                0x000000000000314c                __mulsi3
+ .text          0x0000000000003174      0x118 ../semafor_bsp//libhal_bsp.a(alt_close.o)
+                0x00000000000031b0                close
+ .text          0x000000000000328c       0x28 ../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
+                0x000000000000328c                alt_dcache_flush
+ .text          0x00000000000032b4       0x2c ../semafor_bsp//libhal_bsp.a(alt_dev.o)
+ .text          0x00000000000032e0        0x0 ../semafor_bsp//libhal_bsp.a(alt_errno.o)
+ .text          0x00000000000032e0       0xf8 ../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+                0x000000000000331c                fstat
+ .text          0x00000000000033d8       0xec ../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+                0x0000000000003414                isatty
+ .text          0x00000000000034c4      0x11c ../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+                0x0000000000003500                lseek
+ .text          0x00000000000035e0       0x7c ../semafor_bsp//libhal_bsp.a(alt_main.o)
+                0x00000000000035e0                alt_main
+ .text          0x000000000000365c       0x48 ../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+                0x000000000000365c                __malloc_lock
+                0x0000000000003680                __malloc_unlock
+ .text          0x00000000000036a4      0x144 ../semafor_bsp//libhal_bsp.a(alt_read.o)
+                0x00000000000036e0                read
+ .text          0x00000000000037e8       0x70 ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+                0x00000000000037e8                alt_release_fd
+ .text          0x0000000000003858       0xb8 ../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+                0x0000000000003858                sbrk
+ .text          0x0000000000003910      0x140 ../semafor_bsp//libhal_bsp.a(alt_write.o)
+                0x000000000000394c                write
+ .text          0x0000000000003a50       0xd0 ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+                0x0000000000003a84                alt_irq_init
+                0x0000000000003ac0                alt_sys_init
+ .text          0x0000000000003b20      0x164 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+                0x0000000000003b20                altera_avalon_jtag_uart_read_fd
+                0x0000000000003b80                altera_avalon_jtag_uart_write_fd
+                0x0000000000003be0                altera_avalon_jtag_uart_close_fd
+                0x0000000000003c30                altera_avalon_jtag_uart_ioctl_fd
+ .text          0x0000000000003c84      0x3d4 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+                0x0000000000003c84                altera_avalon_jtag_uart_init
+                0x0000000000003ff0                altera_avalon_jtag_uart_close
+ .text          0x0000000000004058       0xf4 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+                0x0000000000004058                altera_avalon_jtag_uart_ioctl
+ .text          0x000000000000414c      0x220 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+                0x000000000000414c                altera_avalon_jtag_uart_read
+ .text          0x000000000000436c      0x228 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+                0x000000000000436c                altera_avalon_jtag_uart_write
+ .text          0x0000000000004594      0x100 ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+                0x0000000000004610                alt_avalon_timer_sc_init
+ .text          0x0000000000004694      0x134 ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+                0x0000000000004694                alt_alarm_start
+ .text          0x00000000000047c8       0xe4 ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+                0x0000000000004804                alt_dev_llist_insert
+ .text          0x00000000000048ac       0x64 ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+                0x00000000000048ac                _do_ctors
+ .text          0x0000000000004910       0x64 ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+                0x0000000000004910                _do_dtors
+ .text          0x0000000000004974      0x1b0 ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+                0x0000000000004974                alt_ic_isr_register
+                0x00000000000049c4                alt_ic_irq_enable
+                0x0000000000004a4c                alt_ic_irq_disable
+                0x0000000000004ad8                alt_ic_irq_enabled
+ .text          0x0000000000004b24       0xe8 ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+                0x0000000000004b24                alt_iic_isr_register
+ .text          0x0000000000004c0c      0x150 ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+                0x0000000000004ce0                alt_io_redirect
+ .text          0x0000000000004d5c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .text          0x0000000000004d5c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .text          0x0000000000004d5c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+ .text          0x0000000000004d5c      0x278 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+                0x0000000000004e74                open
+ .text          0x0000000000004fd4      0x1ac ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+                0x0000000000004fd4                alt_alarm_stop
+                0x0000000000005078                alt_tick
+ .text          0x0000000000005180       0x24 ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+                0x0000000000005180                altera_nios2_gen2_irq_init
+ .text          0x00000000000051a4        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .text          0x00000000000051a4       0x90 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+                0x00000000000051a4                alt_find_dev
+ .text          0x0000000000005234      0x108 ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+                0x0000000000005234                alt_find_file
+ .text          0x000000000000533c       0xb8 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+                0x000000000000533c                alt_get_fd
+ .text          0x00000000000053f4       0x98 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                0x00000000000053f4                alt_exception_cause_generated_bad_addr
+ .text          0x000000000000548c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .text.atexit   0x000000000000548c       0x14 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+                0x000000000000548c                atexit
+ .text          0x00000000000054a0        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .text.exit     0x00000000000054a0       0x34 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+                0x00000000000054a0                exit
+ .text          0x00000000000054d4        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .text.memcmp   0x00000000000054d4       0x78 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+                0x00000000000054d4                memcmp
+ .text          0x000000000000554c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
  .text.__register_exitproc
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-                0x0000000000005514                __register_exitproc
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+                0x000000000000554c       0x90 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+                0x000000000000554c                __register_exitproc
+ .text          0x00000000000055dc        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
  .text.__call_exitprocs
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-                0x000000000000562c                __call_exitprocs
- .text          0x00000000000057ac       0x34 ../semafor_bsp/\libhal_bsp.a(alt_exit.o)
-                0x00000000000057ac                _exit
+                0x00000000000055dc      0x120 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+                0x00000000000055dc                __call_exitprocs
+ .text          0x00000000000056fc       0x38 ../semafor_bsp//libhal_bsp.a(alt_exit.o)
+                0x00000000000056fc                _exit
  *(.gnu.warning.*)
  *(.fini)
-                [!provide]                        PROVIDE (__etext, ABSOLUTE (.))
-                [!provide]                        PROVIDE (_etext, ABSOLUTE (.))
-                [!provide]                        PROVIDE (etext, ABSOLUTE (.))
+                [!provide]                        PROVIDE (__etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (etext = ABSOLUTE (.))
  *(.eh_frame_hdr)
-                0x00000000000057e0                . = ALIGN (0x4)
-                [!provide]                        PROVIDE (__preinit_array_start, ABSOLUTE (.))
+                0x0000000000005734                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (__preinit_array_start = ABSOLUTE (.))
  *(.preinit_array)
-                [!provide]                        PROVIDE (__preinit_array_end, ABSOLUTE (.))
-                [!provide]                        PROVIDE (__init_array_start, ABSOLUTE (.))
+                [!provide]                        PROVIDE (__preinit_array_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__init_array_start = ABSOLUTE (.))
  *(.init_array)
-                [!provide]                        PROVIDE (__init_array_end, ABSOLUTE (.))
-                [!provide]                        PROVIDE (__fini_array_start, ABSOLUTE (.))
+                [!provide]                        PROVIDE (__init_array_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__fini_array_start = ABSOLUTE (.))
  *(.fini_array)
-                [!provide]                        PROVIDE (__fini_array_end, ABSOLUTE (.))
+                [!provide]                        PROVIDE (__fini_array_end = ABSOLUTE (.))
  *(.eh_frame)
  *(.gcc_except_table .gcc_except_table.*)
  *(.dynamic)
-                0x00000000000057e0                PROVIDE (__CTOR_LIST__, ABSOLUTE (.))
+                0x0000000000005734                PROVIDE (__CTOR_LIST__ = ABSOLUTE (.))
  *(.ctors)
- *(SORT(.ctors.*))
-                0x00000000000057e0                PROVIDE (__CTOR_END__, ABSOLUTE (.))
-                0x00000000000057e0                PROVIDE (__DTOR_LIST__, ABSOLUTE (.))
+ *(SORT_BY_NAME(.ctors.*))
+                0x0000000000005734                PROVIDE (__CTOR_END__ = ABSOLUTE (.))
+                0x0000000000005734                PROVIDE (__DTOR_LIST__ = ABSOLUTE (.))
  *(.dtors)
- *(SORT(.dtors.*))
-                0x00000000000057e0                PROVIDE (__DTOR_END__, ABSOLUTE (.))
+ *(SORT_BY_NAME(.dtors.*))
+                0x0000000000005734                PROVIDE (__DTOR_END__ = ABSOLUTE (.))
  *(.jcr)
-                0x00000000000057e0                . = ALIGN (0x4)
+                0x0000000000005734                . = ALIGN (0x4)
 
-.rodata         0x00000000000057e0       0x7c
-                [!provide]                        PROVIDE (__ram_rodata_start, ABSOLUTE (.))
-                0x00000000000057e0                . = ALIGN (0x4)
+.rodata         0x0000000000005734       0x78
+                [!provide]                        PROVIDE (__ram_rodata_start = ABSOLUTE (.))
+                0x0000000000005734                . = ALIGN (0x4)
  *(.rodata .rodata.* .gnu.linkonce.r.*)
- .rodata        0x00000000000057e0       0x46 obj/default/sem.o
-                0x00000000000057e0                divisors
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- .rodata.str1.4
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- *fill*         0x000000000000582a        0x2 
- .rodata.str1.4
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-                                          0x2 (size before relaxing)
- .rodata        0x0000000000005830        0xa ../semafor_bsp/\libhal_bsp.a(alt_dev.o)
- *fill*         0x000000000000583a        0x2 
- .rodata        0x000000000000583c        0xf ../semafor_bsp/\libhal_bsp.a(alt_main.o)
- *fill*         0x000000000000584b        0x1 
- .rodata        0x000000000000584c        0xf ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o)
+ .rodata        0x0000000000005734       0x46 obj/default/sem.o
+                0x0000000000005734                divisors
+ *fill*         0x000000000000577a        0x2 
+ .rodata._puts_r.str1.4
+                0x000000000000577c        0x2 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ *fill*         0x000000000000577e        0x2 
+ .rodata        0x0000000000005780        0xa ../semafor_bsp//libhal_bsp.a(alt_dev.o)
+ *fill*         0x000000000000578a        0x2 
+ .rodata        0x000000000000578c        0xf ../semafor_bsp//libhal_bsp.a(alt_main.o)
+ *fill*         0x000000000000579b        0x1 
+ .rodata        0x000000000000579c        0xf ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
  *(.rodata1)
-                0x000000000000585c                . = ALIGN (0x4)
- *fill*         0x000000000000585b        0x1 
-                [!provide]                        PROVIDE (__ram_rodata_end, ABSOLUTE (.))
-                [!provide]                        PROVIDE (__flash_rodata_start, LOADADDR (.rodata))
+                0x00000000000057ac                . = ALIGN (0x4)
+ *fill*         0x00000000000057ab        0x1 
+                [!provide]                        PROVIDE (__ram_rodata_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_rodata_start = LOADADDR (.rodata))
 
-.rwdata         0x000000000000585c     0x1a6c
-                [!provide]                        PROVIDE (__ram_rwdata_start, ABSOLUTE (.))
-                0x000000000000585c                . = ALIGN (0x4)
+.rwdata         0x00000000000057ac     0x1a6c
+                [!provide]                        PROVIDE (__ram_rwdata_start = ABSOLUTE (.))
+                0x00000000000057ac                . = ALIGN (0x4)
  *(.got.plt)
  *(.got)
  *(.data1)
  *(.data .data.* .gnu.linkonce.d.*)
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- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_close.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_dev.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_errno.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_fstat.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_isatty.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_lseek.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_main.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_malloc_lock.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_read.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_release_fd.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_sbrk.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_write.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_alarm_start.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_dev_llist_insert.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_do_ctors.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_do_dtors.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_iic.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_vars.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_open.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_tick.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_find_dev.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_find_file.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_get_fd.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o)
- .bss           0x000000000000731c        0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o)
- .bss           0x000000000000731c        0x0 ../semafor_bsp/\libhal_bsp.a(alt_exit.o)
+                0x0000000000007244       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+                0x0000000000007244                __malloc_current_mallinfo
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-int_errno.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .bss           0x000000000000726c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_close.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_dev.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_errno.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_main.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_read.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_write.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+ .bss           0x000000000000726c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .bss           0x000000000000726c      0x100 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+                0x000000000000726c                alt_irq
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .bss           0x000000000000736c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .bss           0x000000000000736c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .bss           0x000000000000736c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .bss           0x000000000000736c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .bss           0x000000000000736c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+ .bss           0x000000000000736c        0x0 ../semafor_bsp//libhal_bsp.a(alt_exit.o)
  *(COMMON)
- COMMON         0x000000000000731c      0x100 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
-                0x000000000000731c                alt_irq
-                0x000000000000741c                . = ALIGN (0x4)
-                0x000000000000741c                __bss_end = ABSOLUTE (.)
+                0x000000000000736c                . = ALIGN (0x4)
+                0x000000000000736c                __bss_end = ABSOLUTE (.)
 
-.mem            0x000000000000741c        0x0
-                [!provide]                        PROVIDE (_alt_partition_mem_start, ABSOLUTE (.))
+.mem            0x000000000000736c        0x0
+                [!provide]                        PROVIDE (_alt_partition_mem_start = ABSOLUTE (.))
  *(.mem .mem. mem.*)
-                0x000000000000741c                . = ALIGN (0x4)
-                [!provide]                        PROVIDE (_alt_partition_mem_end, ABSOLUTE (.))
-                0x000000000000741c                _end = ABSOLUTE (.)
-                0x000000000000741c                end = ABSOLUTE (.)
-                0x000000000000741c                __alt_stack_base = ABSOLUTE (.)
-                [!provide]                        PROVIDE (_alt_partition_mem_load_addr, LOADADDR (.mem))
+                0x000000000000736c                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_mem_end = ABSOLUTE (.))
+                0x000000000000736c                _end = ABSOLUTE (.)
+                0x000000000000736c                end = ABSOLUTE (.)
+                0x000000000000736c                __alt_stack_base = ABSOLUTE (.)
+                [!provide]                        PROVIDE (_alt_partition_mem_load_addr = LOADADDR (.mem))
 
 .stab
  *(.stab)
@@ -860,80 +855,80 @@ LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../li
 .stab.indexstr
  *(.stab.indexstr)
 
-.comment        0x0000000000000000       0x23
+.comment        0x0000000000000000       0x2d
  *(.comment)
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- .comment       0x0000000000000023       0x24 ../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o)
- .comment       0x0000000000000023       0x24 ../semafor_bsp/\libhal_bsp.a(alt_dev.o)
- .comment       0x0000000000000023       0x24 ../semafor_bsp/\libhal_bsp.a(alt_errno.o)
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+ .comment       0x0000000000000000       0x2d obj/default/sem.o
+                                         0x2e (size before relaxing)
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+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_close.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dev.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_errno.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_main.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_read.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_write.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_open.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_exit.o)
 
 .debug
  *(.debug)
@@ -947,639 +942,644 @@ LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../li
 .debug_sfnames
  *(.debug_sfnames)
 
-.debug_aranges  0x0000000000000000      0x9f0
+.debug_aranges  0x0000000000000000      0xa00
  *(.debug_aranges)
  .debug_aranges
                 0x0000000000000000       0x28 ../semafor_bsp//obj/HAL/src/crt0.o
  .debug_aranges
                 0x0000000000000028       0x20 obj/default/sem.o
  .debug_aranges
-                0x0000000000000048       0x28 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o)
+                0x0000000000000048       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
  .debug_aranges
-                0x0000000000000070       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o)
+                0x0000000000000070       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
  .debug_aranges
-                0x0000000000000090       0x68 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o)
+                0x0000000000000090       0x68 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
  .debug_aranges
-                0x00000000000000f8       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o)
+                0x00000000000000f8       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
  .debug_aranges
-                0x0000000000000118       0x28 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o)
+                0x0000000000000118       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
  .debug_aranges
-                0x0000000000000140       0x18 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-impure.o)
+                0x0000000000000140       0x18 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-impure.o)
  .debug_aranges
-                0x0000000000000158       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o)
+                0x0000000000000158       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
  .debug_aranges
-                0x0000000000000178       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memchr.o)
+                0x0000000000000178       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
  .debug_aranges
-                0x0000000000000198       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcpy.o)
+                0x0000000000000198       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
  .debug_aranges
-                0x00000000000001b8       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memmove.o)
+                0x00000000000001b8       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
  .debug_aranges
-                0x00000000000001d8       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memset.o)
+                0x00000000000001d8       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
  .debug_aranges
-                0x00000000000001f8       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o)
+                0x00000000000001f8       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
  .debug_aranges
-                0x0000000000000218       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o)
+                0x0000000000000218       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
  .debug_aranges
-                0x0000000000000238       0x40 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o)
+                0x0000000000000238       0x40 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
  .debug_aranges
-                0x0000000000000278       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o)
+                0x0000000000000278       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
  .debug_aranges
-                0x0000000000000298       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o)
+                0x0000000000000298       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
  .debug_aranges
-                0x00000000000002b8       0x20 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o)
+                0x00000000000002b8       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
  .debug_aranges
-                0x00000000000002d8       0x28 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o)
+                0x00000000000002d8       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
  .debug_aranges
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  .debug_aranges
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  .debug_aranges
-                0x0000000000000358       0x18 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o)
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  .debug_aranges
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+ .debug_abbrev  0x000000000000438d       0xea ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
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+ .debug_frame   0x0000000000000af0       0x2c ../semafor_bsp//libhal_bsp.a(alt_main.o)
+ .debug_frame   0x0000000000000b1c       0x58 ../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+ .debug_frame   0x0000000000000b74       0x60 ../semafor_bsp//libhal_bsp.a(alt_read.o)
+ .debug_frame   0x0000000000000bd4       0x34 ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+ .debug_frame   0x0000000000000c08       0x34 ../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+ .debug_frame   0x0000000000000c3c       0x60 ../semafor_bsp//libhal_bsp.a(alt_write.o)
+ .debug_frame   0x0000000000000c9c       0x88 ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+ .debug_frame   0x0000000000000d24       0xb0 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+ .debug_frame   0x0000000000000dd4       0xa4 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .debug_frame   0x0000000000000e78       0x34 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+ .debug_frame   0x0000000000000eac       0x38 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .debug_frame   0x0000000000000ee4       0x38 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+ .debug_frame   0x0000000000000f1c       0x60 ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+ .debug_frame   0x0000000000000f7c       0x34 ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+ .debug_frame   0x0000000000000fb0       0x60 ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+ .debug_frame   0x0000000000001010       0x38 ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+ .debug_frame   0x0000000000001048       0x38 ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+ .debug_frame   0x0000000000001080       0xa4 ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+ .debug_frame   0x0000000000001124       0x38 ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+ .debug_frame   0x000000000000115c       0x60 ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+ .debug_frame   0x00000000000011bc       0x38 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .debug_frame   0x00000000000011f4       0x84 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+ .debug_frame   0x0000000000001278       0x5c ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+ .debug_frame   0x00000000000012d4       0x34 ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_frame   0x0000000000001308       0x38 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+ .debug_frame   0x0000000000001340       0x38 ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+ .debug_frame   0x0000000000001378       0x34 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+ .debug_frame   0x00000000000013ac       0x5c ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .debug_frame   0x0000000000001408       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .debug_frame   0x0000000000001428       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .debug_frame   0x0000000000001450       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .debug_frame   0x0000000000001470       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .debug_frame   0x0000000000001490       0x54 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+ .debug_frame   0x00000000000014e4       0x2c ../semafor_bsp//libhal_bsp.a(alt_exit.o)
 
-.debug_str      0x0000000000000000     0x2692
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- .debug_loc     0x0000000000002e2d       0x58 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o)
- .debug_loc     0x0000000000002e85      0x33a c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o)
- .debug_loc     0x00000000000031bf       0xb0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o)
- .debug_loc     0x000000000000326f       0xa2 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o)
- .debug_loc     0x0000000000003311       0x58 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o)
- .debug_loc     0x0000000000003369      0x199 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o)
- .debug_loc     0x0000000000003502      0x36f c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o)
- .debug_loc     0x0000000000003871      0x4e7 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o)
- .debug_loc     0x0000000000003d58       0xb0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o)
- .debug_loc     0x0000000000003e08      0x122 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o)
- .debug_loc     0x0000000000003f2a       0xb0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o)
- .debug_loc     0x0000000000003fda       0x84 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
- .debug_loc     0x000000000000405e       0x58 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
- .debug_loc     0x00000000000040b6      0x4ce c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o)
- .debug_loc     0x0000000000004584       0x93 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o)
- .debug_loc     0x0000000000004617       0x2c c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
- .debug_loc     0x0000000000004643       0x1e c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
- .debug_loc     0x0000000000004661      0x126 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
- .debug_loc     0x0000000000004787      0x185 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o)
- .debug_loc     0x000000000000490c      0x1ce c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o)
+ .debug_loc     0x0000000000000000      0x143 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .debug_loc     0x0000000000000143       0x73 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .debug_loc     0x00000000000001b6      0x339 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .debug_loc     0x00000000000004ef      0x748 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .debug_loc     0x0000000000000c37      0x1eb /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .debug_loc     0x0000000000000e22      0xd34 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+ .debug_loc     0x0000000000001b56      0x240 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+ .debug_loc     0x0000000000001d96      0x347 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+ .debug_loc     0x00000000000020dd      0x3ff /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+ .debug_loc     0x00000000000024dc      0x1b5 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+ .debug_loc     0x0000000000002691     0x11ff /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+ .debug_loc     0x0000000000003890       0x89 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+ .debug_loc     0x0000000000003919      0x43c /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+ .debug_loc     0x0000000000003d55       0xed /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+ .debug_loc     0x0000000000003e42       0xd4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+ .debug_loc     0x0000000000003f16       0x89 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+ .debug_loc     0x0000000000003f9f      0x2fc /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+ .debug_loc     0x000000000000429b      0x4c6 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+ .debug_loc     0x0000000000004761      0x614 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+ .debug_loc     0x0000000000004d75       0xed /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+ .debug_loc     0x0000000000004e62      0x449 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .debug_loc     0x00000000000052ab       0xed /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .debug_loc     0x0000000000005398       0xbb /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .debug_loc     0x0000000000005453       0x89 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .debug_loc     0x00000000000054dc      0x5d0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .debug_loc     0x0000000000005aac       0xa7 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+ .debug_loc     0x0000000000005b53       0x32 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .debug_loc     0x0000000000005b85       0x22 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .debug_loc     0x0000000000005ba7      0x158 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .debug_loc     0x0000000000005cff       0xf7 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .debug_loc     0x0000000000005df6      0x1ca /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
 
 .debug_macinfo
  *(.debug_macinfo)
@@ -1599,47 +1599,48 @@ LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../li
 .debug_alt_sim_info
  *(.debug_alt_sim_info)
                 0x0000000000020000                __alt_data_end = 0x20000
-                0x0000000000020000                PROVIDE (__alt_stack_pointer, __alt_data_end)
-                [!provide]                        PROVIDE (__alt_stack_limit, __alt_stack_base)
-                0x000000000000741c                PROVIDE (__alt_heap_start, end)
-                0x0000000000020000                PROVIDE (__alt_heap_limit, 0x20000)
+                0x0000000000020000                PROVIDE (__alt_stack_pointer = __alt_data_end)
+                [!provide]                        PROVIDE (__alt_stack_limit = __alt_stack_base)
+                0x000000000000736c                PROVIDE (__alt_heap_start = end)
+                0x0000000000020000                PROVIDE (__alt_heap_limit = 0x20000)
 OUTPUT(RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf elf32-littlenios2)
+LOAD linker stubs
 
-.debug_ranges   0x0000000000000000      0x680
+.debug_ranges   0x0000000000000000      0x8a8
  .debug_ranges  0x0000000000000000       0x20 ../semafor_bsp//obj/HAL/src/crt0.o
- .debug_ranges  0x0000000000000020       0x30 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o)
- .debug_ranges  0x0000000000000050       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o)
- .debug_ranges  0x0000000000000060       0xc8 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o)
- .debug_ranges  0x0000000000000128       0x30 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o)
- .debug_ranges  0x0000000000000158       0x18 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o)
- .debug_ranges  0x0000000000000170       0x48 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o)
- .debug_ranges  0x00000000000001b8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memchr.o)
- .debug_ranges  0x00000000000001c8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcpy.o)
- .debug_ranges  0x00000000000001d8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memmove.o)
- .debug_ranges  0x00000000000001e8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memset.o)
- .debug_ranges  0x00000000000001f8      0x148 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o)
- .debug_ranges  0x0000000000000340       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o)
- .debug_ranges  0x0000000000000350       0x30 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o)
- .debug_ranges  0x0000000000000380       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o)
- .debug_ranges  0x0000000000000390       0x40 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o)
- .debug_ranges  0x00000000000003d0       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o)
- .debug_ranges  0x00000000000003e0       0x48 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o)
- .debug_ranges  0x0000000000000428       0x58 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o)
- .debug_ranges  0x0000000000000480       0x18 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o)
- .debug_ranges  0x0000000000000498       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o)
- .debug_ranges  0x00000000000004a8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o)
- .debug_ranges  0x00000000000004b8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o)
- .debug_ranges  0x00000000000004c8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o)
- .debug_ranges  0x00000000000004d8       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o)
- .debug_ranges  0x00000000000004e8       0x60 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o)
- .debug_ranges  0x0000000000000548       0x30 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o)
- .debug_ranges  0x0000000000000578       0x18 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o)
- .debug_ranges  0x0000000000000590       0x28 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o)
- .debug_ranges  0x00000000000005b8       0x10 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o)
- .debug_ranges  0x00000000000005c8       0x30 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o)
- .debug_ranges  0x00000000000005f8       0x18 ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o)
- .debug_ranges  0x0000000000000610       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o)
- .debug_ranges  0x0000000000000620       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o)
- .debug_ranges  0x0000000000000630       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o)
- .debug_ranges  0x0000000000000640       0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o)
- .debug_ranges  0x0000000000000650       0x30 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o)
+ .debug_ranges  0x0000000000000020       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .debug_ranges  0x0000000000000050       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .debug_ranges  0x0000000000000060      0x148 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .debug_ranges  0x00000000000001a8       0x38 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .debug_ranges  0x00000000000001e0       0x18 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .debug_ranges  0x00000000000001f8       0x60 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+ .debug_ranges  0x0000000000000258       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+ .debug_ranges  0x0000000000000268       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+ .debug_ranges  0x0000000000000278       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+ .debug_ranges  0x0000000000000288       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+ .debug_ranges  0x0000000000000298      0x160 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+ .debug_ranges  0x00000000000003f8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+ .debug_ranges  0x0000000000000408       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+ .debug_ranges  0x0000000000000438       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+ .debug_ranges  0x0000000000000448       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+ .debug_ranges  0x0000000000000478       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+ .debug_ranges  0x0000000000000488       0x90 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+ .debug_ranges  0x0000000000000518       0xc8 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+ .debug_ranges  0x00000000000005e0       0x18 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+ .debug_ranges  0x00000000000005f8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+ .debug_ranges  0x0000000000000608       0xc0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .debug_ranges  0x00000000000006c8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .debug_ranges  0x00000000000006d8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .debug_ranges  0x00000000000006e8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .debug_ranges  0x00000000000006f8       0x70 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .debug_ranges  0x0000000000000768       0x30 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .debug_ranges  0x0000000000000798       0x18 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .debug_ranges  0x00000000000007b0       0x28 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .debug_ranges  0x00000000000007d8       0x10 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .debug_ranges  0x00000000000007e8       0x30 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .debug_ranges  0x0000000000000818       0x18 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .debug_ranges  0x0000000000000830       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .debug_ranges  0x0000000000000840       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .debug_ranges  0x0000000000000850       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .debug_ranges  0x0000000000000860       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .debug_ranges  0x0000000000000870       0x38 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
index 0d308f7..5386a40 100644
--- a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
+++ b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
@@ -3,78 +3,78 @@ RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf:     file format elf32-littlenios2
 RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
 architecture: nios2:r1, flags 0x00000112:
 EXEC_P, HAS_SYMS, D_PAGED
-start address 0x00000230
+start address 0x00000224
 
 Program Header:
     LOAD off    0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12
          filesz 0x00000020 memsz 0x00000020 flags r-x
     LOAD off    0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12
-         filesz 0x000072a8 memsz 0x000073fc flags rwx
+         filesz 0x000071f8 memsz 0x0000734c flags rwx
 
 Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .entry        00000020  00000000  00000000  00001000  2**5
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  1 .exceptions   00000210  00000020  00000020  00001020  2**2
+  1 .exceptions   00000204  00000020  00000020  00001020  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .text         000055b0  00000230  00000230  00001230  2**2
+  2 .text         00005510  00000224  00000224  00001224  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  3 .rodata       0000007c  000057e0  000057e0  000067e0  2**2
+  3 .rodata       00000078  00005734  00005734  00006734  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  4 .rwdata       00001a6c  0000585c  0000585c  0000685c  2**2
+  4 .rwdata       00001a6c  000057ac  000057ac  000067ac  2**2
                   CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
-  5 .bss          00000154  000072c8  000072c8  000082c8  2**2
+  5 .bss          00000154  00007218  00007218  00008218  2**2
                   ALLOC, SMALL_DATA
-  6 .mem          00000000  0000741c  0000741c  000082c8  2**0
+  6 .mem          00000000  0000736c  0000736c  00008218  2**0
                   CONTENTS
-  7 .comment      00000023  00000000  00000000  000082c8  2**0
+  7 .comment      0000002d  00000000  00000000  00008218  2**0
                   CONTENTS, READONLY
-  8 .debug_aranges 000009f0  00000000  00000000  000082f0  2**3
-                  CONTENTS, READONLY, DEBUGGING
-  9 .debug_info   00016367  00000000  00000000  00008ce0  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 10 .debug_abbrev 00005fe5  00000000  00000000  0001f047  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 11 .debug_line   00006941  00000000  00000000  0002502c  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 12 .debug_frame  00001504  00000000  00000000  0002b970  2**2
-                  CONTENTS, READONLY, DEBUGGING
- 13 .debug_str    00002692  00000000  00000000  0002ce74  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 14 .debug_loc    00004ada  00000000  00000000  0002f506  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000680  00000000  00000000  00033fe0  2**3
-                  CONTENTS, READONLY, DEBUGGING
- 16 .thread_model 00000003  00000000  00000000  000368f6  2**0
+  8 .debug_aranges 00000a00  00000000  00000000  00008248  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_info   00017dec  00000000  00000000  00008c48  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 10 .debug_abbrev 00006a83  00000000  00000000  00020a34  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 11 .debug_line   00009a57  00000000  00000000  000274b7  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 12 .debug_frame  00001510  00000000  00000000  00030f10  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    000027a7  00000000  00000000  00032420  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_loc    00005fc0  00000000  00000000  00034bc7  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 000008a8  00000000  00000000  0003ab88  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .thread_model 00000003  00000000  00000000  0003d706  2**0
                   CONTENTS, READONLY
- 17 .cpu          00000003  00000000  00000000  000368f9  2**0
+ 17 .cpu          00000003  00000000  00000000  0003d709  2**0
                   CONTENTS, READONLY
- 18 .qsys         00000001  00000000  00000000  000368fc  2**0
+ 18 .qsys         00000001  00000000  00000000  0003d70c  2**0
                   CONTENTS, READONLY
- 19 .simulation_enabled 00000001  00000000  00000000  000368fd  2**0
+ 19 .simulation_enabled 00000001  00000000  00000000  0003d70d  2**0
                   CONTENTS, READONLY
- 20 .stderr_dev   00000009  00000000  00000000  000368fe  2**0
+ 20 .stderr_dev   00000009  00000000  00000000  0003d70e  2**0
                   CONTENTS, READONLY
- 21 .stdin_dev    00000009  00000000  00000000  00036907  2**0
+ 21 .stdin_dev    00000009  00000000  00000000  0003d717  2**0
                   CONTENTS, READONLY
- 22 .stdout_dev   00000009  00000000  00000000  00036910  2**0
+ 22 .stdout_dev   00000009  00000000  00000000  0003d720  2**0
                   CONTENTS, READONLY
- 23 .sopc_system_name 00000006  00000000  00000000  00036919  2**0
+ 23 .sopc_system_name 00000006  00000000  00000000  0003d729  2**0
                   CONTENTS, READONLY
- 24 .quartus_project_dir 00000021  00000000  00000000  0003691f  2**0
+ 24 .quartus_project_dir 00000022  00000000  00000000  0003d72f  2**0
                   CONTENTS, READONLY
- 25 .jdi          0000438e  00000000  00000000  00036940  2**0
+ 25 .jdi          0000438e  00000000  00000000  0003d751  2**0
                   CONTENTS, READONLY
- 26 .sopcinfo     0003cf5c  00000000  00000000  0003acce  2**0
+ 26 .sopcinfo     0003cf5c  00000000  00000000  00041adf  2**0
                   CONTENTS, READONLY
 SYMBOL TABLE:
 00000000 l    d  .entry	00000000 .entry
 00000020 l    d  .exceptions	00000000 .exceptions
-00000230 l    d  .text	00000000 .text
-000057e0 l    d  .rodata	00000000 .rodata
-0000585c l    d  .rwdata	00000000 .rwdata
-000072c8 l    d  .bss	00000000 .bss
-0000741c l    d  .mem	00000000 .mem
+00000224 l    d  .text	00000000 .text
+00005734 l    d  .rodata	00000000 .rodata
+000057ac l    d  .rwdata	00000000 .rwdata
+00007218 l    d  .bss	00000000 .bss
+0000736c l    d  .mem	00000000 .mem
 00000000 l    d  .comment	00000000 .comment
 00000000 l    d  .debug_aranges	00000000 .debug_aranges
 00000000 l    d  .debug_info	00000000 .debug_info
@@ -85,20 +85,20 @@ SYMBOL TABLE:
 00000000 l    d  .debug_loc	00000000 .debug_loc
 00000000 l    d  .debug_ranges	00000000 .debug_ranges
 00000000 l    df *ABS*	00000000 ../semafor_bsp//obj/HAL/src/crt0.o
-00000244 l       .text	00000000 alt_after_alt_main
+00000238 l       .text	00000000 alt_after_alt_main
 00000000 l    df *ABS*	00000000 alt_irq_handler.c
 00000000 l    df *ABS*	00000000 alt_instruction_exception_entry.c
 00000000 l    df *ABS*	00000000 sem.c
 00000000 l    df *ABS*	00000000 puts.c
 00000000 l    df *ABS*	00000000 strlen.c
 00000000 l    df *ABS*	00000000 findfp.c
-000004a4 l     F .text	00000008 __fp_unlock
-000004b8 l     F .text	0000019c __sinit.part.1
-00000654 l     F .text	00000008 __fp_lock
+00000470 l     F .text	00000008 __fp_lock
+00000484 l     F .text	00000008 __fp_unlock
+0000048c l     F .text	00000168 __sinit.part.0
 00000000 l    df *ABS*	00000000 fvwrite.c
 00000000 l    df *ABS*	00000000 fwalk.c
 00000000 l    df *ABS*	00000000 impure.c
-0000585c l     O .rwdata	00000424 impure_data
+000057ac l     O .rwdata	00000424 impure_data
 00000000 l    df *ABS*	00000000 mallocr.c
 00000000 l    df *ABS*	00000000 memchr.c
 00000000 l    df *ABS*	00000000 memcpy.c
@@ -111,6 +111,7 @@ SYMBOL TABLE:
 00000000 l    df *ABS*	00000000 wsetup.c
 00000000 l    df *ABS*	00000000 closer.c
 00000000 l    df *ABS*	00000000 fclose.c
+0000230c l     F .text	000000c0 _fclose_r.part.0
 00000000 l    df *ABS*	00000000 fflush.c
 00000000 l    df *ABS*	00000000 mallocr.c
 00000000 l    df *ABS*	00000000 int_errno.c
@@ -122,51 +123,51 @@ SYMBOL TABLE:
 00000000 l    df *ABS*	00000000 lib2-divmod.c
 00000000 l    df *ABS*	00000000 lib2-mul.c
 00000000 l    df *ABS*	00000000 alt_close.c
-00003144 l     F .text	0000003c alt_get_errno
+00003174 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_dcache_flush.c
 00000000 l    df *ABS*	00000000 alt_dev.c
-00003280 l     F .text	0000002c alt_dev_null_write
+000032b4 l     F .text	0000002c alt_dev_null_write
 00000000 l    df *ABS*	00000000 alt_errno.c
 00000000 l    df *ABS*	00000000 alt_fstat.c
-000032ac l     F .text	0000003c alt_get_errno
+000032e0 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_isatty.c
-000033a0 l     F .text	0000003c alt_get_errno
+000033d8 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_lseek.c
-00003488 l     F .text	0000003c alt_get_errno
+000034c4 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_main.c
 00000000 l    df *ABS*	00000000 alt_malloc_lock.c
 00000000 l    df *ABS*	00000000 alt_read.c
-00003664 l     F .text	0000003c alt_get_errno
+000036a4 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_release_fd.c
 00000000 l    df *ABS*	00000000 alt_sbrk.c
-000072b8 l     O .rwdata	00000004 heap_end
+00007208 l     O .rwdata	00000004 heap_end
 00000000 l    df *ABS*	00000000 alt_write.c
-000038d8 l     F .text	0000003c alt_get_errno
+00003910 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_sys_init.c
-00003a14 l     F .text	00000034 alt_dev_reg
-00006230 l     O .rwdata	00001060 jtag_uart
+00003a50 l     F .text	00000034 alt_dev_reg
+00006180 l     O .rwdata	00001060 jtag_uart
 00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_fd.c
 00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_init.c
-00003d04 l     F .text	0000020c altera_avalon_jtag_uart_irq
-00003f10 l     F .text	000000a0 altera_avalon_jtag_uart_timeout
+00003d44 l     F .text	0000020c altera_avalon_jtag_uart_irq
+00003f50 l     F .text	000000a0 altera_avalon_jtag_uart_timeout
 00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_ioctl.c
 00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_read.c
 00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_write.c
 00000000 l    df *ABS*	00000000 altera_avalon_timer_sc.c
-00004548 l     F .text	00000078 alt_avalon_timer_sc_irq
+00004594 l     F .text	0000007c alt_avalon_timer_sc_irq
 00000000 l    df *ABS*	00000000 alt_alarm_start.c
 00000000 l    df *ABS*	00000000 alt_dev_llist_insert.c
-00004768 l     F .text	0000003c alt_get_errno
+000047c8 l     F .text	0000003c alt_get_errno
 00000000 l    df *ABS*	00000000 alt_do_ctors.c
 00000000 l    df *ABS*	00000000 alt_do_dtors.c
 00000000 l    df *ABS*	00000000 alt_iic.c
 00000000 l    df *ABS*	00000000 alt_iic_isr_register.c
 00000000 l    df *ABS*	00000000 alt_io_redirect.c
-00004ba8 l     F .text	000000e4 alt_open_fd
+00004c0c l     F .text	000000d4 alt_open_fd
 00000000 l    df *ABS*	00000000 alt_irq_vars.c
 00000000 l    df *ABS*	00000000 alt_open.c
-00004d08 l     F .text	0000003c alt_get_errno
-00004d44 l     F .text	000000ec alt_file_locked
+00004d5c l     F .text	0000003c alt_get_errno
+00004d98 l     F .text	000000dc alt_file_locked
 00000000 l    df *ABS*	00000000 alt_tick.c
 00000000 l    df *ABS*	00000000 altera_nios2_gen2_irq.c
 00000000 l    df *ABS*	00000000 alt_find_dev.c
@@ -178,153 +179,154 @@ SYMBOL TABLE:
 00000000 l    df *ABS*	00000000 __atexit.c
 00000000 l    df *ABS*	00000000 __call_atexit.c
 00000000 l    df *ABS*	00000000 alt_exit.c
-000072f0 g     O .bss	00000004 alt_instruction_exception_handler
-00002f14 g     F .text	00000054 _isatty_r
-000035a0 g     F .text	0000007c alt_main
-00000338 g     F .text	000000c0 _puts_r
-0000731c g     O .bss	00000100 alt_irq
-00002c3c g     F .text	00000060 _lseek_r
-0000741c g       *ABS*	00000000 __alt_heap_start
-000021f0 g     F .text	0000005c __sseek
-00000804 g     F .text	00000010 __sinit
-0000065c g     F .text	00000078 __sfmoreglue
-00003640 g     F .text	00000024 __malloc_unlock
-000057e0 g     O .rodata	00000040 divisors
-000018dc g     F .text	0000015c memmove
-000007ec g     F .text	00000018 _cleanup
-00005130 g     F .text	00000024 altera_nios2_gen2_irq_init
+00007240 g     O .bss	00000004 alt_instruction_exception_handler
+00002f40 g     F .text	00000058 _isatty_r
+000035e0 g     F .text	0000007c alt_main
+000002fc g     F .text	000000cc _puts_r
+0000726c g     O .bss	00000100 alt_irq
+00002bd0 g     F .text	00000064 _lseek_r
+0000736c g       *ABS*	00000000 __alt_heap_start
+00002088 g     F .text	0000005c __sseek
+000007d4 g     F .text	00000010 __sinit
+000005f4 g     F .text	00000078 __sfmoreglue
+00003680 g     F .text	00000024 __malloc_unlock
+00005734 g     O .rodata	00000040 divisors
+000017d4 g     F .text	0000012c memmove
+000007c0 g     F .text	00000014 _cleanup
+00005180 g     F .text	00000024 altera_nios2_gen2_irq_init
 00000000 g     F .entry	0000000c __reset
-00002eb8 g     F .text	0000005c _fstat_r
-000072d4 g     O .bss	00000004 errno
-0000216c g     F .text	00000008 __seofread
-000072dc g     O .bss	00000004 alt_argv
-0000f290 g       *ABS*	00000000 _gp
-000060b0 g     O .rwdata	00000180 alt_fd_list
-00005154 g     F .text	00000090 alt_find_dev
-00001794 g     F .text	00000148 memcpy
-000004ac g     F .text	0000000c _cleanup_r
-00004c8c g     F .text	0000007c alt_io_redirect
-000057e0 g       *ABS*	00000000 __DTOR_END__
-000003f8 g     F .text	00000014 puts
-000053b0 g     F .text	0000009c alt_exception_cause_generated_bad_addr
-00004108 g     F .text	0000021c altera_avalon_jtag_uart_read
-00003060 g     F .text	00000064 .hidden __udivsi3
-000033dc g     F .text	000000ac isatty
-000072d0 g     O .bss	00000004 __malloc_top_pad
-00000854 g     F .text	000004c8 __sfvwrite_r
-000020c4 g     F .text	00000054 _sbrk_r
-00002e58 g     F .text	00000060 _read_r
-00003258 g     F .text	00000028 alt_dcache_flush
-000072b0 g     O .rwdata	00000004 alt_max_fd
-0000245c g     F .text	000000f0 _fclose_r
-000027d8 g     F .text	00000030 fflush
-000072cc g     O .bss	00000004 __malloc_max_sbrked_mem
-000034c4 g     F .text	000000dc lseek
-00007290 g     O .rwdata	00000004 _global_impure_ptr
-00001b60 g     F .text	00000564 _realloc_r
-0000741c g       *ABS*	00000000 __bss_end
-00004ab8 g     F .text	000000f0 alt_iic_isr_register
-00005028 g     F .text	00000108 alt_tick
-00000824 g     F .text	00000018 __fp_lock_all
-00004a6c g     F .text	0000004c alt_ic_irq_enabled
+00002ee0 g     F .text	00000060 _fstat_r
+00007224 g     O .bss	00000004 errno
+00002000 g     F .text	00000008 __seofread
+0000722c g     O .bss	00000004 alt_argv
+0000f1e0 g       *ABS*	00000000 _gp
+00006000 g     O .rwdata	00000180 alt_fd_list
+000051a4 g     F .text	00000090 alt_find_dev
+000016d4 g     F .text	00000100 memcpy
+00000478 g     F .text	0000000c _cleanup_r
+00004ce0 g     F .text	0000007c alt_io_redirect
+00005734 g       *ABS*	00000000 __DTOR_END__
+000003c8 g     F .text	00000010 puts
+000053f4 g     F .text	00000098 alt_exception_cause_generated_bad_addr
+0000414c g     F .text	00000220 altera_avalon_jtag_uart_read
+0000308c g     F .text	00000064 .hidden __udivsi3
+00003414 g     F .text	000000b0 isatty
+00007220 g     O .bss	00000004 __malloc_top_pad
+0000081c g     F .text	000004c8 __sfvwrite_r
+00001f54 g     F .text	00000058 _sbrk_r
+00002e7c g     F .text	00000064 _read_r
+0000328c g     F .text	00000028 alt_dcache_flush
+00007200 g     O .rwdata	00000004 alt_max_fd
+000023cc g     F .text	00000070 _fclose_r
+00002734 g     F .text	00000084 fflush
+0000721c g     O .bss	00000004 __malloc_max_sbrked_mem
+00003500 g     F .text	000000e0 lseek
+000071e0 g     O .rwdata	00000004 _global_impure_ptr
+000019f0 g     F .text	00000564 _realloc_r
+0000736c g       *ABS*	00000000 __bss_end
+00004b24 g     F .text	000000e8 alt_iic_isr_register
+00005078 g     F .text	00000108 alt_tick
+000007f4 g     F .text	00000014 __fp_lock_all
+00004ad8 g     F .text	0000004c alt_ic_irq_enabled
 00000000 g       *ABS*	00000000 __alt_mem_mem
-00004f8c g     F .text	0000009c alt_alarm_stop
-000072e4 g     O .bss	00000004 alt_irq_active
-000000fc g     F .exceptions	000000d4 alt_irq_handler
-00006088 g     O .rwdata	00000028 alt_dev_null
-000072a8 g     O .rwdata	00000008 alt_dev_list
-00003914 g     F .text	00000100 write
-000032e8 g     F .text	000000b8 fstat
-000030c4 g     F .text	00000058 .hidden __umodsi3
-0000741c g       *ABS*	00000000 end
-00003c44 g     F .text	000000c0 altera_avalon_jtag_uart_init
-000001d0 g     F .exceptions	00000060 alt_instruction_exception_entry
-000057e0 g       *ABS*	00000000 __CTOR_LIST__
+00004fd4 g     F .text	000000a4 alt_alarm_stop
+00007234 g     O .bss	00000004 alt_irq_active
+000000fc g     F .exceptions	000000c8 alt_irq_handler
+00005fd8 g     O .rwdata	00000028 alt_dev_null
+000071f8 g     O .rwdata	00000008 alt_dev_list
+0000394c g     F .text	00000104 write
+0000331c g     F .text	000000bc fstat
+000030f0 g     F .text	0000005c .hidden __umodsi3
+0000736c g       *ABS*	00000000 end
+00003c84 g     F .text	000000c0 altera_avalon_jtag_uart_init
+000001c4 g     F .exceptions	00000060 alt_instruction_exception_entry
+00005734 g       *ABS*	00000000 __CTOR_LIST__
 00020000 g       *ABS*	00000000 __alt_stack_pointer
-000045c0 g     F .text	0000007c alt_avalon_timer_sc_init
-00004324 g     F .text	00000224 altera_avalon_jtag_uart_write
-00000814 g     F .text	00000004 __sfp_lock_acquire
-000016b0 g     F .text	000000e4 memchr
-0000292c g     F .text	00000310 _free_r
-0000562c g     F .text	00000180 __call_exitprocs
-00007298 g     O .rwdata	00000004 __malloc_sbrk_base
-00000230 g     F .text	00000018 _start
-000072e8 g     O .bss	00000004 _alt_tick_rate
-000072ec g     O .bss	00000004 _alt_nticks
-000036a0 g     F .text	00000104 read
-00003a80 g     F .text	00000060 alt_sys_init
-00005514 g     F .text	00000118 __register_exitproc
-00003fb0 g     F .text	00000068 altera_avalon_jtag_uart_close
-0000311c g     F .text	00000028 .hidden __mulsi3
-000072f4 g     O .bss	00000028 __malloc_current_mallinfo
-00003ae0 g     F .text	00000060 altera_avalon_jtag_uart_read_fd
-000052ec g     F .text	000000c4 alt_get_fd
-00002408 g     F .text	00000054 _close_r
-00005498 g     F .text	0000007c memcmp
-00003ba0 g     F .text	00000050 altera_avalon_jtag_uart_close_fd
-0000741c g       *ABS*	00000000 __alt_stack_base
-00003bf0 g     F .text	00000054 altera_avalon_jtag_uart_ioctl_fd
-000022b4 g     F .text	00000154 __swsetup_r
-000006d4 g     F .text	00000118 __sfp
-00005c80 g     O .rwdata	00000408 __malloc_av_
-00000820 g     F .text	00000004 __sinit_lock_release
-00002118 g     F .text	00000054 __sread
-000051e4 g     F .text	00000108 alt_find_file
-000047a4 g     F .text	000000a4 alt_dev_llist_insert
-0000361c g     F .text	00000024 __malloc_lock
-00003828 g     F .text	000000b0 sbrk
-0000277c g     F .text	0000005c _fflush_r
-000072c8 g       *ABS*	00000000 __bss_start
-00001a38 g     F .text	00000128 memset
-00000248 g     F .text	000000f0 main
-000072e0 g     O .bss	00000004 alt_envp
-000072c8 g     O .bss	00000004 __malloc_max_total_mem
-00003b40 g     F .text	00000060 altera_avalon_jtag_uart_write_fd
-0000224c g     F .text	00000008 __sclose
+00004610 g     F .text	00000084 alt_avalon_timer_sc_init
+0000436c g     F .text	00000228 altera_avalon_jtag_uart_write
+000007e4 g     F .text	00000004 __sfp_lock_acquire
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+000055dc g     F .text	00000120 __call_exitprocs
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+00003ff0 g     F .text	00000068 altera_avalon_jtag_uart_close
+0000314c g     F .text	00000028 .hidden __mulsi3
+00007244 g     O .bss	00000028 __malloc_current_mallinfo
+00003b20 g     F .text	00000060 altera_avalon_jtag_uart_read_fd
+0000533c g     F .text	000000b8 alt_get_fd
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+0000736c g       *ABS*	00000000 __alt_stack_base
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+00002150 g     F .text	00000164 __swsetup_r
+0000066c g     F .text	00000154 __sfp
+00005bd0 g     O .rwdata	00000408 __malloc_av_
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+00001fac g     F .text	00000054 __sread
+00005234 g     F .text	00000108 alt_find_file
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+00007218 g       *ABS*	00000000 __bss_start
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+00007230 g     O .bss	00000004 alt_envp
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+000020e4 g     F .text	00000008 __sclose
 00020000 g       *ABS*	00000000 __alt_heap_limit
-0000254c g     F .text	00000014 fclose
-00000ea4 g     F .text	0000080c _malloc_r
-000072b4 g     O .rwdata	00000004 alt_errno
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-00002808 g     F .text	00000124 _malloc_trim_r
-000057e0 g       *ABS*	00000000 __CTOR_END__
-000057e0 g       *ABS*	00000000 __DTOR_LIST__
-00003a48 g     F .text	00000038 alt_irq_init
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-0000544c g     F .text	00000014 atexit
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-00007294 g     O .rwdata	00000004 _impure_ptr
-000072d8 g     O .bss	00000004 alt_argc
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 00000020 g       .exceptions	00000000 alt_irq_entry
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-000072a0 g     O .rwdata	00000008 alt_fs_list
-00004908 g     F .text	00000050 alt_ic_isr_register
-000072c8 g       *ABS*	00000000 _edata
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-00004018 g     F .text	000000f0 altera_avalon_jtag_uart_ioctl
-000049e0 g     F .text	0000008c alt_ic_irq_disable
-00002174 g     F .text	0000007c __swrite
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-00005460 g     F .text	00000038 exit
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-00002fec g     F .text	00000074 .hidden __modsi3
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+00004974 g     F .text	00000050 alt_ic_isr_register
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+000054a0 g     F .text	00000034 exit
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 00020000 g       *ABS*	00000000 __alt_data_end
 00000020 g     F .exceptions	00000000 alt_exception
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-0000463c g     F .text	0000012c alt_alarm_start
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-00004e30 g     F .text	0000015c open
-000072bc g     O .rwdata	00000004 alt_priority_mask
-00004958 g     F .text	00000088 alt_ic_irq_enable
-000072c0 g     O .rwdata	00000008 alt_alarm_list
-00004848 g     F .text	00000060 _do_ctors
-00003180 g     F .text	000000d8 close
-0000081c g     F .text	00000004 __sinit_lock_acquire
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+000056fc g     F .text	00000038 _exit
+00004694 g     F .text	00000134 alt_alarm_start
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+000003d8 g     F .text	00000098 strlen
+00004e74 g     F .text	00000160 open
+0000720c g     O .rwdata	00000004 alt_priority_mask
+000049c4 g     F .text	00000088 alt_ic_irq_enable
+00007210 g     O .rwdata	00000008 alt_alarm_list
+000048ac g     F .text	00000064 _do_ctors
+000031b0 g     F .text	000000dc close
+000007ec g     F .text	00000004 __sinit_lock_acquire
 
 
 
@@ -339,7 +341,7 @@ Disassembly of section .entry:
     movhi r1, %hi(_start)
    0:	00400034 	movhi	at,0
     ori r1, r1, %lo(_start)
-   4:	08408c14 	ori	at,at,560
+   4:	08408914 	ori	at,at,548
     jmp r1
    8:	0800683a 	jmp	at
 	...
@@ -453,7 +455,7 @@ Disassembly of section .exceptions:
 
         /* Call the instruction-exception entry */
         call   alt_instruction_exception_entry
-  98:	00001d00 	call	1d0 <alt_instruction_exception_entry>
+  98:	00001c40 	call	1c4 <alt_instruction_exception_entry>
          * instruction
          *
          * Return code was 0: Skip. The instruction after the exception is
@@ -560,17 +562,17 @@ static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
 
   NIOS2_READ_IPENDING (active);
  110:	0005313a 	rdctl	r2,ipending
- 114:	e0bffe15 	stw	r2,-8(fp)
+ 114:	e0bffc15 	stw	r2,-16(fp)
 
   return active;
- 118:	e0bffe17 	ldw	r2,-8(fp)
+ 118:	e0bffc17 	ldw	r2,-16(fp)
    * Consider the case where the high priority interupt is asserted during
    * the interrupt entry sequence for a lower priority interrupt to see why
    * this is the case.
    */
 
   active = alt_irq_pending ();
- 11c:	e0bffb15 	stw	r2,-20(fp)
+ 11c:	e0bfff15 	stw	r2,-4(fp)
 
   do
   {
@@ -578,3736 +580,3695 @@ static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
  120:	e03ffd15 	stw	zero,-12(fp)
     mask = 1;
  124:	00800044 	movi	r2,1
- 128:	e0bffc15 	stw	r2,-16(fp)
+ 128:	e0bffe15 	stw	r2,-8(fp)
      * called to clear the interrupt condition.
      */
 
     do
     {
       if (active & mask)
- 12c:	e0fffb17 	ldw	r3,-20(fp)
- 130:	e0bffc17 	ldw	r2,-16(fp)
+ 12c:	e0ffff17 	ldw	r3,-4(fp)
+ 130:	e0bffe17 	ldw	r2,-8(fp)
  134:	1884703a 	and	r2,r3,r2
- 138:	10001426 	beq	r2,zero,18c <alt_irq_handler+0x90>
+ 138:	10001126 	beq	r2,zero,180 <alt_irq_handler+0x84>
       { 
 #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
         alt_irq[i].handler(alt_irq[i].context); 
- 13c:	00800034 	movhi	r2,0
- 140:	109cc704 	addi	r2,r2,29468
- 144:	e0fffd17 	ldw	r3,-12(fp)
- 148:	180690fa 	slli	r3,r3,3
- 14c:	10c5883a 	add	r2,r2,r3
- 150:	10c00017 	ldw	r3,0(r2)
- 154:	00800034 	movhi	r2,0
- 158:	109cc704 	addi	r2,r2,29468
- 15c:	e13ffd17 	ldw	r4,-12(fp)
- 160:	200890fa 	slli	r4,r4,3
- 164:	1105883a 	add	r2,r2,r4
- 168:	10800104 	addi	r2,r2,4
- 16c:	10800017 	ldw	r2,0(r2)
- 170:	1009883a 	mov	r4,r2
- 174:	183ee83a 	callr	r3
+ 13c:	e0bffd17 	ldw	r2,-12(fp)
+ 140:	100690fa 	slli	r3,r2,3
+ 144:	00800034 	movhi	r2,0
+ 148:	1885883a 	add	r2,r3,r2
+ 14c:	10dc9b17 	ldw	r3,29292(r2)
+ 150:	e0bffd17 	ldw	r2,-12(fp)
+ 154:	100890fa 	slli	r4,r2,3
+ 158:	00800034 	movhi	r2,0
+ 15c:	2085883a 	add	r2,r4,r2
+ 160:	109c9c17 	ldw	r2,29296(r2)
+ 164:	1009883a 	mov	r4,r2
+ 168:	183ee83a 	callr	r3
 #else
         alt_irq[i].handler(alt_irq[i].context, i); 
 #endif
         break;
- 178:	0001883a 	nop
-#ifndef NIOS2_EIC_PRESENT
-static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
-{
-  alt_u32 active;
-
+ 16c:	0001883a 	nop
   NIOS2_READ_IPENDING (active);
- 17c:	0005313a 	rdctl	r2,ipending
- 180:	e0bfff15 	stw	r2,-4(fp)
-
+ 170:	0005313a 	rdctl	r2,ipending
+ 174:	e0bffb15 	stw	r2,-20(fp)
   return active;
- 184:	e0bfff17 	ldw	r2,-4(fp)
- 188:	00000706 	br	1a8 <alt_irq_handler+0xac>
+ 178:	e0bffb17 	ldw	r2,-20(fp)
+ 17c:	00000706 	br	19c <alt_irq_handler+0xa0>
       }
       mask <<= 1;
- 18c:	e0bffc17 	ldw	r2,-16(fp)
- 190:	1085883a 	add	r2,r2,r2
- 194:	e0bffc15 	stw	r2,-16(fp)
+ 180:	e0bffe17 	ldw	r2,-8(fp)
+ 184:	1085883a 	add	r2,r2,r2
+ 188:	e0bffe15 	stw	r2,-8(fp)
       i++;
- 198:	e0bffd17 	ldw	r2,-12(fp)
- 19c:	10800044 	addi	r2,r2,1
- 1a0:	e0bffd15 	stw	r2,-12(fp)
+ 18c:	e0bffd17 	ldw	r2,-12(fp)
+ 190:	10800044 	addi	r2,r2,1
+ 194:	e0bffd15 	stw	r2,-12(fp)
+      if (active & mask)
+ 198:	003fe406 	br	12c <alt_irq_handler+0x30>
 
     } while (1);
- 1a4:	003fe106 	br	12c <__alt_data_end+0xfffe012c>
 
     active = alt_irq_pending ();
- 1a8:	e0bffb15 	stw	r2,-20(fp)
+ 19c:	e0bfff15 	stw	r2,-4(fp)
     
   } while (active);
- 1ac:	e0bffb17 	ldw	r2,-20(fp)
- 1b0:	103fdb1e 	bne	r2,zero,120 <__alt_data_end+0xfffe0120>
+ 1a0:	e0bfff17 	ldw	r2,-4(fp)
+ 1a4:	103fde1e 	bne	r2,zero,120 <alt_irq_handler+0x24>
 
   /*
    * Notify the operating system that interrupt processing is complete.
    */ 
 
   ALT_OS_INT_EXIT();
- 1b4:	0001883a 	nop
+ 1a8:	0001883a 	nop
 }
- 1b8:	0001883a 	nop
- 1bc:	e037883a 	mov	sp,fp
- 1c0:	dfc00117 	ldw	ra,4(sp)
- 1c4:	df000017 	ldw	fp,0(sp)
- 1c8:	dec00204 	addi	sp,sp,8
- 1cc:	f800283a 	ret
+ 1ac:	0001883a 	nop
+ 1b0:	e037883a 	mov	sp,fp
+ 1b4:	dfc00117 	ldw	ra,4(sp)
+ 1b8:	df000017 	ldw	fp,0(sp)
+ 1bc:	dec00204 	addi	sp,sp,8
+ 1c0:	f800283a 	ret
 
-000001d0 <alt_instruction_exception_entry>:
+000001c4 <alt_instruction_exception_entry>:
  * that handler if it has been registered. Absent a handler, it will
  * break break or hang as discussed below.
  */
 int 
 alt_instruction_exception_entry (alt_u32 exception_pc)
 {
- 1d0:	defffb04 	addi	sp,sp,-20
- 1d4:	dfc00415 	stw	ra,16(sp)
- 1d8:	df000315 	stw	fp,12(sp)
- 1dc:	df000304 	addi	fp,sp,12
- 1e0:	e13fff15 	stw	r4,-4(fp)
+ 1c4:	defffb04 	addi	sp,sp,-20
+ 1c8:	dfc00415 	stw	ra,16(sp)
+ 1cc:	df000315 	stw	fp,12(sp)
+ 1d0:	df000304 	addi	fp,sp,12
+ 1d4:	e13ffd15 	stw	r4,-12(fp)
   cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >>
               NIOS2_EXCEPTION_REG_CAUSE_OFST );
 
   NIOS2_READ_BADADDR(badaddr);
 #else
   cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT;
- 1e4:	00bfffc4 	movi	r2,-1
- 1e8:	e0bffd15 	stw	r2,-12(fp)
+ 1d8:	00bfffc4 	movi	r2,-1
+ 1dc:	e0bfff15 	stw	r2,-4(fp)
   badaddr = 0;
- 1ec:	e03ffe15 	stw	zero,-8(fp)
+ 1e0:	e03ffe15 	stw	zero,-8(fp)
 #endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
 
   if(alt_instruction_exception_handler) {
- 1f0:	d0a01817 	ldw	r2,-32672(gp)
- 1f4:	10000726 	beq	r2,zero,214 <alt_instruction_exception_entry+0x44>
+ 1e4:	d0a01817 	ldw	r2,-32672(gp)
+ 1e8:	10000726 	beq	r2,zero,208 <alt_instruction_exception_entry+0x44>
      * Call handler. Its return value indicates whether the exception-causing
      * instruction should be re-issued. The code that called us,
      * alt_eceptions_entry.S, will look at this value and adjust the ea
      * register as necessary
      */
     return alt_instruction_exception_handler(cause, exception_pc, badaddr);
- 1f8:	d0a01817 	ldw	r2,-32672(gp)
- 1fc:	e0fffd17 	ldw	r3,-12(fp)
- 200:	e1bffe17 	ldw	r6,-8(fp)
- 204:	e17fff17 	ldw	r5,-4(fp)
- 208:	1809883a 	mov	r4,r3
- 20c:	103ee83a 	callr	r2
- 210:	00000206 	br	21c <alt_instruction_exception_entry+0x4c>
+ 1ec:	d0a01817 	ldw	r2,-32672(gp)
+ 1f0:	e0ffff17 	ldw	r3,-4(fp)
+ 1f4:	e1bffe17 	ldw	r6,-8(fp)
+ 1f8:	e17ffd17 	ldw	r5,-12(fp)
+ 1fc:	1809883a 	mov	r4,r3
+ 200:	103ee83a 	callr	r2
+ 204:	00000206 	br	210 <alt_instruction_exception_entry+0x4c>
    *    (a peripheral which negates its interrupt output before its
    *    interrupt handler has been executed will cause spurious interrupts)
    */
   else {
 #ifdef NIOS2_HAS_DEBUG_STUB
     NIOS2_BREAK();
- 214:	003da03a 	break	0
+ 208:	003da03a 	break	0
       ;
 #endif /* NIOS2_HAS_DEBUG_STUB */
   }
 
   /* We should not get here. Remove compiler warning. */
   return NIOS2_EXCEPTION_RETURN_REISSUE_INST;
- 218:	0005883a 	mov	r2,zero
+ 20c:	0005883a 	mov	r2,zero
 }
- 21c:	e037883a 	mov	sp,fp
- 220:	dfc00117 	ldw	ra,4(sp)
- 224:	df000017 	ldw	fp,0(sp)
- 228:	dec00204 	addi	sp,sp,8
- 22c:	f800283a 	ret
+ 210:	e037883a 	mov	sp,fp
+ 214:	dfc00117 	ldw	ra,4(sp)
+ 218:	df000017 	ldw	fp,0(sp)
+ 21c:	dec00204 	addi	sp,sp,8
+ 220:	f800283a 	ret
 
 Disassembly of section .text:
 
-00000230 <_start>:
+00000224 <_start>:
 
     /*
      * Now that the caches are initialized, set up the stack pointer and global pointer.
      * The values provided by the linker are assumed to be correctly aligned.
      */
     movhi sp, %hi(__alt_stack_pointer)
-     230:	06c000b4 	movhi	sp,2
+     224:	06c000b4 	movhi	sp,2
     ori sp, sp, %lo(__alt_stack_pointer)
-     234:	dec00014 	ori	sp,sp,0
+     228:	dec00014 	ori	sp,sp,0
     movhi gp, %hi(_gp)
-     238:	06800034 	movhi	gp,0
+     22c:	06800034 	movhi	gp,0
     ori gp, gp, %lo(_gp)
-     23c:	d6bca414 	ori	gp,gp,62096
+     230:	d6bc7814 	ori	gp,gp,61920
 
     /* Log that alt_main is about to be called. */
     ALT_LOG_PUTS(alt_log_msg_alt_main)
 
     /* Call the C entry point. It should never return. */
     call alt_main
-     240:	00035a00 	call	35a0 <alt_main>
+     234:	00035e00 	call	35e0 <alt_main>
 
-00000244 <alt_after_alt_main>:
+00000238 <alt_after_alt_main>:
 
     /* Wait in infinite loop in case alt_main does return. */
 alt_after_alt_main:
     br alt_after_alt_main
-     244:	003fff06 	br	244 <__alt_data_end+0xfffe0244>
+     238:	003fff06 	br	238 <alt_after_alt_main>
 
-00000248 <main>:
+0000023c <main>:
 		{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
 		{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
 };
 
 int main()
 { 
-     248:	defffa04 	addi	sp,sp,-24
-     24c:	dfc00515 	stw	ra,20(sp)
-     250:	df000415 	stw	fp,16(sp)
-     254:	df000404 	addi	fp,sp,16
+     23c:	defffb04 	addi	sp,sp,-20
+     240:	dfc00415 	stw	ra,16(sp)
+     244:	df000315 	stw	fp,12(sp)
+     248:	df000304 	addi	fp,sp,12
 	int i,j;
 	volatile alt_u32 *p;
 	alt_u32 tmp;
 
 	//program divisors
 	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
-     258:	008000b4 	movhi	r2,2
-     25c:	10840004 	addi	r2,r2,4096
-     260:	e0bffe15 	stw	r2,-8(fp)
+     24c:	008000b4 	movhi	r2,2
+     250:	10840004 	addi	r2,r2,4096
+     254:	e0bffd15 	stw	r2,-12(fp)
 	for (i = 0; i < TIME_SETS; i++)	{
-     264:	e03ffc15 	stw	zero,-16(fp)
-     268:	00002306 	br	2f8 <main+0xb0>
-		tmp = 0;
-     26c:	e03fff15 	stw	zero,-4(fp)
+     258:	e03fff15 	stw	zero,-4(fp)
+     25c:	00001a06 	br	2c8 <main+0x8c>
 		for (j = TIME_STATES; j > 0; j--) {
-     270:	00800104 	movi	r2,4
-     274:	e0bffd15 	stw	r2,-12(fp)
-     278:	00001406 	br	2cc <main+0x84>
-			tmp = (tmp << 32) | divisors[i][j - 1];
-     27c:	e0ffff17 	ldw	r3,-4(fp)
-     280:	00800804 	movi	r2,32
-     284:	1888983a 	sll	r4,r3,r2
-     288:	e0bffd17 	ldw	r2,-12(fp)
-     28c:	117fffc4 	addi	r5,r2,-1
-     290:	00800034 	movhi	r2,0
-     294:	1095f804 	addi	r2,r2,22496
-     298:	e0fffc17 	ldw	r3,-16(fp)
-     29c:	18c7883a 	add	r3,r3,r3
-     2a0:	18c7883a 	add	r3,r3,r3
-     2a4:	1947883a 	add	r3,r3,r5
-     2a8:	18c7883a 	add	r3,r3,r3
-     2ac:	18c7883a 	add	r3,r3,r3
-     2b0:	10c5883a 	add	r2,r2,r3
-     2b4:	10800017 	ldw	r2,0(r2)
-     2b8:	2084b03a 	or	r2,r4,r2
-     2bc:	e0bfff15 	stw	r2,-4(fp)
-
-	//program divisors
-	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
+     260:	00800104 	movi	r2,4
+     264:	e0bffe15 	stw	r2,-8(fp)
+     268:	00001206 	br	2b4 <main+0x78>
+			*p = divisors[i][j - 1];
+     26c:	e0bffe17 	ldw	r2,-8(fp)
+     270:	10bfffc4 	addi	r2,r2,-1
+     274:	e0ffff17 	ldw	r3,-4(fp)
+     278:	180690ba 	slli	r3,r3,2
+     27c:	1885883a 	add	r2,r3,r2
+     280:	100690ba 	slli	r3,r2,2
+     284:	00800034 	movhi	r2,0
+     288:	1885883a 	add	r2,r3,r2
+     28c:	10d5cd17 	ldw	r3,22324(r2)
+     290:	e0bffd17 	ldw	r2,-12(fp)
+     294:	10c00015 	stw	r3,0(r2)
+			alt_dcache_flush();
+     298:	000328c0 	call	328c <alt_dcache_flush>
+			p++;
+     29c:	e0bffd17 	ldw	r2,-12(fp)
+     2a0:	10800104 	addi	r2,r2,4
+     2a4:	e0bffd15 	stw	r2,-12(fp)
+		for (j = TIME_STATES; j > 0; j--) {
+     2a8:	e0bffe17 	ldw	r2,-8(fp)
+     2ac:	10bfffc4 	addi	r2,r2,-1
+     2b0:	e0bffe15 	stw	r2,-8(fp)
+     2b4:	e0bffe17 	ldw	r2,-8(fp)
+     2b8:	00bfec16 	blt	zero,r2,26c <main+0x30>
 	for (i = 0; i < TIME_SETS; i++)	{
-		tmp = 0;
-		for (j = TIME_STATES; j > 0; j--) {
-     2c0:	e0bffd17 	ldw	r2,-12(fp)
-     2c4:	10bfffc4 	addi	r2,r2,-1
-     2c8:	e0bffd15 	stw	r2,-12(fp)
-     2cc:	e0bffd17 	ldw	r2,-12(fp)
-     2d0:	00bfea16 	blt	zero,r2,27c <__alt_data_end+0xfffe027c>
-			tmp = (tmp << 32) | divisors[i][j - 1];
+     2bc:	e0bfff17 	ldw	r2,-4(fp)
+     2c0:	10800044 	addi	r2,r2,1
+     2c4:	e0bfff15 	stw	r2,-4(fp)
+     2c8:	e0bfff17 	ldw	r2,-4(fp)
+     2cc:	10800110 	cmplti	r2,r2,4
+     2d0:	103fe31e 	bne	r2,zero,260 <main+0x24>
 		}
-		*p = tmp;
-     2d4:	e0bffe17 	ldw	r2,-8(fp)
-     2d8:	e0ffff17 	ldw	r3,-4(fp)
-     2dc:	10c00015 	stw	r3,0(r2)
-		p++;
-     2e0:	e0bffe17 	ldw	r2,-8(fp)
-     2e4:	10800104 	addi	r2,r2,4
-     2e8:	e0bffe15 	stw	r2,-8(fp)
-	volatile alt_u32 *p;
-	alt_u32 tmp;
-
-	//program divisors
-	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
-	for (i = 0; i < TIME_SETS; i++)	{
-     2ec:	e0bffc17 	ldw	r2,-16(fp)
-     2f0:	10800044 	addi	r2,r2,1
-     2f4:	e0bffc15 	stw	r2,-16(fp)
-     2f8:	e0bffc17 	ldw	r2,-16(fp)
-     2fc:	10800110 	cmplti	r2,r2,4
-     300:	103fda1e 	bne	r2,zero,26c <__alt_data_end+0xfffe026c>
-		*p = tmp;
-		p++;
 	}
-	//since we use pointers (cached data access) to write divisor RAM, 
-	//and not direct i/o access with IOWR, we need to flush cache
-	alt_dcache_flush();
-     304:	00032580 	call	3258 <alt_dcache_flush>
 	
 	//select timeset and run semafor
-	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00);
-     308:	0007883a 	mov	r3,zero
-     30c:	008000b4 	movhi	r2,2
-     310:	10841904 	addi	r2,r2,4196
-     314:	10c00035 	stwio	r3,0(r2)
+	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x02);
+     2d4:	00c00084 	movi	r3,2
+     2d8:	008000b4 	movhi	r2,2
+     2dc:	10c41935 	stwio	r3,4196(r2)
 	IOWR_ALTERA_AVALON_SEM_CTL(SEM_CTL_SLAVE_BASE,0x01);
-     318:	00c00044 	movi	r3,1
-     31c:	008000b4 	movhi	r2,2
-     320:	10841804 	addi	r2,r2,4192
-     324:	10c00035 	stwio	r3,0(r2)
+     2e0:	00c00044 	movi	r3,1
+     2e4:	008000b4 	movhi	r2,2
+     2e8:	10c41835 	stwio	r3,4192(r2)
 
 	printf("Ready\n");
-     328:	01000034 	movhi	r4,0
-     32c:	21160804 	addi	r4,r4,22560
-     330:	00003f80 	call	3f8 <puts>
+     2ec:	01000034 	movhi	r4,0
+     2f0:	2115dd04 	addi	r4,r4,22388
+     2f4:	00003c80 	call	3c8 <puts>
 
 	while (1)
-	{
-		;
-	}
-     334:	003fff06 	br	334 <__alt_data_end+0xfffe0334>
+     2f8:	003fff06 	br	2f8 <main+0xbc>
 
-00000338 <_puts_r>:
-     338:	defff604 	addi	sp,sp,-40
-     33c:	dc000715 	stw	r16,28(sp)
-     340:	2021883a 	mov	r16,r4
-     344:	2809883a 	mov	r4,r5
-     348:	dc400815 	stw	r17,32(sp)
-     34c:	dfc00915 	stw	ra,36(sp)
-     350:	2823883a 	mov	r17,r5
-     354:	000040c0 	call	40c <strlen>
-     358:	10c00044 	addi	r3,r2,1
-     35c:	d8800115 	stw	r2,4(sp)
-     360:	00800034 	movhi	r2,0
-     364:	10960a04 	addi	r2,r2,22568
-     368:	d8800215 	stw	r2,8(sp)
-     36c:	00800044 	movi	r2,1
-     370:	d8800315 	stw	r2,12(sp)
-     374:	00800084 	movi	r2,2
-     378:	dc400015 	stw	r17,0(sp)
-     37c:	d8c00615 	stw	r3,24(sp)
-     380:	dec00415 	stw	sp,16(sp)
-     384:	d8800515 	stw	r2,20(sp)
-     388:	80000226 	beq	r16,zero,394 <_puts_r+0x5c>
-     38c:	80800e17 	ldw	r2,56(r16)
-     390:	10001426 	beq	r2,zero,3e4 <_puts_r+0xac>
-     394:	81400217 	ldw	r5,8(r16)
-     398:	2880030b 	ldhu	r2,12(r5)
-     39c:	10c8000c 	andi	r3,r2,8192
-     3a0:	1800061e 	bne	r3,zero,3bc <_puts_r+0x84>
-     3a4:	29001917 	ldw	r4,100(r5)
-     3a8:	00f7ffc4 	movi	r3,-8193
-     3ac:	10880014 	ori	r2,r2,8192
-     3b0:	20c6703a 	and	r3,r4,r3
-     3b4:	2880030d 	sth	r2,12(r5)
-     3b8:	28c01915 	stw	r3,100(r5)
-     3bc:	d9800404 	addi	r6,sp,16
-     3c0:	8009883a 	mov	r4,r16
-     3c4:	00008540 	call	854 <__sfvwrite_r>
-     3c8:	1000091e 	bne	r2,zero,3f0 <_puts_r+0xb8>
-     3cc:	00800284 	movi	r2,10
-     3d0:	dfc00917 	ldw	ra,36(sp)
-     3d4:	dc400817 	ldw	r17,32(sp)
-     3d8:	dc000717 	ldw	r16,28(sp)
-     3dc:	dec00a04 	addi	sp,sp,40
-     3e0:	f800283a 	ret
-     3e4:	8009883a 	mov	r4,r16
-     3e8:	00008040 	call	804 <__sinit>
-     3ec:	003fe906 	br	394 <__alt_data_end+0xfffe0394>
-     3f0:	00bfffc4 	movi	r2,-1
-     3f4:	003ff606 	br	3d0 <__alt_data_end+0xfffe03d0>
+000002fc <_puts_r>:
+     2fc:	defff504 	addi	sp,sp,-44
+     300:	dc000815 	stw	r16,32(sp)
+     304:	2021883a 	mov	r16,r4
+     308:	2809883a 	mov	r4,r5
+     30c:	dc400915 	stw	r17,36(sp)
+     310:	dfc00a15 	stw	ra,40(sp)
+     314:	2823883a 	mov	r17,r5
+     318:	00003d80 	call	3d8 <strlen>
+     31c:	11000044 	addi	r4,r2,1
+     320:	d8800515 	stw	r2,20(sp)
+     324:	00800044 	movi	r2,1
+     328:	00c00034 	movhi	r3,0
+     32c:	d8800715 	stw	r2,28(sp)
+     330:	d8800404 	addi	r2,sp,16
+     334:	18d5df04 	addi	r3,r3,22396
+     338:	d8800115 	stw	r2,4(sp)
+     33c:	00800084 	movi	r2,2
+     340:	dc400415 	stw	r17,16(sp)
+     344:	d8c00615 	stw	r3,24(sp)
+     348:	d9000315 	stw	r4,12(sp)
+     34c:	d8800215 	stw	r2,8(sp)
+     350:	81400217 	ldw	r5,8(r16)
+     354:	80000226 	beq	r16,zero,360 <_puts_r+0x64>
+     358:	80800e17 	ldw	r2,56(r16)
+     35c:	10001326 	beq	r2,zero,3ac <_puts_r+0xb0>
+     360:	2880030b 	ldhu	r2,12(r5)
+     364:	10c8000c 	andi	r3,r2,8192
+     368:	1800061e 	bne	r3,zero,384 <_puts_r+0x88>
+     36c:	28c01917 	ldw	r3,100(r5)
+     370:	0137ffc4 	movi	r4,-8193
+     374:	10880014 	ori	r2,r2,8192
+     378:	1906703a 	and	r3,r3,r4
+     37c:	2880030d 	sth	r2,12(r5)
+     380:	28c01915 	stw	r3,100(r5)
+     384:	d9800104 	addi	r6,sp,4
+     388:	8009883a 	mov	r4,r16
+     38c:	000081c0 	call	81c <__sfvwrite_r>
+     390:	10000b1e 	bne	r2,zero,3c0 <_puts_r+0xc4>
+     394:	00800284 	movi	r2,10
+     398:	dfc00a17 	ldw	ra,40(sp)
+     39c:	dc400917 	ldw	r17,36(sp)
+     3a0:	dc000817 	ldw	r16,32(sp)
+     3a4:	dec00b04 	addi	sp,sp,44
+     3a8:	f800283a 	ret
+     3ac:	8009883a 	mov	r4,r16
+     3b0:	d9400015 	stw	r5,0(sp)
+     3b4:	00007d40 	call	7d4 <__sinit>
+     3b8:	d9400017 	ldw	r5,0(sp)
+     3bc:	003fe806 	br	360 <_puts_r+0x64>
+     3c0:	00bfffc4 	movi	r2,-1
+     3c4:	003ff406 	br	398 <_puts_r+0x9c>
 
-000003f8 <puts>:
-     3f8:	00800034 	movhi	r2,0
-     3fc:	109ca504 	addi	r2,r2,29332
-     400:	200b883a 	mov	r5,r4
-     404:	11000017 	ldw	r4,0(r2)
-     408:	00003381 	jmpi	338 <_puts_r>
+000003c8 <puts>:
+     3c8:	00800034 	movhi	r2,0
+     3cc:	200b883a 	mov	r5,r4
+     3d0:	111c7917 	ldw	r4,29156(r2)
+     3d4:	00002fc1 	jmpi	2fc <_puts_r>
 
-0000040c <strlen>:
-     40c:	208000cc 	andi	r2,r4,3
-     410:	10002026 	beq	r2,zero,494 <strlen+0x88>
-     414:	20800007 	ldb	r2,0(r4)
-     418:	10002026 	beq	r2,zero,49c <strlen+0x90>
-     41c:	2005883a 	mov	r2,r4
-     420:	00000206 	br	42c <strlen+0x20>
-     424:	10c00007 	ldb	r3,0(r2)
-     428:	18001826 	beq	r3,zero,48c <strlen+0x80>
-     42c:	10800044 	addi	r2,r2,1
-     430:	10c000cc 	andi	r3,r2,3
-     434:	183ffb1e 	bne	r3,zero,424 <__alt_data_end+0xfffe0424>
-     438:	10c00017 	ldw	r3,0(r2)
-     43c:	01ffbff4 	movhi	r7,65279
-     440:	39ffbfc4 	addi	r7,r7,-257
-     444:	00ca303a 	nor	r5,zero,r3
-     448:	01a02074 	movhi	r6,32897
-     44c:	19c7883a 	add	r3,r3,r7
-     450:	31a02004 	addi	r6,r6,-32640
-     454:	1946703a 	and	r3,r3,r5
-     458:	1986703a 	and	r3,r3,r6
-     45c:	1800091e 	bne	r3,zero,484 <strlen+0x78>
-     460:	10800104 	addi	r2,r2,4
-     464:	10c00017 	ldw	r3,0(r2)
-     468:	19cb883a 	add	r5,r3,r7
-     46c:	00c6303a 	nor	r3,zero,r3
-     470:	28c6703a 	and	r3,r5,r3
-     474:	1986703a 	and	r3,r3,r6
-     478:	183ff926 	beq	r3,zero,460 <__alt_data_end+0xfffe0460>
-     47c:	00000106 	br	484 <strlen+0x78>
-     480:	10800044 	addi	r2,r2,1
-     484:	10c00007 	ldb	r3,0(r2)
-     488:	183ffd1e 	bne	r3,zero,480 <__alt_data_end+0xfffe0480>
-     48c:	1105c83a 	sub	r2,r2,r4
-     490:	f800283a 	ret
-     494:	2005883a 	mov	r2,r4
-     498:	003fe706 	br	438 <__alt_data_end+0xfffe0438>
-     49c:	0005883a 	mov	r2,zero
-     4a0:	f800283a 	ret
+000003d8 <strlen>:
+     3d8:	208000cc 	andi	r2,r4,3
+     3dc:	10000926 	beq	r2,zero,404 <strlen+0x2c>
+     3e0:	2005883a 	mov	r2,r4
+     3e4:	00000306 	br	3f4 <strlen+0x1c>
+     3e8:	10800044 	addi	r2,r2,1
+     3ec:	10c000cc 	andi	r3,r2,3
+     3f0:	18000526 	beq	r3,zero,408 <strlen+0x30>
+     3f4:	10c00007 	ldb	r3,0(r2)
+     3f8:	183ffb1e 	bne	r3,zero,3e8 <strlen+0x10>
+     3fc:	1105c83a 	sub	r2,r2,r4
+     400:	f800283a 	ret
+     404:	2005883a 	mov	r2,r4
+     408:	11400017 	ldw	r5,0(r2)
+     40c:	01ffbff4 	movhi	r7,65279
+     410:	39ffbfc4 	addi	r7,r7,-257
+     414:	29c7883a 	add	r3,r5,r7
+     418:	01a02074 	movhi	r6,32897
+     41c:	014a303a 	nor	r5,zero,r5
+     420:	1946703a 	and	r3,r3,r5
+     424:	31a02004 	addi	r6,r6,-32640
+     428:	1986703a 	and	r3,r3,r6
+     42c:	1800071e 	bne	r3,zero,44c <strlen+0x74>
+     430:	11400117 	ldw	r5,4(r2)
+     434:	10800104 	addi	r2,r2,4
+     438:	29c7883a 	add	r3,r5,r7
+     43c:	014a303a 	nor	r5,zero,r5
+     440:	1946703a 	and	r3,r3,r5
+     444:	1986703a 	and	r3,r3,r6
+     448:	183ff926 	beq	r3,zero,430 <strlen+0x58>
+     44c:	10c00007 	ldb	r3,0(r2)
+     450:	183fea26 	beq	r3,zero,3fc <strlen+0x24>
+     454:	10c00047 	ldb	r3,1(r2)
+     458:	10800044 	addi	r2,r2,1
+     45c:	183fe726 	beq	r3,zero,3fc <strlen+0x24>
+     460:	10c00047 	ldb	r3,1(r2)
+     464:	10800044 	addi	r2,r2,1
+     468:	183ffa1e 	bne	r3,zero,454 <strlen+0x7c>
+     46c:	003fe306 	br	3fc <strlen+0x24>
 
-000004a4 <__fp_unlock>:
-     4a4:	0005883a 	mov	r2,zero
-     4a8:	f800283a 	ret
+00000470 <__fp_lock>:
+     470:	0005883a 	mov	r2,zero
+     474:	f800283a 	ret
 
-000004ac <_cleanup_r>:
-     4ac:	01400034 	movhi	r5,0
-     4b0:	29491704 	addi	r5,r5,9308
-     4b4:	0000de01 	jmpi	de0 <_fwalk_reent>
+00000478 <_cleanup_r>:
+     478:	01400034 	movhi	r5,0
+     47c:	2948f304 	addi	r5,r5,9164
+     480:	0000d7c1 	jmpi	d7c <_fwalk_reent>
 
-000004b8 <__sinit.part.1>:
-     4b8:	defff704 	addi	sp,sp,-36
-     4bc:	00c00034 	movhi	r3,0
-     4c0:	dfc00815 	stw	ra,32(sp)
-     4c4:	ddc00715 	stw	r23,28(sp)
-     4c8:	dd800615 	stw	r22,24(sp)
-     4cc:	dd400515 	stw	r21,20(sp)
-     4d0:	dd000415 	stw	r20,16(sp)
-     4d4:	dcc00315 	stw	r19,12(sp)
-     4d8:	dc800215 	stw	r18,8(sp)
-     4dc:	dc400115 	stw	r17,4(sp)
-     4e0:	dc000015 	stw	r16,0(sp)
-     4e4:	18c12b04 	addi	r3,r3,1196
-     4e8:	24000117 	ldw	r16,4(r4)
-     4ec:	20c00f15 	stw	r3,60(r4)
-     4f0:	2080bb04 	addi	r2,r4,748
-     4f4:	00c000c4 	movi	r3,3
-     4f8:	20c0b915 	stw	r3,740(r4)
-     4fc:	2080ba15 	stw	r2,744(r4)
-     500:	2000b815 	stw	zero,736(r4)
-     504:	05c00204 	movi	r23,8
-     508:	00800104 	movi	r2,4
-     50c:	2025883a 	mov	r18,r4
-     510:	b80d883a 	mov	r6,r23
-     514:	81001704 	addi	r4,r16,92
-     518:	000b883a 	mov	r5,zero
-     51c:	80000015 	stw	zero,0(r16)
-     520:	80000115 	stw	zero,4(r16)
-     524:	80000215 	stw	zero,8(r16)
-     528:	8080030d 	sth	r2,12(r16)
-     52c:	80001915 	stw	zero,100(r16)
-     530:	8000038d 	sth	zero,14(r16)
-     534:	80000415 	stw	zero,16(r16)
-     538:	80000515 	stw	zero,20(r16)
-     53c:	80000615 	stw	zero,24(r16)
-     540:	0001a380 	call	1a38 <memset>
-     544:	05800034 	movhi	r22,0
-     548:	94400217 	ldw	r17,8(r18)
-     54c:	05400034 	movhi	r21,0
-     550:	05000034 	movhi	r20,0
-     554:	04c00034 	movhi	r19,0
-     558:	b5884604 	addi	r22,r22,8472
-     55c:	ad485d04 	addi	r21,r21,8564
-     560:	a5087c04 	addi	r20,r20,8688
-     564:	9cc89304 	addi	r19,r19,8780
-     568:	85800815 	stw	r22,32(r16)
-     56c:	85400915 	stw	r21,36(r16)
-     570:	85000a15 	stw	r20,40(r16)
-     574:	84c00b15 	stw	r19,44(r16)
-     578:	84000715 	stw	r16,28(r16)
-     57c:	00800284 	movi	r2,10
-     580:	8880030d 	sth	r2,12(r17)
-     584:	00800044 	movi	r2,1
-     588:	b80d883a 	mov	r6,r23
-     58c:	89001704 	addi	r4,r17,92
-     590:	000b883a 	mov	r5,zero
-     594:	88000015 	stw	zero,0(r17)
-     598:	88000115 	stw	zero,4(r17)
-     59c:	88000215 	stw	zero,8(r17)
-     5a0:	88001915 	stw	zero,100(r17)
-     5a4:	8880038d 	sth	r2,14(r17)
-     5a8:	88000415 	stw	zero,16(r17)
-     5ac:	88000515 	stw	zero,20(r17)
-     5b0:	88000615 	stw	zero,24(r17)
-     5b4:	0001a380 	call	1a38 <memset>
-     5b8:	94000317 	ldw	r16,12(r18)
-     5bc:	00800484 	movi	r2,18
-     5c0:	8c400715 	stw	r17,28(r17)
-     5c4:	8d800815 	stw	r22,32(r17)
-     5c8:	8d400915 	stw	r21,36(r17)
-     5cc:	8d000a15 	stw	r20,40(r17)
-     5d0:	8cc00b15 	stw	r19,44(r17)
-     5d4:	8080030d 	sth	r2,12(r16)
-     5d8:	00800084 	movi	r2,2
-     5dc:	80000015 	stw	zero,0(r16)
-     5e0:	80000115 	stw	zero,4(r16)
-     5e4:	80000215 	stw	zero,8(r16)
-     5e8:	80001915 	stw	zero,100(r16)
-     5ec:	8080038d 	sth	r2,14(r16)
-     5f0:	80000415 	stw	zero,16(r16)
-     5f4:	80000515 	stw	zero,20(r16)
-     5f8:	80000615 	stw	zero,24(r16)
-     5fc:	b80d883a 	mov	r6,r23
-     600:	000b883a 	mov	r5,zero
-     604:	81001704 	addi	r4,r16,92
-     608:	0001a380 	call	1a38 <memset>
-     60c:	00800044 	movi	r2,1
-     610:	84000715 	stw	r16,28(r16)
-     614:	85800815 	stw	r22,32(r16)
-     618:	85400915 	stw	r21,36(r16)
-     61c:	85000a15 	stw	r20,40(r16)
-     620:	84c00b15 	stw	r19,44(r16)
-     624:	90800e15 	stw	r2,56(r18)
-     628:	dfc00817 	ldw	ra,32(sp)
-     62c:	ddc00717 	ldw	r23,28(sp)
-     630:	dd800617 	ldw	r22,24(sp)
-     634:	dd400517 	ldw	r21,20(sp)
-     638:	dd000417 	ldw	r20,16(sp)
-     63c:	dcc00317 	ldw	r19,12(sp)
-     640:	dc800217 	ldw	r18,8(sp)
-     644:	dc400117 	ldw	r17,4(sp)
-     648:	dc000017 	ldw	r16,0(sp)
-     64c:	dec00904 	addi	sp,sp,36
-     650:	f800283a 	ret
+00000484 <__fp_unlock>:
+     484:	0005883a 	mov	r2,zero
+     488:	f800283a 	ret
 
-00000654 <__fp_lock>:
-     654:	0005883a 	mov	r2,zero
-     658:	f800283a 	ret
+0000048c <__sinit.part.0>:
+     48c:	00c00034 	movhi	r3,0
+     490:	20800117 	ldw	r2,4(r4)
+     494:	18c11e04 	addi	r3,r3,1144
+     498:	20c00f15 	stw	r3,60(r4)
+     49c:	2140bb04 	addi	r5,r4,748
+     4a0:	00c000c4 	movi	r3,3
+     4a4:	20c0b915 	stw	r3,740(r4)
+     4a8:	2140ba15 	stw	r5,744(r4)
+     4ac:	2000b815 	stw	zero,736(r4)
+     4b0:	10001705 	stb	zero,92(r2)
+     4b4:	10001745 	stb	zero,93(r2)
+     4b8:	10001785 	stb	zero,94(r2)
+     4bc:	100017c5 	stb	zero,95(r2)
+     4c0:	10001805 	stb	zero,96(r2)
+     4c4:	10001845 	stb	zero,97(r2)
+     4c8:	10001885 	stb	zero,98(r2)
+     4cc:	100018c5 	stb	zero,99(r2)
+     4d0:	00c00104 	movi	r3,4
+     4d4:	10c00315 	stw	r3,12(r2)
+     4d8:	02000034 	movhi	r8,0
+     4dc:	20c00217 	ldw	r3,8(r4)
+     4e0:	01c00034 	movhi	r7,0
+     4e4:	01800034 	movhi	r6,0
+     4e8:	01400034 	movhi	r5,0
+     4ec:	4207eb04 	addi	r8,r8,8108
+     4f0:	39c80204 	addi	r7,r7,8200
+     4f4:	31882204 	addi	r6,r6,8328
+     4f8:	29483904 	addi	r5,r5,8420
+     4fc:	02400074 	movhi	r9,1
+     500:	10001915 	stw	zero,100(r2)
+     504:	10000015 	stw	zero,0(r2)
+     508:	10000115 	stw	zero,4(r2)
+     50c:	10000215 	stw	zero,8(r2)
+     510:	10000415 	stw	zero,16(r2)
+     514:	10000515 	stw	zero,20(r2)
+     518:	10000615 	stw	zero,24(r2)
+     51c:	10800715 	stw	r2,28(r2)
+     520:	12000815 	stw	r8,32(r2)
+     524:	11c00915 	stw	r7,36(r2)
+     528:	11800a15 	stw	r6,40(r2)
+     52c:	11400b15 	stw	r5,44(r2)
+     530:	4a400284 	addi	r9,r9,10
+     534:	1a400315 	stw	r9,12(r3)
+     538:	18001915 	stw	zero,100(r3)
+     53c:	18000015 	stw	zero,0(r3)
+     540:	18000115 	stw	zero,4(r3)
+     544:	18000215 	stw	zero,8(r3)
+     548:	18000415 	stw	zero,16(r3)
+     54c:	18001705 	stb	zero,92(r3)
+     550:	18001745 	stb	zero,93(r3)
+     554:	18001785 	stb	zero,94(r3)
+     558:	180017c5 	stb	zero,95(r3)
+     55c:	18001805 	stb	zero,96(r3)
+     560:	18001845 	stb	zero,97(r3)
+     564:	18001885 	stb	zero,98(r3)
+     568:	180018c5 	stb	zero,99(r3)
+     56c:	20800317 	ldw	r2,12(r4)
+     570:	024000b4 	movhi	r9,2
+     574:	18000515 	stw	zero,20(r3)
+     578:	18000615 	stw	zero,24(r3)
+     57c:	18c00715 	stw	r3,28(r3)
+     580:	1a000815 	stw	r8,32(r3)
+     584:	19c00915 	stw	r7,36(r3)
+     588:	19800a15 	stw	r6,40(r3)
+     58c:	19400b15 	stw	r5,44(r3)
+     590:	4a400484 	addi	r9,r9,18
+     594:	10001915 	stw	zero,100(r2)
+     598:	10000015 	stw	zero,0(r2)
+     59c:	10000115 	stw	zero,4(r2)
+     5a0:	10000215 	stw	zero,8(r2)
+     5a4:	12400315 	stw	r9,12(r2)
+     5a8:	10000415 	stw	zero,16(r2)
+     5ac:	10000515 	stw	zero,20(r2)
+     5b0:	10000615 	stw	zero,24(r2)
+     5b4:	10001705 	stb	zero,92(r2)
+     5b8:	10001745 	stb	zero,93(r2)
+     5bc:	10001785 	stb	zero,94(r2)
+     5c0:	100017c5 	stb	zero,95(r2)
+     5c4:	10001805 	stb	zero,96(r2)
+     5c8:	10001845 	stb	zero,97(r2)
+     5cc:	10001885 	stb	zero,98(r2)
+     5d0:	100018c5 	stb	zero,99(r2)
+     5d4:	10800715 	stw	r2,28(r2)
+     5d8:	12000815 	stw	r8,32(r2)
+     5dc:	11c00915 	stw	r7,36(r2)
+     5e0:	11800a15 	stw	r6,40(r2)
+     5e4:	11400b15 	stw	r5,44(r2)
+     5e8:	00800044 	movi	r2,1
+     5ec:	20800e15 	stw	r2,56(r4)
+     5f0:	f800283a 	ret
 
-0000065c <__sfmoreglue>:
-     65c:	defffc04 	addi	sp,sp,-16
-     660:	dc800215 	stw	r18,8(sp)
-     664:	2825883a 	mov	r18,r5
-     668:	dc000015 	stw	r16,0(sp)
-     66c:	01401a04 	movi	r5,104
-     670:	2021883a 	mov	r16,r4
-     674:	913fffc4 	addi	r4,r18,-1
-     678:	dfc00315 	stw	ra,12(sp)
+000005f4 <__sfmoreglue>:
+     5f4:	defffc04 	addi	sp,sp,-16
+     5f8:	dc800215 	stw	r18,8(sp)
+     5fc:	2825883a 	mov	r18,r5
+     600:	dc000015 	stw	r16,0(sp)
+     604:	01401a04 	movi	r5,104
+     608:	2021883a 	mov	r16,r4
+     60c:	913fffc4 	addi	r4,r18,-1
+     610:	dfc00315 	stw	ra,12(sp)
+     614:	dc400115 	stw	r17,4(sp)
+     618:	000314c0 	call	314c <__mulsi3>
+     61c:	8009883a 	mov	r4,r16
+     620:	11401d04 	addi	r5,r2,116
+     624:	1023883a 	mov	r17,r2
+     628:	0000e240 	call	e24 <_malloc_r>
+     62c:	1021883a 	mov	r16,r2
+     630:	10000726 	beq	r2,zero,650 <__sfmoreglue+0x5c>
+     634:	11000304 	addi	r4,r2,12
+     638:	10000015 	stw	zero,0(r2)
+     63c:	14800115 	stw	r18,4(r2)
+     640:	11000215 	stw	r4,8(r2)
+     644:	89801a04 	addi	r6,r17,104
+     648:	000b883a 	mov	r5,zero
+     64c:	00019000 	call	1900 <memset>
+     650:	8005883a 	mov	r2,r16
+     654:	dfc00317 	ldw	ra,12(sp)
+     658:	dc800217 	ldw	r18,8(sp)
+     65c:	dc400117 	ldw	r17,4(sp)
+     660:	dc000017 	ldw	r16,0(sp)
+     664:	dec00404 	addi	sp,sp,16
+     668:	f800283a 	ret
+
+0000066c <__sfp>:
+     66c:	defffb04 	addi	sp,sp,-20
+     670:	00800034 	movhi	r2,0
+     674:	dc000015 	stw	r16,0(sp)
+     678:	141c7817 	ldw	r16,29152(r2)
      67c:	dc400115 	stw	r17,4(sp)
-     680:	000311c0 	call	311c <__mulsi3>
-     684:	8009883a 	mov	r4,r16
-     688:	11401d04 	addi	r5,r2,116
-     68c:	1023883a 	mov	r17,r2
-     690:	0000ea40 	call	ea4 <_malloc_r>
-     694:	1021883a 	mov	r16,r2
-     698:	10000726 	beq	r2,zero,6b8 <__sfmoreglue+0x5c>
-     69c:	11000304 	addi	r4,r2,12
-     6a0:	10000015 	stw	zero,0(r2)
-     6a4:	14800115 	stw	r18,4(r2)
-     6a8:	11000215 	stw	r4,8(r2)
-     6ac:	89801a04 	addi	r6,r17,104
-     6b0:	000b883a 	mov	r5,zero
-     6b4:	0001a380 	call	1a38 <memset>
-     6b8:	8005883a 	mov	r2,r16
-     6bc:	dfc00317 	ldw	ra,12(sp)
-     6c0:	dc800217 	ldw	r18,8(sp)
-     6c4:	dc400117 	ldw	r17,4(sp)
-     6c8:	dc000017 	ldw	r16,0(sp)
-     6cc:	dec00404 	addi	sp,sp,16
-     6d0:	f800283a 	ret
+     680:	dfc00415 	stw	ra,16(sp)
+     684:	80800e17 	ldw	r2,56(r16)
+     688:	dcc00315 	stw	r19,12(sp)
+     68c:	dc800215 	stw	r18,8(sp)
+     690:	2023883a 	mov	r17,r4
+     694:	10003126 	beq	r2,zero,75c <__sfp+0xf0>
+     698:	8100ba17 	ldw	r4,744(r16)
+     69c:	8140b917 	ldw	r5,740(r16)
+     6a0:	04c00104 	movi	r19,4
+     6a4:	8400b804 	addi	r16,r16,736
+     6a8:	297fffc4 	addi	r5,r5,-1
+     6ac:	2800050e 	bge	r5,zero,6c4 <__sfp+0x58>
+     6b0:	00002406 	br	744 <__sfp+0xd8>
+     6b4:	297fffc4 	addi	r5,r5,-1
+     6b8:	28bfffd8 	cmpnei	r2,r5,-1
+     6bc:	21001a04 	addi	r4,r4,104
+     6c0:	10002026 	beq	r2,zero,744 <__sfp+0xd8>
+     6c4:	2080030f 	ldh	r2,12(r4)
+     6c8:	103ffa1e 	bne	r2,zero,6b4 <__sfp+0x48>
+     6cc:	00bffff4 	movhi	r2,65535
+     6d0:	10800044 	addi	r2,r2,1
+     6d4:	20001915 	stw	zero,100(r4)
+     6d8:	20000015 	stw	zero,0(r4)
+     6dc:	20000115 	stw	zero,4(r4)
+     6e0:	20000215 	stw	zero,8(r4)
+     6e4:	20800315 	stw	r2,12(r4)
+     6e8:	20000415 	stw	zero,16(r4)
+     6ec:	20000515 	stw	zero,20(r4)
+     6f0:	20000615 	stw	zero,24(r4)
+     6f4:	20001705 	stb	zero,92(r4)
+     6f8:	20001745 	stb	zero,93(r4)
+     6fc:	20001785 	stb	zero,94(r4)
+     700:	200017c5 	stb	zero,95(r4)
+     704:	20001805 	stb	zero,96(r4)
+     708:	20001845 	stb	zero,97(r4)
+     70c:	20001885 	stb	zero,98(r4)
+     710:	200018c5 	stb	zero,99(r4)
+     714:	20000c15 	stw	zero,48(r4)
+     718:	20000d15 	stw	zero,52(r4)
+     71c:	20001115 	stw	zero,68(r4)
+     720:	20001215 	stw	zero,72(r4)
+     724:	2005883a 	mov	r2,r4
+     728:	dfc00417 	ldw	ra,16(sp)
+     72c:	dcc00317 	ldw	r19,12(sp)
+     730:	dc800217 	ldw	r18,8(sp)
+     734:	dc400117 	ldw	r17,4(sp)
+     738:	dc000017 	ldw	r16,0(sp)
+     73c:	dec00504 	addi	sp,sp,20
+     740:	f800283a 	ret
+     744:	80800017 	ldw	r2,0(r16)
+     748:	10000726 	beq	r2,zero,768 <__sfp+0xfc>
+     74c:	11000217 	ldw	r4,8(r2)
+     750:	11400117 	ldw	r5,4(r2)
+     754:	1021883a 	mov	r16,r2
+     758:	003fd306 	br	6a8 <__sfp+0x3c>
+     75c:	8009883a 	mov	r4,r16
+     760:	000048c0 	call	48c <__sinit.part.0>
+     764:	003fcc06 	br	698 <__sfp+0x2c>
+     768:	01406b04 	movi	r5,428
+     76c:	8809883a 	mov	r4,r17
+     770:	0000e240 	call	e24 <_malloc_r>
+     774:	1025883a 	mov	r18,r2
+     778:	10000c26 	beq	r2,zero,7ac <__sfp+0x140>
+     77c:	11000304 	addi	r4,r2,12
+     780:	11000215 	stw	r4,8(r2)
+     784:	000b883a 	mov	r5,zero
+     788:	10000015 	stw	zero,0(r2)
+     78c:	14c00115 	stw	r19,4(r2)
+     790:	01806804 	movi	r6,416
+     794:	00019000 	call	1900 <memset>
+     798:	1009883a 	mov	r4,r2
+     79c:	84800015 	stw	r18,0(r16)
+     7a0:	014000c4 	movi	r5,3
+     7a4:	9021883a 	mov	r16,r18
+     7a8:	003fc606 	br	6c4 <__sfp+0x58>
+     7ac:	80000015 	stw	zero,0(r16)
+     7b0:	00800304 	movi	r2,12
+     7b4:	88800015 	stw	r2,0(r17)
+     7b8:	0009883a 	mov	r4,zero
+     7bc:	003fd906 	br	724 <__sfp+0xb8>
 
-000006d4 <__sfp>:
-     6d4:	defffb04 	addi	sp,sp,-20
-     6d8:	dc000015 	stw	r16,0(sp)
-     6dc:	04000034 	movhi	r16,0
-     6e0:	841ca404 	addi	r16,r16,29328
-     6e4:	dcc00315 	stw	r19,12(sp)
-     6e8:	2027883a 	mov	r19,r4
-     6ec:	81000017 	ldw	r4,0(r16)
-     6f0:	dfc00415 	stw	ra,16(sp)
-     6f4:	dc800215 	stw	r18,8(sp)
-     6f8:	20800e17 	ldw	r2,56(r4)
-     6fc:	dc400115 	stw	r17,4(sp)
-     700:	1000021e 	bne	r2,zero,70c <__sfp+0x38>
-     704:	00004b80 	call	4b8 <__sinit.part.1>
-     708:	81000017 	ldw	r4,0(r16)
-     70c:	2480b804 	addi	r18,r4,736
-     710:	047fffc4 	movi	r17,-1
-     714:	91000117 	ldw	r4,4(r18)
-     718:	94000217 	ldw	r16,8(r18)
-     71c:	213fffc4 	addi	r4,r4,-1
-     720:	20000a16 	blt	r4,zero,74c <__sfp+0x78>
-     724:	8080030f 	ldh	r2,12(r16)
-     728:	10000c26 	beq	r2,zero,75c <__sfp+0x88>
-     72c:	80c01d04 	addi	r3,r16,116
-     730:	00000206 	br	73c <__sfp+0x68>
-     734:	18bfe60f 	ldh	r2,-104(r3)
-     738:	10000826 	beq	r2,zero,75c <__sfp+0x88>
-     73c:	213fffc4 	addi	r4,r4,-1
-     740:	1c3ffd04 	addi	r16,r3,-12
-     744:	18c01a04 	addi	r3,r3,104
-     748:	247ffa1e 	bne	r4,r17,734 <__alt_data_end+0xfffe0734>
-     74c:	90800017 	ldw	r2,0(r18)
-     750:	10001d26 	beq	r2,zero,7c8 <__sfp+0xf4>
-     754:	1025883a 	mov	r18,r2
-     758:	003fee06 	br	714 <__alt_data_end+0xfffe0714>
-     75c:	00bfffc4 	movi	r2,-1
-     760:	8080038d 	sth	r2,14(r16)
-     764:	00800044 	movi	r2,1
-     768:	8080030d 	sth	r2,12(r16)
-     76c:	80001915 	stw	zero,100(r16)
-     770:	80000015 	stw	zero,0(r16)
-     774:	80000215 	stw	zero,8(r16)
-     778:	80000115 	stw	zero,4(r16)
-     77c:	80000415 	stw	zero,16(r16)
-     780:	80000515 	stw	zero,20(r16)
-     784:	80000615 	stw	zero,24(r16)
-     788:	01800204 	movi	r6,8
-     78c:	000b883a 	mov	r5,zero
-     790:	81001704 	addi	r4,r16,92
-     794:	0001a380 	call	1a38 <memset>
-     798:	8005883a 	mov	r2,r16
-     79c:	80000c15 	stw	zero,48(r16)
-     7a0:	80000d15 	stw	zero,52(r16)
-     7a4:	80001115 	stw	zero,68(r16)
-     7a8:	80001215 	stw	zero,72(r16)
-     7ac:	dfc00417 	ldw	ra,16(sp)
-     7b0:	dcc00317 	ldw	r19,12(sp)
-     7b4:	dc800217 	ldw	r18,8(sp)
-     7b8:	dc400117 	ldw	r17,4(sp)
-     7bc:	dc000017 	ldw	r16,0(sp)
-     7c0:	dec00504 	addi	sp,sp,20
-     7c4:	f800283a 	ret
-     7c8:	01400104 	movi	r5,4
-     7cc:	9809883a 	mov	r4,r19
-     7d0:	000065c0 	call	65c <__sfmoreglue>
-     7d4:	90800015 	stw	r2,0(r18)
-     7d8:	103fde1e 	bne	r2,zero,754 <__alt_data_end+0xfffe0754>
-     7dc:	00800304 	movi	r2,12
-     7e0:	98800015 	stw	r2,0(r19)
-     7e4:	0005883a 	mov	r2,zero
-     7e8:	003ff006 	br	7ac <__alt_data_end+0xfffe07ac>
+000007c0 <_cleanup>:
+     7c0:	00800034 	movhi	r2,0
+     7c4:	111c7817 	ldw	r4,29152(r2)
+     7c8:	01400034 	movhi	r5,0
+     7cc:	2948f304 	addi	r5,r5,9164
+     7d0:	0000d7c1 	jmpi	d7c <_fwalk_reent>
 
-000007ec <_cleanup>:
-     7ec:	00800034 	movhi	r2,0
-     7f0:	109ca404 	addi	r2,r2,29328
-     7f4:	11000017 	ldw	r4,0(r2)
-     7f8:	01400034 	movhi	r5,0
-     7fc:	29491704 	addi	r5,r5,9308
-     800:	0000de01 	jmpi	de0 <_fwalk_reent>
+000007d4 <__sinit>:
+     7d4:	20800e17 	ldw	r2,56(r4)
+     7d8:	10000126 	beq	r2,zero,7e0 <__sinit+0xc>
+     7dc:	f800283a 	ret
+     7e0:	000048c1 	jmpi	48c <__sinit.part.0>
 
-00000804 <__sinit>:
-     804:	20800e17 	ldw	r2,56(r4)
-     808:	10000126 	beq	r2,zero,810 <__sinit+0xc>
-     80c:	f800283a 	ret
-     810:	00004b81 	jmpi	4b8 <__sinit.part.1>
+000007e4 <__sfp_lock_acquire>:
+     7e4:	f800283a 	ret
 
-00000814 <__sfp_lock_acquire>:
-     814:	f800283a 	ret
+000007e8 <__sfp_lock_release>:
+     7e8:	f800283a 	ret
 
-00000818 <__sfp_lock_release>:
-     818:	f800283a 	ret
+000007ec <__sinit_lock_acquire>:
+     7ec:	f800283a 	ret
 
-0000081c <__sinit_lock_acquire>:
-     81c:	f800283a 	ret
+000007f0 <__sinit_lock_release>:
+     7f0:	f800283a 	ret
 
-00000820 <__sinit_lock_release>:
-     820:	f800283a 	ret
+000007f4 <__fp_lock_all>:
+     7f4:	00800034 	movhi	r2,0
+     7f8:	111c7917 	ldw	r4,29156(r2)
+     7fc:	01400034 	movhi	r5,0
+     800:	29411c04 	addi	r5,r5,1136
+     804:	0000ce41 	jmpi	ce4 <_fwalk>
 
-00000824 <__fp_lock_all>:
-     824:	00800034 	movhi	r2,0
-     828:	109ca504 	addi	r2,r2,29332
-     82c:	11000017 	ldw	r4,0(r2)
-     830:	01400034 	movhi	r5,0
-     834:	29419504 	addi	r5,r5,1620
-     838:	0000d1c1 	jmpi	d1c <_fwalk>
+00000808 <__fp_unlock_all>:
+     808:	00800034 	movhi	r2,0
+     80c:	111c7917 	ldw	r4,29156(r2)
+     810:	01400034 	movhi	r5,0
+     814:	29412104 	addi	r5,r5,1156
+     818:	0000ce41 	jmpi	ce4 <_fwalk>
 
-0000083c <__fp_unlock_all>:
-     83c:	00800034 	movhi	r2,0
-     840:	109ca504 	addi	r2,r2,29332
-     844:	11000017 	ldw	r4,0(r2)
-     848:	01400034 	movhi	r5,0
-     84c:	29412904 	addi	r5,r5,1188
-     850:	0000d1c1 	jmpi	d1c <_fwalk>
+0000081c <__sfvwrite_r>:
+     81c:	30800217 	ldw	r2,8(r6)
+     820:	1000a326 	beq	r2,zero,ab0 <__sfvwrite_r+0x294>
+     824:	29c0030b 	ldhu	r7,12(r5)
+     828:	defff404 	addi	sp,sp,-48
+     82c:	ddc00915 	stw	r23,36(sp)
+     830:	dd400715 	stw	r21,28(sp)
+     834:	dc000215 	stw	r16,8(sp)
+     838:	dfc00b15 	stw	ra,44(sp)
+     83c:	df000a15 	stw	fp,40(sp)
+     840:	dd800815 	stw	r22,32(sp)
+     844:	dd000615 	stw	r20,24(sp)
+     848:	dcc00515 	stw	r19,20(sp)
+     84c:	dc800415 	stw	r18,16(sp)
+     850:	dc400315 	stw	r17,12(sp)
+     854:	3880020c 	andi	r2,r7,8
+     858:	302f883a 	mov	r23,r6
+     85c:	202b883a 	mov	r21,r4
+     860:	2821883a 	mov	r16,r5
+     864:	10002226 	beq	r2,zero,8f0 <__sfvwrite_r+0xd4>
+     868:	28800417 	ldw	r2,16(r5)
+     86c:	10002026 	beq	r2,zero,8f0 <__sfvwrite_r+0xd4>
+     870:	3880008c 	andi	r2,r7,2
+     874:	bc400017 	ldw	r17,0(r23)
+     878:	10002526 	beq	r2,zero,910 <__sfvwrite_r+0xf4>
+     87c:	80800917 	ldw	r2,36(r16)
+     880:	81400717 	ldw	r5,28(r16)
+     884:	05200034 	movhi	r20,32768
+     888:	0027883a 	mov	r19,zero
+     88c:	0025883a 	mov	r18,zero
+     890:	a53f0004 	addi	r20,r20,-1024
+     894:	980d883a 	mov	r6,r19
+     898:	a809883a 	mov	r4,r21
+     89c:	90001026 	beq	r18,zero,8e0 <__sfvwrite_r+0xc4>
+     8a0:	900f883a 	mov	r7,r18
+     8a4:	a480012e 	bgeu	r20,r18,8ac <__sfvwrite_r+0x90>
+     8a8:	a00f883a 	mov	r7,r20
+     8ac:	103ee83a 	callr	r2
+     8b0:	00807a0e 	bge	zero,r2,a9c <__sfvwrite_r+0x280>
+     8b4:	b9000217 	ldw	r4,8(r23)
+     8b8:	98a7883a 	add	r19,r19,r2
+     8bc:	90a5c83a 	sub	r18,r18,r2
+     8c0:	2085c83a 	sub	r2,r4,r2
+     8c4:	b8800215 	stw	r2,8(r23)
+     8c8:	10006326 	beq	r2,zero,a58 <__sfvwrite_r+0x23c>
+     8cc:	80800917 	ldw	r2,36(r16)
+     8d0:	81400717 	ldw	r5,28(r16)
+     8d4:	980d883a 	mov	r6,r19
+     8d8:	a809883a 	mov	r4,r21
+     8dc:	903ff01e 	bne	r18,zero,8a0 <__sfvwrite_r+0x84>
+     8e0:	8cc00017 	ldw	r19,0(r17)
+     8e4:	8c800117 	ldw	r18,4(r17)
+     8e8:	8c400204 	addi	r17,r17,8
+     8ec:	003fe906 	br	894 <__sfvwrite_r+0x78>
+     8f0:	800b883a 	mov	r5,r16
+     8f4:	a809883a 	mov	r4,r21
+     8f8:	00021500 	call	2150 <__swsetup_r>
+     8fc:	1000f71e 	bne	r2,zero,cdc <__sfvwrite_r+0x4c0>
+     900:	81c0030b 	ldhu	r7,12(r16)
+     904:	bc400017 	ldw	r17,0(r23)
+     908:	3880008c 	andi	r2,r7,2
+     90c:	103fdb1e 	bne	r2,zero,87c <__sfvwrite_r+0x60>
+     910:	3880004c 	andi	r2,r7,1
+     914:	84800217 	ldw	r18,8(r16)
+     918:	82000017 	ldw	r8,0(r16)
+     91c:	1000661e 	bne	r2,zero,ab8 <__sfvwrite_r+0x29c>
+     920:	00a00034 	movhi	r2,32768
+     924:	10bfff84 	addi	r2,r2,-2
+     928:	00e00034 	movhi	r3,32768
+     92c:	d8800015 	stw	r2,0(sp)
+     930:	18bfffc4 	addi	r2,r3,-1
+     934:	0039883a 	mov	fp,zero
+     938:	0027883a 	mov	r19,zero
+     93c:	d8800115 	stw	r2,4(sp)
+     940:	98004126 	beq	r19,zero,a48 <__sfvwrite_r+0x22c>
+     944:	3880800c 	andi	r2,r7,512
+     948:	10009726 	beq	r2,zero,ba8 <__sfvwrite_r+0x38c>
+     94c:	902d883a 	mov	r22,r18
+     950:	9c80be36 	bltu	r19,r18,c4c <__sfvwrite_r+0x430>
+     954:	3881200c 	andi	r2,r7,1152
+     958:	10002626 	beq	r2,zero,9f4 <__sfvwrite_r+0x1d8>
+     95c:	81800517 	ldw	r6,20(r16)
+     960:	81400417 	ldw	r5,16(r16)
+     964:	98800044 	addi	r2,r19,1
+     968:	3189883a 	add	r4,r6,r6
+     96c:	2189883a 	add	r4,r4,r6
+     970:	2028d7fa 	srli	r20,r4,31
+     974:	4165c83a 	sub	r18,r8,r5
+     978:	1485883a 	add	r2,r2,r18
+     97c:	a109883a 	add	r4,r20,r4
+     980:	2029d07a 	srai	r20,r4,1
+     984:	a00d883a 	mov	r6,r20
+     988:	a080022e 	bgeu	r20,r2,994 <__sfvwrite_r+0x178>
+     98c:	1029883a 	mov	r20,r2
+     990:	100d883a 	mov	r6,r2
+     994:	39c1000c 	andi	r7,r7,1024
+     998:	3800c026 	beq	r7,zero,c9c <__sfvwrite_r+0x480>
+     99c:	a809883a 	mov	r4,r21
+     9a0:	300b883a 	mov	r5,r6
+     9a4:	0000e240 	call	e24 <_malloc_r>
+     9a8:	1009883a 	mov	r4,r2
+     9ac:	1000c726 	beq	r2,zero,ccc <__sfvwrite_r+0x4b0>
+     9b0:	81400417 	ldw	r5,16(r16)
+     9b4:	900d883a 	mov	r6,r18
+     9b8:	00016d40 	call	16d4 <memcpy>
+     9bc:	1009883a 	mov	r4,r2
+     9c0:	8080030b 	ldhu	r2,12(r16)
+     9c4:	00fedfc4 	movi	r3,-1153
+     9c8:	10c4703a 	and	r2,r2,r3
+     9cc:	10802014 	ori	r2,r2,128
+     9d0:	8080030d 	sth	r2,12(r16)
+     9d4:	2491883a 	add	r8,r4,r18
+     9d8:	a485c83a 	sub	r2,r20,r18
+     9dc:	81000415 	stw	r4,16(r16)
+     9e0:	82000015 	stw	r8,0(r16)
+     9e4:	85000515 	stw	r20,20(r16)
+     9e8:	9825883a 	mov	r18,r19
+     9ec:	80800215 	stw	r2,8(r16)
+     9f0:	982d883a 	mov	r22,r19
+     9f4:	4009883a 	mov	r4,r8
+     9f8:	b00d883a 	mov	r6,r22
+     9fc:	e00b883a 	mov	r5,fp
+     a00:	00017d40 	call	17d4 <memmove>
+     a04:	81000217 	ldw	r4,8(r16)
+     a08:	80800017 	ldw	r2,0(r16)
+     a0c:	9829883a 	mov	r20,r19
+     a10:	24a5c83a 	sub	r18,r4,r18
+     a14:	1585883a 	add	r2,r2,r22
+     a18:	84800215 	stw	r18,8(r16)
+     a1c:	80800015 	stw	r2,0(r16)
+     a20:	0027883a 	mov	r19,zero
+     a24:	b8800217 	ldw	r2,8(r23)
+     a28:	e539883a 	add	fp,fp,r20
+     a2c:	1529c83a 	sub	r20,r2,r20
+     a30:	bd000215 	stw	r20,8(r23)
+     a34:	a0000826 	beq	r20,zero,a58 <__sfvwrite_r+0x23c>
+     a38:	81c0030b 	ldhu	r7,12(r16)
+     a3c:	84800217 	ldw	r18,8(r16)
+     a40:	82000017 	ldw	r8,0(r16)
+     a44:	983fbf1e 	bne	r19,zero,944 <__sfvwrite_r+0x128>
+     a48:	8f000017 	ldw	fp,0(r17)
+     a4c:	8cc00117 	ldw	r19,4(r17)
+     a50:	8c400204 	addi	r17,r17,8
+     a54:	003fba06 	br	940 <__sfvwrite_r+0x124>
+     a58:	0005883a 	mov	r2,zero
+     a5c:	dfc00b17 	ldw	ra,44(sp)
+     a60:	df000a17 	ldw	fp,40(sp)
+     a64:	ddc00917 	ldw	r23,36(sp)
+     a68:	dd800817 	ldw	r22,32(sp)
+     a6c:	dd400717 	ldw	r21,28(sp)
+     a70:	dd000617 	ldw	r20,24(sp)
+     a74:	dcc00517 	ldw	r19,20(sp)
+     a78:	dc800417 	ldw	r18,16(sp)
+     a7c:	dc400317 	ldw	r17,12(sp)
+     a80:	dc000217 	ldw	r16,8(sp)
+     a84:	dec00c04 	addi	sp,sp,48
+     a88:	f800283a 	ret
+     a8c:	800b883a 	mov	r5,r16
+     a90:	a809883a 	mov	r4,r21
+     a94:	00026d40 	call	26d4 <_fflush_r>
+     a98:	10002026 	beq	r2,zero,b1c <__sfvwrite_r+0x300>
+     a9c:	8080030b 	ldhu	r2,12(r16)
+     aa0:	10801014 	ori	r2,r2,64
+     aa4:	8080030d 	sth	r2,12(r16)
+     aa8:	00bfffc4 	movi	r2,-1
+     aac:	003feb06 	br	a5c <__sfvwrite_r+0x240>
+     ab0:	0005883a 	mov	r2,zero
+     ab4:	f800283a 	ret
+     ab8:	002d883a 	mov	r22,zero
+     abc:	0027883a 	mov	r19,zero
+     ac0:	0005883a 	mov	r2,zero
+     ac4:	0039883a 	mov	fp,zero
+     ac8:	b0001d26 	beq	r22,zero,b40 <__sfvwrite_r+0x324>
+     acc:	10002026 	beq	r2,zero,b50 <__sfvwrite_r+0x334>
+     ad0:	9829883a 	mov	r20,r19
+     ad4:	b500012e 	bgeu	r22,r20,adc <__sfvwrite_r+0x2c0>
+     ad8:	b029883a 	mov	r20,r22
+     adc:	80800417 	ldw	r2,16(r16)
+     ae0:	81c00517 	ldw	r7,20(r16)
+     ae4:	1200022e 	bgeu	r2,r8,af0 <__sfvwrite_r+0x2d4>
+     ae8:	3ca5883a 	add	r18,r7,r18
+     aec:	95002216 	blt	r18,r20,b78 <__sfvwrite_r+0x35c>
+     af0:	a1c05916 	blt	r20,r7,c58 <__sfvwrite_r+0x43c>
+     af4:	80800917 	ldw	r2,36(r16)
+     af8:	81400717 	ldw	r5,28(r16)
+     afc:	e00d883a 	mov	r6,fp
+     b00:	a809883a 	mov	r4,r21
+     b04:	103ee83a 	callr	r2
+     b08:	1025883a 	mov	r18,r2
+     b0c:	00bfe30e 	bge	zero,r2,a9c <__sfvwrite_r+0x280>
+     b10:	9ca7c83a 	sub	r19,r19,r18
+     b14:	983fdd26 	beq	r19,zero,a8c <__sfvwrite_r+0x270>
+     b18:	00800044 	movi	r2,1
+     b1c:	b9800217 	ldw	r6,8(r23)
+     b20:	e4b9883a 	add	fp,fp,r18
+     b24:	b4adc83a 	sub	r22,r22,r18
+     b28:	34a5c83a 	sub	r18,r6,r18
+     b2c:	bc800215 	stw	r18,8(r23)
+     b30:	903fc926 	beq	r18,zero,a58 <__sfvwrite_r+0x23c>
+     b34:	84800217 	ldw	r18,8(r16)
+     b38:	82000017 	ldw	r8,0(r16)
+     b3c:	b03fe31e 	bne	r22,zero,acc <__sfvwrite_r+0x2b0>
+     b40:	8d800117 	ldw	r22,4(r17)
+     b44:	8f000017 	ldw	fp,0(r17)
+     b48:	8c400204 	addi	r17,r17,8
+     b4c:	b03ffc26 	beq	r22,zero,b40 <__sfvwrite_r+0x324>
+     b50:	b00d883a 	mov	r6,r22
+     b54:	01400284 	movi	r5,10
+     b58:	e009883a 	mov	r4,fp
+     b5c:	da000015 	stw	r8,0(sp)
+     b60:	00016040 	call	1604 <memchr>
+     b64:	da000017 	ldw	r8,0(sp)
+     b68:	10004926 	beq	r2,zero,c90 <__sfvwrite_r+0x474>
+     b6c:	10800044 	addi	r2,r2,1
+     b70:	1727c83a 	sub	r19,r2,fp
+     b74:	003fd606 	br	ad0 <__sfvwrite_r+0x2b4>
+     b78:	e00b883a 	mov	r5,fp
+     b7c:	4009883a 	mov	r4,r8
+     b80:	900d883a 	mov	r6,r18
+     b84:	00017d40 	call	17d4 <memmove>
+     b88:	80800017 	ldw	r2,0(r16)
+     b8c:	800b883a 	mov	r5,r16
+     b90:	a809883a 	mov	r4,r21
+     b94:	1485883a 	add	r2,r2,r18
+     b98:	80800015 	stw	r2,0(r16)
+     b9c:	00026d40 	call	26d4 <_fflush_r>
+     ba0:	103fdb26 	beq	r2,zero,b10 <__sfvwrite_r+0x2f4>
+     ba4:	003fbd06 	br	a9c <__sfvwrite_r+0x280>
+     ba8:	80800417 	ldw	r2,16(r16)
+     bac:	12001436 	bltu	r2,r8,c00 <__sfvwrite_r+0x3e4>
+     bb0:	85000517 	ldw	r20,20(r16)
+     bb4:	9d001236 	bltu	r19,r20,c00 <__sfvwrite_r+0x3e4>
+     bb8:	d8800017 	ldw	r2,0(sp)
+     bbc:	14c0322e 	bgeu	r2,r19,c88 <__sfvwrite_r+0x46c>
+     bc0:	d9000117 	ldw	r4,4(sp)
+     bc4:	a00b883a 	mov	r5,r20
+     bc8:	0002f980 	call	2f98 <__divsi3>
+     bcc:	a00b883a 	mov	r5,r20
+     bd0:	1009883a 	mov	r4,r2
+     bd4:	000314c0 	call	314c <__mulsi3>
+     bd8:	82000917 	ldw	r8,36(r16)
+     bdc:	81400717 	ldw	r5,28(r16)
+     be0:	100f883a 	mov	r7,r2
+     be4:	e00d883a 	mov	r6,fp
+     be8:	a809883a 	mov	r4,r21
+     bec:	403ee83a 	callr	r8
+     bf0:	1029883a 	mov	r20,r2
+     bf4:	00bfa90e 	bge	zero,r2,a9c <__sfvwrite_r+0x280>
+     bf8:	9d27c83a 	sub	r19,r19,r20
+     bfc:	003f8906 	br	a24 <__sfvwrite_r+0x208>
+     c00:	9029883a 	mov	r20,r18
+     c04:	9c80012e 	bgeu	r19,r18,c0c <__sfvwrite_r+0x3f0>
+     c08:	9829883a 	mov	r20,r19
+     c0c:	4009883a 	mov	r4,r8
+     c10:	a00d883a 	mov	r6,r20
+     c14:	e00b883a 	mov	r5,fp
+     c18:	00017d40 	call	17d4 <memmove>
+     c1c:	80800217 	ldw	r2,8(r16)
+     c20:	81000017 	ldw	r4,0(r16)
+     c24:	1505c83a 	sub	r2,r2,r20
+     c28:	2509883a 	add	r4,r4,r20
+     c2c:	80800215 	stw	r2,8(r16)
+     c30:	81000015 	stw	r4,0(r16)
+     c34:	103ff01e 	bne	r2,zero,bf8 <__sfvwrite_r+0x3dc>
+     c38:	800b883a 	mov	r5,r16
+     c3c:	a809883a 	mov	r4,r21
+     c40:	00026d40 	call	26d4 <_fflush_r>
+     c44:	103fec26 	beq	r2,zero,bf8 <__sfvwrite_r+0x3dc>
+     c48:	003f9406 	br	a9c <__sfvwrite_r+0x280>
+     c4c:	9825883a 	mov	r18,r19
+     c50:	982d883a 	mov	r22,r19
+     c54:	003f6706 	br	9f4 <__sfvwrite_r+0x1d8>
+     c58:	4009883a 	mov	r4,r8
+     c5c:	a00d883a 	mov	r6,r20
+     c60:	e00b883a 	mov	r5,fp
+     c64:	00017d40 	call	17d4 <memmove>
+     c68:	81000217 	ldw	r4,8(r16)
+     c6c:	80800017 	ldw	r2,0(r16)
+     c70:	a025883a 	mov	r18,r20
+     c74:	2509c83a 	sub	r4,r4,r20
+     c78:	1505883a 	add	r2,r2,r20
+     c7c:	81000215 	stw	r4,8(r16)
+     c80:	80800015 	stw	r2,0(r16)
+     c84:	003fa206 	br	b10 <__sfvwrite_r+0x2f4>
+     c88:	9809883a 	mov	r4,r19
+     c8c:	003fcd06 	br	bc4 <__sfvwrite_r+0x3a8>
+     c90:	b5000044 	addi	r20,r22,1
+     c94:	a027883a 	mov	r19,r20
+     c98:	003f8e06 	br	ad4 <__sfvwrite_r+0x2b8>
+     c9c:	a809883a 	mov	r4,r21
+     ca0:	00019f00 	call	19f0 <_realloc_r>
+     ca4:	1009883a 	mov	r4,r2
+     ca8:	103f4a1e 	bne	r2,zero,9d4 <__sfvwrite_r+0x1b8>
+     cac:	81400417 	ldw	r5,16(r16)
+     cb0:	a809883a 	mov	r4,r21
+     cb4:	00028d40 	call	28d4 <_free_r>
+     cb8:	8080030b 	ldhu	r2,12(r16)
+     cbc:	00c00304 	movi	r3,12
+     cc0:	a8c00015 	stw	r3,0(r21)
+     cc4:	10bfdfcc 	andi	r2,r2,65407
+     cc8:	003f7506 	br	aa0 <__sfvwrite_r+0x284>
+     ccc:	00c00304 	movi	r3,12
+     cd0:	8080030b 	ldhu	r2,12(r16)
+     cd4:	a8c00015 	stw	r3,0(r21)
+     cd8:	003f7106 	br	aa0 <__sfvwrite_r+0x284>
+     cdc:	00bfffc4 	movi	r2,-1
+     ce0:	003f5e06 	br	a5c <__sfvwrite_r+0x240>
 
-00000854 <__sfvwrite_r>:
-     854:	30800217 	ldw	r2,8(r6)
-     858:	10006726 	beq	r2,zero,9f8 <__sfvwrite_r+0x1a4>
-     85c:	28c0030b 	ldhu	r3,12(r5)
-     860:	defff404 	addi	sp,sp,-48
-     864:	dd400715 	stw	r21,28(sp)
-     868:	dd000615 	stw	r20,24(sp)
-     86c:	dc000215 	stw	r16,8(sp)
-     870:	dfc00b15 	stw	ra,44(sp)
-     874:	df000a15 	stw	fp,40(sp)
-     878:	ddc00915 	stw	r23,36(sp)
-     87c:	dd800815 	stw	r22,32(sp)
-     880:	dcc00515 	stw	r19,20(sp)
-     884:	dc800415 	stw	r18,16(sp)
-     888:	dc400315 	stw	r17,12(sp)
-     88c:	1880020c 	andi	r2,r3,8
-     890:	2821883a 	mov	r16,r5
-     894:	202b883a 	mov	r21,r4
-     898:	3029883a 	mov	r20,r6
-     89c:	10002726 	beq	r2,zero,93c <__sfvwrite_r+0xe8>
-     8a0:	28800417 	ldw	r2,16(r5)
-     8a4:	10002526 	beq	r2,zero,93c <__sfvwrite_r+0xe8>
-     8a8:	1880008c 	andi	r2,r3,2
-     8ac:	a4400017 	ldw	r17,0(r20)
-     8b0:	10002a26 	beq	r2,zero,95c <__sfvwrite_r+0x108>
-     8b4:	05a00034 	movhi	r22,32768
-     8b8:	0027883a 	mov	r19,zero
-     8bc:	0025883a 	mov	r18,zero
-     8c0:	b5bf0004 	addi	r22,r22,-1024
-     8c4:	980d883a 	mov	r6,r19
-     8c8:	a809883a 	mov	r4,r21
-     8cc:	90004626 	beq	r18,zero,9e8 <__sfvwrite_r+0x194>
-     8d0:	900f883a 	mov	r7,r18
-     8d4:	b480022e 	bgeu	r22,r18,8e0 <__sfvwrite_r+0x8c>
-     8d8:	01e00034 	movhi	r7,32768
-     8dc:	39ff0004 	addi	r7,r7,-1024
-     8e0:	80800917 	ldw	r2,36(r16)
-     8e4:	81400717 	ldw	r5,28(r16)
-     8e8:	103ee83a 	callr	r2
-     8ec:	00805a0e 	bge	zero,r2,a58 <__sfvwrite_r+0x204>
-     8f0:	a0c00217 	ldw	r3,8(r20)
-     8f4:	98a7883a 	add	r19,r19,r2
-     8f8:	90a5c83a 	sub	r18,r18,r2
-     8fc:	1885c83a 	sub	r2,r3,r2
-     900:	a0800215 	stw	r2,8(r20)
-     904:	103fef1e 	bne	r2,zero,8c4 <__alt_data_end+0xfffe08c4>
-     908:	0005883a 	mov	r2,zero
-     90c:	dfc00b17 	ldw	ra,44(sp)
-     910:	df000a17 	ldw	fp,40(sp)
-     914:	ddc00917 	ldw	r23,36(sp)
-     918:	dd800817 	ldw	r22,32(sp)
-     91c:	dd400717 	ldw	r21,28(sp)
-     920:	dd000617 	ldw	r20,24(sp)
-     924:	dcc00517 	ldw	r19,20(sp)
-     928:	dc800417 	ldw	r18,16(sp)
-     92c:	dc400317 	ldw	r17,12(sp)
-     930:	dc000217 	ldw	r16,8(sp)
-     934:	dec00c04 	addi	sp,sp,48
-     938:	f800283a 	ret
-     93c:	800b883a 	mov	r5,r16
-     940:	a809883a 	mov	r4,r21
-     944:	00022b40 	call	22b4 <__swsetup_r>
-     948:	1000ee1e 	bne	r2,zero,d04 <__sfvwrite_r+0x4b0>
-     94c:	80c0030b 	ldhu	r3,12(r16)
-     950:	a4400017 	ldw	r17,0(r20)
-     954:	1880008c 	andi	r2,r3,2
-     958:	103fd61e 	bne	r2,zero,8b4 <__alt_data_end+0xfffe08b4>
-     95c:	1880004c 	andi	r2,r3,1
-     960:	1000421e 	bne	r2,zero,a6c <__sfvwrite_r+0x218>
-     964:	0039883a 	mov	fp,zero
-     968:	0025883a 	mov	r18,zero
-     96c:	90001a26 	beq	r18,zero,9d8 <__sfvwrite_r+0x184>
-     970:	1880800c 	andi	r2,r3,512
-     974:	84c00217 	ldw	r19,8(r16)
-     978:	10002126 	beq	r2,zero,a00 <__sfvwrite_r+0x1ac>
-     97c:	982f883a 	mov	r23,r19
-     980:	94c09636 	bltu	r18,r19,bdc <__sfvwrite_r+0x388>
-     984:	1881200c 	andi	r2,r3,1152
-     988:	1000a11e 	bne	r2,zero,c10 <__sfvwrite_r+0x3bc>
-     98c:	81000017 	ldw	r4,0(r16)
-     990:	b80d883a 	mov	r6,r23
-     994:	e00b883a 	mov	r5,fp
-     998:	00018dc0 	call	18dc <memmove>
-     99c:	80c00217 	ldw	r3,8(r16)
-     9a0:	81000017 	ldw	r4,0(r16)
-     9a4:	9005883a 	mov	r2,r18
-     9a8:	1ce7c83a 	sub	r19,r3,r19
-     9ac:	25cf883a 	add	r7,r4,r23
-     9b0:	84c00215 	stw	r19,8(r16)
-     9b4:	81c00015 	stw	r7,0(r16)
-     9b8:	a0c00217 	ldw	r3,8(r20)
-     9bc:	e0b9883a 	add	fp,fp,r2
-     9c0:	90a5c83a 	sub	r18,r18,r2
-     9c4:	18a7c83a 	sub	r19,r3,r2
-     9c8:	a4c00215 	stw	r19,8(r20)
-     9cc:	983fce26 	beq	r19,zero,908 <__alt_data_end+0xfffe0908>
-     9d0:	80c0030b 	ldhu	r3,12(r16)
-     9d4:	903fe61e 	bne	r18,zero,970 <__alt_data_end+0xfffe0970>
-     9d8:	8f000017 	ldw	fp,0(r17)
-     9dc:	8c800117 	ldw	r18,4(r17)
-     9e0:	8c400204 	addi	r17,r17,8
-     9e4:	003fe106 	br	96c <__alt_data_end+0xfffe096c>
-     9e8:	8cc00017 	ldw	r19,0(r17)
-     9ec:	8c800117 	ldw	r18,4(r17)
-     9f0:	8c400204 	addi	r17,r17,8
-     9f4:	003fb306 	br	8c4 <__alt_data_end+0xfffe08c4>
-     9f8:	0005883a 	mov	r2,zero
-     9fc:	f800283a 	ret
-     a00:	81000017 	ldw	r4,0(r16)
-     a04:	80800417 	ldw	r2,16(r16)
-     a08:	11005a36 	bltu	r2,r4,b74 <__sfvwrite_r+0x320>
-     a0c:	85c00517 	ldw	r23,20(r16)
-     a10:	95c05836 	bltu	r18,r23,b74 <__sfvwrite_r+0x320>
-     a14:	00a00034 	movhi	r2,32768
-     a18:	10bfffc4 	addi	r2,r2,-1
-     a1c:	9009883a 	mov	r4,r18
-     a20:	1480012e 	bgeu	r2,r18,a28 <__sfvwrite_r+0x1d4>
-     a24:	1009883a 	mov	r4,r2
-     a28:	b80b883a 	mov	r5,r23
-     a2c:	0002f680 	call	2f68 <__divsi3>
-     a30:	b80b883a 	mov	r5,r23
-     a34:	1009883a 	mov	r4,r2
-     a38:	000311c0 	call	311c <__mulsi3>
-     a3c:	81400717 	ldw	r5,28(r16)
-     a40:	80c00917 	ldw	r3,36(r16)
-     a44:	100f883a 	mov	r7,r2
-     a48:	e00d883a 	mov	r6,fp
-     a4c:	a809883a 	mov	r4,r21
-     a50:	183ee83a 	callr	r3
-     a54:	00bfd816 	blt	zero,r2,9b8 <__alt_data_end+0xfffe09b8>
-     a58:	8080030b 	ldhu	r2,12(r16)
-     a5c:	10801014 	ori	r2,r2,64
-     a60:	8080030d 	sth	r2,12(r16)
-     a64:	00bfffc4 	movi	r2,-1
-     a68:	003fa806 	br	90c <__alt_data_end+0xfffe090c>
-     a6c:	0027883a 	mov	r19,zero
-     a70:	0011883a 	mov	r8,zero
-     a74:	0039883a 	mov	fp,zero
-     a78:	0025883a 	mov	r18,zero
-     a7c:	90001f26 	beq	r18,zero,afc <__sfvwrite_r+0x2a8>
-     a80:	40005a26 	beq	r8,zero,bec <__sfvwrite_r+0x398>
-     a84:	982d883a 	mov	r22,r19
-     a88:	94c0012e 	bgeu	r18,r19,a90 <__sfvwrite_r+0x23c>
-     a8c:	902d883a 	mov	r22,r18
-     a90:	81000017 	ldw	r4,0(r16)
-     a94:	80800417 	ldw	r2,16(r16)
-     a98:	b02f883a 	mov	r23,r22
-     a9c:	81c00517 	ldw	r7,20(r16)
-     aa0:	1100032e 	bgeu	r2,r4,ab0 <__sfvwrite_r+0x25c>
-     aa4:	80c00217 	ldw	r3,8(r16)
-     aa8:	38c7883a 	add	r3,r7,r3
-     aac:	1d801816 	blt	r3,r22,b10 <__sfvwrite_r+0x2bc>
-     ab0:	b1c03e16 	blt	r22,r7,bac <__sfvwrite_r+0x358>
-     ab4:	80800917 	ldw	r2,36(r16)
-     ab8:	81400717 	ldw	r5,28(r16)
-     abc:	e00d883a 	mov	r6,fp
-     ac0:	da000115 	stw	r8,4(sp)
-     ac4:	a809883a 	mov	r4,r21
-     ac8:	103ee83a 	callr	r2
-     acc:	102f883a 	mov	r23,r2
-     ad0:	da000117 	ldw	r8,4(sp)
-     ad4:	00bfe00e 	bge	zero,r2,a58 <__alt_data_end+0xfffe0a58>
-     ad8:	9de7c83a 	sub	r19,r19,r23
-     adc:	98001f26 	beq	r19,zero,b5c <__sfvwrite_r+0x308>
-     ae0:	a0800217 	ldw	r2,8(r20)
-     ae4:	e5f9883a 	add	fp,fp,r23
-     ae8:	95e5c83a 	sub	r18,r18,r23
-     aec:	15efc83a 	sub	r23,r2,r23
-     af0:	a5c00215 	stw	r23,8(r20)
-     af4:	b83f8426 	beq	r23,zero,908 <__alt_data_end+0xfffe0908>
-     af8:	903fe11e 	bne	r18,zero,a80 <__alt_data_end+0xfffe0a80>
-     afc:	8f000017 	ldw	fp,0(r17)
-     b00:	8c800117 	ldw	r18,4(r17)
-     b04:	0011883a 	mov	r8,zero
-     b08:	8c400204 	addi	r17,r17,8
-     b0c:	003fdb06 	br	a7c <__alt_data_end+0xfffe0a7c>
-     b10:	180d883a 	mov	r6,r3
-     b14:	e00b883a 	mov	r5,fp
-     b18:	da000115 	stw	r8,4(sp)
-     b1c:	d8c00015 	stw	r3,0(sp)
-     b20:	00018dc0 	call	18dc <memmove>
-     b24:	d8c00017 	ldw	r3,0(sp)
-     b28:	80800017 	ldw	r2,0(r16)
-     b2c:	800b883a 	mov	r5,r16
-     b30:	a809883a 	mov	r4,r21
-     b34:	10c5883a 	add	r2,r2,r3
-     b38:	80800015 	stw	r2,0(r16)
-     b3c:	d8c00015 	stw	r3,0(sp)
-     b40:	000277c0 	call	277c <_fflush_r>
-     b44:	d8c00017 	ldw	r3,0(sp)
-     b48:	da000117 	ldw	r8,4(sp)
-     b4c:	103fc21e 	bne	r2,zero,a58 <__alt_data_end+0xfffe0a58>
-     b50:	182f883a 	mov	r23,r3
-     b54:	9de7c83a 	sub	r19,r19,r23
-     b58:	983fe11e 	bne	r19,zero,ae0 <__alt_data_end+0xfffe0ae0>
-     b5c:	800b883a 	mov	r5,r16
-     b60:	a809883a 	mov	r4,r21
-     b64:	000277c0 	call	277c <_fflush_r>
-     b68:	103fbb1e 	bne	r2,zero,a58 <__alt_data_end+0xfffe0a58>
-     b6c:	0011883a 	mov	r8,zero
-     b70:	003fdb06 	br	ae0 <__alt_data_end+0xfffe0ae0>
-     b74:	94c0012e 	bgeu	r18,r19,b7c <__sfvwrite_r+0x328>
-     b78:	9027883a 	mov	r19,r18
-     b7c:	980d883a 	mov	r6,r19
-     b80:	e00b883a 	mov	r5,fp
-     b84:	00018dc0 	call	18dc <memmove>
-     b88:	80800217 	ldw	r2,8(r16)
-     b8c:	80c00017 	ldw	r3,0(r16)
-     b90:	14c5c83a 	sub	r2,r2,r19
-     b94:	1cc7883a 	add	r3,r3,r19
-     b98:	80800215 	stw	r2,8(r16)
-     b9c:	80c00015 	stw	r3,0(r16)
-     ba0:	10004326 	beq	r2,zero,cb0 <__sfvwrite_r+0x45c>
-     ba4:	9805883a 	mov	r2,r19
-     ba8:	003f8306 	br	9b8 <__alt_data_end+0xfffe09b8>
-     bac:	b00d883a 	mov	r6,r22
-     bb0:	e00b883a 	mov	r5,fp
-     bb4:	da000115 	stw	r8,4(sp)
-     bb8:	00018dc0 	call	18dc <memmove>
-     bbc:	80800217 	ldw	r2,8(r16)
-     bc0:	80c00017 	ldw	r3,0(r16)
-     bc4:	da000117 	ldw	r8,4(sp)
-     bc8:	1585c83a 	sub	r2,r2,r22
-     bcc:	1dad883a 	add	r22,r3,r22
-     bd0:	80800215 	stw	r2,8(r16)
-     bd4:	85800015 	stw	r22,0(r16)
-     bd8:	003fbf06 	br	ad8 <__alt_data_end+0xfffe0ad8>
-     bdc:	81000017 	ldw	r4,0(r16)
-     be0:	9027883a 	mov	r19,r18
-     be4:	902f883a 	mov	r23,r18
-     be8:	003f6906 	br	990 <__alt_data_end+0xfffe0990>
-     bec:	900d883a 	mov	r6,r18
-     bf0:	01400284 	movi	r5,10
-     bf4:	e009883a 	mov	r4,fp
-     bf8:	00016b00 	call	16b0 <memchr>
-     bfc:	10003e26 	beq	r2,zero,cf8 <__sfvwrite_r+0x4a4>
-     c00:	10800044 	addi	r2,r2,1
-     c04:	1727c83a 	sub	r19,r2,fp
-     c08:	02000044 	movi	r8,1
-     c0c:	003f9d06 	br	a84 <__alt_data_end+0xfffe0a84>
-     c10:	80800517 	ldw	r2,20(r16)
-     c14:	81400417 	ldw	r5,16(r16)
-     c18:	81c00017 	ldw	r7,0(r16)
-     c1c:	10a7883a 	add	r19,r2,r2
-     c20:	9885883a 	add	r2,r19,r2
-     c24:	1026d7fa 	srli	r19,r2,31
-     c28:	396dc83a 	sub	r22,r7,r5
-     c2c:	b1000044 	addi	r4,r22,1
-     c30:	9885883a 	add	r2,r19,r2
-     c34:	1027d07a 	srai	r19,r2,1
-     c38:	2485883a 	add	r2,r4,r18
-     c3c:	980d883a 	mov	r6,r19
-     c40:	9880022e 	bgeu	r19,r2,c4c <__sfvwrite_r+0x3f8>
-     c44:	1027883a 	mov	r19,r2
-     c48:	100d883a 	mov	r6,r2
-     c4c:	18c1000c 	andi	r3,r3,1024
-     c50:	18001c26 	beq	r3,zero,cc4 <__sfvwrite_r+0x470>
-     c54:	300b883a 	mov	r5,r6
-     c58:	a809883a 	mov	r4,r21
-     c5c:	0000ea40 	call	ea4 <_malloc_r>
-     c60:	102f883a 	mov	r23,r2
-     c64:	10002926 	beq	r2,zero,d0c <__sfvwrite_r+0x4b8>
-     c68:	81400417 	ldw	r5,16(r16)
-     c6c:	b00d883a 	mov	r6,r22
-     c70:	1009883a 	mov	r4,r2
-     c74:	00017940 	call	1794 <memcpy>
-     c78:	8080030b 	ldhu	r2,12(r16)
-     c7c:	00fedfc4 	movi	r3,-1153
-     c80:	10c4703a 	and	r2,r2,r3
-     c84:	10802014 	ori	r2,r2,128
-     c88:	8080030d 	sth	r2,12(r16)
-     c8c:	bd89883a 	add	r4,r23,r22
-     c90:	9d8fc83a 	sub	r7,r19,r22
-     c94:	85c00415 	stw	r23,16(r16)
-     c98:	84c00515 	stw	r19,20(r16)
-     c9c:	81000015 	stw	r4,0(r16)
-     ca0:	9027883a 	mov	r19,r18
-     ca4:	81c00215 	stw	r7,8(r16)
-     ca8:	902f883a 	mov	r23,r18
-     cac:	003f3806 	br	990 <__alt_data_end+0xfffe0990>
-     cb0:	800b883a 	mov	r5,r16
-     cb4:	a809883a 	mov	r4,r21
-     cb8:	000277c0 	call	277c <_fflush_r>
-     cbc:	103fb926 	beq	r2,zero,ba4 <__alt_data_end+0xfffe0ba4>
-     cc0:	003f6506 	br	a58 <__alt_data_end+0xfffe0a58>
-     cc4:	a809883a 	mov	r4,r21
-     cc8:	0001b600 	call	1b60 <_realloc_r>
-     ccc:	102f883a 	mov	r23,r2
-     cd0:	103fee1e 	bne	r2,zero,c8c <__alt_data_end+0xfffe0c8c>
-     cd4:	81400417 	ldw	r5,16(r16)
-     cd8:	a809883a 	mov	r4,r21
-     cdc:	000292c0 	call	292c <_free_r>
-     ce0:	8080030b 	ldhu	r2,12(r16)
-     ce4:	00ffdfc4 	movi	r3,-129
-     ce8:	1884703a 	and	r2,r3,r2
-     cec:	00c00304 	movi	r3,12
-     cf0:	a8c00015 	stw	r3,0(r21)
-     cf4:	003f5906 	br	a5c <__alt_data_end+0xfffe0a5c>
-     cf8:	94c00044 	addi	r19,r18,1
-     cfc:	02000044 	movi	r8,1
-     d00:	003f6006 	br	a84 <__alt_data_end+0xfffe0a84>
-     d04:	00bfffc4 	movi	r2,-1
-     d08:	003f0006 	br	90c <__alt_data_end+0xfffe090c>
-     d0c:	00800304 	movi	r2,12
-     d10:	a8800015 	stw	r2,0(r21)
-     d14:	8080030b 	ldhu	r2,12(r16)
-     d18:	003f5006 	br	a5c <__alt_data_end+0xfffe0a5c>
+00000ce4 <_fwalk>:
+     ce4:	defffa04 	addi	sp,sp,-24
+     ce8:	dd000415 	stw	r20,16(sp)
+     cec:	dcc00315 	stw	r19,12(sp)
+     cf0:	dc800215 	stw	r18,8(sp)
+     cf4:	dfc00515 	stw	ra,20(sp)
+     cf8:	dc400115 	stw	r17,4(sp)
+     cfc:	dc000015 	stw	r16,0(sp)
+     d00:	2827883a 	mov	r19,r5
+     d04:	2480b804 	addi	r18,r4,736
+     d08:	0029883a 	mov	r20,zero
+     d0c:	94400117 	ldw	r17,4(r18)
+     d10:	94000217 	ldw	r16,8(r18)
+     d14:	8c7fffc4 	addi	r17,r17,-1
+     d18:	88000d16 	blt	r17,zero,d50 <_fwalk+0x6c>
+     d1c:	8080030b 	ldhu	r2,12(r16)
+     d20:	8c7fffc4 	addi	r17,r17,-1
+     d24:	108000b0 	cmpltui	r2,r2,2
+     d28:	1000061e 	bne	r2,zero,d44 <_fwalk+0x60>
+     d2c:	8080038f 	ldh	r2,14(r16)
+     d30:	8009883a 	mov	r4,r16
+     d34:	10bfffe0 	cmpeqi	r2,r2,-1
+     d38:	1000021e 	bne	r2,zero,d44 <_fwalk+0x60>
+     d3c:	983ee83a 	callr	r19
+     d40:	a0a8b03a 	or	r20,r20,r2
+     d44:	88bfffd8 	cmpnei	r2,r17,-1
+     d48:	84001a04 	addi	r16,r16,104
+     d4c:	103ff31e 	bne	r2,zero,d1c <_fwalk+0x38>
+     d50:	94800017 	ldw	r18,0(r18)
+     d54:	903fed1e 	bne	r18,zero,d0c <_fwalk+0x28>
+     d58:	a005883a 	mov	r2,r20
+     d5c:	dfc00517 	ldw	ra,20(sp)
+     d60:	dd000417 	ldw	r20,16(sp)
+     d64:	dcc00317 	ldw	r19,12(sp)
+     d68:	dc800217 	ldw	r18,8(sp)
+     d6c:	dc400117 	ldw	r17,4(sp)
+     d70:	dc000017 	ldw	r16,0(sp)
+     d74:	dec00604 	addi	sp,sp,24
+     d78:	f800283a 	ret
 
-00000d1c <_fwalk>:
-     d1c:	defff704 	addi	sp,sp,-36
-     d20:	dd000415 	stw	r20,16(sp)
-     d24:	dfc00815 	stw	ra,32(sp)
-     d28:	ddc00715 	stw	r23,28(sp)
-     d2c:	dd800615 	stw	r22,24(sp)
-     d30:	dd400515 	stw	r21,20(sp)
-     d34:	dcc00315 	stw	r19,12(sp)
-     d38:	dc800215 	stw	r18,8(sp)
-     d3c:	dc400115 	stw	r17,4(sp)
-     d40:	dc000015 	stw	r16,0(sp)
-     d44:	2500b804 	addi	r20,r4,736
-     d48:	a0002326 	beq	r20,zero,dd8 <_fwalk+0xbc>
-     d4c:	282b883a 	mov	r21,r5
-     d50:	002f883a 	mov	r23,zero
-     d54:	05800044 	movi	r22,1
-     d58:	04ffffc4 	movi	r19,-1
-     d5c:	a4400117 	ldw	r17,4(r20)
-     d60:	a4800217 	ldw	r18,8(r20)
-     d64:	8c7fffc4 	addi	r17,r17,-1
-     d68:	88000d16 	blt	r17,zero,da0 <_fwalk+0x84>
-     d6c:	94000304 	addi	r16,r18,12
-     d70:	94800384 	addi	r18,r18,14
-     d74:	8080000b 	ldhu	r2,0(r16)
-     d78:	8c7fffc4 	addi	r17,r17,-1
-     d7c:	813ffd04 	addi	r4,r16,-12
-     d80:	b080042e 	bgeu	r22,r2,d94 <_fwalk+0x78>
-     d84:	9080000f 	ldh	r2,0(r18)
-     d88:	14c00226 	beq	r2,r19,d94 <_fwalk+0x78>
-     d8c:	a83ee83a 	callr	r21
-     d90:	b8aeb03a 	or	r23,r23,r2
-     d94:	84001a04 	addi	r16,r16,104
-     d98:	94801a04 	addi	r18,r18,104
-     d9c:	8cfff51e 	bne	r17,r19,d74 <__alt_data_end+0xfffe0d74>
-     da0:	a5000017 	ldw	r20,0(r20)
-     da4:	a03fed1e 	bne	r20,zero,d5c <__alt_data_end+0xfffe0d5c>
-     da8:	b805883a 	mov	r2,r23
-     dac:	dfc00817 	ldw	ra,32(sp)
-     db0:	ddc00717 	ldw	r23,28(sp)
-     db4:	dd800617 	ldw	r22,24(sp)
-     db8:	dd400517 	ldw	r21,20(sp)
-     dbc:	dd000417 	ldw	r20,16(sp)
-     dc0:	dcc00317 	ldw	r19,12(sp)
-     dc4:	dc800217 	ldw	r18,8(sp)
-     dc8:	dc400117 	ldw	r17,4(sp)
-     dcc:	dc000017 	ldw	r16,0(sp)
-     dd0:	dec00904 	addi	sp,sp,36
-     dd4:	f800283a 	ret
-     dd8:	002f883a 	mov	r23,zero
-     ddc:	003ff206 	br	da8 <__alt_data_end+0xfffe0da8>
+00000d7c <_fwalk_reent>:
+     d7c:	defff904 	addi	sp,sp,-28
+     d80:	dd400515 	stw	r21,20(sp)
+     d84:	dd000415 	stw	r20,16(sp)
+     d88:	dcc00315 	stw	r19,12(sp)
+     d8c:	dc800215 	stw	r18,8(sp)
+     d90:	dfc00615 	stw	ra,24(sp)
+     d94:	dc400115 	stw	r17,4(sp)
+     d98:	dc000015 	stw	r16,0(sp)
+     d9c:	202b883a 	mov	r21,r4
+     da0:	2827883a 	mov	r19,r5
+     da4:	2480b804 	addi	r18,r4,736
+     da8:	0029883a 	mov	r20,zero
+     dac:	94400117 	ldw	r17,4(r18)
+     db0:	94000217 	ldw	r16,8(r18)
+     db4:	8c7fffc4 	addi	r17,r17,-1
+     db8:	88000e16 	blt	r17,zero,df4 <_fwalk_reent+0x78>
+     dbc:	8080030b 	ldhu	r2,12(r16)
+     dc0:	8c7fffc4 	addi	r17,r17,-1
+     dc4:	108000b0 	cmpltui	r2,r2,2
+     dc8:	1000071e 	bne	r2,zero,de8 <_fwalk_reent+0x6c>
+     dcc:	8080038f 	ldh	r2,14(r16)
+     dd0:	800b883a 	mov	r5,r16
+     dd4:	a809883a 	mov	r4,r21
+     dd8:	10bfffe0 	cmpeqi	r2,r2,-1
+     ddc:	1000021e 	bne	r2,zero,de8 <_fwalk_reent+0x6c>
+     de0:	983ee83a 	callr	r19
+     de4:	a0a8b03a 	or	r20,r20,r2
+     de8:	88bfffd8 	cmpnei	r2,r17,-1
+     dec:	84001a04 	addi	r16,r16,104
+     df0:	103ff21e 	bne	r2,zero,dbc <_fwalk_reent+0x40>
+     df4:	94800017 	ldw	r18,0(r18)
+     df8:	903fec1e 	bne	r18,zero,dac <_fwalk_reent+0x30>
+     dfc:	a005883a 	mov	r2,r20
+     e00:	dfc00617 	ldw	ra,24(sp)
+     e04:	dd400517 	ldw	r21,20(sp)
+     e08:	dd000417 	ldw	r20,16(sp)
+     e0c:	dcc00317 	ldw	r19,12(sp)
+     e10:	dc800217 	ldw	r18,8(sp)
+     e14:	dc400117 	ldw	r17,4(sp)
+     e18:	dc000017 	ldw	r16,0(sp)
+     e1c:	dec00704 	addi	sp,sp,28
+     e20:	f800283a 	ret
 
-00000de0 <_fwalk_reent>:
-     de0:	defff704 	addi	sp,sp,-36
-     de4:	dd000415 	stw	r20,16(sp)
-     de8:	dfc00815 	stw	ra,32(sp)
-     dec:	ddc00715 	stw	r23,28(sp)
-     df0:	dd800615 	stw	r22,24(sp)
-     df4:	dd400515 	stw	r21,20(sp)
-     df8:	dcc00315 	stw	r19,12(sp)
-     dfc:	dc800215 	stw	r18,8(sp)
-     e00:	dc400115 	stw	r17,4(sp)
-     e04:	dc000015 	stw	r16,0(sp)
-     e08:	2500b804 	addi	r20,r4,736
-     e0c:	a0002326 	beq	r20,zero,e9c <_fwalk_reent+0xbc>
-     e10:	282b883a 	mov	r21,r5
-     e14:	2027883a 	mov	r19,r4
-     e18:	002f883a 	mov	r23,zero
-     e1c:	05800044 	movi	r22,1
-     e20:	04bfffc4 	movi	r18,-1
-     e24:	a4400117 	ldw	r17,4(r20)
-     e28:	a4000217 	ldw	r16,8(r20)
-     e2c:	8c7fffc4 	addi	r17,r17,-1
-     e30:	88000c16 	blt	r17,zero,e64 <_fwalk_reent+0x84>
-     e34:	84000304 	addi	r16,r16,12
-     e38:	8080000b 	ldhu	r2,0(r16)
-     e3c:	8c7fffc4 	addi	r17,r17,-1
-     e40:	817ffd04 	addi	r5,r16,-12
-     e44:	b080052e 	bgeu	r22,r2,e5c <_fwalk_reent+0x7c>
-     e48:	8080008f 	ldh	r2,2(r16)
-     e4c:	9809883a 	mov	r4,r19
-     e50:	14800226 	beq	r2,r18,e5c <_fwalk_reent+0x7c>
-     e54:	a83ee83a 	callr	r21
-     e58:	b8aeb03a 	or	r23,r23,r2
-     e5c:	84001a04 	addi	r16,r16,104
-     e60:	8cbff51e 	bne	r17,r18,e38 <__alt_data_end+0xfffe0e38>
-     e64:	a5000017 	ldw	r20,0(r20)
-     e68:	a03fee1e 	bne	r20,zero,e24 <__alt_data_end+0xfffe0e24>
-     e6c:	b805883a 	mov	r2,r23
-     e70:	dfc00817 	ldw	ra,32(sp)
-     e74:	ddc00717 	ldw	r23,28(sp)
-     e78:	dd800617 	ldw	r22,24(sp)
-     e7c:	dd400517 	ldw	r21,20(sp)
-     e80:	dd000417 	ldw	r20,16(sp)
-     e84:	dcc00317 	ldw	r19,12(sp)
-     e88:	dc800217 	ldw	r18,8(sp)
-     e8c:	dc400117 	ldw	r17,4(sp)
-     e90:	dc000017 	ldw	r16,0(sp)
-     e94:	dec00904 	addi	sp,sp,36
-     e98:	f800283a 	ret
-     e9c:	002f883a 	mov	r23,zero
-     ea0:	003ff206 	br	e6c <__alt_data_end+0xfffe0e6c>
-
-00000ea4 <_malloc_r>:
-     ea4:	defff504 	addi	sp,sp,-44
-     ea8:	dc800315 	stw	r18,12(sp)
-     eac:	dfc00a15 	stw	ra,40(sp)
-     eb0:	df000915 	stw	fp,36(sp)
-     eb4:	ddc00815 	stw	r23,32(sp)
-     eb8:	dd800715 	stw	r22,28(sp)
-     ebc:	dd400615 	stw	r21,24(sp)
-     ec0:	dd000515 	stw	r20,20(sp)
-     ec4:	dcc00415 	stw	r19,16(sp)
-     ec8:	dc400215 	stw	r17,8(sp)
-     ecc:	dc000115 	stw	r16,4(sp)
-     ed0:	288002c4 	addi	r2,r5,11
-     ed4:	00c00584 	movi	r3,22
-     ed8:	2025883a 	mov	r18,r4
-     edc:	18807f2e 	bgeu	r3,r2,10dc <_malloc_r+0x238>
-     ee0:	047ffe04 	movi	r17,-8
-     ee4:	1462703a 	and	r17,r2,r17
-     ee8:	8800a316 	blt	r17,zero,1178 <_malloc_r+0x2d4>
-     eec:	8940a236 	bltu	r17,r5,1178 <_malloc_r+0x2d4>
-     ef0:	000361c0 	call	361c <__malloc_lock>
-     ef4:	00807dc4 	movi	r2,503
-     ef8:	1441e92e 	bgeu	r2,r17,16a0 <_malloc_r+0x7fc>
-     efc:	8804d27a 	srli	r2,r17,9
-     f00:	1000a126 	beq	r2,zero,1188 <_malloc_r+0x2e4>
-     f04:	00c00104 	movi	r3,4
-     f08:	18811e36 	bltu	r3,r2,1384 <_malloc_r+0x4e0>
-     f0c:	8804d1ba 	srli	r2,r17,6
-     f10:	12000e44 	addi	r8,r2,57
-     f14:	11c00e04 	addi	r7,r2,56
-     f18:	4209883a 	add	r4,r8,r8
-     f1c:	04c00034 	movhi	r19,0
-     f20:	2109883a 	add	r4,r4,r4
-     f24:	9cd72004 	addi	r19,r19,23680
-     f28:	2109883a 	add	r4,r4,r4
-     f2c:	9909883a 	add	r4,r19,r4
-     f30:	24000117 	ldw	r16,4(r4)
-     f34:	213ffe04 	addi	r4,r4,-8
-     f38:	24009726 	beq	r4,r16,1198 <_malloc_r+0x2f4>
-     f3c:	80800117 	ldw	r2,4(r16)
-     f40:	01bfff04 	movi	r6,-4
-     f44:	014003c4 	movi	r5,15
-     f48:	1184703a 	and	r2,r2,r6
-     f4c:	1447c83a 	sub	r3,r2,r17
-     f50:	28c00716 	blt	r5,r3,f70 <_malloc_r+0xcc>
-     f54:	1800920e 	bge	r3,zero,11a0 <_malloc_r+0x2fc>
-     f58:	84000317 	ldw	r16,12(r16)
-     f5c:	24008e26 	beq	r4,r16,1198 <_malloc_r+0x2f4>
-     f60:	80800117 	ldw	r2,4(r16)
-     f64:	1184703a 	and	r2,r2,r6
+00000e24 <_malloc_r>:
+     e24:	defff604 	addi	sp,sp,-40
+     e28:	dc400115 	stw	r17,4(sp)
+     e2c:	2c4002c4 	addi	r17,r5,11
+     e30:	dc800215 	stw	r18,8(sp)
+     e34:	dfc00915 	stw	ra,36(sp)
+     e38:	df000815 	stw	fp,32(sp)
+     e3c:	ddc00715 	stw	r23,28(sp)
+     e40:	dd800615 	stw	r22,24(sp)
+     e44:	dd400515 	stw	r21,20(sp)
+     e48:	dd000415 	stw	r20,16(sp)
+     e4c:	dcc00315 	stw	r19,12(sp)
+     e50:	dc000015 	stw	r16,0(sp)
+     e54:	888005e8 	cmpgeui	r2,r17,23
+     e58:	2025883a 	mov	r18,r4
+     e5c:	10001b1e 	bne	r2,zero,ecc <_malloc_r+0xa8>
+     e60:	29400468 	cmpgeui	r5,r5,17
+     e64:	2800821e 	bne	r5,zero,1070 <_malloc_r+0x24c>
+     e68:	000365c0 	call	365c <__malloc_lock>
+     e6c:	04400404 	movi	r17,16
+     e70:	00800604 	movi	r2,24
+     e74:	01c00084 	movi	r7,2
+     e78:	04c00034 	movhi	r19,0
+     e7c:	9cd6f404 	addi	r19,r19,23504
+     e80:	9885883a 	add	r2,r19,r2
+     e84:	14000117 	ldw	r16,4(r2)
+     e88:	10fffe04 	addi	r3,r2,-8
+     e8c:	80c08b26 	beq	r16,r3,10bc <_malloc_r+0x298>
+     e90:	80800117 	ldw	r2,4(r16)
+     e94:	81000317 	ldw	r4,12(r16)
+     e98:	00ffff04 	movi	r3,-4
+     e9c:	10c4703a 	and	r2,r2,r3
+     ea0:	81400217 	ldw	r5,8(r16)
+     ea4:	8085883a 	add	r2,r16,r2
+     ea8:	10c00117 	ldw	r3,4(r2)
+     eac:	29000315 	stw	r4,12(r5)
+     eb0:	21400215 	stw	r5,8(r4)
+     eb4:	18c00054 	ori	r3,r3,1
+     eb8:	10c00115 	stw	r3,4(r2)
+     ebc:	9009883a 	mov	r4,r18
+     ec0:	00036800 	call	3680 <__malloc_unlock>
+     ec4:	80800204 	addi	r2,r16,8
+     ec8:	00006c06 	br	107c <_malloc_r+0x258>
+     ecc:	00bffe04 	movi	r2,-8
+     ed0:	88a2703a 	and	r17,r17,r2
+     ed4:	88006616 	blt	r17,zero,1070 <_malloc_r+0x24c>
+     ed8:	89406536 	bltu	r17,r5,1070 <_malloc_r+0x24c>
+     edc:	000365c0 	call	365c <__malloc_lock>
+     ee0:	88807e28 	cmpgeui	r2,r17,504
+     ee4:	10012226 	beq	r2,zero,1370 <_malloc_r+0x54c>
+     ee8:	8804d27a 	srli	r2,r17,9
+     eec:	10006f26 	beq	r2,zero,10ac <_malloc_r+0x288>
+     ef0:	10c00168 	cmpgeui	r3,r2,5
+     ef4:	1800fe1e 	bne	r3,zero,12f0 <_malloc_r+0x4cc>
+     ef8:	8804d1ba 	srli	r2,r17,6
+     efc:	11c00e44 	addi	r7,r2,57
+     f00:	380890fa 	slli	r4,r7,3
+     f04:	12000e04 	addi	r8,r2,56
+     f08:	04c00034 	movhi	r19,0
+     f0c:	9cd6f404 	addi	r19,r19,23504
+     f10:	9909883a 	add	r4,r19,r4
+     f14:	24000117 	ldw	r16,4(r4)
+     f18:	213ffe04 	addi	r4,r4,-8
+     f1c:	24000b26 	beq	r4,r16,f4c <_malloc_r+0x128>
+     f20:	01bfff04 	movi	r6,-4
+     f24:	00000306 	br	f34 <_malloc_r+0x110>
+     f28:	1800d60e 	bge	r3,zero,1284 <_malloc_r+0x460>
+     f2c:	84000317 	ldw	r16,12(r16)
+     f30:	24000626 	beq	r4,r16,f4c <_malloc_r+0x128>
+     f34:	80800117 	ldw	r2,4(r16)
+     f38:	1184703a 	and	r2,r2,r6
+     f3c:	1447c83a 	sub	r3,r2,r17
+     f40:	19400408 	cmpgei	r5,r3,16
+     f44:	283ff826 	beq	r5,zero,f28 <_malloc_r+0x104>
+     f48:	400f883a 	mov	r7,r8
+     f4c:	9c000417 	ldw	r16,16(r19)
+     f50:	02400034 	movhi	r9,0
+     f54:	4a56f604 	addi	r9,r9,23512
+     f58:	82405f26 	beq	r16,r9,10d8 <_malloc_r+0x2b4>
+     f5c:	80c00117 	ldw	r3,4(r16)
+     f60:	00bfff04 	movi	r2,-4
+     f64:	1884703a 	and	r2,r3,r2
      f68:	1447c83a 	sub	r3,r2,r17
-     f6c:	28fff90e 	bge	r5,r3,f54 <__alt_data_end+0xfffe0f54>
-     f70:	3809883a 	mov	r4,r7
-     f74:	01800034 	movhi	r6,0
-     f78:	9c000417 	ldw	r16,16(r19)
-     f7c:	31972004 	addi	r6,r6,23680
-     f80:	32000204 	addi	r8,r6,8
-     f84:	82013426 	beq	r16,r8,1458 <_malloc_r+0x5b4>
-     f88:	80c00117 	ldw	r3,4(r16)
-     f8c:	00bfff04 	movi	r2,-4
-     f90:	188e703a 	and	r7,r3,r2
-     f94:	3c45c83a 	sub	r2,r7,r17
-     f98:	00c003c4 	movi	r3,15
-     f9c:	18811f16 	blt	r3,r2,141c <_malloc_r+0x578>
-     fa0:	32000515 	stw	r8,20(r6)
-     fa4:	32000415 	stw	r8,16(r6)
-     fa8:	10007f0e 	bge	r2,zero,11a8 <_malloc_r+0x304>
-     fac:	00807fc4 	movi	r2,511
-     fb0:	11c0fd36 	bltu	r2,r7,13a8 <_malloc_r+0x504>
-     fb4:	3806d0fa 	srli	r3,r7,3
-     fb8:	01c00044 	movi	r7,1
-     fbc:	30800117 	ldw	r2,4(r6)
-     fc0:	19400044 	addi	r5,r3,1
-     fc4:	294b883a 	add	r5,r5,r5
-     fc8:	1807d0ba 	srai	r3,r3,2
-     fcc:	294b883a 	add	r5,r5,r5
-     fd0:	294b883a 	add	r5,r5,r5
-     fd4:	298b883a 	add	r5,r5,r6
-     fd8:	38c6983a 	sll	r3,r7,r3
-     fdc:	29c00017 	ldw	r7,0(r5)
-     fe0:	2a7ffe04 	addi	r9,r5,-8
-     fe4:	1886b03a 	or	r3,r3,r2
-     fe8:	82400315 	stw	r9,12(r16)
-     fec:	81c00215 	stw	r7,8(r16)
-     ff0:	30c00115 	stw	r3,4(r6)
-     ff4:	2c000015 	stw	r16,0(r5)
-     ff8:	3c000315 	stw	r16,12(r7)
-     ffc:	2005d0ba 	srai	r2,r4,2
-    1000:	01400044 	movi	r5,1
-    1004:	288a983a 	sll	r5,r5,r2
-    1008:	19406f36 	bltu	r3,r5,11c8 <_malloc_r+0x324>
-    100c:	28c4703a 	and	r2,r5,r3
-    1010:	10000a1e 	bne	r2,zero,103c <_malloc_r+0x198>
-    1014:	00bfff04 	movi	r2,-4
-    1018:	294b883a 	add	r5,r5,r5
-    101c:	2088703a 	and	r4,r4,r2
-    1020:	28c4703a 	and	r2,r5,r3
-    1024:	21000104 	addi	r4,r4,4
-    1028:	1000041e 	bne	r2,zero,103c <_malloc_r+0x198>
-    102c:	294b883a 	add	r5,r5,r5
-    1030:	28c4703a 	and	r2,r5,r3
-    1034:	21000104 	addi	r4,r4,4
-    1038:	103ffc26 	beq	r2,zero,102c <__alt_data_end+0xfffe102c>
-    103c:	02bfff04 	movi	r10,-4
-    1040:	024003c4 	movi	r9,15
-    1044:	21800044 	addi	r6,r4,1
-    1048:	318d883a 	add	r6,r6,r6
-    104c:	318d883a 	add	r6,r6,r6
-    1050:	318d883a 	add	r6,r6,r6
-    1054:	998d883a 	add	r6,r19,r6
-    1058:	333ffe04 	addi	r12,r6,-8
-    105c:	2017883a 	mov	r11,r4
-    1060:	31800104 	addi	r6,r6,4
-    1064:	34000017 	ldw	r16,0(r6)
-    1068:	31fffd04 	addi	r7,r6,-12
-    106c:	81c0041e 	bne	r16,r7,1080 <_malloc_r+0x1dc>
-    1070:	0000fb06 	br	1460 <_malloc_r+0x5bc>
-    1074:	1801030e 	bge	r3,zero,1484 <_malloc_r+0x5e0>
-    1078:	84000317 	ldw	r16,12(r16)
-    107c:	81c0f826 	beq	r16,r7,1460 <_malloc_r+0x5bc>
-    1080:	80800117 	ldw	r2,4(r16)
-    1084:	1284703a 	and	r2,r2,r10
-    1088:	1447c83a 	sub	r3,r2,r17
-    108c:	48fff90e 	bge	r9,r3,1074 <__alt_data_end+0xfffe1074>
-    1090:	80800317 	ldw	r2,12(r16)
-    1094:	81000217 	ldw	r4,8(r16)
-    1098:	89400054 	ori	r5,r17,1
-    109c:	81400115 	stw	r5,4(r16)
-    10a0:	20800315 	stw	r2,12(r4)
-    10a4:	11000215 	stw	r4,8(r2)
-    10a8:	8463883a 	add	r17,r16,r17
-    10ac:	9c400515 	stw	r17,20(r19)
-    10b0:	9c400415 	stw	r17,16(r19)
-    10b4:	18800054 	ori	r2,r3,1
-    10b8:	88800115 	stw	r2,4(r17)
-    10bc:	8a000315 	stw	r8,12(r17)
-    10c0:	8a000215 	stw	r8,8(r17)
-    10c4:	88e3883a 	add	r17,r17,r3
-    10c8:	88c00015 	stw	r3,0(r17)
-    10cc:	9009883a 	mov	r4,r18
-    10d0:	00036400 	call	3640 <__malloc_unlock>
-    10d4:	80800204 	addi	r2,r16,8
-    10d8:	00001b06 	br	1148 <_malloc_r+0x2a4>
-    10dc:	04400404 	movi	r17,16
-    10e0:	89402536 	bltu	r17,r5,1178 <_malloc_r+0x2d4>
-    10e4:	000361c0 	call	361c <__malloc_lock>
-    10e8:	00800184 	movi	r2,6
-    10ec:	01000084 	movi	r4,2
-    10f0:	04c00034 	movhi	r19,0
-    10f4:	1085883a 	add	r2,r2,r2
-    10f8:	9cd72004 	addi	r19,r19,23680
-    10fc:	1085883a 	add	r2,r2,r2
-    1100:	9885883a 	add	r2,r19,r2
-    1104:	14000117 	ldw	r16,4(r2)
-    1108:	10fffe04 	addi	r3,r2,-8
-    110c:	80c0d926 	beq	r16,r3,1474 <_malloc_r+0x5d0>
-    1110:	80c00117 	ldw	r3,4(r16)
-    1114:	81000317 	ldw	r4,12(r16)
-    1118:	00bfff04 	movi	r2,-4
-    111c:	1884703a 	and	r2,r3,r2
-    1120:	81400217 	ldw	r5,8(r16)
-    1124:	8085883a 	add	r2,r16,r2
-    1128:	10c00117 	ldw	r3,4(r2)
-    112c:	29000315 	stw	r4,12(r5)
-    1130:	21400215 	stw	r5,8(r4)
-    1134:	18c00054 	ori	r3,r3,1
-    1138:	10c00115 	stw	r3,4(r2)
+     f6c:	19000410 	cmplti	r4,r3,16
+     f70:	20010a26 	beq	r4,zero,139c <_malloc_r+0x578>
+     f74:	9a400515 	stw	r9,20(r19)
+     f78:	9a400415 	stw	r9,16(r19)
+     f7c:	1800ff0e 	bge	r3,zero,137c <_malloc_r+0x558>
+     f80:	10c08028 	cmpgeui	r3,r2,512
+     f84:	1800c11e 	bne	r3,zero,128c <_malloc_r+0x468>
+     f88:	1006d0fa 	srli	r3,r2,3
+     f8c:	1008d17a 	srli	r4,r2,5
+     f90:	00800044 	movi	r2,1
+     f94:	18c00044 	addi	r3,r3,1
+     f98:	180690fa 	slli	r3,r3,3
+     f9c:	99400117 	ldw	r5,4(r19)
+     fa0:	1104983a 	sll	r2,r2,r4
+     fa4:	98c7883a 	add	r3,r19,r3
+     fa8:	19000017 	ldw	r4,0(r3)
+     fac:	1144b03a 	or	r2,r2,r5
+     fb0:	197ffe04 	addi	r5,r3,-8
+     fb4:	81400315 	stw	r5,12(r16)
+     fb8:	81000215 	stw	r4,8(r16)
+     fbc:	98800115 	stw	r2,4(r19)
+     fc0:	1c000015 	stw	r16,0(r3)
+     fc4:	24000315 	stw	r16,12(r4)
+     fc8:	3807d0ba 	srai	r3,r7,2
+     fcc:	01000044 	movi	r4,1
+     fd0:	20c8983a 	sll	r4,r4,r3
+     fd4:	11004536 	bltu	r2,r4,10ec <_malloc_r+0x2c8>
+     fd8:	2086703a 	and	r3,r4,r2
+     fdc:	18000a1e 	bne	r3,zero,1008 <_malloc_r+0x1e4>
+     fe0:	00ffff04 	movi	r3,-4
+     fe4:	2109883a 	add	r4,r4,r4
+     fe8:	38ce703a 	and	r7,r7,r3
+     fec:	2086703a 	and	r3,r4,r2
+     ff0:	39c00104 	addi	r7,r7,4
+     ff4:	1800041e 	bne	r3,zero,1008 <_malloc_r+0x1e4>
+     ff8:	2109883a 	add	r4,r4,r4
+     ffc:	2086703a 	and	r3,r4,r2
+    1000:	39c00104 	addi	r7,r7,4
+    1004:	183ffc26 	beq	r3,zero,ff8 <_malloc_r+0x1d4>
+    1008:	02bfff04 	movi	r10,-4
+    100c:	381690fa 	slli	r11,r7,3
+    1010:	3819883a 	mov	r12,r7
+    1014:	9ad7883a 	add	r11,r19,r11
+    1018:	5811883a 	mov	r8,r11
+    101c:	40800317 	ldw	r2,12(r8)
+    1020:	4080bc26 	beq	r8,r2,1314 <_malloc_r+0x4f0>
+    1024:	10c00117 	ldw	r3,4(r2)
+    1028:	1021883a 	mov	r16,r2
+    102c:	10800317 	ldw	r2,12(r2)
+    1030:	1a86703a 	and	r3,r3,r10
+    1034:	1c4bc83a 	sub	r5,r3,r17
+    1038:	29800410 	cmplti	r6,r5,16
+    103c:	3000ba26 	beq	r6,zero,1328 <_malloc_r+0x504>
+    1040:	283ff716 	blt	r5,zero,1020 <_malloc_r+0x1fc>
+    1044:	80c7883a 	add	r3,r16,r3
+    1048:	19400117 	ldw	r5,4(r3)
+    104c:	81800217 	ldw	r6,8(r16)
+    1050:	9009883a 	mov	r4,r18
+    1054:	29400054 	ori	r5,r5,1
+    1058:	19400115 	stw	r5,4(r3)
+    105c:	30800315 	stw	r2,12(r6)
+    1060:	11800215 	stw	r6,8(r2)
+    1064:	00036800 	call	3680 <__malloc_unlock>
+    1068:	80800204 	addi	r2,r16,8
+    106c:	00000306 	br	107c <_malloc_r+0x258>
+    1070:	00800304 	movi	r2,12
+    1074:	90800015 	stw	r2,0(r18)
+    1078:	0005883a 	mov	r2,zero
+    107c:	dfc00917 	ldw	ra,36(sp)
+    1080:	df000817 	ldw	fp,32(sp)
+    1084:	ddc00717 	ldw	r23,28(sp)
+    1088:	dd800617 	ldw	r22,24(sp)
+    108c:	dd400517 	ldw	r21,20(sp)
+    1090:	dd000417 	ldw	r20,16(sp)
+    1094:	dcc00317 	ldw	r19,12(sp)
+    1098:	dc800217 	ldw	r18,8(sp)
+    109c:	dc400117 	ldw	r17,4(sp)
+    10a0:	dc000017 	ldw	r16,0(sp)
+    10a4:	dec00a04 	addi	sp,sp,40
+    10a8:	f800283a 	ret
+    10ac:	01008004 	movi	r4,512
+    10b0:	01c01004 	movi	r7,64
+    10b4:	02000fc4 	movi	r8,63
+    10b8:	003f9306 	br	f08 <_malloc_r+0xe4>
+    10bc:	14000317 	ldw	r16,12(r2)
+    10c0:	39c00084 	addi	r7,r7,2
+    10c4:	143f721e 	bne	r2,r16,e90 <_malloc_r+0x6c>
+    10c8:	9c000417 	ldw	r16,16(r19)
+    10cc:	02400034 	movhi	r9,0
+    10d0:	4a56f604 	addi	r9,r9,23512
+    10d4:	827fa11e 	bne	r16,r9,f5c <_malloc_r+0x138>
+    10d8:	3807d0ba 	srai	r3,r7,2
+    10dc:	01000044 	movi	r4,1
+    10e0:	98800117 	ldw	r2,4(r19)
+    10e4:	20c8983a 	sll	r4,r4,r3
+    10e8:	113fbb2e 	bgeu	r2,r4,fd8 <_malloc_r+0x1b4>
+    10ec:	9c000217 	ldw	r16,8(r19)
+    10f0:	00bfff04 	movi	r2,-4
+    10f4:	85400117 	ldw	r21,4(r16)
+    10f8:	a8ac703a 	and	r22,r21,r2
+    10fc:	b4400336 	bltu	r22,r17,110c <_malloc_r+0x2e8>
+    1100:	b445c83a 	sub	r2,r22,r17
+    1104:	10c00408 	cmpgei	r3,r2,16
+    1108:	1800541e 	bne	r3,zero,125c <_malloc_r+0x438>
+    110c:	00800034 	movhi	r2,0
+    1110:	109c7a17 	ldw	r2,29160(r2)
+    1114:	00c00034 	movhi	r3,0
+    1118:	1d5c8817 	ldw	r21,29216(r3)
+    111c:	10bfffd8 	cmpnei	r2,r2,-1
+    1120:	85b9883a 	add	fp,r16,r22
+    1124:	8d6b883a 	add	r21,r17,r21
+    1128:	1000d626 	beq	r2,zero,1484 <_malloc_r+0x660>
+    112c:	ad4403c4 	addi	r21,r21,4111
+    1130:	00bc0004 	movi	r2,-4096
+    1134:	a8aa703a 	and	r21,r21,r2
+    1138:	a80b883a 	mov	r5,r21
     113c:	9009883a 	mov	r4,r18
-    1140:	00036400 	call	3640 <__malloc_unlock>
-    1144:	80800204 	addi	r2,r16,8
-    1148:	dfc00a17 	ldw	ra,40(sp)
-    114c:	df000917 	ldw	fp,36(sp)
-    1150:	ddc00817 	ldw	r23,32(sp)
-    1154:	dd800717 	ldw	r22,28(sp)
-    1158:	dd400617 	ldw	r21,24(sp)
-    115c:	dd000517 	ldw	r20,20(sp)
-    1160:	dcc00417 	ldw	r19,16(sp)
-    1164:	dc800317 	ldw	r18,12(sp)
-    1168:	dc400217 	ldw	r17,8(sp)
-    116c:	dc000117 	ldw	r16,4(sp)
-    1170:	dec00b04 	addi	sp,sp,44
-    1174:	f800283a 	ret
-    1178:	00800304 	movi	r2,12
-    117c:	90800015 	stw	r2,0(r18)
-    1180:	0005883a 	mov	r2,zero
-    1184:	003ff006 	br	1148 <__alt_data_end+0xfffe1148>
-    1188:	01002004 	movi	r4,128
-    118c:	02001004 	movi	r8,64
-    1190:	01c00fc4 	movi	r7,63
-    1194:	003f6106 	br	f1c <__alt_data_end+0xfffe0f1c>
-    1198:	4009883a 	mov	r4,r8
-    119c:	003f7506 	br	f74 <__alt_data_end+0xfffe0f74>
-    11a0:	81000317 	ldw	r4,12(r16)
-    11a4:	003fde06 	br	1120 <__alt_data_end+0xfffe1120>
-    11a8:	81c5883a 	add	r2,r16,r7
-    11ac:	11400117 	ldw	r5,4(r2)
-    11b0:	9009883a 	mov	r4,r18
-    11b4:	29400054 	ori	r5,r5,1
-    11b8:	11400115 	stw	r5,4(r2)
-    11bc:	00036400 	call	3640 <__malloc_unlock>
-    11c0:	80800204 	addi	r2,r16,8
-    11c4:	003fe006 	br	1148 <__alt_data_end+0xfffe1148>
-    11c8:	9c000217 	ldw	r16,8(r19)
-    11cc:	00bfff04 	movi	r2,-4
-    11d0:	85800117 	ldw	r22,4(r16)
-    11d4:	b0ac703a 	and	r22,r22,r2
-    11d8:	b4400336 	bltu	r22,r17,11e8 <_malloc_r+0x344>
-    11dc:	b445c83a 	sub	r2,r22,r17
-    11e0:	00c003c4 	movi	r3,15
-    11e4:	18805d16 	blt	r3,r2,135c <_malloc_r+0x4b8>
-    11e8:	05c00034 	movhi	r23,0
-    11ec:	00800034 	movhi	r2,0
-    11f0:	109cb404 	addi	r2,r2,29392
-    11f4:	bddca604 	addi	r23,r23,29336
-    11f8:	15400017 	ldw	r21,0(r2)
-    11fc:	b8c00017 	ldw	r3,0(r23)
-    1200:	00bfffc4 	movi	r2,-1
-    1204:	858d883a 	add	r6,r16,r22
-    1208:	8d6b883a 	add	r21,r17,r21
-    120c:	1880ea26 	beq	r3,r2,15b8 <_malloc_r+0x714>
-    1210:	ad4403c4 	addi	r21,r21,4111
-    1214:	00bc0004 	movi	r2,-4096
-    1218:	a8aa703a 	and	r21,r21,r2
-    121c:	a80b883a 	mov	r5,r21
-    1220:	9009883a 	mov	r4,r18
-    1224:	d9800015 	stw	r6,0(sp)
-    1228:	00020c40 	call	20c4 <_sbrk_r>
-    122c:	1029883a 	mov	r20,r2
-    1230:	00bfffc4 	movi	r2,-1
-    1234:	d9800017 	ldw	r6,0(sp)
-    1238:	a080e826 	beq	r20,r2,15dc <_malloc_r+0x738>
-    123c:	a180a636 	bltu	r20,r6,14d8 <_malloc_r+0x634>
-    1240:	07000034 	movhi	fp,0
-    1244:	e71cbd04 	addi	fp,fp,29428
-    1248:	e0800017 	ldw	r2,0(fp)
-    124c:	a887883a 	add	r3,r21,r2
-    1250:	e0c00015 	stw	r3,0(fp)
-    1254:	3500e626 	beq	r6,r20,15f0 <_malloc_r+0x74c>
-    1258:	b9000017 	ldw	r4,0(r23)
-    125c:	00bfffc4 	movi	r2,-1
-    1260:	2080ee26 	beq	r4,r2,161c <_malloc_r+0x778>
-    1264:	a185c83a 	sub	r2,r20,r6
-    1268:	10c5883a 	add	r2,r2,r3
-    126c:	e0800015 	stw	r2,0(fp)
-    1270:	a0c001cc 	andi	r3,r20,7
-    1274:	1800bc26 	beq	r3,zero,1568 <_malloc_r+0x6c4>
-    1278:	a0e9c83a 	sub	r20,r20,r3
-    127c:	00840204 	movi	r2,4104
-    1280:	a5000204 	addi	r20,r20,8
-    1284:	10c7c83a 	sub	r3,r2,r3
-    1288:	a545883a 	add	r2,r20,r21
-    128c:	1083ffcc 	andi	r2,r2,4095
-    1290:	18abc83a 	sub	r21,r3,r2
-    1294:	a80b883a 	mov	r5,r21
-    1298:	9009883a 	mov	r4,r18
-    129c:	00020c40 	call	20c4 <_sbrk_r>
-    12a0:	00ffffc4 	movi	r3,-1
-    12a4:	10c0e126 	beq	r2,r3,162c <_malloc_r+0x788>
-    12a8:	1505c83a 	sub	r2,r2,r20
-    12ac:	1545883a 	add	r2,r2,r21
-    12b0:	10800054 	ori	r2,r2,1
-    12b4:	e0c00017 	ldw	r3,0(fp)
-    12b8:	9d000215 	stw	r20,8(r19)
-    12bc:	a0800115 	stw	r2,4(r20)
-    12c0:	a8c7883a 	add	r3,r21,r3
-    12c4:	e0c00015 	stw	r3,0(fp)
-    12c8:	84c00e26 	beq	r16,r19,1304 <_malloc_r+0x460>
-    12cc:	018003c4 	movi	r6,15
-    12d0:	3580a72e 	bgeu	r6,r22,1570 <_malloc_r+0x6cc>
-    12d4:	81400117 	ldw	r5,4(r16)
-    12d8:	013ffe04 	movi	r4,-8
-    12dc:	b0bffd04 	addi	r2,r22,-12
-    12e0:	1104703a 	and	r2,r2,r4
-    12e4:	2900004c 	andi	r4,r5,1
-    12e8:	2088b03a 	or	r4,r4,r2
-    12ec:	81000115 	stw	r4,4(r16)
-    12f0:	01400144 	movi	r5,5
-    12f4:	8089883a 	add	r4,r16,r2
-    12f8:	21400115 	stw	r5,4(r4)
-    12fc:	21400215 	stw	r5,8(r4)
-    1300:	3080cd36 	bltu	r6,r2,1638 <_malloc_r+0x794>
-    1304:	00800034 	movhi	r2,0
-    1308:	109cb304 	addi	r2,r2,29388
-    130c:	11000017 	ldw	r4,0(r2)
-    1310:	20c0012e 	bgeu	r4,r3,1318 <_malloc_r+0x474>
-    1314:	10c00015 	stw	r3,0(r2)
-    1318:	00800034 	movhi	r2,0
-    131c:	109cb204 	addi	r2,r2,29384
-    1320:	11000017 	ldw	r4,0(r2)
-    1324:	9c000217 	ldw	r16,8(r19)
-    1328:	20c0012e 	bgeu	r4,r3,1330 <_malloc_r+0x48c>
-    132c:	10c00015 	stw	r3,0(r2)
-    1330:	80c00117 	ldw	r3,4(r16)
-    1334:	00bfff04 	movi	r2,-4
-    1338:	1886703a 	and	r3,r3,r2
-    133c:	1c45c83a 	sub	r2,r3,r17
-    1340:	1c400236 	bltu	r3,r17,134c <_malloc_r+0x4a8>
-    1344:	00c003c4 	movi	r3,15
-    1348:	18800416 	blt	r3,r2,135c <_malloc_r+0x4b8>
-    134c:	9009883a 	mov	r4,r18
-    1350:	00036400 	call	3640 <__malloc_unlock>
-    1354:	0005883a 	mov	r2,zero
-    1358:	003f7b06 	br	1148 <__alt_data_end+0xfffe1148>
-    135c:	88c00054 	ori	r3,r17,1
-    1360:	80c00115 	stw	r3,4(r16)
-    1364:	8463883a 	add	r17,r16,r17
-    1368:	10800054 	ori	r2,r2,1
-    136c:	9c400215 	stw	r17,8(r19)
-    1370:	88800115 	stw	r2,4(r17)
-    1374:	9009883a 	mov	r4,r18
-    1378:	00036400 	call	3640 <__malloc_unlock>
-    137c:	80800204 	addi	r2,r16,8
-    1380:	003f7106 	br	1148 <__alt_data_end+0xfffe1148>
-    1384:	00c00504 	movi	r3,20
-    1388:	18804a2e 	bgeu	r3,r2,14b4 <_malloc_r+0x610>
-    138c:	00c01504 	movi	r3,84
-    1390:	18806e36 	bltu	r3,r2,154c <_malloc_r+0x6a8>
-    1394:	8804d33a 	srli	r2,r17,12
-    1398:	12001bc4 	addi	r8,r2,111
-    139c:	11c01b84 	addi	r7,r2,110
-    13a0:	4209883a 	add	r4,r8,r8
-    13a4:	003edd06 	br	f1c <__alt_data_end+0xfffe0f1c>
-    13a8:	3804d27a 	srli	r2,r7,9
-    13ac:	00c00104 	movi	r3,4
-    13b0:	1880442e 	bgeu	r3,r2,14c4 <_malloc_r+0x620>
-    13b4:	00c00504 	movi	r3,20
-    13b8:	18808136 	bltu	r3,r2,15c0 <_malloc_r+0x71c>
-    13bc:	11401704 	addi	r5,r2,92
-    13c0:	10c016c4 	addi	r3,r2,91
-    13c4:	294b883a 	add	r5,r5,r5
-    13c8:	294b883a 	add	r5,r5,r5
-    13cc:	294b883a 	add	r5,r5,r5
-    13d0:	994b883a 	add	r5,r19,r5
-    13d4:	28800017 	ldw	r2,0(r5)
-    13d8:	01800034 	movhi	r6,0
-    13dc:	297ffe04 	addi	r5,r5,-8
-    13e0:	31972004 	addi	r6,r6,23680
-    13e4:	28806526 	beq	r5,r2,157c <_malloc_r+0x6d8>
-    13e8:	01bfff04 	movi	r6,-4
-    13ec:	10c00117 	ldw	r3,4(r2)
-    13f0:	1986703a 	and	r3,r3,r6
-    13f4:	38c0022e 	bgeu	r7,r3,1400 <_malloc_r+0x55c>
-    13f8:	10800217 	ldw	r2,8(r2)
-    13fc:	28bffb1e 	bne	r5,r2,13ec <__alt_data_end+0xfffe13ec>
-    1400:	11400317 	ldw	r5,12(r2)
-    1404:	98c00117 	ldw	r3,4(r19)
-    1408:	81400315 	stw	r5,12(r16)
-    140c:	80800215 	stw	r2,8(r16)
-    1410:	2c000215 	stw	r16,8(r5)
-    1414:	14000315 	stw	r16,12(r2)
-    1418:	003ef806 	br	ffc <__alt_data_end+0xfffe0ffc>
-    141c:	88c00054 	ori	r3,r17,1
-    1420:	80c00115 	stw	r3,4(r16)
-    1424:	8463883a 	add	r17,r16,r17
-    1428:	34400515 	stw	r17,20(r6)
-    142c:	34400415 	stw	r17,16(r6)
-    1430:	10c00054 	ori	r3,r2,1
-    1434:	8a000315 	stw	r8,12(r17)
-    1438:	8a000215 	stw	r8,8(r17)
-    143c:	88c00115 	stw	r3,4(r17)
-    1440:	88a3883a 	add	r17,r17,r2
-    1444:	88800015 	stw	r2,0(r17)
-    1448:	9009883a 	mov	r4,r18
-    144c:	00036400 	call	3640 <__malloc_unlock>
-    1450:	80800204 	addi	r2,r16,8
-    1454:	003f3c06 	br	1148 <__alt_data_end+0xfffe1148>
-    1458:	30c00117 	ldw	r3,4(r6)
-    145c:	003ee706 	br	ffc <__alt_data_end+0xfffe0ffc>
-    1460:	5ac00044 	addi	r11,r11,1
-    1464:	588000cc 	andi	r2,r11,3
-    1468:	31800204 	addi	r6,r6,8
-    146c:	103efd1e 	bne	r2,zero,1064 <__alt_data_end+0xfffe1064>
-    1470:	00002406 	br	1504 <_malloc_r+0x660>
-    1474:	14000317 	ldw	r16,12(r2)
-    1478:	143f251e 	bne	r2,r16,1110 <__alt_data_end+0xfffe1110>
-    147c:	21000084 	addi	r4,r4,2
-    1480:	003ebc06 	br	f74 <__alt_data_end+0xfffe0f74>
-    1484:	8085883a 	add	r2,r16,r2
-    1488:	10c00117 	ldw	r3,4(r2)
-    148c:	81000317 	ldw	r4,12(r16)
-    1490:	81400217 	ldw	r5,8(r16)
-    1494:	18c00054 	ori	r3,r3,1
-    1498:	10c00115 	stw	r3,4(r2)
-    149c:	29000315 	stw	r4,12(r5)
-    14a0:	21400215 	stw	r5,8(r4)
-    14a4:	9009883a 	mov	r4,r18
-    14a8:	00036400 	call	3640 <__malloc_unlock>
-    14ac:	80800204 	addi	r2,r16,8
-    14b0:	003f2506 	br	1148 <__alt_data_end+0xfffe1148>
-    14b4:	12001704 	addi	r8,r2,92
-    14b8:	11c016c4 	addi	r7,r2,91
-    14bc:	4209883a 	add	r4,r8,r8
-    14c0:	003e9606 	br	f1c <__alt_data_end+0xfffe0f1c>
-    14c4:	3804d1ba 	srli	r2,r7,6
-    14c8:	11400e44 	addi	r5,r2,57
-    14cc:	10c00e04 	addi	r3,r2,56
-    14d0:	294b883a 	add	r5,r5,r5
-    14d4:	003fbc06 	br	13c8 <__alt_data_end+0xfffe13c8>
-    14d8:	84ff5926 	beq	r16,r19,1240 <__alt_data_end+0xfffe1240>
-    14dc:	00800034 	movhi	r2,0
-    14e0:	10972004 	addi	r2,r2,23680
-    14e4:	14000217 	ldw	r16,8(r2)
-    14e8:	00bfff04 	movi	r2,-4
-    14ec:	80c00117 	ldw	r3,4(r16)
-    14f0:	1886703a 	and	r3,r3,r2
-    14f4:	003f9106 	br	133c <__alt_data_end+0xfffe133c>
-    14f8:	60800217 	ldw	r2,8(r12)
-    14fc:	213fffc4 	addi	r4,r4,-1
-    1500:	1300651e 	bne	r2,r12,1698 <_malloc_r+0x7f4>
-    1504:	208000cc 	andi	r2,r4,3
-    1508:	633ffe04 	addi	r12,r12,-8
-    150c:	103ffa1e 	bne	r2,zero,14f8 <__alt_data_end+0xfffe14f8>
-    1510:	98800117 	ldw	r2,4(r19)
-    1514:	0146303a 	nor	r3,zero,r5
-    1518:	1884703a 	and	r2,r3,r2
-    151c:	98800115 	stw	r2,4(r19)
-    1520:	294b883a 	add	r5,r5,r5
-    1524:	117f2836 	bltu	r2,r5,11c8 <__alt_data_end+0xfffe11c8>
-    1528:	283f2726 	beq	r5,zero,11c8 <__alt_data_end+0xfffe11c8>
-    152c:	2886703a 	and	r3,r5,r2
-    1530:	5809883a 	mov	r4,r11
-    1534:	183ec31e 	bne	r3,zero,1044 <__alt_data_end+0xfffe1044>
-    1538:	294b883a 	add	r5,r5,r5
-    153c:	2886703a 	and	r3,r5,r2
-    1540:	21000104 	addi	r4,r4,4
-    1544:	183ffc26 	beq	r3,zero,1538 <__alt_data_end+0xfffe1538>
-    1548:	003ebe06 	br	1044 <__alt_data_end+0xfffe1044>
-    154c:	00c05504 	movi	r3,340
-    1550:	18801236 	bltu	r3,r2,159c <_malloc_r+0x6f8>
-    1554:	8804d3fa 	srli	r2,r17,15
-    1558:	12001e04 	addi	r8,r2,120
-    155c:	11c01dc4 	addi	r7,r2,119
-    1560:	4209883a 	add	r4,r8,r8
-    1564:	003e6d06 	br	f1c <__alt_data_end+0xfffe0f1c>
-    1568:	00c40004 	movi	r3,4096
-    156c:	003f4606 	br	1288 <__alt_data_end+0xfffe1288>
-    1570:	00800044 	movi	r2,1
-    1574:	a0800115 	stw	r2,4(r20)
-    1578:	003f7406 	br	134c <__alt_data_end+0xfffe134c>
-    157c:	1805d0ba 	srai	r2,r3,2
-    1580:	01c00044 	movi	r7,1
-    1584:	30c00117 	ldw	r3,4(r6)
-    1588:	388e983a 	sll	r7,r7,r2
-    158c:	2805883a 	mov	r2,r5
-    1590:	38c6b03a 	or	r3,r7,r3
-    1594:	30c00115 	stw	r3,4(r6)
-    1598:	003f9b06 	br	1408 <__alt_data_end+0xfffe1408>
-    159c:	00c15504 	movi	r3,1364
-    15a0:	18801a36 	bltu	r3,r2,160c <_malloc_r+0x768>
-    15a4:	8804d4ba 	srli	r2,r17,18
-    15a8:	12001f44 	addi	r8,r2,125
-    15ac:	11c01f04 	addi	r7,r2,124
-    15b0:	4209883a 	add	r4,r8,r8
-    15b4:	003e5906 	br	f1c <__alt_data_end+0xfffe0f1c>
-    15b8:	ad400404 	addi	r21,r21,16
-    15bc:	003f1706 	br	121c <__alt_data_end+0xfffe121c>
-    15c0:	00c01504 	movi	r3,84
-    15c4:	18802336 	bltu	r3,r2,1654 <_malloc_r+0x7b0>
-    15c8:	3804d33a 	srli	r2,r7,12
-    15cc:	11401bc4 	addi	r5,r2,111
-    15d0:	10c01b84 	addi	r3,r2,110
-    15d4:	294b883a 	add	r5,r5,r5
-    15d8:	003f7b06 	br	13c8 <__alt_data_end+0xfffe13c8>
-    15dc:	9c000217 	ldw	r16,8(r19)
-    15e0:	00bfff04 	movi	r2,-4
-    15e4:	80c00117 	ldw	r3,4(r16)
-    15e8:	1886703a 	and	r3,r3,r2
-    15ec:	003f5306 	br	133c <__alt_data_end+0xfffe133c>
-    15f0:	3083ffcc 	andi	r2,r6,4095
-    15f4:	103f181e 	bne	r2,zero,1258 <__alt_data_end+0xfffe1258>
-    15f8:	99000217 	ldw	r4,8(r19)
-    15fc:	b545883a 	add	r2,r22,r21
-    1600:	10800054 	ori	r2,r2,1
-    1604:	20800115 	stw	r2,4(r4)
-    1608:	003f3e06 	br	1304 <__alt_data_end+0xfffe1304>
-    160c:	01003f84 	movi	r4,254
-    1610:	02001fc4 	movi	r8,127
-    1614:	01c01f84 	movi	r7,126
-    1618:	003e4006 	br	f1c <__alt_data_end+0xfffe0f1c>
-    161c:	00800034 	movhi	r2,0
-    1620:	109ca604 	addi	r2,r2,29336
-    1624:	15000015 	stw	r20,0(r2)
-    1628:	003f1106 	br	1270 <__alt_data_end+0xfffe1270>
-    162c:	00800044 	movi	r2,1
-    1630:	002b883a 	mov	r21,zero
-    1634:	003f1f06 	br	12b4 <__alt_data_end+0xfffe12b4>
-    1638:	81400204 	addi	r5,r16,8
-    163c:	9009883a 	mov	r4,r18
-    1640:	000292c0 	call	292c <_free_r>
-    1644:	00800034 	movhi	r2,0
-    1648:	109cbd04 	addi	r2,r2,29428
-    164c:	10c00017 	ldw	r3,0(r2)
-    1650:	003f2c06 	br	1304 <__alt_data_end+0xfffe1304>
-    1654:	00c05504 	movi	r3,340
-    1658:	18800536 	bltu	r3,r2,1670 <_malloc_r+0x7cc>
-    165c:	3804d3fa 	srli	r2,r7,15
-    1660:	11401e04 	addi	r5,r2,120
-    1664:	10c01dc4 	addi	r3,r2,119
-    1668:	294b883a 	add	r5,r5,r5
-    166c:	003f5606 	br	13c8 <__alt_data_end+0xfffe13c8>
-    1670:	00c15504 	movi	r3,1364
-    1674:	18800536 	bltu	r3,r2,168c <_malloc_r+0x7e8>
-    1678:	3804d4ba 	srli	r2,r7,18
-    167c:	11401f44 	addi	r5,r2,125
-    1680:	10c01f04 	addi	r3,r2,124
-    1684:	294b883a 	add	r5,r5,r5
-    1688:	003f4f06 	br	13c8 <__alt_data_end+0xfffe13c8>
-    168c:	01403f84 	movi	r5,254
-    1690:	00c01f84 	movi	r3,126
-    1694:	003f4c06 	br	13c8 <__alt_data_end+0xfffe13c8>
-    1698:	98800117 	ldw	r2,4(r19)
-    169c:	003fa006 	br	1520 <__alt_data_end+0xfffe1520>
-    16a0:	8808d0fa 	srli	r4,r17,3
-    16a4:	20800044 	addi	r2,r4,1
-    16a8:	1085883a 	add	r2,r2,r2
-    16ac:	003e9006 	br	10f0 <__alt_data_end+0xfffe10f0>
+    1140:	0001f540 	call	1f54 <_sbrk_r>
+    1144:	102f883a 	mov	r23,r2
+    1148:	10bfffd8 	cmpnei	r2,r2,-1
+    114c:	1000a826 	beq	r2,zero,13f0 <_malloc_r+0x5cc>
+    1150:	bf00a636 	bltu	r23,fp,13ec <_malloc_r+0x5c8>
+    1154:	00800034 	movhi	r2,0
+    1158:	151c9117 	ldw	r20,29252(r2)
+    115c:	ad29883a 	add	r20,r21,r20
+    1160:	151c9115 	stw	r20,29252(r2)
+    1164:	a007883a 	mov	r3,r20
+    1168:	e5c0ec26 	beq	fp,r23,151c <_malloc_r+0x6f8>
+    116c:	00800034 	movhi	r2,0
+    1170:	109c7a17 	ldw	r2,29160(r2)
+    1174:	10bfffd8 	cmpnei	r2,r2,-1
+    1178:	1000ef26 	beq	r2,zero,1538 <_malloc_r+0x714>
+    117c:	bf39c83a 	sub	fp,r23,fp
+    1180:	e0c7883a 	add	r3,fp,r3
+    1184:	00800034 	movhi	r2,0
+    1188:	10dc9115 	stw	r3,29252(r2)
+    118c:	bf0001cc 	andi	fp,r23,7
+    1190:	e000c526 	beq	fp,zero,14a8 <_malloc_r+0x684>
+    1194:	bf2fc83a 	sub	r23,r23,fp
+    1198:	bdc00204 	addi	r23,r23,8
+    119c:	05040204 	movi	r20,4104
+    11a0:	a729c83a 	sub	r20,r20,fp
+    11a4:	bd6b883a 	add	r21,r23,r21
+    11a8:	a569c83a 	sub	r20,r20,r21
+    11ac:	a503ffcc 	andi	r20,r20,4095
+    11b0:	a00b883a 	mov	r5,r20
+    11b4:	9009883a 	mov	r4,r18
+    11b8:	0001f540 	call	1f54 <_sbrk_r>
+    11bc:	10ffffe0 	cmpeqi	r3,r2,-1
+    11c0:	1800f31e 	bne	r3,zero,1590 <_malloc_r+0x76c>
+    11c4:	15c5c83a 	sub	r2,r2,r23
+    11c8:	152b883a 	add	r21,r2,r20
+    11cc:	00800034 	movhi	r2,0
+    11d0:	115c9117 	ldw	r5,29252(r2)
+    11d4:	9dc00215 	stw	r23,8(r19)
+    11d8:	ad400054 	ori	r21,r21,1
+    11dc:	a169883a 	add	r20,r20,r5
+    11e0:	151c9115 	stw	r20,29252(r2)
+    11e4:	bd400115 	stw	r21,4(r23)
+    11e8:	84c0d626 	beq	r16,r19,1544 <_malloc_r+0x720>
+    11ec:	b0800428 	cmpgeui	r2,r22,16
+    11f0:	1000d626 	beq	r2,zero,154c <_malloc_r+0x728>
+    11f4:	80c00117 	ldw	r3,4(r16)
+    11f8:	013ffe04 	movi	r4,-8
+    11fc:	b0bffd04 	addi	r2,r22,-12
+    1200:	1104703a 	and	r2,r2,r4
+    1204:	18c0004c 	andi	r3,r3,1
+    1208:	1886b03a 	or	r3,r3,r2
+    120c:	80c00115 	stw	r3,4(r16)
+    1210:	01000144 	movi	r4,5
+    1214:	8087883a 	add	r3,r16,r2
+    1218:	19000115 	stw	r4,4(r3)
+    121c:	19000215 	stw	r4,8(r3)
+    1220:	10800428 	cmpgeui	r2,r2,16
+    1224:	1000df1e 	bne	r2,zero,15a4 <_malloc_r+0x780>
+    1228:	bd400117 	ldw	r21,4(r23)
+    122c:	b821883a 	mov	r16,r23
+    1230:	00800034 	movhi	r2,0
+    1234:	109c8717 	ldw	r2,29212(r2)
+    1238:	1500022e 	bgeu	r2,r20,1244 <_malloc_r+0x420>
+    123c:	00800034 	movhi	r2,0
+    1240:	151c8715 	stw	r20,29212(r2)
+    1244:	00800034 	movhi	r2,0
+    1248:	109c8617 	ldw	r2,29208(r2)
+    124c:	15006a2e 	bgeu	r2,r20,13f8 <_malloc_r+0x5d4>
+    1250:	00800034 	movhi	r2,0
+    1254:	151c8615 	stw	r20,29208(r2)
+    1258:	00006706 	br	13f8 <_malloc_r+0x5d4>
+    125c:	88c00054 	ori	r3,r17,1
+    1260:	80c00115 	stw	r3,4(r16)
+    1264:	8463883a 	add	r17,r16,r17
+    1268:	10800054 	ori	r2,r2,1
+    126c:	9c400215 	stw	r17,8(r19)
+    1270:	88800115 	stw	r2,4(r17)
+    1274:	9009883a 	mov	r4,r18
+    1278:	00036800 	call	3680 <__malloc_unlock>
+    127c:	80800204 	addi	r2,r16,8
+    1280:	003f7e06 	br	107c <_malloc_r+0x258>
+    1284:	81000317 	ldw	r4,12(r16)
+    1288:	003f0506 	br	ea0 <_malloc_r+0x7c>
+    128c:	1006d27a 	srli	r3,r2,9
+    1290:	19000168 	cmpgeui	r4,r3,5
+    1294:	20005026 	beq	r4,zero,13d8 <_malloc_r+0x5b4>
+    1298:	19000568 	cmpgeui	r4,r3,21
+    129c:	20008c1e 	bne	r4,zero,14d0 <_malloc_r+0x6ac>
+    12a0:	19401704 	addi	r5,r3,92
+    12a4:	280a90fa 	slli	r5,r5,3
+    12a8:	190016c4 	addi	r4,r3,91
+    12ac:	994b883a 	add	r5,r19,r5
+    12b0:	28c00017 	ldw	r3,0(r5)
+    12b4:	297ffe04 	addi	r5,r5,-8
+    12b8:	28c07426 	beq	r5,r3,148c <_malloc_r+0x668>
+    12bc:	01bfff04 	movi	r6,-4
+    12c0:	19000117 	ldw	r4,4(r3)
+    12c4:	2188703a 	and	r4,r4,r6
+    12c8:	1100022e 	bgeu	r2,r4,12d4 <_malloc_r+0x4b0>
+    12cc:	18c00217 	ldw	r3,8(r3)
+    12d0:	28fffb1e 	bne	r5,r3,12c0 <_malloc_r+0x49c>
+    12d4:	19400317 	ldw	r5,12(r3)
+    12d8:	98800117 	ldw	r2,4(r19)
+    12dc:	81400315 	stw	r5,12(r16)
+    12e0:	80c00215 	stw	r3,8(r16)
+    12e4:	2c000215 	stw	r16,8(r5)
+    12e8:	1c000315 	stw	r16,12(r3)
+    12ec:	003f3606 	br	fc8 <_malloc_r+0x1a4>
+    12f0:	10c00568 	cmpgeui	r3,r2,21
+    12f4:	18004a26 	beq	r3,zero,1420 <_malloc_r+0x5fc>
+    12f8:	10c01568 	cmpgeui	r3,r2,85
+    12fc:	18007b1e 	bne	r3,zero,14ec <_malloc_r+0x6c8>
+    1300:	8804d33a 	srli	r2,r17,12
+    1304:	11c01bc4 	addi	r7,r2,111
+    1308:	380890fa 	slli	r4,r7,3
+    130c:	12001b84 	addi	r8,r2,110
+    1310:	003efd06 	br	f08 <_malloc_r+0xe4>
+    1314:	63000044 	addi	r12,r12,1
+    1318:	608000cc 	andi	r2,r12,3
+    131c:	42000204 	addi	r8,r8,8
+    1320:	103f3e1e 	bne	r2,zero,101c <_malloc_r+0x1f8>
+    1324:	00004506 	br	143c <_malloc_r+0x618>
+    1328:	81000217 	ldw	r4,8(r16)
+    132c:	89800054 	ori	r6,r17,1
+    1330:	81800115 	stw	r6,4(r16)
+    1334:	20800315 	stw	r2,12(r4)
+    1338:	11000215 	stw	r4,8(r2)
+    133c:	8463883a 	add	r17,r16,r17
+    1340:	9c400515 	stw	r17,20(r19)
+    1344:	9c400415 	stw	r17,16(r19)
+    1348:	28800054 	ori	r2,r5,1
+    134c:	88800115 	stw	r2,4(r17)
+    1350:	8a400315 	stw	r9,12(r17)
+    1354:	8a400215 	stw	r9,8(r17)
+    1358:	80c7883a 	add	r3,r16,r3
+    135c:	19400015 	stw	r5,0(r3)
+    1360:	9009883a 	mov	r4,r18
+    1364:	00036800 	call	3680 <__malloc_unlock>
+    1368:	80800204 	addi	r2,r16,8
+    136c:	003f4306 	br	107c <_malloc_r+0x258>
+    1370:	880ed0fa 	srli	r7,r17,3
+    1374:	88800204 	addi	r2,r17,8
+    1378:	003ebf06 	br	e78 <_malloc_r+0x54>
+    137c:	8085883a 	add	r2,r16,r2
+    1380:	10c00117 	ldw	r3,4(r2)
+    1384:	9009883a 	mov	r4,r18
+    1388:	18c00054 	ori	r3,r3,1
+    138c:	10c00115 	stw	r3,4(r2)
+    1390:	00036800 	call	3680 <__malloc_unlock>
+    1394:	80800204 	addi	r2,r16,8
+    1398:	003f3806 	br	107c <_malloc_r+0x258>
+    139c:	89000054 	ori	r4,r17,1
+    13a0:	81000115 	stw	r4,4(r16)
+    13a4:	8463883a 	add	r17,r16,r17
+    13a8:	9c400515 	stw	r17,20(r19)
+    13ac:	9c400415 	stw	r17,16(r19)
+    13b0:	19000054 	ori	r4,r3,1
+    13b4:	89000115 	stw	r4,4(r17)
+    13b8:	8085883a 	add	r2,r16,r2
+    13bc:	8a400315 	stw	r9,12(r17)
+    13c0:	8a400215 	stw	r9,8(r17)
+    13c4:	10c00015 	stw	r3,0(r2)
+    13c8:	9009883a 	mov	r4,r18
+    13cc:	00036800 	call	3680 <__malloc_unlock>
+    13d0:	80800204 	addi	r2,r16,8
+    13d4:	003f2906 	br	107c <_malloc_r+0x258>
+    13d8:	1006d1ba 	srli	r3,r2,6
+    13dc:	19400e44 	addi	r5,r3,57
+    13e0:	280a90fa 	slli	r5,r5,3
+    13e4:	19000e04 	addi	r4,r3,56
+    13e8:	003fb006 	br	12ac <_malloc_r+0x488>
+    13ec:	84c04626 	beq	r16,r19,1508 <_malloc_r+0x6e4>
+    13f0:	9c000217 	ldw	r16,8(r19)
+    13f4:	85400117 	ldw	r21,4(r16)
+    13f8:	00bfff04 	movi	r2,-4
+    13fc:	a8aa703a 	and	r21,r21,r2
+    1400:	ac45c83a 	sub	r2,r21,r17
+    1404:	ac400236 	bltu	r21,r17,1410 <_malloc_r+0x5ec>
+    1408:	10c00408 	cmpgei	r3,r2,16
+    140c:	183f931e 	bne	r3,zero,125c <_malloc_r+0x438>
+    1410:	9009883a 	mov	r4,r18
+    1414:	00036800 	call	3680 <__malloc_unlock>
+    1418:	0005883a 	mov	r2,zero
+    141c:	003f1706 	br	107c <_malloc_r+0x258>
+    1420:	11c01704 	addi	r7,r2,92
+    1424:	380890fa 	slli	r4,r7,3
+    1428:	120016c4 	addi	r8,r2,91
+    142c:	003eb606 	br	f08 <_malloc_r+0xe4>
+    1430:	58800217 	ldw	r2,8(r11)
+    1434:	39ffffc4 	addi	r7,r7,-1
+    1438:	12c0701e 	bne	r2,r11,15fc <_malloc_r+0x7d8>
+    143c:	388000cc 	andi	r2,r7,3
+    1440:	5afffe04 	addi	r11,r11,-8
+    1444:	103ffa1e 	bne	r2,zero,1430 <_malloc_r+0x60c>
+    1448:	98c00117 	ldw	r3,4(r19)
+    144c:	0104303a 	nor	r2,zero,r4
+    1450:	10c4703a 	and	r2,r2,r3
+    1454:	98800115 	stw	r2,4(r19)
+    1458:	2109883a 	add	r4,r4,r4
+    145c:	113f2336 	bltu	r2,r4,10ec <_malloc_r+0x2c8>
+    1460:	203f2226 	beq	r4,zero,10ec <_malloc_r+0x2c8>
+    1464:	2086703a 	and	r3,r4,r2
+    1468:	1800041e 	bne	r3,zero,147c <_malloc_r+0x658>
+    146c:	2109883a 	add	r4,r4,r4
+    1470:	2086703a 	and	r3,r4,r2
+    1474:	63000104 	addi	r12,r12,4
+    1478:	183ffc26 	beq	r3,zero,146c <_malloc_r+0x648>
+    147c:	600f883a 	mov	r7,r12
+    1480:	003ee206 	br	100c <_malloc_r+0x1e8>
+    1484:	ad400404 	addi	r21,r21,16
+    1488:	003f2b06 	br	1138 <_malloc_r+0x314>
+    148c:	2009d0ba 	srai	r4,r4,2
+    1490:	00800044 	movi	r2,1
+    1494:	99800117 	ldw	r6,4(r19)
+    1498:	1104983a 	sll	r2,r2,r4
+    149c:	1184b03a 	or	r2,r2,r6
+    14a0:	98800115 	stw	r2,4(r19)
+    14a4:	003f8d06 	br	12dc <_malloc_r+0x4b8>
+    14a8:	bd69883a 	add	r20,r23,r21
+    14ac:	0529c83a 	sub	r20,zero,r20
+    14b0:	a503ffcc 	andi	r20,r20,4095
+    14b4:	a00b883a 	mov	r5,r20
+    14b8:	9009883a 	mov	r4,r18
+    14bc:	0001f540 	call	1f54 <_sbrk_r>
+    14c0:	10ffffe0 	cmpeqi	r3,r2,-1
+    14c4:	183f3f26 	beq	r3,zero,11c4 <_malloc_r+0x3a0>
+    14c8:	0029883a 	mov	r20,zero
+    14cc:	003f3f06 	br	11cc <_malloc_r+0x3a8>
+    14d0:	19001568 	cmpgeui	r4,r3,85
+    14d4:	2000201e 	bne	r4,zero,1558 <_malloc_r+0x734>
+    14d8:	1006d33a 	srli	r3,r2,12
+    14dc:	19401bc4 	addi	r5,r3,111
+    14e0:	280a90fa 	slli	r5,r5,3
+    14e4:	19001b84 	addi	r4,r3,110
+    14e8:	003f7006 	br	12ac <_malloc_r+0x488>
+    14ec:	10c05568 	cmpgeui	r3,r2,341
+    14f0:	1800201e 	bne	r3,zero,1574 <_malloc_r+0x750>
+    14f4:	8804d3fa 	srli	r2,r17,15
+    14f8:	11c01e04 	addi	r7,r2,120
+    14fc:	380890fa 	slli	r4,r7,3
+    1500:	12001dc4 	addi	r8,r2,119
+    1504:	003e8006 	br	f08 <_malloc_r+0xe4>
+    1508:	00800034 	movhi	r2,0
+    150c:	10dc9117 	ldw	r3,29252(r2)
+    1510:	a8c7883a 	add	r3,r21,r3
+    1514:	10dc9115 	stw	r3,29252(r2)
+    1518:	003f1406 	br	116c <_malloc_r+0x348>
+    151c:	e083ffcc 	andi	r2,fp,4095
+    1520:	103f121e 	bne	r2,zero,116c <_malloc_r+0x348>
+    1524:	9c000217 	ldw	r16,8(r19)
+    1528:	b56b883a 	add	r21,r22,r21
+    152c:	ad400054 	ori	r21,r21,1
+    1530:	85400115 	stw	r21,4(r16)
+    1534:	003f3e06 	br	1230 <_malloc_r+0x40c>
+    1538:	00800034 	movhi	r2,0
+    153c:	15dc7a15 	stw	r23,29160(r2)
+    1540:	003f1206 	br	118c <_malloc_r+0x368>
+    1544:	b821883a 	mov	r16,r23
+    1548:	003f3906 	br	1230 <_malloc_r+0x40c>
+    154c:	00800044 	movi	r2,1
+    1550:	b8800115 	stw	r2,4(r23)
+    1554:	003fae06 	br	1410 <_malloc_r+0x5ec>
+    1558:	19005568 	cmpgeui	r4,r3,341
+    155c:	2000191e 	bne	r4,zero,15c4 <_malloc_r+0x7a0>
+    1560:	1006d3fa 	srli	r3,r2,15
+    1564:	19401e04 	addi	r5,r3,120
+    1568:	280a90fa 	slli	r5,r5,3
+    156c:	19001dc4 	addi	r4,r3,119
+    1570:	003f4e06 	br	12ac <_malloc_r+0x488>
+    1574:	10815568 	cmpgeui	r2,r2,1365
+    1578:	1000191e 	bne	r2,zero,15e0 <_malloc_r+0x7bc>
+    157c:	8804d4ba 	srli	r2,r17,18
+    1580:	11c01f44 	addi	r7,r2,125
+    1584:	380890fa 	slli	r4,r7,3
+    1588:	12001f04 	addi	r8,r2,124
+    158c:	003e5e06 	br	f08 <_malloc_r+0xe4>
+    1590:	e73ffe04 	addi	fp,fp,-8
+    1594:	af2b883a 	add	r21,r21,fp
+    1598:	adebc83a 	sub	r21,r21,r23
+    159c:	0029883a 	mov	r20,zero
+    15a0:	003f0a06 	br	11cc <_malloc_r+0x3a8>
+    15a4:	81400204 	addi	r5,r16,8
+    15a8:	9009883a 	mov	r4,r18
+    15ac:	00028d40 	call	28d4 <_free_r>
+    15b0:	9c000217 	ldw	r16,8(r19)
+    15b4:	00800034 	movhi	r2,0
+    15b8:	151c9117 	ldw	r20,29252(r2)
+    15bc:	85400117 	ldw	r21,4(r16)
+    15c0:	003f1b06 	br	1230 <_malloc_r+0x40c>
+    15c4:	18c15568 	cmpgeui	r3,r3,1365
+    15c8:	1800091e 	bne	r3,zero,15f0 <_malloc_r+0x7cc>
+    15cc:	1006d4ba 	srli	r3,r2,18
+    15d0:	19401f44 	addi	r5,r3,125
+    15d4:	280a90fa 	slli	r5,r5,3
+    15d8:	19001f04 	addi	r4,r3,124
+    15dc:	003f3306 	br	12ac <_malloc_r+0x488>
+    15e0:	0100fe04 	movi	r4,1016
+    15e4:	01c01fc4 	movi	r7,127
+    15e8:	02001f84 	movi	r8,126
+    15ec:	003e4606 	br	f08 <_malloc_r+0xe4>
+    15f0:	0140fe04 	movi	r5,1016
+    15f4:	01001f84 	movi	r4,126
+    15f8:	003f2c06 	br	12ac <_malloc_r+0x488>
+    15fc:	98800117 	ldw	r2,4(r19)
+    1600:	003f9506 	br	1458 <_malloc_r+0x634>
 
-000016b0 <memchr>:
-    16b0:	208000cc 	andi	r2,r4,3
-    16b4:	280f883a 	mov	r7,r5
-    16b8:	10003426 	beq	r2,zero,178c <memchr+0xdc>
-    16bc:	30bfffc4 	addi	r2,r6,-1
-    16c0:	30001a26 	beq	r6,zero,172c <memchr+0x7c>
-    16c4:	20c00003 	ldbu	r3,0(r4)
-    16c8:	29803fcc 	andi	r6,r5,255
-    16cc:	30c0051e 	bne	r6,r3,16e4 <memchr+0x34>
-    16d0:	00001806 	br	1734 <memchr+0x84>
-    16d4:	10001526 	beq	r2,zero,172c <memchr+0x7c>
-    16d8:	20c00003 	ldbu	r3,0(r4)
-    16dc:	10bfffc4 	addi	r2,r2,-1
-    16e0:	30c01426 	beq	r6,r3,1734 <memchr+0x84>
-    16e4:	21000044 	addi	r4,r4,1
-    16e8:	20c000cc 	andi	r3,r4,3
-    16ec:	183ff91e 	bne	r3,zero,16d4 <__alt_data_end+0xfffe16d4>
-    16f0:	020000c4 	movi	r8,3
-    16f4:	40801136 	bltu	r8,r2,173c <memchr+0x8c>
-    16f8:	10000c26 	beq	r2,zero,172c <memchr+0x7c>
-    16fc:	20c00003 	ldbu	r3,0(r4)
-    1700:	29403fcc 	andi	r5,r5,255
-    1704:	28c00b26 	beq	r5,r3,1734 <memchr+0x84>
-    1708:	20c00044 	addi	r3,r4,1
-    170c:	39803fcc 	andi	r6,r7,255
-    1710:	2089883a 	add	r4,r4,r2
-    1714:	00000306 	br	1724 <memchr+0x74>
-    1718:	18c00044 	addi	r3,r3,1
-    171c:	197fffc3 	ldbu	r5,-1(r3)
-    1720:	31400526 	beq	r6,r5,1738 <memchr+0x88>
-    1724:	1805883a 	mov	r2,r3
-    1728:	20fffb1e 	bne	r4,r3,1718 <__alt_data_end+0xfffe1718>
-    172c:	0005883a 	mov	r2,zero
-    1730:	f800283a 	ret
-    1734:	2005883a 	mov	r2,r4
-    1738:	f800283a 	ret
-    173c:	28c03fcc 	andi	r3,r5,255
-    1740:	1812923a 	slli	r9,r3,8
-    1744:	02ffbff4 	movhi	r11,65279
-    1748:	02a02074 	movhi	r10,32897
-    174c:	48d2b03a 	or	r9,r9,r3
-    1750:	4806943a 	slli	r3,r9,16
-    1754:	5affbfc4 	addi	r11,r11,-257
-    1758:	52a02004 	addi	r10,r10,-32640
-    175c:	48d2b03a 	or	r9,r9,r3
-    1760:	20c00017 	ldw	r3,0(r4)
-    1764:	48c6f03a 	xor	r3,r9,r3
-    1768:	1acd883a 	add	r6,r3,r11
-    176c:	00c6303a 	nor	r3,zero,r3
-    1770:	30c6703a 	and	r3,r6,r3
-    1774:	1a86703a 	and	r3,r3,r10
-    1778:	183fe01e 	bne	r3,zero,16fc <__alt_data_end+0xfffe16fc>
-    177c:	10bfff04 	addi	r2,r2,-4
-    1780:	21000104 	addi	r4,r4,4
-    1784:	40bff636 	bltu	r8,r2,1760 <__alt_data_end+0xfffe1760>
-    1788:	003fdb06 	br	16f8 <__alt_data_end+0xfffe16f8>
-    178c:	3005883a 	mov	r2,r6
-    1790:	003fd706 	br	16f0 <__alt_data_end+0xfffe16f0>
+00001604 <memchr>:
+    1604:	208000cc 	andi	r2,r4,3
+    1608:	280f883a 	mov	r7,r5
+    160c:	10000e26 	beq	r2,zero,1648 <memchr+0x44>
+    1610:	30bfffc4 	addi	r2,r6,-1
+    1614:	30001726 	beq	r6,zero,1674 <memchr+0x70>
+    1618:	29803fcc 	andi	r6,r5,255
+    161c:	00000606 	br	1638 <memchr+0x34>
+    1620:	21000044 	addi	r4,r4,1
+    1624:	20c000cc 	andi	r3,r4,3
+    1628:	18000826 	beq	r3,zero,164c <memchr+0x48>
+    162c:	10bfffc4 	addi	r2,r2,-1
+    1630:	10ffffe0 	cmpeqi	r3,r2,-1
+    1634:	18000f1e 	bne	r3,zero,1674 <memchr+0x70>
+    1638:	20c00003 	ldbu	r3,0(r4)
+    163c:	19bff81e 	bne	r3,r6,1620 <memchr+0x1c>
+    1640:	2005883a 	mov	r2,r4
+    1644:	f800283a 	ret
+    1648:	3005883a 	mov	r2,r6
+    164c:	10c00128 	cmpgeui	r3,r2,4
+    1650:	18000a1e 	bne	r3,zero,167c <memchr+0x78>
+    1654:	10001e26 	beq	r2,zero,16d0 <memchr+0xcc>
+    1658:	2087883a 	add	r3,r4,r2
+    165c:	39803fcc 	andi	r6,r7,255
+    1660:	2005883a 	mov	r2,r4
+    1664:	11000003 	ldbu	r4,0(r2)
+    1668:	21bff626 	beq	r4,r6,1644 <memchr+0x40>
+    166c:	10800044 	addi	r2,r2,1
+    1670:	18bffc1e 	bne	r3,r2,1664 <memchr+0x60>
+    1674:	0005883a 	mov	r2,zero
+    1678:	f800283a 	ret
+    167c:	29403fcc 	andi	r5,r5,255
+    1680:	280c923a 	slli	r6,r5,8
+    1684:	027fbff4 	movhi	r9,65279
+    1688:	02202074 	movhi	r8,32897
+    168c:	314ab03a 	or	r5,r6,r5
+    1690:	280c943a 	slli	r6,r5,16
+    1694:	4a7fbfc4 	addi	r9,r9,-257
+    1698:	42202004 	addi	r8,r8,-32640
+    169c:	314cb03a 	or	r6,r6,r5
+    16a0:	20c00017 	ldw	r3,0(r4)
+    16a4:	30c6f03a 	xor	r3,r6,r3
+    16a8:	1a4b883a 	add	r5,r3,r9
+    16ac:	00c6303a 	nor	r3,zero,r3
+    16b0:	28c6703a 	and	r3,r5,r3
+    16b4:	1a06703a 	and	r3,r3,r8
+    16b8:	183fe71e 	bne	r3,zero,1658 <memchr+0x54>
+    16bc:	10bfff04 	addi	r2,r2,-4
+    16c0:	10c00128 	cmpgeui	r3,r2,4
+    16c4:	21000104 	addi	r4,r4,4
+    16c8:	183ff51e 	bne	r3,zero,16a0 <memchr+0x9c>
+    16cc:	003fe106 	br	1654 <memchr+0x50>
+    16d0:	f800283a 	ret
 
-00001794 <memcpy>:
-    1794:	defffd04 	addi	sp,sp,-12
-    1798:	dfc00215 	stw	ra,8(sp)
-    179c:	dc400115 	stw	r17,4(sp)
-    17a0:	dc000015 	stw	r16,0(sp)
-    17a4:	00c003c4 	movi	r3,15
-    17a8:	2005883a 	mov	r2,r4
-    17ac:	1980452e 	bgeu	r3,r6,18c4 <memcpy+0x130>
-    17b0:	2906b03a 	or	r3,r5,r4
-    17b4:	18c000cc 	andi	r3,r3,3
-    17b8:	1800441e 	bne	r3,zero,18cc <memcpy+0x138>
-    17bc:	347ffc04 	addi	r17,r6,-16
-    17c0:	8822d13a 	srli	r17,r17,4
-    17c4:	28c00104 	addi	r3,r5,4
-    17c8:	23400104 	addi	r13,r4,4
-    17cc:	8820913a 	slli	r16,r17,4
-    17d0:	2b000204 	addi	r12,r5,8
-    17d4:	22c00204 	addi	r11,r4,8
-    17d8:	84000504 	addi	r16,r16,20
-    17dc:	2a800304 	addi	r10,r5,12
-    17e0:	22400304 	addi	r9,r4,12
-    17e4:	2c21883a 	add	r16,r5,r16
-    17e8:	2811883a 	mov	r8,r5
-    17ec:	200f883a 	mov	r7,r4
-    17f0:	41000017 	ldw	r4,0(r8)
-    17f4:	1fc00017 	ldw	ra,0(r3)
-    17f8:	63c00017 	ldw	r15,0(r12)
-    17fc:	39000015 	stw	r4,0(r7)
-    1800:	53800017 	ldw	r14,0(r10)
-    1804:	6fc00015 	stw	ra,0(r13)
-    1808:	5bc00015 	stw	r15,0(r11)
-    180c:	4b800015 	stw	r14,0(r9)
-    1810:	18c00404 	addi	r3,r3,16
-    1814:	39c00404 	addi	r7,r7,16
-    1818:	42000404 	addi	r8,r8,16
-    181c:	6b400404 	addi	r13,r13,16
-    1820:	63000404 	addi	r12,r12,16
-    1824:	5ac00404 	addi	r11,r11,16
-    1828:	52800404 	addi	r10,r10,16
-    182c:	4a400404 	addi	r9,r9,16
-    1830:	1c3fef1e 	bne	r3,r16,17f0 <__alt_data_end+0xfffe17f0>
-    1834:	89c00044 	addi	r7,r17,1
-    1838:	380e913a 	slli	r7,r7,4
-    183c:	310003cc 	andi	r4,r6,15
-    1840:	02c000c4 	movi	r11,3
-    1844:	11c7883a 	add	r3,r2,r7
-    1848:	29cb883a 	add	r5,r5,r7
-    184c:	5900212e 	bgeu	r11,r4,18d4 <memcpy+0x140>
-    1850:	1813883a 	mov	r9,r3
-    1854:	2811883a 	mov	r8,r5
-    1858:	200f883a 	mov	r7,r4
-    185c:	42800017 	ldw	r10,0(r8)
-    1860:	4a400104 	addi	r9,r9,4
-    1864:	39ffff04 	addi	r7,r7,-4
-    1868:	4abfff15 	stw	r10,-4(r9)
-    186c:	42000104 	addi	r8,r8,4
-    1870:	59fffa36 	bltu	r11,r7,185c <__alt_data_end+0xfffe185c>
-    1874:	213fff04 	addi	r4,r4,-4
-    1878:	2008d0ba 	srli	r4,r4,2
-    187c:	318000cc 	andi	r6,r6,3
-    1880:	21000044 	addi	r4,r4,1
-    1884:	2109883a 	add	r4,r4,r4
-    1888:	2109883a 	add	r4,r4,r4
-    188c:	1907883a 	add	r3,r3,r4
-    1890:	290b883a 	add	r5,r5,r4
-    1894:	30000626 	beq	r6,zero,18b0 <memcpy+0x11c>
-    1898:	198d883a 	add	r6,r3,r6
-    189c:	29c00003 	ldbu	r7,0(r5)
-    18a0:	18c00044 	addi	r3,r3,1
-    18a4:	29400044 	addi	r5,r5,1
-    18a8:	19ffffc5 	stb	r7,-1(r3)
-    18ac:	19bffb1e 	bne	r3,r6,189c <__alt_data_end+0xfffe189c>
-    18b0:	dfc00217 	ldw	ra,8(sp)
-    18b4:	dc400117 	ldw	r17,4(sp)
-    18b8:	dc000017 	ldw	r16,0(sp)
-    18bc:	dec00304 	addi	sp,sp,12
-    18c0:	f800283a 	ret
-    18c4:	2007883a 	mov	r3,r4
-    18c8:	003ff206 	br	1894 <__alt_data_end+0xfffe1894>
-    18cc:	2007883a 	mov	r3,r4
-    18d0:	003ff106 	br	1898 <__alt_data_end+0xfffe1898>
-    18d4:	200d883a 	mov	r6,r4
-    18d8:	003fee06 	br	1894 <__alt_data_end+0xfffe1894>
+000016d4 <memcpy>:
+    16d4:	30c00430 	cmpltui	r3,r6,16
+    16d8:	2005883a 	mov	r2,r4
+    16dc:	18002d1e 	bne	r3,zero,1794 <memcpy+0xc0>
+    16e0:	2906b03a 	or	r3,r5,r4
+    16e4:	18c000cc 	andi	r3,r3,3
+    16e8:	1800351e 	bne	r3,zero,17c0 <memcpy+0xec>
+    16ec:	32fffc04 	addi	r11,r6,-16
+    16f0:	5816d13a 	srli	r11,r11,4
+    16f4:	280f883a 	mov	r7,r5
+    16f8:	2007883a 	mov	r3,r4
+    16fc:	5ac00044 	addi	r11,r11,1
+    1700:	5816913a 	slli	r11,r11,4
+    1704:	22d5883a 	add	r10,r4,r11
+    1708:	39000117 	ldw	r4,4(r7)
+    170c:	3a400017 	ldw	r9,0(r7)
+    1710:	3a000217 	ldw	r8,8(r7)
+    1714:	19000115 	stw	r4,4(r3)
+    1718:	39000317 	ldw	r4,12(r7)
+    171c:	1a400015 	stw	r9,0(r3)
+    1720:	1a000215 	stw	r8,8(r3)
+    1724:	19000315 	stw	r4,12(r3)
+    1728:	18c00404 	addi	r3,r3,16
+    172c:	39c00404 	addi	r7,r7,16
+    1730:	50fff51e 	bne	r10,r3,1708 <memcpy+0x34>
+    1734:	3100030c 	andi	r4,r6,12
+    1738:	2acb883a 	add	r5,r5,r11
+    173c:	320003cc 	andi	r8,r6,15
+    1740:	20002226 	beq	r4,zero,17cc <memcpy+0xf8>
+    1744:	280f883a 	mov	r7,r5
+    1748:	1813883a 	mov	r9,r3
+    174c:	39c00104 	addi	r7,r7,4
+    1750:	3abfff17 	ldw	r10,-4(r7)
+    1754:	41c9c83a 	sub	r4,r8,r7
+    1758:	2909883a 	add	r4,r5,r4
+    175c:	4a800015 	stw	r10,0(r9)
+    1760:	21000128 	cmpgeui	r4,r4,4
+    1764:	4a400104 	addi	r9,r9,4
+    1768:	203ff81e 	bne	r4,zero,174c <memcpy+0x78>
+    176c:	413fff04 	addi	r4,r8,-4
+    1770:	2008d0ba 	srli	r4,r4,2
+    1774:	318000cc 	andi	r6,r6,3
+    1778:	31ffffc4 	addi	r7,r6,-1
+    177c:	21000044 	addi	r4,r4,1
+    1780:	200890ba 	slli	r4,r4,2
+    1784:	1907883a 	add	r3,r3,r4
+    1788:	290b883a 	add	r5,r5,r4
+    178c:	3000041e 	bne	r6,zero,17a0 <memcpy+0xcc>
+    1790:	f800283a 	ret
+    1794:	2007883a 	mov	r3,r4
+    1798:	31ffffc4 	addi	r7,r6,-1
+    179c:	303ffc26 	beq	r6,zero,1790 <memcpy+0xbc>
+    17a0:	39c00044 	addi	r7,r7,1
+    17a4:	19cf883a 	add	r7,r3,r7
+    17a8:	29800003 	ldbu	r6,0(r5)
+    17ac:	18c00044 	addi	r3,r3,1
+    17b0:	29400044 	addi	r5,r5,1
+    17b4:	19bfffc5 	stb	r6,-1(r3)
+    17b8:	38fffb1e 	bne	r7,r3,17a8 <memcpy+0xd4>
+    17bc:	f800283a 	ret
+    17c0:	31ffffc4 	addi	r7,r6,-1
+    17c4:	2007883a 	mov	r3,r4
+    17c8:	003ff506 	br	17a0 <memcpy+0xcc>
+    17cc:	400d883a 	mov	r6,r8
+    17d0:	003ff106 	br	1798 <memcpy+0xc4>
 
-000018dc <memmove>:
-    18dc:	2005883a 	mov	r2,r4
-    18e0:	29000b2e 	bgeu	r5,r4,1910 <memmove+0x34>
-    18e4:	298f883a 	add	r7,r5,r6
-    18e8:	21c0092e 	bgeu	r4,r7,1910 <memmove+0x34>
-    18ec:	2187883a 	add	r3,r4,r6
-    18f0:	198bc83a 	sub	r5,r3,r6
-    18f4:	30004826 	beq	r6,zero,1a18 <memmove+0x13c>
-    18f8:	39ffffc4 	addi	r7,r7,-1
-    18fc:	39000003 	ldbu	r4,0(r7)
-    1900:	18ffffc4 	addi	r3,r3,-1
-    1904:	19000005 	stb	r4,0(r3)
-    1908:	28fffb1e 	bne	r5,r3,18f8 <__alt_data_end+0xfffe18f8>
-    190c:	f800283a 	ret
-    1910:	00c003c4 	movi	r3,15
-    1914:	1980412e 	bgeu	r3,r6,1a1c <memmove+0x140>
-    1918:	2886b03a 	or	r3,r5,r2
-    191c:	18c000cc 	andi	r3,r3,3
-    1920:	1800401e 	bne	r3,zero,1a24 <memmove+0x148>
-    1924:	33fffc04 	addi	r15,r6,-16
-    1928:	781ed13a 	srli	r15,r15,4
-    192c:	28c00104 	addi	r3,r5,4
-    1930:	13400104 	addi	r13,r2,4
-    1934:	781c913a 	slli	r14,r15,4
-    1938:	2b000204 	addi	r12,r5,8
-    193c:	12c00204 	addi	r11,r2,8
-    1940:	73800504 	addi	r14,r14,20
-    1944:	2a800304 	addi	r10,r5,12
-    1948:	12400304 	addi	r9,r2,12
-    194c:	2b9d883a 	add	r14,r5,r14
-    1950:	2811883a 	mov	r8,r5
-    1954:	100f883a 	mov	r7,r2
-    1958:	41000017 	ldw	r4,0(r8)
-    195c:	39c00404 	addi	r7,r7,16
-    1960:	18c00404 	addi	r3,r3,16
-    1964:	393ffc15 	stw	r4,-16(r7)
-    1968:	193ffc17 	ldw	r4,-16(r3)
-    196c:	6b400404 	addi	r13,r13,16
-    1970:	5ac00404 	addi	r11,r11,16
-    1974:	693ffc15 	stw	r4,-16(r13)
-    1978:	61000017 	ldw	r4,0(r12)
-    197c:	4a400404 	addi	r9,r9,16
-    1980:	42000404 	addi	r8,r8,16
-    1984:	593ffc15 	stw	r4,-16(r11)
-    1988:	51000017 	ldw	r4,0(r10)
-    198c:	63000404 	addi	r12,r12,16
-    1990:	52800404 	addi	r10,r10,16
-    1994:	493ffc15 	stw	r4,-16(r9)
-    1998:	1bbfef1e 	bne	r3,r14,1958 <__alt_data_end+0xfffe1958>
-    199c:	79000044 	addi	r4,r15,1
-    19a0:	2008913a 	slli	r4,r4,4
-    19a4:	328003cc 	andi	r10,r6,15
-    19a8:	02c000c4 	movi	r11,3
-    19ac:	1107883a 	add	r3,r2,r4
-    19b0:	290b883a 	add	r5,r5,r4
-    19b4:	5a801e2e 	bgeu	r11,r10,1a30 <memmove+0x154>
-    19b8:	1813883a 	mov	r9,r3
-    19bc:	2811883a 	mov	r8,r5
-    19c0:	500f883a 	mov	r7,r10
-    19c4:	41000017 	ldw	r4,0(r8)
-    19c8:	4a400104 	addi	r9,r9,4
-    19cc:	39ffff04 	addi	r7,r7,-4
-    19d0:	493fff15 	stw	r4,-4(r9)
-    19d4:	42000104 	addi	r8,r8,4
-    19d8:	59fffa36 	bltu	r11,r7,19c4 <__alt_data_end+0xfffe19c4>
-    19dc:	513fff04 	addi	r4,r10,-4
-    19e0:	2008d0ba 	srli	r4,r4,2
-    19e4:	318000cc 	andi	r6,r6,3
-    19e8:	21000044 	addi	r4,r4,1
-    19ec:	2109883a 	add	r4,r4,r4
-    19f0:	2109883a 	add	r4,r4,r4
-    19f4:	1907883a 	add	r3,r3,r4
-    19f8:	290b883a 	add	r5,r5,r4
-    19fc:	30000b26 	beq	r6,zero,1a2c <memmove+0x150>
-    1a00:	198d883a 	add	r6,r3,r6
-    1a04:	29c00003 	ldbu	r7,0(r5)
-    1a08:	18c00044 	addi	r3,r3,1
-    1a0c:	29400044 	addi	r5,r5,1
-    1a10:	19ffffc5 	stb	r7,-1(r3)
-    1a14:	19bffb1e 	bne	r3,r6,1a04 <__alt_data_end+0xfffe1a04>
-    1a18:	f800283a 	ret
-    1a1c:	1007883a 	mov	r3,r2
-    1a20:	003ff606 	br	19fc <__alt_data_end+0xfffe19fc>
-    1a24:	1007883a 	mov	r3,r2
-    1a28:	003ff506 	br	1a00 <__alt_data_end+0xfffe1a00>
-    1a2c:	f800283a 	ret
-    1a30:	500d883a 	mov	r6,r10
-    1a34:	003ff106 	br	19fc <__alt_data_end+0xfffe19fc>
+000017d4 <memmove>:
+    17d4:	2005883a 	mov	r2,r4
+    17d8:	29000a2e 	bgeu	r5,r4,1804 <memmove+0x30>
+    17dc:	2989883a 	add	r4,r5,r6
+    17e0:	1100082e 	bgeu	r2,r4,1804 <memmove+0x30>
+    17e4:	1187883a 	add	r3,r2,r6
+    17e8:	30003e26 	beq	r6,zero,18e4 <memmove+0x110>
+    17ec:	217fffc3 	ldbu	r5,-1(r4)
+    17f0:	18ffffc4 	addi	r3,r3,-1
+    17f4:	213fffc4 	addi	r4,r4,-1
+    17f8:	19400005 	stb	r5,0(r3)
+    17fc:	10fffb1e 	bne	r2,r3,17ec <memmove+0x18>
+    1800:	f800283a 	ret
+    1804:	30c00430 	cmpltui	r3,r6,16
+    1808:	18000b26 	beq	r3,zero,1838 <memmove+0x64>
+    180c:	1007883a 	mov	r3,r2
+    1810:	31ffffc4 	addi	r7,r6,-1
+    1814:	30003726 	beq	r6,zero,18f4 <memmove+0x120>
+    1818:	39c00044 	addi	r7,r7,1
+    181c:	29cf883a 	add	r7,r5,r7
+    1820:	29800003 	ldbu	r6,0(r5)
+    1824:	29400044 	addi	r5,r5,1
+    1828:	18c00044 	addi	r3,r3,1
+    182c:	19bfffc5 	stb	r6,-1(r3)
+    1830:	29fffb1e 	bne	r5,r7,1820 <memmove+0x4c>
+    1834:	f800283a 	ret
+    1838:	2886b03a 	or	r3,r5,r2
+    183c:	18c000cc 	andi	r3,r3,3
+    1840:	1800291e 	bne	r3,zero,18e8 <memmove+0x114>
+    1844:	327ffc04 	addi	r9,r6,-16
+    1848:	4812d13a 	srli	r9,r9,4
+    184c:	280f883a 	mov	r7,r5
+    1850:	1007883a 	mov	r3,r2
+    1854:	4a400044 	addi	r9,r9,1
+    1858:	4812913a 	slli	r9,r9,4
+    185c:	1251883a 	add	r8,r2,r9
+    1860:	39000017 	ldw	r4,0(r7)
+    1864:	39c00404 	addi	r7,r7,16
+    1868:	18c00404 	addi	r3,r3,16
+    186c:	193ffc15 	stw	r4,-16(r3)
+    1870:	393ffd17 	ldw	r4,-12(r7)
+    1874:	193ffd15 	stw	r4,-12(r3)
+    1878:	393ffe17 	ldw	r4,-8(r7)
+    187c:	193ffe15 	stw	r4,-8(r3)
+    1880:	393fff17 	ldw	r4,-4(r7)
+    1884:	193fff15 	stw	r4,-4(r3)
+    1888:	40fff51e 	bne	r8,r3,1860 <memmove+0x8c>
+    188c:	3100030c 	andi	r4,r6,12
+    1890:	2a4b883a 	add	r5,r5,r9
+    1894:	320003cc 	andi	r8,r6,15
+    1898:	20001726 	beq	r4,zero,18f8 <memmove+0x124>
+    189c:	2813883a 	mov	r9,r5
+    18a0:	180f883a 	mov	r7,r3
+    18a4:	4a800017 	ldw	r10,0(r9)
+    18a8:	39c00104 	addi	r7,r7,4
+    18ac:	41c9c83a 	sub	r4,r8,r7
+    18b0:	1909883a 	add	r4,r3,r4
+    18b4:	21000128 	cmpgeui	r4,r4,4
+    18b8:	3abfff15 	stw	r10,-4(r7)
+    18bc:	4a400104 	addi	r9,r9,4
+    18c0:	203ff81e 	bne	r4,zero,18a4 <memmove+0xd0>
+    18c4:	413fff04 	addi	r4,r8,-4
+    18c8:	2008d0ba 	srli	r4,r4,2
+    18cc:	318000cc 	andi	r6,r6,3
+    18d0:	21000044 	addi	r4,r4,1
+    18d4:	200890ba 	slli	r4,r4,2
+    18d8:	1907883a 	add	r3,r3,r4
+    18dc:	290b883a 	add	r5,r5,r4
+    18e0:	003fcb06 	br	1810 <memmove+0x3c>
+    18e4:	f800283a 	ret
+    18e8:	31ffffc4 	addi	r7,r6,-1
+    18ec:	1007883a 	mov	r3,r2
+    18f0:	003fc906 	br	1818 <memmove+0x44>
+    18f4:	f800283a 	ret
+    18f8:	400d883a 	mov	r6,r8
+    18fc:	003fc406 	br	1810 <memmove+0x3c>
 
-00001a38 <memset>:
-    1a38:	20c000cc 	andi	r3,r4,3
-    1a3c:	2005883a 	mov	r2,r4
-    1a40:	18004426 	beq	r3,zero,1b54 <memset+0x11c>
-    1a44:	31ffffc4 	addi	r7,r6,-1
-    1a48:	30004026 	beq	r6,zero,1b4c <memset+0x114>
-    1a4c:	2813883a 	mov	r9,r5
-    1a50:	200d883a 	mov	r6,r4
-    1a54:	2007883a 	mov	r3,r4
-    1a58:	00000406 	br	1a6c <memset+0x34>
-    1a5c:	3a3fffc4 	addi	r8,r7,-1
-    1a60:	31800044 	addi	r6,r6,1
-    1a64:	38003926 	beq	r7,zero,1b4c <memset+0x114>
-    1a68:	400f883a 	mov	r7,r8
-    1a6c:	18c00044 	addi	r3,r3,1
-    1a70:	32400005 	stb	r9,0(r6)
-    1a74:	1a0000cc 	andi	r8,r3,3
-    1a78:	403ff81e 	bne	r8,zero,1a5c <__alt_data_end+0xfffe1a5c>
-    1a7c:	010000c4 	movi	r4,3
-    1a80:	21c02d2e 	bgeu	r4,r7,1b38 <memset+0x100>
-    1a84:	29003fcc 	andi	r4,r5,255
-    1a88:	200c923a 	slli	r6,r4,8
-    1a8c:	3108b03a 	or	r4,r6,r4
-    1a90:	200c943a 	slli	r6,r4,16
-    1a94:	218cb03a 	or	r6,r4,r6
-    1a98:	010003c4 	movi	r4,15
-    1a9c:	21c0182e 	bgeu	r4,r7,1b00 <memset+0xc8>
-    1aa0:	3b3ffc04 	addi	r12,r7,-16
-    1aa4:	6018d13a 	srli	r12,r12,4
-    1aa8:	1a000104 	addi	r8,r3,4
-    1aac:	1ac00204 	addi	r11,r3,8
-    1ab0:	6008913a 	slli	r4,r12,4
-    1ab4:	1a800304 	addi	r10,r3,12
-    1ab8:	1813883a 	mov	r9,r3
-    1abc:	21000504 	addi	r4,r4,20
-    1ac0:	1909883a 	add	r4,r3,r4
-    1ac4:	49800015 	stw	r6,0(r9)
-    1ac8:	41800015 	stw	r6,0(r8)
-    1acc:	59800015 	stw	r6,0(r11)
-    1ad0:	51800015 	stw	r6,0(r10)
-    1ad4:	42000404 	addi	r8,r8,16
-    1ad8:	4a400404 	addi	r9,r9,16
-    1adc:	5ac00404 	addi	r11,r11,16
-    1ae0:	52800404 	addi	r10,r10,16
-    1ae4:	413ff71e 	bne	r8,r4,1ac4 <__alt_data_end+0xfffe1ac4>
-    1ae8:	63000044 	addi	r12,r12,1
-    1aec:	6018913a 	slli	r12,r12,4
-    1af0:	39c003cc 	andi	r7,r7,15
-    1af4:	010000c4 	movi	r4,3
-    1af8:	1b07883a 	add	r3,r3,r12
-    1afc:	21c00e2e 	bgeu	r4,r7,1b38 <memset+0x100>
-    1b00:	1813883a 	mov	r9,r3
-    1b04:	3811883a 	mov	r8,r7
-    1b08:	010000c4 	movi	r4,3
-    1b0c:	49800015 	stw	r6,0(r9)
-    1b10:	423fff04 	addi	r8,r8,-4
-    1b14:	4a400104 	addi	r9,r9,4
-    1b18:	223ffc36 	bltu	r4,r8,1b0c <__alt_data_end+0xfffe1b0c>
-    1b1c:	393fff04 	addi	r4,r7,-4
-    1b20:	2008d0ba 	srli	r4,r4,2
-    1b24:	39c000cc 	andi	r7,r7,3
-    1b28:	21000044 	addi	r4,r4,1
-    1b2c:	2109883a 	add	r4,r4,r4
-    1b30:	2109883a 	add	r4,r4,r4
-    1b34:	1907883a 	add	r3,r3,r4
-    1b38:	38000526 	beq	r7,zero,1b50 <memset+0x118>
-    1b3c:	19cf883a 	add	r7,r3,r7
-    1b40:	19400005 	stb	r5,0(r3)
-    1b44:	18c00044 	addi	r3,r3,1
-    1b48:	38fffd1e 	bne	r7,r3,1b40 <__alt_data_end+0xfffe1b40>
-    1b4c:	f800283a 	ret
-    1b50:	f800283a 	ret
-    1b54:	2007883a 	mov	r3,r4
-    1b58:	300f883a 	mov	r7,r6
-    1b5c:	003fc706 	br	1a7c <__alt_data_end+0xfffe1a7c>
+00001900 <memset>:
+    1900:	20c000cc 	andi	r3,r4,3
+    1904:	2005883a 	mov	r2,r4
+    1908:	18003626 	beq	r3,zero,19e4 <memset+0xe4>
+    190c:	31ffffc4 	addi	r7,r6,-1
+    1910:	30003326 	beq	r6,zero,19e0 <memset+0xe0>
+    1914:	2811883a 	mov	r8,r5
+    1918:	2007883a 	mov	r3,r4
+    191c:	00000306 	br	192c <memset+0x2c>
+    1920:	39ffffc4 	addi	r7,r7,-1
+    1924:	39bfffe0 	cmpeqi	r6,r7,-1
+    1928:	30002d1e 	bne	r6,zero,19e0 <memset+0xe0>
+    192c:	18c00044 	addi	r3,r3,1
+    1930:	198000cc 	andi	r6,r3,3
+    1934:	1a3fffc5 	stb	r8,-1(r3)
+    1938:	303ff91e 	bne	r6,zero,1920 <memset+0x20>
+    193c:	39000130 	cmpltui	r4,r7,4
+    1940:	2000221e 	bne	r4,zero,19cc <memset+0xcc>
+    1944:	29003fcc 	andi	r4,r5,255
+    1948:	200c923a 	slli	r6,r4,8
+    194c:	3a000430 	cmpltui	r8,r7,16
+    1950:	3108b03a 	or	r4,r6,r4
+    1954:	200c943a 	slli	r6,r4,16
+    1958:	310cb03a 	or	r6,r6,r4
+    195c:	40000e1e 	bne	r8,zero,1998 <memset+0x98>
+    1960:	393ffc04 	addi	r4,r7,-16
+    1964:	2008d13a 	srli	r4,r4,4
+    1968:	21000044 	addi	r4,r4,1
+    196c:	2008913a 	slli	r4,r4,4
+    1970:	1909883a 	add	r4,r3,r4
+    1974:	19800015 	stw	r6,0(r3)
+    1978:	19800115 	stw	r6,4(r3)
+    197c:	19800215 	stw	r6,8(r3)
+    1980:	19800315 	stw	r6,12(r3)
+    1984:	18c00404 	addi	r3,r3,16
+    1988:	20fffa1e 	bne	r4,r3,1974 <memset+0x74>
+    198c:	3900030c 	andi	r4,r7,12
+    1990:	39c003cc 	andi	r7,r7,15
+    1994:	20000d26 	beq	r4,zero,19cc <memset+0xcc>
+    1998:	1811883a 	mov	r8,r3
+    199c:	42000104 	addi	r8,r8,4
+    19a0:	3a09c83a 	sub	r4,r7,r8
+    19a4:	1909883a 	add	r4,r3,r4
+    19a8:	21000128 	cmpgeui	r4,r4,4
+    19ac:	41bfff15 	stw	r6,-4(r8)
+    19b0:	203ffa1e 	bne	r4,zero,199c <memset+0x9c>
+    19b4:	393fff04 	addi	r4,r7,-4
+    19b8:	2008d0ba 	srli	r4,r4,2
+    19bc:	39c000cc 	andi	r7,r7,3
+    19c0:	21000044 	addi	r4,r4,1
+    19c4:	200890ba 	slli	r4,r4,2
+    19c8:	1907883a 	add	r3,r3,r4
+    19cc:	38000426 	beq	r7,zero,19e0 <memset+0xe0>
+    19d0:	19cf883a 	add	r7,r3,r7
+    19d4:	18c00044 	addi	r3,r3,1
+    19d8:	197fffc5 	stb	r5,-1(r3)
+    19dc:	38fffd1e 	bne	r7,r3,19d4 <memset+0xd4>
+    19e0:	f800283a 	ret
+    19e4:	2007883a 	mov	r3,r4
+    19e8:	300f883a 	mov	r7,r6
+    19ec:	003fd306 	br	193c <memset+0x3c>
 
-00001b60 <_realloc_r>:
-    1b60:	defff604 	addi	sp,sp,-40
-    1b64:	dc800215 	stw	r18,8(sp)
-    1b68:	dfc00915 	stw	ra,36(sp)
-    1b6c:	df000815 	stw	fp,32(sp)
-    1b70:	ddc00715 	stw	r23,28(sp)
-    1b74:	dd800615 	stw	r22,24(sp)
-    1b78:	dd400515 	stw	r21,20(sp)
-    1b7c:	dd000415 	stw	r20,16(sp)
-    1b80:	dcc00315 	stw	r19,12(sp)
-    1b84:	dc400115 	stw	r17,4(sp)
-    1b88:	dc000015 	stw	r16,0(sp)
-    1b8c:	3025883a 	mov	r18,r6
-    1b90:	2800b726 	beq	r5,zero,1e70 <_realloc_r+0x310>
-    1b94:	282b883a 	mov	r21,r5
-    1b98:	2029883a 	mov	r20,r4
-    1b9c:	000361c0 	call	361c <__malloc_lock>
-    1ba0:	a8bfff17 	ldw	r2,-4(r21)
-    1ba4:	043fff04 	movi	r16,-4
-    1ba8:	90c002c4 	addi	r3,r18,11
-    1bac:	01000584 	movi	r4,22
-    1bb0:	acfffe04 	addi	r19,r21,-8
-    1bb4:	1420703a 	and	r16,r2,r16
-    1bb8:	20c0332e 	bgeu	r4,r3,1c88 <_realloc_r+0x128>
-    1bbc:	047ffe04 	movi	r17,-8
-    1bc0:	1c62703a 	and	r17,r3,r17
-    1bc4:	8807883a 	mov	r3,r17
-    1bc8:	88005816 	blt	r17,zero,1d2c <_realloc_r+0x1cc>
-    1bcc:	8c805736 	bltu	r17,r18,1d2c <_realloc_r+0x1cc>
-    1bd0:	80c0300e 	bge	r16,r3,1c94 <_realloc_r+0x134>
-    1bd4:	07000034 	movhi	fp,0
-    1bd8:	e7172004 	addi	fp,fp,23680
-    1bdc:	e1c00217 	ldw	r7,8(fp)
-    1be0:	9c09883a 	add	r4,r19,r16
-    1be4:	22000117 	ldw	r8,4(r4)
-    1be8:	21c06326 	beq	r4,r7,1d78 <_realloc_r+0x218>
-    1bec:	017fff84 	movi	r5,-2
-    1bf0:	414a703a 	and	r5,r8,r5
-    1bf4:	214b883a 	add	r5,r4,r5
-    1bf8:	29800117 	ldw	r6,4(r5)
-    1bfc:	3180004c 	andi	r6,r6,1
-    1c00:	30003f26 	beq	r6,zero,1d00 <_realloc_r+0x1a0>
-    1c04:	1080004c 	andi	r2,r2,1
-    1c08:	10008326 	beq	r2,zero,1e18 <_realloc_r+0x2b8>
-    1c0c:	900b883a 	mov	r5,r18
-    1c10:	a009883a 	mov	r4,r20
-    1c14:	0000ea40 	call	ea4 <_malloc_r>
-    1c18:	1025883a 	mov	r18,r2
-    1c1c:	10011e26 	beq	r2,zero,2098 <_realloc_r+0x538>
-    1c20:	a93fff17 	ldw	r4,-4(r21)
-    1c24:	10fffe04 	addi	r3,r2,-8
-    1c28:	00bfff84 	movi	r2,-2
-    1c2c:	2084703a 	and	r2,r4,r2
-    1c30:	9885883a 	add	r2,r19,r2
-    1c34:	1880ee26 	beq	r3,r2,1ff0 <_realloc_r+0x490>
-    1c38:	81bfff04 	addi	r6,r16,-4
-    1c3c:	00800904 	movi	r2,36
-    1c40:	1180b836 	bltu	r2,r6,1f24 <_realloc_r+0x3c4>
-    1c44:	00c004c4 	movi	r3,19
-    1c48:	19809636 	bltu	r3,r6,1ea4 <_realloc_r+0x344>
-    1c4c:	9005883a 	mov	r2,r18
-    1c50:	a807883a 	mov	r3,r21
-    1c54:	19000017 	ldw	r4,0(r3)
-    1c58:	11000015 	stw	r4,0(r2)
-    1c5c:	19000117 	ldw	r4,4(r3)
-    1c60:	11000115 	stw	r4,4(r2)
-    1c64:	18c00217 	ldw	r3,8(r3)
-    1c68:	10c00215 	stw	r3,8(r2)
-    1c6c:	a80b883a 	mov	r5,r21
-    1c70:	a009883a 	mov	r4,r20
-    1c74:	000292c0 	call	292c <_free_r>
-    1c78:	a009883a 	mov	r4,r20
-    1c7c:	00036400 	call	3640 <__malloc_unlock>
-    1c80:	9005883a 	mov	r2,r18
-    1c84:	00001206 	br	1cd0 <_realloc_r+0x170>
-    1c88:	00c00404 	movi	r3,16
-    1c8c:	1823883a 	mov	r17,r3
-    1c90:	003fce06 	br	1bcc <__alt_data_end+0xfffe1bcc>
-    1c94:	a825883a 	mov	r18,r21
-    1c98:	8445c83a 	sub	r2,r16,r17
-    1c9c:	00c003c4 	movi	r3,15
-    1ca0:	18802636 	bltu	r3,r2,1d3c <_realloc_r+0x1dc>
-    1ca4:	99800117 	ldw	r6,4(r19)
-    1ca8:	9c07883a 	add	r3,r19,r16
-    1cac:	3180004c 	andi	r6,r6,1
-    1cb0:	3420b03a 	or	r16,r6,r16
-    1cb4:	9c000115 	stw	r16,4(r19)
-    1cb8:	18800117 	ldw	r2,4(r3)
-    1cbc:	10800054 	ori	r2,r2,1
-    1cc0:	18800115 	stw	r2,4(r3)
-    1cc4:	a009883a 	mov	r4,r20
-    1cc8:	00036400 	call	3640 <__malloc_unlock>
-    1ccc:	9005883a 	mov	r2,r18
-    1cd0:	dfc00917 	ldw	ra,36(sp)
-    1cd4:	df000817 	ldw	fp,32(sp)
-    1cd8:	ddc00717 	ldw	r23,28(sp)
-    1cdc:	dd800617 	ldw	r22,24(sp)
-    1ce0:	dd400517 	ldw	r21,20(sp)
-    1ce4:	dd000417 	ldw	r20,16(sp)
-    1ce8:	dcc00317 	ldw	r19,12(sp)
-    1cec:	dc800217 	ldw	r18,8(sp)
-    1cf0:	dc400117 	ldw	r17,4(sp)
-    1cf4:	dc000017 	ldw	r16,0(sp)
-    1cf8:	dec00a04 	addi	sp,sp,40
-    1cfc:	f800283a 	ret
-    1d00:	017fff04 	movi	r5,-4
-    1d04:	414a703a 	and	r5,r8,r5
-    1d08:	814d883a 	add	r6,r16,r5
-    1d0c:	30c01f16 	blt	r6,r3,1d8c <_realloc_r+0x22c>
-    1d10:	20800317 	ldw	r2,12(r4)
-    1d14:	20c00217 	ldw	r3,8(r4)
-    1d18:	a825883a 	mov	r18,r21
-    1d1c:	3021883a 	mov	r16,r6
-    1d20:	18800315 	stw	r2,12(r3)
-    1d24:	10c00215 	stw	r3,8(r2)
-    1d28:	003fdb06 	br	1c98 <__alt_data_end+0xfffe1c98>
-    1d2c:	00800304 	movi	r2,12
-    1d30:	a0800015 	stw	r2,0(r20)
-    1d34:	0005883a 	mov	r2,zero
-    1d38:	003fe506 	br	1cd0 <__alt_data_end+0xfffe1cd0>
-    1d3c:	98c00117 	ldw	r3,4(r19)
-    1d40:	9c4b883a 	add	r5,r19,r17
-    1d44:	11000054 	ori	r4,r2,1
-    1d48:	18c0004c 	andi	r3,r3,1
-    1d4c:	1c62b03a 	or	r17,r3,r17
-    1d50:	9c400115 	stw	r17,4(r19)
-    1d54:	29000115 	stw	r4,4(r5)
-    1d58:	2885883a 	add	r2,r5,r2
-    1d5c:	10c00117 	ldw	r3,4(r2)
-    1d60:	29400204 	addi	r5,r5,8
-    1d64:	a009883a 	mov	r4,r20
-    1d68:	18c00054 	ori	r3,r3,1
-    1d6c:	10c00115 	stw	r3,4(r2)
-    1d70:	000292c0 	call	292c <_free_r>
-    1d74:	003fd306 	br	1cc4 <__alt_data_end+0xfffe1cc4>
-    1d78:	017fff04 	movi	r5,-4
-    1d7c:	414a703a 	and	r5,r8,r5
-    1d80:	89800404 	addi	r6,r17,16
-    1d84:	8151883a 	add	r8,r16,r5
-    1d88:	4180590e 	bge	r8,r6,1ef0 <_realloc_r+0x390>
-    1d8c:	1080004c 	andi	r2,r2,1
-    1d90:	103f9e1e 	bne	r2,zero,1c0c <__alt_data_end+0xfffe1c0c>
-    1d94:	adbffe17 	ldw	r22,-8(r21)
-    1d98:	00bfff04 	movi	r2,-4
-    1d9c:	9dadc83a 	sub	r22,r19,r22
-    1da0:	b1800117 	ldw	r6,4(r22)
-    1da4:	3084703a 	and	r2,r6,r2
-    1da8:	20002026 	beq	r4,zero,1e2c <_realloc_r+0x2cc>
-    1dac:	80af883a 	add	r23,r16,r2
-    1db0:	b96f883a 	add	r23,r23,r5
-    1db4:	21c05f26 	beq	r4,r7,1f34 <_realloc_r+0x3d4>
-    1db8:	b8c01c16 	blt	r23,r3,1e2c <_realloc_r+0x2cc>
-    1dbc:	20800317 	ldw	r2,12(r4)
-    1dc0:	20c00217 	ldw	r3,8(r4)
-    1dc4:	81bfff04 	addi	r6,r16,-4
-    1dc8:	01000904 	movi	r4,36
-    1dcc:	18800315 	stw	r2,12(r3)
-    1dd0:	10c00215 	stw	r3,8(r2)
-    1dd4:	b0c00217 	ldw	r3,8(r22)
-    1dd8:	b0800317 	ldw	r2,12(r22)
-    1ddc:	b4800204 	addi	r18,r22,8
+000019f0 <_realloc_r>:
+    19f0:	defff504 	addi	sp,sp,-44
+    19f4:	dc800315 	stw	r18,12(sp)
+    19f8:	dfc00a15 	stw	ra,40(sp)
+    19fc:	df000915 	stw	fp,36(sp)
+    1a00:	ddc00815 	stw	r23,32(sp)
+    1a04:	dd800715 	stw	r22,28(sp)
+    1a08:	dd400615 	stw	r21,24(sp)
+    1a0c:	dd000515 	stw	r20,20(sp)
+    1a10:	dcc00415 	stw	r19,16(sp)
+    1a14:	dc400215 	stw	r17,8(sp)
+    1a18:	dc000115 	stw	r16,4(sp)
+    1a1c:	3025883a 	mov	r18,r6
+    1a20:	28008b26 	beq	r5,zero,1c50 <_realloc_r+0x260>
+    1a24:	2821883a 	mov	r16,r5
+    1a28:	2027883a 	mov	r19,r4
+    1a2c:	944002c4 	addi	r17,r18,11
+    1a30:	000365c0 	call	365c <__malloc_lock>
+    1a34:	888005f0 	cmpltui	r2,r17,23
+    1a38:	1000521e 	bne	r2,zero,1b84 <_realloc_r+0x194>
+    1a3c:	017ffe04 	movi	r5,-8
+    1a40:	8962703a 	and	r17,r17,r5
+    1a44:	8807883a 	mov	r3,r17
+    1a48:	88005116 	blt	r17,zero,1b90 <_realloc_r+0x1a0>
+    1a4c:	8c805036 	bltu	r17,r18,1b90 <_realloc_r+0x1a0>
+    1a50:	80bfff17 	ldw	r2,-4(r16)
+    1a54:	017fff04 	movi	r5,-4
+    1a58:	857ffe04 	addi	r21,r16,-8
+    1a5c:	1168703a 	and	r20,r2,r5
+    1a60:	ad2d883a 	add	r22,r21,r20
+    1a64:	a0c0390e 	bge	r20,r3,1b4c <_realloc_r+0x15c>
+    1a68:	07000034 	movhi	fp,0
+    1a6c:	e716f404 	addi	fp,fp,23504
+    1a70:	e2000217 	ldw	r8,8(fp)
+    1a74:	b1000117 	ldw	r4,4(r22)
+    1a78:	45808e26 	beq	r8,r22,1cb4 <_realloc_r+0x2c4>
+    1a7c:	01bfff84 	movi	r6,-2
+    1a80:	218c703a 	and	r6,r4,r6
+    1a84:	b18d883a 	add	r6,r22,r6
+    1a88:	31800117 	ldw	r6,4(r6)
+    1a8c:	3180004c 	andi	r6,r6,1
+    1a90:	30004f1e 	bne	r6,zero,1bd0 <_realloc_r+0x1e0>
+    1a94:	2148703a 	and	r4,r4,r5
+    1a98:	a10b883a 	add	r5,r20,r4
+    1a9c:	28c0bf0e 	bge	r5,r3,1d9c <_realloc_r+0x3ac>
+    1aa0:	1080004c 	andi	r2,r2,1
+    1aa4:	10004c1e 	bne	r2,zero,1bd8 <_realloc_r+0x1e8>
+    1aa8:	81fffe17 	ldw	r7,-8(r16)
+    1aac:	00bfff04 	movi	r2,-4
+    1ab0:	a9cfc83a 	sub	r7,r21,r7
+    1ab4:	39400117 	ldw	r5,4(r7)
+    1ab8:	288a703a 	and	r5,r5,r2
+    1abc:	b0000426 	beq	r22,zero,1ad0 <_realloc_r+0xe0>
+    1ac0:	a16f883a 	add	r23,r20,r5
+    1ac4:	b92f883a 	add	r23,r23,r4
+    1ac8:	4580bf26 	beq	r8,r22,1dc8 <_realloc_r+0x3d8>
+    1acc:	b8c0930e 	bge	r23,r3,1d1c <_realloc_r+0x32c>
+    1ad0:	38004126 	beq	r7,zero,1bd8 <_realloc_r+0x1e8>
+    1ad4:	a16f883a 	add	r23,r20,r5
+    1ad8:	b8c03f16 	blt	r23,r3,1bd8 <_realloc_r+0x1e8>
+    1adc:	38800317 	ldw	r2,12(r7)
+    1ae0:	38c00217 	ldw	r3,8(r7)
+    1ae4:	a1bfff04 	addi	r6,r20,-4
+    1ae8:	31400968 	cmpgeui	r5,r6,37
+    1aec:	18800315 	stw	r2,12(r3)
+    1af0:	10c00215 	stw	r3,8(r2)
+    1af4:	39000204 	addi	r4,r7,8
+    1af8:	3ded883a 	add	r22,r7,r23
+    1afc:	2800941e 	bne	r5,zero,1d50 <_realloc_r+0x360>
+    1b00:	30800530 	cmpltui	r2,r6,20
+    1b04:	80c00017 	ldw	r3,0(r16)
+    1b08:	1000df1e 	bne	r2,zero,1e88 <_realloc_r+0x498>
+    1b0c:	38c00215 	stw	r3,8(r7)
+    1b10:	80c00117 	ldw	r3,4(r16)
+    1b14:	30800728 	cmpgeui	r2,r6,28
+    1b18:	38c00315 	stw	r3,12(r7)
+    1b1c:	1000dc1e 	bne	r2,zero,1e90 <_realloc_r+0x4a0>
+    1b20:	80c00217 	ldw	r3,8(r16)
+    1b24:	38800404 	addi	r2,r7,16
+    1b28:	84000204 	addi	r16,r16,8
+    1b2c:	10c00015 	stw	r3,0(r2)
+    1b30:	80c00117 	ldw	r3,4(r16)
+    1b34:	b829883a 	mov	r20,r23
+    1b38:	382b883a 	mov	r21,r7
+    1b3c:	10c00115 	stw	r3,4(r2)
+    1b40:	80c00217 	ldw	r3,8(r16)
+    1b44:	2021883a 	mov	r16,r4
+    1b48:	10c00215 	stw	r3,8(r2)
+    1b4c:	a9800117 	ldw	r6,4(r21)
+    1b50:	a445c83a 	sub	r2,r20,r17
+    1b54:	10c00430 	cmpltui	r3,r2,16
+    1b58:	3180004c 	andi	r6,r6,1
+    1b5c:	18004926 	beq	r3,zero,1c84 <_realloc_r+0x294>
+    1b60:	a18cb03a 	or	r6,r20,r6
+    1b64:	a9800115 	stw	r6,4(r21)
+    1b68:	b0800117 	ldw	r2,4(r22)
+    1b6c:	10800054 	ori	r2,r2,1
+    1b70:	b0800115 	stw	r2,4(r22)
+    1b74:	9809883a 	mov	r4,r19
+    1b78:	00036800 	call	3680 <__malloc_unlock>
+    1b7c:	8025883a 	mov	r18,r16
+    1b80:	00000606 	br	1b9c <_realloc_r+0x1ac>
+    1b84:	04400404 	movi	r17,16
+    1b88:	00c00404 	movi	r3,16
+    1b8c:	8cbfb02e 	bgeu	r17,r18,1a50 <_realloc_r+0x60>
+    1b90:	00800304 	movi	r2,12
+    1b94:	98800015 	stw	r2,0(r19)
+    1b98:	0025883a 	mov	r18,zero
+    1b9c:	9005883a 	mov	r2,r18
+    1ba0:	dfc00a17 	ldw	ra,40(sp)
+    1ba4:	df000917 	ldw	fp,36(sp)
+    1ba8:	ddc00817 	ldw	r23,32(sp)
+    1bac:	dd800717 	ldw	r22,28(sp)
+    1bb0:	dd400617 	ldw	r21,24(sp)
+    1bb4:	dd000517 	ldw	r20,20(sp)
+    1bb8:	dcc00417 	ldw	r19,16(sp)
+    1bbc:	dc800317 	ldw	r18,12(sp)
+    1bc0:	dc400217 	ldw	r17,8(sp)
+    1bc4:	dc000117 	ldw	r16,4(sp)
+    1bc8:	dec00b04 	addi	sp,sp,44
+    1bcc:	f800283a 	ret
+    1bd0:	1080004c 	andi	r2,r2,1
+    1bd4:	10006c26 	beq	r2,zero,1d88 <_realloc_r+0x398>
+    1bd8:	900b883a 	mov	r5,r18
+    1bdc:	9809883a 	mov	r4,r19
+    1be0:	0000e240 	call	e24 <_malloc_r>
+    1be4:	1025883a 	mov	r18,r2
+    1be8:	10001626 	beq	r2,zero,1c44 <_realloc_r+0x254>
+    1bec:	80bfff17 	ldw	r2,-4(r16)
+    1bf0:	013fff84 	movi	r4,-2
+    1bf4:	90fffe04 	addi	r3,r18,-8
+    1bf8:	1104703a 	and	r2,r2,r4
+    1bfc:	a885883a 	add	r2,r21,r2
+    1c00:	10c05b26 	beq	r2,r3,1d70 <_realloc_r+0x380>
+    1c04:	a1bfff04 	addi	r6,r20,-4
+    1c08:	30800968 	cmpgeui	r2,r6,37
+    1c0c:	10006a1e 	bne	r2,zero,1db8 <_realloc_r+0x3c8>
+    1c10:	30800530 	cmpltui	r2,r6,20
+    1c14:	81000017 	ldw	r4,0(r16)
+    1c18:	10003726 	beq	r2,zero,1cf8 <_realloc_r+0x308>
+    1c1c:	9005883a 	mov	r2,r18
+    1c20:	8007883a 	mov	r3,r16
+    1c24:	11000015 	stw	r4,0(r2)
+    1c28:	19000117 	ldw	r4,4(r3)
+    1c2c:	11000115 	stw	r4,4(r2)
+    1c30:	18c00217 	ldw	r3,8(r3)
+    1c34:	10c00215 	stw	r3,8(r2)
+    1c38:	800b883a 	mov	r5,r16
+    1c3c:	9809883a 	mov	r4,r19
+    1c40:	00028d40 	call	28d4 <_free_r>
+    1c44:	9809883a 	mov	r4,r19
+    1c48:	00036800 	call	3680 <__malloc_unlock>
+    1c4c:	003fd306 	br	1b9c <_realloc_r+0x1ac>
+    1c50:	300b883a 	mov	r5,r6
+    1c54:	dfc00a17 	ldw	ra,40(sp)
+    1c58:	df000917 	ldw	fp,36(sp)
+    1c5c:	ddc00817 	ldw	r23,32(sp)
+    1c60:	dd800717 	ldw	r22,28(sp)
+    1c64:	dd400617 	ldw	r21,24(sp)
+    1c68:	dd000517 	ldw	r20,20(sp)
+    1c6c:	dcc00417 	ldw	r19,16(sp)
+    1c70:	dc800317 	ldw	r18,12(sp)
+    1c74:	dc400217 	ldw	r17,8(sp)
+    1c78:	dc000117 	ldw	r16,4(sp)
+    1c7c:	dec00b04 	addi	sp,sp,44
+    1c80:	0000e241 	jmpi	e24 <_malloc_r>
+    1c84:	344cb03a 	or	r6,r6,r17
+    1c88:	a9800115 	stw	r6,4(r21)
+    1c8c:	ac4b883a 	add	r5,r21,r17
+    1c90:	10800054 	ori	r2,r2,1
+    1c94:	28800115 	stw	r2,4(r5)
+    1c98:	b0800117 	ldw	r2,4(r22)
+    1c9c:	29400204 	addi	r5,r5,8
+    1ca0:	9809883a 	mov	r4,r19
+    1ca4:	10800054 	ori	r2,r2,1
+    1ca8:	b0800115 	stw	r2,4(r22)
+    1cac:	00028d40 	call	28d4 <_free_r>
+    1cb0:	003fb006 	br	1b74 <_realloc_r+0x184>
+    1cb4:	2148703a 	and	r4,r4,r5
+    1cb8:	a10b883a 	add	r5,r20,r4
+    1cbc:	89800404 	addi	r6,r17,16
+    1cc0:	29bf7716 	blt	r5,r6,1aa0 <_realloc_r+0xb0>
+    1cc4:	ac6b883a 	add	r21,r21,r17
+    1cc8:	2c45c83a 	sub	r2,r5,r17
+    1ccc:	e5400215 	stw	r21,8(fp)
+    1cd0:	10800054 	ori	r2,r2,1
+    1cd4:	a8800115 	stw	r2,4(r21)
+    1cd8:	80bfff17 	ldw	r2,-4(r16)
+    1cdc:	9809883a 	mov	r4,r19
+    1ce0:	8025883a 	mov	r18,r16
+    1ce4:	1080004c 	andi	r2,r2,1
+    1ce8:	1462b03a 	or	r17,r2,r17
+    1cec:	847fff15 	stw	r17,-4(r16)
+    1cf0:	00036800 	call	3680 <__malloc_unlock>
+    1cf4:	003fa906 	br	1b9c <_realloc_r+0x1ac>
+    1cf8:	91000015 	stw	r4,0(r18)
+    1cfc:	80c00117 	ldw	r3,4(r16)
+    1d00:	30800728 	cmpgeui	r2,r6,28
+    1d04:	90c00115 	stw	r3,4(r18)
+    1d08:	1000551e 	bne	r2,zero,1e60 <_realloc_r+0x470>
+    1d0c:	81000217 	ldw	r4,8(r16)
+    1d10:	80c00204 	addi	r3,r16,8
+    1d14:	90800204 	addi	r2,r18,8
+    1d18:	003fc206 	br	1c24 <_realloc_r+0x234>
+    1d1c:	b0800317 	ldw	r2,12(r22)
+    1d20:	b0c00217 	ldw	r3,8(r22)
+    1d24:	a1bfff04 	addi	r6,r20,-4
+    1d28:	31400968 	cmpgeui	r5,r6,37
+    1d2c:	18800315 	stw	r2,12(r3)
+    1d30:	10c00215 	stw	r3,8(r2)
+    1d34:	38c00217 	ldw	r3,8(r7)
+    1d38:	38800317 	ldw	r2,12(r7)
+    1d3c:	39000204 	addi	r4,r7,8
+    1d40:	3ded883a 	add	r22,r7,r23
+    1d44:	18800315 	stw	r2,12(r3)
+    1d48:	10c00215 	stw	r3,8(r2)
+    1d4c:	283f6c26 	beq	r5,zero,1b00 <_realloc_r+0x110>
+    1d50:	800b883a 	mov	r5,r16
+    1d54:	d9c00015 	stw	r7,0(sp)
+    1d58:	00017d40 	call	17d4 <memmove>
+    1d5c:	d9c00017 	ldw	r7,0(sp)
+    1d60:	1021883a 	mov	r16,r2
+    1d64:	b829883a 	mov	r20,r23
+    1d68:	382b883a 	mov	r21,r7
+    1d6c:	003f7706 	br	1b4c <_realloc_r+0x15c>
+    1d70:	90bfff17 	ldw	r2,-4(r18)
+    1d74:	00ffff04 	movi	r3,-4
+    1d78:	10c4703a 	and	r2,r2,r3
+    1d7c:	a0a9883a 	add	r20,r20,r2
+    1d80:	ad2d883a 	add	r22,r21,r20
+    1d84:	003f7106 	br	1b4c <_realloc_r+0x15c>
+    1d88:	81fffe17 	ldw	r7,-8(r16)
+    1d8c:	a9cfc83a 	sub	r7,r21,r7
+    1d90:	38800117 	ldw	r2,4(r7)
+    1d94:	114a703a 	and	r5,r2,r5
+    1d98:	003f4d06 	br	1ad0 <_realloc_r+0xe0>
+    1d9c:	b0800317 	ldw	r2,12(r22)
+    1da0:	b0c00217 	ldw	r3,8(r22)
+    1da4:	2829883a 	mov	r20,r5
+    1da8:	a96d883a 	add	r22,r21,r5
+    1dac:	18800315 	stw	r2,12(r3)
+    1db0:	10c00215 	stw	r3,8(r2)
+    1db4:	003f6506 	br	1b4c <_realloc_r+0x15c>
+    1db8:	800b883a 	mov	r5,r16
+    1dbc:	9009883a 	mov	r4,r18
+    1dc0:	00017d40 	call	17d4 <memmove>
+    1dc4:	003f9c06 	br	1c38 <_realloc_r+0x248>
+    1dc8:	88800404 	addi	r2,r17,16
+    1dcc:	b8bf4016 	blt	r23,r2,1ad0 <_realloc_r+0xe0>
+    1dd0:	38800317 	ldw	r2,12(r7)
+    1dd4:	38c00217 	ldw	r3,8(r7)
+    1dd8:	a1bfff04 	addi	r6,r20,-4
+    1ddc:	31000968 	cmpgeui	r4,r6,37
     1de0:	18800315 	stw	r2,12(r3)
     1de4:	10c00215 	stw	r3,8(r2)
-    1de8:	21801b36 	bltu	r4,r6,1e58 <_realloc_r+0x2f8>
-    1dec:	008004c4 	movi	r2,19
-    1df0:	1180352e 	bgeu	r2,r6,1ec8 <_realloc_r+0x368>
-    1df4:	a8800017 	ldw	r2,0(r21)
-    1df8:	b0800215 	stw	r2,8(r22)
-    1dfc:	a8800117 	ldw	r2,4(r21)
-    1e00:	b0800315 	stw	r2,12(r22)
-    1e04:	008006c4 	movi	r2,27
-    1e08:	11807f36 	bltu	r2,r6,2008 <_realloc_r+0x4a8>
-    1e0c:	b0800404 	addi	r2,r22,16
-    1e10:	ad400204 	addi	r21,r21,8
-    1e14:	00002d06 	br	1ecc <_realloc_r+0x36c>
-    1e18:	adbffe17 	ldw	r22,-8(r21)
-    1e1c:	00bfff04 	movi	r2,-4
-    1e20:	9dadc83a 	sub	r22,r19,r22
-    1e24:	b1000117 	ldw	r4,4(r22)
-    1e28:	2084703a 	and	r2,r4,r2
-    1e2c:	b03f7726 	beq	r22,zero,1c0c <__alt_data_end+0xfffe1c0c>
-    1e30:	80af883a 	add	r23,r16,r2
-    1e34:	b8ff7516 	blt	r23,r3,1c0c <__alt_data_end+0xfffe1c0c>
-    1e38:	b0800317 	ldw	r2,12(r22)
-    1e3c:	b0c00217 	ldw	r3,8(r22)
-    1e40:	81bfff04 	addi	r6,r16,-4
-    1e44:	01000904 	movi	r4,36
-    1e48:	18800315 	stw	r2,12(r3)
-    1e4c:	10c00215 	stw	r3,8(r2)
-    1e50:	b4800204 	addi	r18,r22,8
-    1e54:	21bfe52e 	bgeu	r4,r6,1dec <__alt_data_end+0xfffe1dec>
-    1e58:	a80b883a 	mov	r5,r21
-    1e5c:	9009883a 	mov	r4,r18
-    1e60:	00018dc0 	call	18dc <memmove>
-    1e64:	b821883a 	mov	r16,r23
-    1e68:	b027883a 	mov	r19,r22
-    1e6c:	003f8a06 	br	1c98 <__alt_data_end+0xfffe1c98>
-    1e70:	300b883a 	mov	r5,r6
-    1e74:	dfc00917 	ldw	ra,36(sp)
-    1e78:	df000817 	ldw	fp,32(sp)
-    1e7c:	ddc00717 	ldw	r23,28(sp)
-    1e80:	dd800617 	ldw	r22,24(sp)
-    1e84:	dd400517 	ldw	r21,20(sp)
-    1e88:	dd000417 	ldw	r20,16(sp)
-    1e8c:	dcc00317 	ldw	r19,12(sp)
-    1e90:	dc800217 	ldw	r18,8(sp)
-    1e94:	dc400117 	ldw	r17,4(sp)
-    1e98:	dc000017 	ldw	r16,0(sp)
-    1e9c:	dec00a04 	addi	sp,sp,40
-    1ea0:	0000ea41 	jmpi	ea4 <_malloc_r>
-    1ea4:	a8c00017 	ldw	r3,0(r21)
-    1ea8:	90c00015 	stw	r3,0(r18)
-    1eac:	a8c00117 	ldw	r3,4(r21)
-    1eb0:	90c00115 	stw	r3,4(r18)
-    1eb4:	00c006c4 	movi	r3,27
-    1eb8:	19804536 	bltu	r3,r6,1fd0 <_realloc_r+0x470>
-    1ebc:	90800204 	addi	r2,r18,8
-    1ec0:	a8c00204 	addi	r3,r21,8
-    1ec4:	003f6306 	br	1c54 <__alt_data_end+0xfffe1c54>
-    1ec8:	9005883a 	mov	r2,r18
-    1ecc:	a8c00017 	ldw	r3,0(r21)
-    1ed0:	b821883a 	mov	r16,r23
-    1ed4:	b027883a 	mov	r19,r22
-    1ed8:	10c00015 	stw	r3,0(r2)
-    1edc:	a8c00117 	ldw	r3,4(r21)
-    1ee0:	10c00115 	stw	r3,4(r2)
-    1ee4:	a8c00217 	ldw	r3,8(r21)
-    1ee8:	10c00215 	stw	r3,8(r2)
-    1eec:	003f6a06 	br	1c98 <__alt_data_end+0xfffe1c98>
-    1ef0:	9c67883a 	add	r19,r19,r17
-    1ef4:	4445c83a 	sub	r2,r8,r17
-    1ef8:	e4c00215 	stw	r19,8(fp)
-    1efc:	10800054 	ori	r2,r2,1
-    1f00:	98800115 	stw	r2,4(r19)
-    1f04:	a8bfff17 	ldw	r2,-4(r21)
-    1f08:	a009883a 	mov	r4,r20
-    1f0c:	1080004c 	andi	r2,r2,1
-    1f10:	1462b03a 	or	r17,r2,r17
-    1f14:	ac7fff15 	stw	r17,-4(r21)
-    1f18:	00036400 	call	3640 <__malloc_unlock>
-    1f1c:	a805883a 	mov	r2,r21
-    1f20:	003f6b06 	br	1cd0 <__alt_data_end+0xfffe1cd0>
-    1f24:	a80b883a 	mov	r5,r21
-    1f28:	9009883a 	mov	r4,r18
-    1f2c:	00018dc0 	call	18dc <memmove>
-    1f30:	003f4e06 	br	1c6c <__alt_data_end+0xfffe1c6c>
-    1f34:	89000404 	addi	r4,r17,16
-    1f38:	b93fbc16 	blt	r23,r4,1e2c <__alt_data_end+0xfffe1e2c>
-    1f3c:	b0800317 	ldw	r2,12(r22)
-    1f40:	b0c00217 	ldw	r3,8(r22)
-    1f44:	81bfff04 	addi	r6,r16,-4
-    1f48:	01000904 	movi	r4,36
-    1f4c:	18800315 	stw	r2,12(r3)
-    1f50:	10c00215 	stw	r3,8(r2)
-    1f54:	b4800204 	addi	r18,r22,8
-    1f58:	21804336 	bltu	r4,r6,2068 <_realloc_r+0x508>
-    1f5c:	008004c4 	movi	r2,19
-    1f60:	11803f2e 	bgeu	r2,r6,2060 <_realloc_r+0x500>
-    1f64:	a8800017 	ldw	r2,0(r21)
-    1f68:	b0800215 	stw	r2,8(r22)
-    1f6c:	a8800117 	ldw	r2,4(r21)
-    1f70:	b0800315 	stw	r2,12(r22)
-    1f74:	008006c4 	movi	r2,27
-    1f78:	11803f36 	bltu	r2,r6,2078 <_realloc_r+0x518>
-    1f7c:	b0800404 	addi	r2,r22,16
-    1f80:	ad400204 	addi	r21,r21,8
-    1f84:	a8c00017 	ldw	r3,0(r21)
-    1f88:	10c00015 	stw	r3,0(r2)
-    1f8c:	a8c00117 	ldw	r3,4(r21)
-    1f90:	10c00115 	stw	r3,4(r2)
-    1f94:	a8c00217 	ldw	r3,8(r21)
-    1f98:	10c00215 	stw	r3,8(r2)
-    1f9c:	b447883a 	add	r3,r22,r17
-    1fa0:	bc45c83a 	sub	r2,r23,r17
-    1fa4:	e0c00215 	stw	r3,8(fp)
-    1fa8:	10800054 	ori	r2,r2,1
-    1fac:	18800115 	stw	r2,4(r3)
-    1fb0:	b0800117 	ldw	r2,4(r22)
-    1fb4:	a009883a 	mov	r4,r20
-    1fb8:	1080004c 	andi	r2,r2,1
-    1fbc:	1462b03a 	or	r17,r2,r17
-    1fc0:	b4400115 	stw	r17,4(r22)
-    1fc4:	00036400 	call	3640 <__malloc_unlock>
-    1fc8:	9005883a 	mov	r2,r18
-    1fcc:	003f4006 	br	1cd0 <__alt_data_end+0xfffe1cd0>
-    1fd0:	a8c00217 	ldw	r3,8(r21)
-    1fd4:	90c00215 	stw	r3,8(r18)
-    1fd8:	a8c00317 	ldw	r3,12(r21)
-    1fdc:	90c00315 	stw	r3,12(r18)
-    1fe0:	30801126 	beq	r6,r2,2028 <_realloc_r+0x4c8>
-    1fe4:	90800404 	addi	r2,r18,16
-    1fe8:	a8c00404 	addi	r3,r21,16
-    1fec:	003f1906 	br	1c54 <__alt_data_end+0xfffe1c54>
-    1ff0:	90ffff17 	ldw	r3,-4(r18)
-    1ff4:	00bfff04 	movi	r2,-4
-    1ff8:	a825883a 	mov	r18,r21
-    1ffc:	1884703a 	and	r2,r3,r2
-    2000:	80a1883a 	add	r16,r16,r2
-    2004:	003f2406 	br	1c98 <__alt_data_end+0xfffe1c98>
-    2008:	a8800217 	ldw	r2,8(r21)
-    200c:	b0800415 	stw	r2,16(r22)
-    2010:	a8800317 	ldw	r2,12(r21)
-    2014:	b0800515 	stw	r2,20(r22)
-    2018:	31000a26 	beq	r6,r4,2044 <_realloc_r+0x4e4>
-    201c:	b0800604 	addi	r2,r22,24
-    2020:	ad400404 	addi	r21,r21,16
-    2024:	003fa906 	br	1ecc <__alt_data_end+0xfffe1ecc>
-    2028:	a9000417 	ldw	r4,16(r21)
-    202c:	90800604 	addi	r2,r18,24
-    2030:	a8c00604 	addi	r3,r21,24
-    2034:	91000415 	stw	r4,16(r18)
-    2038:	a9000517 	ldw	r4,20(r21)
-    203c:	91000515 	stw	r4,20(r18)
-    2040:	003f0406 	br	1c54 <__alt_data_end+0xfffe1c54>
-    2044:	a8c00417 	ldw	r3,16(r21)
-    2048:	ad400604 	addi	r21,r21,24
-    204c:	b0800804 	addi	r2,r22,32
-    2050:	b0c00615 	stw	r3,24(r22)
-    2054:	a8ffff17 	ldw	r3,-4(r21)
-    2058:	b0c00715 	stw	r3,28(r22)
-    205c:	003f9b06 	br	1ecc <__alt_data_end+0xfffe1ecc>
-    2060:	9005883a 	mov	r2,r18
-    2064:	003fc706 	br	1f84 <__alt_data_end+0xfffe1f84>
-    2068:	a80b883a 	mov	r5,r21
-    206c:	9009883a 	mov	r4,r18
-    2070:	00018dc0 	call	18dc <memmove>
-    2074:	003fc906 	br	1f9c <__alt_data_end+0xfffe1f9c>
-    2078:	a8800217 	ldw	r2,8(r21)
-    207c:	b0800415 	stw	r2,16(r22)
-    2080:	a8800317 	ldw	r2,12(r21)
-    2084:	b0800515 	stw	r2,20(r22)
-    2088:	31000726 	beq	r6,r4,20a8 <_realloc_r+0x548>
-    208c:	b0800604 	addi	r2,r22,24
-    2090:	ad400404 	addi	r21,r21,16
-    2094:	003fbb06 	br	1f84 <__alt_data_end+0xfffe1f84>
-    2098:	a009883a 	mov	r4,r20
-    209c:	00036400 	call	3640 <__malloc_unlock>
-    20a0:	0005883a 	mov	r2,zero
-    20a4:	003f0a06 	br	1cd0 <__alt_data_end+0xfffe1cd0>
-    20a8:	a8c00417 	ldw	r3,16(r21)
-    20ac:	ad400604 	addi	r21,r21,24
-    20b0:	b0800804 	addi	r2,r22,32
-    20b4:	b0c00615 	stw	r3,24(r22)
-    20b8:	a8ffff17 	ldw	r3,-4(r21)
-    20bc:	b0c00715 	stw	r3,28(r22)
-    20c0:	003fb006 	br	1f84 <__alt_data_end+0xfffe1f84>
+    1de8:	3c800204 	addi	r18,r7,8
+    1dec:	20003b1e 	bne	r4,zero,1edc <_realloc_r+0x4ec>
+    1df0:	30800530 	cmpltui	r2,r6,20
+    1df4:	80c00017 	ldw	r3,0(r16)
+    1df8:	1000361e 	bne	r2,zero,1ed4 <_realloc_r+0x4e4>
+    1dfc:	38c00215 	stw	r3,8(r7)
+    1e00:	80c00117 	ldw	r3,4(r16)
+    1e04:	30800728 	cmpgeui	r2,r6,28
+    1e08:	38c00315 	stw	r3,12(r7)
+    1e0c:	1000401e 	bne	r2,zero,1f10 <_realloc_r+0x520>
+    1e10:	80c00217 	ldw	r3,8(r16)
+    1e14:	38800404 	addi	r2,r7,16
+    1e18:	84000204 	addi	r16,r16,8
+    1e1c:	10c00015 	stw	r3,0(r2)
+    1e20:	80c00117 	ldw	r3,4(r16)
+    1e24:	10c00115 	stw	r3,4(r2)
+    1e28:	80c00217 	ldw	r3,8(r16)
+    1e2c:	10c00215 	stw	r3,8(r2)
+    1e30:	3c47883a 	add	r3,r7,r17
+    1e34:	bc45c83a 	sub	r2,r23,r17
+    1e38:	e0c00215 	stw	r3,8(fp)
+    1e3c:	10800054 	ori	r2,r2,1
+    1e40:	18800115 	stw	r2,4(r3)
+    1e44:	38800117 	ldw	r2,4(r7)
+    1e48:	9809883a 	mov	r4,r19
+    1e4c:	1080004c 	andi	r2,r2,1
+    1e50:	1462b03a 	or	r17,r2,r17
+    1e54:	3c400115 	stw	r17,4(r7)
+    1e58:	00036800 	call	3680 <__malloc_unlock>
+    1e5c:	003f4f06 	br	1b9c <_realloc_r+0x1ac>
+    1e60:	80800217 	ldw	r2,8(r16)
+    1e64:	31800920 	cmpeqi	r6,r6,36
+    1e68:	90800215 	stw	r2,8(r18)
+    1e6c:	80800317 	ldw	r2,12(r16)
+    1e70:	90800315 	stw	r2,12(r18)
+    1e74:	81000417 	ldw	r4,16(r16)
+    1e78:	30000f1e 	bne	r6,zero,1eb8 <_realloc_r+0x4c8>
+    1e7c:	80c00404 	addi	r3,r16,16
+    1e80:	90800404 	addi	r2,r18,16
+    1e84:	003f6706 	br	1c24 <_realloc_r+0x234>
+    1e88:	2005883a 	mov	r2,r4
+    1e8c:	003f2706 	br	1b2c <_realloc_r+0x13c>
+    1e90:	80800217 	ldw	r2,8(r16)
+    1e94:	31800920 	cmpeqi	r6,r6,36
+    1e98:	38800415 	stw	r2,16(r7)
+    1e9c:	80800317 	ldw	r2,12(r16)
+    1ea0:	38800515 	stw	r2,20(r7)
+    1ea4:	80c00417 	ldw	r3,16(r16)
+    1ea8:	3000121e 	bne	r6,zero,1ef4 <_realloc_r+0x504>
+    1eac:	38800604 	addi	r2,r7,24
+    1eb0:	84000404 	addi	r16,r16,16
+    1eb4:	003f1d06 	br	1b2c <_realloc_r+0x13c>
+    1eb8:	91000415 	stw	r4,16(r18)
+    1ebc:	81000517 	ldw	r4,20(r16)
+    1ec0:	80c00604 	addi	r3,r16,24
+    1ec4:	90800604 	addi	r2,r18,24
+    1ec8:	91000515 	stw	r4,20(r18)
+    1ecc:	81000617 	ldw	r4,24(r16)
+    1ed0:	003f5406 	br	1c24 <_realloc_r+0x234>
+    1ed4:	9005883a 	mov	r2,r18
+    1ed8:	003fd006 	br	1e1c <_realloc_r+0x42c>
+    1edc:	800b883a 	mov	r5,r16
+    1ee0:	9009883a 	mov	r4,r18
+    1ee4:	d9c00015 	stw	r7,0(sp)
+    1ee8:	00017d40 	call	17d4 <memmove>
+    1eec:	d9c00017 	ldw	r7,0(sp)
+    1ef0:	003fcf06 	br	1e30 <_realloc_r+0x440>
+    1ef4:	84000604 	addi	r16,r16,24
+    1ef8:	38c00615 	stw	r3,24(r7)
+    1efc:	80ffff17 	ldw	r3,-4(r16)
+    1f00:	38800804 	addi	r2,r7,32
+    1f04:	38c00715 	stw	r3,28(r7)
+    1f08:	80c00017 	ldw	r3,0(r16)
+    1f0c:	003f0706 	br	1b2c <_realloc_r+0x13c>
+    1f10:	80800217 	ldw	r2,8(r16)
+    1f14:	31800920 	cmpeqi	r6,r6,36
+    1f18:	38800415 	stw	r2,16(r7)
+    1f1c:	80800317 	ldw	r2,12(r16)
+    1f20:	38800515 	stw	r2,20(r7)
+    1f24:	80c00417 	ldw	r3,16(r16)
+    1f28:	3000031e 	bne	r6,zero,1f38 <_realloc_r+0x548>
+    1f2c:	38800604 	addi	r2,r7,24
+    1f30:	84000404 	addi	r16,r16,16
+    1f34:	003fb906 	br	1e1c <_realloc_r+0x42c>
+    1f38:	84000604 	addi	r16,r16,24
+    1f3c:	38c00615 	stw	r3,24(r7)
+    1f40:	80ffff17 	ldw	r3,-4(r16)
+    1f44:	38800804 	addi	r2,r7,32
+    1f48:	38c00715 	stw	r3,28(r7)
+    1f4c:	80c00017 	ldw	r3,0(r16)
+    1f50:	003fb206 	br	1e1c <_realloc_r+0x42c>
 
-000020c4 <_sbrk_r>:
-    20c4:	defffd04 	addi	sp,sp,-12
-    20c8:	dc000015 	stw	r16,0(sp)
-    20cc:	04000034 	movhi	r16,0
-    20d0:	dc400115 	stw	r17,4(sp)
-    20d4:	841cb504 	addi	r16,r16,29396
-    20d8:	2023883a 	mov	r17,r4
-    20dc:	2809883a 	mov	r4,r5
-    20e0:	dfc00215 	stw	ra,8(sp)
-    20e4:	80000015 	stw	zero,0(r16)
-    20e8:	00038280 	call	3828 <sbrk>
-    20ec:	00ffffc4 	movi	r3,-1
-    20f0:	10c00526 	beq	r2,r3,2108 <_sbrk_r+0x44>
-    20f4:	dfc00217 	ldw	ra,8(sp)
-    20f8:	dc400117 	ldw	r17,4(sp)
-    20fc:	dc000017 	ldw	r16,0(sp)
-    2100:	dec00304 	addi	sp,sp,12
-    2104:	f800283a 	ret
-    2108:	80c00017 	ldw	r3,0(r16)
-    210c:	183ff926 	beq	r3,zero,20f4 <__alt_data_end+0xfffe20f4>
-    2110:	88c00015 	stw	r3,0(r17)
-    2114:	003ff706 	br	20f4 <__alt_data_end+0xfffe20f4>
+00001f54 <_sbrk_r>:
+    1f54:	defffe04 	addi	sp,sp,-8
+    1f58:	dc000015 	stw	r16,0(sp)
+    1f5c:	00800034 	movhi	r2,0
+    1f60:	2021883a 	mov	r16,r4
+    1f64:	2809883a 	mov	r4,r5
+    1f68:	dfc00115 	stw	ra,4(sp)
+    1f6c:	101c8915 	stw	zero,29220(r2)
+    1f70:	00038580 	call	3858 <sbrk>
+    1f74:	10ffffd8 	cmpnei	r3,r2,-1
+    1f78:	18000426 	beq	r3,zero,1f8c <_sbrk_r+0x38>
+    1f7c:	dfc00117 	ldw	ra,4(sp)
+    1f80:	dc000017 	ldw	r16,0(sp)
+    1f84:	dec00204 	addi	sp,sp,8
+    1f88:	f800283a 	ret
+    1f8c:	00c00034 	movhi	r3,0
+    1f90:	18dc8917 	ldw	r3,29220(r3)
+    1f94:	183ff926 	beq	r3,zero,1f7c <_sbrk_r+0x28>
+    1f98:	80c00015 	stw	r3,0(r16)
+    1f9c:	dfc00117 	ldw	ra,4(sp)
+    1fa0:	dc000017 	ldw	r16,0(sp)
+    1fa4:	dec00204 	addi	sp,sp,8
+    1fa8:	f800283a 	ret
 
-00002118 <__sread>:
-    2118:	defffe04 	addi	sp,sp,-8
-    211c:	dc000015 	stw	r16,0(sp)
-    2120:	2821883a 	mov	r16,r5
-    2124:	2940038f 	ldh	r5,14(r5)
-    2128:	dfc00115 	stw	ra,4(sp)
-    212c:	0002e580 	call	2e58 <_read_r>
-    2130:	10000716 	blt	r2,zero,2150 <__sread+0x38>
-    2134:	80c01417 	ldw	r3,80(r16)
-    2138:	1887883a 	add	r3,r3,r2
-    213c:	80c01415 	stw	r3,80(r16)
+00001fac <__sread>:
+    1fac:	defffe04 	addi	sp,sp,-8
+    1fb0:	dc000015 	stw	r16,0(sp)
+    1fb4:	2821883a 	mov	r16,r5
+    1fb8:	2940038f 	ldh	r5,14(r5)
+    1fbc:	dfc00115 	stw	ra,4(sp)
+    1fc0:	0002e7c0 	call	2e7c <_read_r>
+    1fc4:	10000716 	blt	r2,zero,1fe4 <__sread+0x38>
+    1fc8:	80c01417 	ldw	r3,80(r16)
+    1fcc:	1887883a 	add	r3,r3,r2
+    1fd0:	80c01415 	stw	r3,80(r16)
+    1fd4:	dfc00117 	ldw	ra,4(sp)
+    1fd8:	dc000017 	ldw	r16,0(sp)
+    1fdc:	dec00204 	addi	sp,sp,8
+    1fe0:	f800283a 	ret
+    1fe4:	80c0030b 	ldhu	r3,12(r16)
+    1fe8:	18fbffcc 	andi	r3,r3,61439
+    1fec:	80c0030d 	sth	r3,12(r16)
+    1ff0:	dfc00117 	ldw	ra,4(sp)
+    1ff4:	dc000017 	ldw	r16,0(sp)
+    1ff8:	dec00204 	addi	sp,sp,8
+    1ffc:	f800283a 	ret
+
+00002000 <__seofread>:
+    2000:	0005883a 	mov	r2,zero
+    2004:	f800283a 	ret
+
+00002008 <__swrite>:
+    2008:	2880030b 	ldhu	r2,12(r5)
+    200c:	defffb04 	addi	sp,sp,-20
+    2010:	dcc00315 	stw	r19,12(sp)
+    2014:	dc800215 	stw	r18,8(sp)
+    2018:	dc400115 	stw	r17,4(sp)
+    201c:	dc000015 	stw	r16,0(sp)
+    2020:	dfc00415 	stw	ra,16(sp)
+    2024:	10c0400c 	andi	r3,r2,256
+    2028:	2821883a 	mov	r16,r5
+    202c:	2023883a 	mov	r17,r4
+    2030:	2940038f 	ldh	r5,14(r5)
+    2034:	3025883a 	mov	r18,r6
+    2038:	3827883a 	mov	r19,r7
+    203c:	18000c1e 	bne	r3,zero,2070 <__swrite+0x68>
+    2040:	10bbffcc 	andi	r2,r2,61439
+    2044:	980f883a 	mov	r7,r19
+    2048:	900d883a 	mov	r6,r18
+    204c:	8809883a 	mov	r4,r17
+    2050:	8080030d 	sth	r2,12(r16)
+    2054:	dfc00417 	ldw	ra,16(sp)
+    2058:	dcc00317 	ldw	r19,12(sp)
+    205c:	dc800217 	ldw	r18,8(sp)
+    2060:	dc400117 	ldw	r17,4(sp)
+    2064:	dc000017 	ldw	r16,0(sp)
+    2068:	dec00504 	addi	sp,sp,20
+    206c:	00020ec1 	jmpi	20ec <_write_r>
+    2070:	01c00084 	movi	r7,2
+    2074:	000d883a 	mov	r6,zero
+    2078:	0002bd00 	call	2bd0 <_lseek_r>
+    207c:	8080030b 	ldhu	r2,12(r16)
+    2080:	8140038f 	ldh	r5,14(r16)
+    2084:	003fee06 	br	2040 <__swrite+0x38>
+
+00002088 <__sseek>:
+    2088:	defffe04 	addi	sp,sp,-8
+    208c:	dc000015 	stw	r16,0(sp)
+    2090:	2821883a 	mov	r16,r5
+    2094:	2940038f 	ldh	r5,14(r5)
+    2098:	dfc00115 	stw	ra,4(sp)
+    209c:	0002bd00 	call	2bd0 <_lseek_r>
+    20a0:	10ffffd8 	cmpnei	r3,r2,-1
+    20a4:	18000826 	beq	r3,zero,20c8 <__sseek+0x40>
+    20a8:	80c0030b 	ldhu	r3,12(r16)
+    20ac:	80801415 	stw	r2,80(r16)
+    20b0:	18c40014 	ori	r3,r3,4096
+    20b4:	80c0030d 	sth	r3,12(r16)
+    20b8:	dfc00117 	ldw	ra,4(sp)
+    20bc:	dc000017 	ldw	r16,0(sp)
+    20c0:	dec00204 	addi	sp,sp,8
+    20c4:	f800283a 	ret
+    20c8:	80c0030b 	ldhu	r3,12(r16)
+    20cc:	18fbffcc 	andi	r3,r3,61439
+    20d0:	80c0030d 	sth	r3,12(r16)
+    20d4:	dfc00117 	ldw	ra,4(sp)
+    20d8:	dc000017 	ldw	r16,0(sp)
+    20dc:	dec00204 	addi	sp,sp,8
+    20e0:	f800283a 	ret
+
+000020e4 <__sclose>:
+    20e4:	2940038f 	ldh	r5,14(r5)
+    20e8:	00022b41 	jmpi	22b4 <_close_r>
+
+000020ec <_write_r>:
+    20ec:	2807883a 	mov	r3,r5
+    20f0:	defffe04 	addi	sp,sp,-8
+    20f4:	dc000015 	stw	r16,0(sp)
+    20f8:	300b883a 	mov	r5,r6
+    20fc:	00800034 	movhi	r2,0
+    2100:	380d883a 	mov	r6,r7
+    2104:	2021883a 	mov	r16,r4
+    2108:	1809883a 	mov	r4,r3
+    210c:	dfc00115 	stw	ra,4(sp)
+    2110:	101c8915 	stw	zero,29220(r2)
+    2114:	000394c0 	call	394c <write>
+    2118:	10ffffd8 	cmpnei	r3,r2,-1
+    211c:	18000426 	beq	r3,zero,2130 <_write_r+0x44>
+    2120:	dfc00117 	ldw	ra,4(sp)
+    2124:	dc000017 	ldw	r16,0(sp)
+    2128:	dec00204 	addi	sp,sp,8
+    212c:	f800283a 	ret
+    2130:	00c00034 	movhi	r3,0
+    2134:	18dc8917 	ldw	r3,29220(r3)
+    2138:	183ff926 	beq	r3,zero,2120 <_write_r+0x34>
+    213c:	80c00015 	stw	r3,0(r16)
     2140:	dfc00117 	ldw	ra,4(sp)
     2144:	dc000017 	ldw	r16,0(sp)
     2148:	dec00204 	addi	sp,sp,8
     214c:	f800283a 	ret
-    2150:	80c0030b 	ldhu	r3,12(r16)
-    2154:	18fbffcc 	andi	r3,r3,61439
-    2158:	80c0030d 	sth	r3,12(r16)
-    215c:	dfc00117 	ldw	ra,4(sp)
-    2160:	dc000017 	ldw	r16,0(sp)
-    2164:	dec00204 	addi	sp,sp,8
-    2168:	f800283a 	ret
 
-0000216c <__seofread>:
-    216c:	0005883a 	mov	r2,zero
-    2170:	f800283a 	ret
+00002150 <__swsetup_r>:
+    2150:	00800034 	movhi	r2,0
+    2154:	109c7917 	ldw	r2,29156(r2)
+    2158:	defffd04 	addi	sp,sp,-12
+    215c:	dc400115 	stw	r17,4(sp)
+    2160:	dc000015 	stw	r16,0(sp)
+    2164:	dfc00215 	stw	ra,8(sp)
+    2168:	2023883a 	mov	r17,r4
+    216c:	2821883a 	mov	r16,r5
+    2170:	10000226 	beq	r2,zero,217c <__swsetup_r+0x2c>
+    2174:	10c00e17 	ldw	r3,56(r2)
+    2178:	18001f26 	beq	r3,zero,21f8 <__swsetup_r+0xa8>
+    217c:	8180030b 	ldhu	r6,12(r16)
+    2180:	30c0020c 	andi	r3,r6,8
+    2184:	3005883a 	mov	r2,r6
+    2188:	18002126 	beq	r3,zero,2210 <__swsetup_r+0xc0>
+    218c:	80c00417 	ldw	r3,16(r16)
+    2190:	18002826 	beq	r3,zero,2234 <__swsetup_r+0xe4>
+    2194:	1100004c 	andi	r4,r2,1
+    2198:	20000b1e 	bne	r4,zero,21c8 <__swsetup_r+0x78>
+    219c:	1100008c 	andi	r4,r2,2
+    21a0:	20002e1e 	bne	r4,zero,225c <__swsetup_r+0x10c>
+    21a4:	81000517 	ldw	r4,20(r16)
+    21a8:	81000215 	stw	r4,8(r16)
+    21ac:	18000b26 	beq	r3,zero,21dc <__swsetup_r+0x8c>
+    21b0:	0005883a 	mov	r2,zero
+    21b4:	dfc00217 	ldw	ra,8(sp)
+    21b8:	dc400117 	ldw	r17,4(sp)
+    21bc:	dc000017 	ldw	r16,0(sp)
+    21c0:	dec00304 	addi	sp,sp,12
+    21c4:	f800283a 	ret
+    21c8:	81000517 	ldw	r4,20(r16)
+    21cc:	80000215 	stw	zero,8(r16)
+    21d0:	0109c83a 	sub	r4,zero,r4
+    21d4:	81000615 	stw	r4,24(r16)
+    21d8:	183ff51e 	bne	r3,zero,21b0 <__swsetup_r+0x60>
+    21dc:	10c0200c 	andi	r3,r2,128
+    21e0:	0005883a 	mov	r2,zero
+    21e4:	183ff326 	beq	r3,zero,21b4 <__swsetup_r+0x64>
+    21e8:	31801014 	ori	r6,r6,64
+    21ec:	8180030d 	sth	r6,12(r16)
+    21f0:	00bfffc4 	movi	r2,-1
+    21f4:	003fef06 	br	21b4 <__swsetup_r+0x64>
+    21f8:	1009883a 	mov	r4,r2
+    21fc:	00007d40 	call	7d4 <__sinit>
+    2200:	8180030b 	ldhu	r6,12(r16)
+    2204:	30c0020c 	andi	r3,r6,8
+    2208:	3005883a 	mov	r2,r6
+    220c:	183fdf1e 	bne	r3,zero,218c <__swsetup_r+0x3c>
+    2210:	3080040c 	andi	r2,r6,16
+    2214:	10002126 	beq	r2,zero,229c <__swsetup_r+0x14c>
+    2218:	3080010c 	andi	r2,r6,4
+    221c:	1000111e 	bne	r2,zero,2264 <__swsetup_r+0x114>
+    2220:	80c00417 	ldw	r3,16(r16)
+    2224:	30800214 	ori	r2,r6,8
+    2228:	8080030d 	sth	r2,12(r16)
+    222c:	100d883a 	mov	r6,r2
+    2230:	183fd81e 	bne	r3,zero,2194 <__swsetup_r+0x44>
+    2234:	1100a00c 	andi	r4,r2,640
+    2238:	21008020 	cmpeqi	r4,r4,512
+    223c:	203fd51e 	bne	r4,zero,2194 <__swsetup_r+0x44>
+    2240:	800b883a 	mov	r5,r16
+    2244:	8809883a 	mov	r4,r17
+    2248:	0002c340 	call	2c34 <__smakebuf_r>
+    224c:	8180030b 	ldhu	r6,12(r16)
+    2250:	80c00417 	ldw	r3,16(r16)
+    2254:	3005883a 	mov	r2,r6
+    2258:	003fce06 	br	2194 <__swsetup_r+0x44>
+    225c:	0009883a 	mov	r4,zero
+    2260:	003fd106 	br	21a8 <__swsetup_r+0x58>
+    2264:	81400c17 	ldw	r5,48(r16)
+    2268:	28000626 	beq	r5,zero,2284 <__swsetup_r+0x134>
+    226c:	80801004 	addi	r2,r16,64
+    2270:	28800326 	beq	r5,r2,2280 <__swsetup_r+0x130>
+    2274:	8809883a 	mov	r4,r17
+    2278:	00028d40 	call	28d4 <_free_r>
+    227c:	8180030b 	ldhu	r6,12(r16)
+    2280:	80000c15 	stw	zero,48(r16)
+    2284:	80c00417 	ldw	r3,16(r16)
+    2288:	00bff6c4 	movi	r2,-37
+    228c:	118c703a 	and	r6,r2,r6
+    2290:	80000115 	stw	zero,4(r16)
+    2294:	80c00015 	stw	r3,0(r16)
+    2298:	003fe206 	br	2224 <__swsetup_r+0xd4>
+    229c:	00800244 	movi	r2,9
+    22a0:	88800015 	stw	r2,0(r17)
+    22a4:	31801014 	ori	r6,r6,64
+    22a8:	8180030d 	sth	r6,12(r16)
+    22ac:	00bfffc4 	movi	r2,-1
+    22b0:	003fc006 	br	21b4 <__swsetup_r+0x64>
 
-00002174 <__swrite>:
-    2174:	2880030b 	ldhu	r2,12(r5)
-    2178:	defffb04 	addi	sp,sp,-20
-    217c:	dcc00315 	stw	r19,12(sp)
-    2180:	dc800215 	stw	r18,8(sp)
-    2184:	dc400115 	stw	r17,4(sp)
-    2188:	dc000015 	stw	r16,0(sp)
-    218c:	dfc00415 	stw	ra,16(sp)
-    2190:	10c0400c 	andi	r3,r2,256
-    2194:	2821883a 	mov	r16,r5
-    2198:	2023883a 	mov	r17,r4
-    219c:	3025883a 	mov	r18,r6
-    21a0:	3827883a 	mov	r19,r7
-    21a4:	18000526 	beq	r3,zero,21bc <__swrite+0x48>
-    21a8:	2940038f 	ldh	r5,14(r5)
-    21ac:	01c00084 	movi	r7,2
-    21b0:	000d883a 	mov	r6,zero
-    21b4:	0002c3c0 	call	2c3c <_lseek_r>
-    21b8:	8080030b 	ldhu	r2,12(r16)
-    21bc:	8140038f 	ldh	r5,14(r16)
-    21c0:	10bbffcc 	andi	r2,r2,61439
-    21c4:	980f883a 	mov	r7,r19
-    21c8:	900d883a 	mov	r6,r18
-    21cc:	8809883a 	mov	r4,r17
-    21d0:	8080030d 	sth	r2,12(r16)
-    21d4:	dfc00417 	ldw	ra,16(sp)
-    21d8:	dcc00317 	ldw	r19,12(sp)
-    21dc:	dc800217 	ldw	r18,8(sp)
-    21e0:	dc400117 	ldw	r17,4(sp)
-    21e4:	dc000017 	ldw	r16,0(sp)
-    21e8:	dec00504 	addi	sp,sp,20
-    21ec:	00022541 	jmpi	2254 <_write_r>
+000022b4 <_close_r>:
+    22b4:	defffe04 	addi	sp,sp,-8
+    22b8:	dc000015 	stw	r16,0(sp)
+    22bc:	00800034 	movhi	r2,0
+    22c0:	2021883a 	mov	r16,r4
+    22c4:	2809883a 	mov	r4,r5
+    22c8:	dfc00115 	stw	ra,4(sp)
+    22cc:	101c8915 	stw	zero,29220(r2)
+    22d0:	00031b00 	call	31b0 <close>
+    22d4:	10ffffd8 	cmpnei	r3,r2,-1
+    22d8:	18000426 	beq	r3,zero,22ec <_close_r+0x38>
+    22dc:	dfc00117 	ldw	ra,4(sp)
+    22e0:	dc000017 	ldw	r16,0(sp)
+    22e4:	dec00204 	addi	sp,sp,8
+    22e8:	f800283a 	ret
+    22ec:	00c00034 	movhi	r3,0
+    22f0:	18dc8917 	ldw	r3,29220(r3)
+    22f4:	183ff926 	beq	r3,zero,22dc <_close_r+0x28>
+    22f8:	80c00015 	stw	r3,0(r16)
+    22fc:	dfc00117 	ldw	ra,4(sp)
+    2300:	dc000017 	ldw	r16,0(sp)
+    2304:	dec00204 	addi	sp,sp,8
+    2308:	f800283a 	ret
 
-000021f0 <__sseek>:
-    21f0:	defffe04 	addi	sp,sp,-8
-    21f4:	dc000015 	stw	r16,0(sp)
-    21f8:	2821883a 	mov	r16,r5
-    21fc:	2940038f 	ldh	r5,14(r5)
-    2200:	dfc00115 	stw	ra,4(sp)
-    2204:	0002c3c0 	call	2c3c <_lseek_r>
-    2208:	00ffffc4 	movi	r3,-1
-    220c:	10c00826 	beq	r2,r3,2230 <__sseek+0x40>
-    2210:	80c0030b 	ldhu	r3,12(r16)
-    2214:	80801415 	stw	r2,80(r16)
-    2218:	18c40014 	ori	r3,r3,4096
-    221c:	80c0030d 	sth	r3,12(r16)
-    2220:	dfc00117 	ldw	ra,4(sp)
-    2224:	dc000017 	ldw	r16,0(sp)
-    2228:	dec00204 	addi	sp,sp,8
-    222c:	f800283a 	ret
-    2230:	80c0030b 	ldhu	r3,12(r16)
-    2234:	18fbffcc 	andi	r3,r3,61439
-    2238:	80c0030d 	sth	r3,12(r16)
-    223c:	dfc00117 	ldw	ra,4(sp)
-    2240:	dc000017 	ldw	r16,0(sp)
-    2244:	dec00204 	addi	sp,sp,8
-    2248:	f800283a 	ret
+0000230c <_fclose_r.part.0>:
+    230c:	defffc04 	addi	sp,sp,-16
+    2310:	dc800215 	stw	r18,8(sp)
+    2314:	dc400115 	stw	r17,4(sp)
+    2318:	dc000015 	stw	r16,0(sp)
+    231c:	dfc00315 	stw	ra,12(sp)
+    2320:	2821883a 	mov	r16,r5
+    2324:	2023883a 	mov	r17,r4
+    2328:	00024ac0 	call	24ac <__sflush_r>
+    232c:	80c00b17 	ldw	r3,44(r16)
+    2330:	1025883a 	mov	r18,r2
+    2334:	18000426 	beq	r3,zero,2348 <_fclose_r.part.0+0x3c>
+    2338:	81400717 	ldw	r5,28(r16)
+    233c:	8809883a 	mov	r4,r17
+    2340:	183ee83a 	callr	r3
+    2344:	10001916 	blt	r2,zero,23ac <_fclose_r.part.0+0xa0>
+    2348:	8080030b 	ldhu	r2,12(r16)
+    234c:	1080200c 	andi	r2,r2,128
+    2350:	10001a1e 	bne	r2,zero,23bc <_fclose_r.part.0+0xb0>
+    2354:	81400c17 	ldw	r5,48(r16)
+    2358:	28000526 	beq	r5,zero,2370 <_fclose_r.part.0+0x64>
+    235c:	80801004 	addi	r2,r16,64
+    2360:	28800226 	beq	r5,r2,236c <_fclose_r.part.0+0x60>
+    2364:	8809883a 	mov	r4,r17
+    2368:	00028d40 	call	28d4 <_free_r>
+    236c:	80000c15 	stw	zero,48(r16)
+    2370:	81401117 	ldw	r5,68(r16)
+    2374:	28000326 	beq	r5,zero,2384 <_fclose_r.part.0+0x78>
+    2378:	8809883a 	mov	r4,r17
+    237c:	00028d40 	call	28d4 <_free_r>
+    2380:	80001115 	stw	zero,68(r16)
+    2384:	00007e40 	call	7e4 <__sfp_lock_acquire>
+    2388:	8000030d 	sth	zero,12(r16)
+    238c:	00007e80 	call	7e8 <__sfp_lock_release>
+    2390:	9005883a 	mov	r2,r18
+    2394:	dfc00317 	ldw	ra,12(sp)
+    2398:	dc800217 	ldw	r18,8(sp)
+    239c:	dc400117 	ldw	r17,4(sp)
+    23a0:	dc000017 	ldw	r16,0(sp)
+    23a4:	dec00404 	addi	sp,sp,16
+    23a8:	f800283a 	ret
+    23ac:	8080030b 	ldhu	r2,12(r16)
+    23b0:	04bfffc4 	movi	r18,-1
+    23b4:	1080200c 	andi	r2,r2,128
+    23b8:	103fe626 	beq	r2,zero,2354 <_fclose_r.part.0+0x48>
+    23bc:	81400417 	ldw	r5,16(r16)
+    23c0:	8809883a 	mov	r4,r17
+    23c4:	00028d40 	call	28d4 <_free_r>
+    23c8:	003fe206 	br	2354 <_fclose_r.part.0+0x48>
 
-0000224c <__sclose>:
-    224c:	2940038f 	ldh	r5,14(r5)
-    2250:	00024081 	jmpi	2408 <_close_r>
+000023cc <_fclose_r>:
+    23cc:	28001926 	beq	r5,zero,2434 <_fclose_r+0x68>
+    23d0:	defffd04 	addi	sp,sp,-12
+    23d4:	dc000115 	stw	r16,4(sp)
+    23d8:	dfc00215 	stw	ra,8(sp)
+    23dc:	2021883a 	mov	r16,r4
+    23e0:	20000226 	beq	r4,zero,23ec <_fclose_r+0x20>
+    23e4:	20800e17 	ldw	r2,56(r4)
+    23e8:	10000c26 	beq	r2,zero,241c <_fclose_r+0x50>
+    23ec:	2880030f 	ldh	r2,12(r5)
+    23f0:	1000051e 	bne	r2,zero,2408 <_fclose_r+0x3c>
+    23f4:	0005883a 	mov	r2,zero
+    23f8:	dfc00217 	ldw	ra,8(sp)
+    23fc:	dc000117 	ldw	r16,4(sp)
+    2400:	dec00304 	addi	sp,sp,12
+    2404:	f800283a 	ret
+    2408:	8009883a 	mov	r4,r16
+    240c:	dfc00217 	ldw	ra,8(sp)
+    2410:	dc000117 	ldw	r16,4(sp)
+    2414:	dec00304 	addi	sp,sp,12
+    2418:	000230c1 	jmpi	230c <_fclose_r.part.0>
+    241c:	d9400015 	stw	r5,0(sp)
+    2420:	00007d40 	call	7d4 <__sinit>
+    2424:	d9400017 	ldw	r5,0(sp)
+    2428:	2880030f 	ldh	r2,12(r5)
+    242c:	103ff126 	beq	r2,zero,23f4 <_fclose_r+0x28>
+    2430:	003ff506 	br	2408 <_fclose_r+0x3c>
+    2434:	0005883a 	mov	r2,zero
+    2438:	f800283a 	ret
 
-00002254 <_write_r>:
-    2254:	defffd04 	addi	sp,sp,-12
-    2258:	2805883a 	mov	r2,r5
-    225c:	dc000015 	stw	r16,0(sp)
-    2260:	04000034 	movhi	r16,0
-    2264:	dc400115 	stw	r17,4(sp)
-    2268:	300b883a 	mov	r5,r6
-    226c:	841cb504 	addi	r16,r16,29396
-    2270:	2023883a 	mov	r17,r4
-    2274:	380d883a 	mov	r6,r7
-    2278:	1009883a 	mov	r4,r2
-    227c:	dfc00215 	stw	ra,8(sp)
-    2280:	80000015 	stw	zero,0(r16)
-    2284:	00039140 	call	3914 <write>
-    2288:	00ffffc4 	movi	r3,-1
-    228c:	10c00526 	beq	r2,r3,22a4 <_write_r+0x50>
-    2290:	dfc00217 	ldw	ra,8(sp)
-    2294:	dc400117 	ldw	r17,4(sp)
-    2298:	dc000017 	ldw	r16,0(sp)
-    229c:	dec00304 	addi	sp,sp,12
-    22a0:	f800283a 	ret
-    22a4:	80c00017 	ldw	r3,0(r16)
-    22a8:	183ff926 	beq	r3,zero,2290 <__alt_data_end+0xfffe2290>
-    22ac:	88c00015 	stw	r3,0(r17)
-    22b0:	003ff706 	br	2290 <__alt_data_end+0xfffe2290>
-
-000022b4 <__swsetup_r>:
-    22b4:	00800034 	movhi	r2,0
-    22b8:	defffd04 	addi	sp,sp,-12
-    22bc:	109ca504 	addi	r2,r2,29332
-    22c0:	dc400115 	stw	r17,4(sp)
-    22c4:	2023883a 	mov	r17,r4
-    22c8:	11000017 	ldw	r4,0(r2)
-    22cc:	dc000015 	stw	r16,0(sp)
-    22d0:	dfc00215 	stw	ra,8(sp)
-    22d4:	2821883a 	mov	r16,r5
-    22d8:	20000226 	beq	r4,zero,22e4 <__swsetup_r+0x30>
-    22dc:	20800e17 	ldw	r2,56(r4)
-    22e0:	10003126 	beq	r2,zero,23a8 <__swsetup_r+0xf4>
-    22e4:	8080030b 	ldhu	r2,12(r16)
-    22e8:	10c0020c 	andi	r3,r2,8
-    22ec:	1009883a 	mov	r4,r2
-    22f0:	18000f26 	beq	r3,zero,2330 <__swsetup_r+0x7c>
-    22f4:	80c00417 	ldw	r3,16(r16)
-    22f8:	18001526 	beq	r3,zero,2350 <__swsetup_r+0x9c>
-    22fc:	1100004c 	andi	r4,r2,1
-    2300:	20001c1e 	bne	r4,zero,2374 <__swsetup_r+0xc0>
-    2304:	1080008c 	andi	r2,r2,2
-    2308:	1000291e 	bne	r2,zero,23b0 <__swsetup_r+0xfc>
-    230c:	80800517 	ldw	r2,20(r16)
-    2310:	80800215 	stw	r2,8(r16)
-    2314:	18001c26 	beq	r3,zero,2388 <__swsetup_r+0xd4>
-    2318:	0005883a 	mov	r2,zero
-    231c:	dfc00217 	ldw	ra,8(sp)
-    2320:	dc400117 	ldw	r17,4(sp)
-    2324:	dc000017 	ldw	r16,0(sp)
-    2328:	dec00304 	addi	sp,sp,12
-    232c:	f800283a 	ret
-    2330:	2080040c 	andi	r2,r4,16
-    2334:	10002e26 	beq	r2,zero,23f0 <__swsetup_r+0x13c>
-    2338:	2080010c 	andi	r2,r4,4
-    233c:	10001e1e 	bne	r2,zero,23b8 <__swsetup_r+0x104>
-    2340:	80c00417 	ldw	r3,16(r16)
-    2344:	20800214 	ori	r2,r4,8
-    2348:	8080030d 	sth	r2,12(r16)
-    234c:	183feb1e 	bne	r3,zero,22fc <__alt_data_end+0xfffe22fc>
-    2350:	1100a00c 	andi	r4,r2,640
-    2354:	01408004 	movi	r5,512
-    2358:	217fe826 	beq	r4,r5,22fc <__alt_data_end+0xfffe22fc>
-    235c:	800b883a 	mov	r5,r16
-    2360:	8809883a 	mov	r4,r17
-    2364:	0002c9c0 	call	2c9c <__smakebuf_r>
-    2368:	8080030b 	ldhu	r2,12(r16)
-    236c:	80c00417 	ldw	r3,16(r16)
-    2370:	003fe206 	br	22fc <__alt_data_end+0xfffe22fc>
-    2374:	80800517 	ldw	r2,20(r16)
-    2378:	80000215 	stw	zero,8(r16)
-    237c:	0085c83a 	sub	r2,zero,r2
-    2380:	80800615 	stw	r2,24(r16)
-    2384:	183fe41e 	bne	r3,zero,2318 <__alt_data_end+0xfffe2318>
-    2388:	80c0030b 	ldhu	r3,12(r16)
-    238c:	0005883a 	mov	r2,zero
-    2390:	1900200c 	andi	r4,r3,128
-    2394:	203fe126 	beq	r4,zero,231c <__alt_data_end+0xfffe231c>
-    2398:	18c01014 	ori	r3,r3,64
-    239c:	80c0030d 	sth	r3,12(r16)
-    23a0:	00bfffc4 	movi	r2,-1
-    23a4:	003fdd06 	br	231c <__alt_data_end+0xfffe231c>
-    23a8:	00008040 	call	804 <__sinit>
-    23ac:	003fcd06 	br	22e4 <__alt_data_end+0xfffe22e4>
-    23b0:	0005883a 	mov	r2,zero
-    23b4:	003fd606 	br	2310 <__alt_data_end+0xfffe2310>
-    23b8:	81400c17 	ldw	r5,48(r16)
-    23bc:	28000626 	beq	r5,zero,23d8 <__swsetup_r+0x124>
-    23c0:	80801004 	addi	r2,r16,64
-    23c4:	28800326 	beq	r5,r2,23d4 <__swsetup_r+0x120>
-    23c8:	8809883a 	mov	r4,r17
-    23cc:	000292c0 	call	292c <_free_r>
-    23d0:	8100030b 	ldhu	r4,12(r16)
-    23d4:	80000c15 	stw	zero,48(r16)
-    23d8:	80c00417 	ldw	r3,16(r16)
-    23dc:	00bff6c4 	movi	r2,-37
-    23e0:	1108703a 	and	r4,r2,r4
-    23e4:	80000115 	stw	zero,4(r16)
-    23e8:	80c00015 	stw	r3,0(r16)
-    23ec:	003fd506 	br	2344 <__alt_data_end+0xfffe2344>
-    23f0:	00800244 	movi	r2,9
-    23f4:	88800015 	stw	r2,0(r17)
-    23f8:	20801014 	ori	r2,r4,64
-    23fc:	8080030d 	sth	r2,12(r16)
-    2400:	00bfffc4 	movi	r2,-1
-    2404:	003fc506 	br	231c <__alt_data_end+0xfffe231c>
-
-00002408 <_close_r>:
-    2408:	defffd04 	addi	sp,sp,-12
-    240c:	dc000015 	stw	r16,0(sp)
-    2410:	04000034 	movhi	r16,0
-    2414:	dc400115 	stw	r17,4(sp)
-    2418:	841cb504 	addi	r16,r16,29396
-    241c:	2023883a 	mov	r17,r4
-    2420:	2809883a 	mov	r4,r5
-    2424:	dfc00215 	stw	ra,8(sp)
-    2428:	80000015 	stw	zero,0(r16)
-    242c:	00031800 	call	3180 <close>
-    2430:	00ffffc4 	movi	r3,-1
-    2434:	10c00526 	beq	r2,r3,244c <_close_r+0x44>
-    2438:	dfc00217 	ldw	ra,8(sp)
-    243c:	dc400117 	ldw	r17,4(sp)
-    2440:	dc000017 	ldw	r16,0(sp)
-    2444:	dec00304 	addi	sp,sp,12
-    2448:	f800283a 	ret
-    244c:	80c00017 	ldw	r3,0(r16)
-    2450:	183ff926 	beq	r3,zero,2438 <__alt_data_end+0xfffe2438>
-    2454:	88c00015 	stw	r3,0(r17)
-    2458:	003ff706 	br	2438 <__alt_data_end+0xfffe2438>
-
-0000245c <_fclose_r>:
-    245c:	28003926 	beq	r5,zero,2544 <_fclose_r+0xe8>
-    2460:	defffc04 	addi	sp,sp,-16
-    2464:	dc400115 	stw	r17,4(sp)
-    2468:	dc000015 	stw	r16,0(sp)
-    246c:	dfc00315 	stw	ra,12(sp)
-    2470:	dc800215 	stw	r18,8(sp)
-    2474:	2023883a 	mov	r17,r4
-    2478:	2821883a 	mov	r16,r5
-    247c:	20000226 	beq	r4,zero,2488 <_fclose_r+0x2c>
-    2480:	20800e17 	ldw	r2,56(r4)
-    2484:	10002726 	beq	r2,zero,2524 <_fclose_r+0xc8>
-    2488:	8080030f 	ldh	r2,12(r16)
-    248c:	1000071e 	bne	r2,zero,24ac <_fclose_r+0x50>
-    2490:	0005883a 	mov	r2,zero
-    2494:	dfc00317 	ldw	ra,12(sp)
-    2498:	dc800217 	ldw	r18,8(sp)
-    249c:	dc400117 	ldw	r17,4(sp)
-    24a0:	dc000017 	ldw	r16,0(sp)
-    24a4:	dec00404 	addi	sp,sp,16
+0000243c <fclose>:
+    243c:	20000826 	beq	r4,zero,2460 <fclose+0x24>
+    2440:	00800034 	movhi	r2,0
+    2444:	200b883a 	mov	r5,r4
+    2448:	111c7917 	ldw	r4,29156(r2)
+    244c:	20000226 	beq	r4,zero,2458 <fclose+0x1c>
+    2450:	20800e17 	ldw	r2,56(r4)
+    2454:	10000526 	beq	r2,zero,246c <fclose+0x30>
+    2458:	2880030f 	ldh	r2,12(r5)
+    245c:	1000021e 	bne	r2,zero,2468 <fclose+0x2c>
+    2460:	0005883a 	mov	r2,zero
+    2464:	f800283a 	ret
+    2468:	000230c1 	jmpi	230c <_fclose_r.part.0>
+    246c:	defffd04 	addi	sp,sp,-12
+    2470:	d9400115 	stw	r5,4(sp)
+    2474:	d9000015 	stw	r4,0(sp)
+    2478:	dfc00215 	stw	ra,8(sp)
+    247c:	00007d40 	call	7d4 <__sinit>
+    2480:	d9400117 	ldw	r5,4(sp)
+    2484:	d9000017 	ldw	r4,0(sp)
+    2488:	2880030f 	ldh	r2,12(r5)
+    248c:	10000326 	beq	r2,zero,249c <fclose+0x60>
+    2490:	dfc00217 	ldw	ra,8(sp)
+    2494:	dec00304 	addi	sp,sp,12
+    2498:	000230c1 	jmpi	230c <_fclose_r.part.0>
+    249c:	0005883a 	mov	r2,zero
+    24a0:	dfc00217 	ldw	ra,8(sp)
+    24a4:	dec00304 	addi	sp,sp,12
     24a8:	f800283a 	ret
-    24ac:	800b883a 	mov	r5,r16
-    24b0:	8809883a 	mov	r4,r17
-    24b4:	00025600 	call	2560 <__sflush_r>
-    24b8:	1025883a 	mov	r18,r2
-    24bc:	80800b17 	ldw	r2,44(r16)
-    24c0:	10000426 	beq	r2,zero,24d4 <_fclose_r+0x78>
-    24c4:	81400717 	ldw	r5,28(r16)
-    24c8:	8809883a 	mov	r4,r17
-    24cc:	103ee83a 	callr	r2
-    24d0:	10001616 	blt	r2,zero,252c <_fclose_r+0xd0>
-    24d4:	8080030b 	ldhu	r2,12(r16)
-    24d8:	1080200c 	andi	r2,r2,128
-    24dc:	1000151e 	bne	r2,zero,2534 <_fclose_r+0xd8>
-    24e0:	81400c17 	ldw	r5,48(r16)
-    24e4:	28000526 	beq	r5,zero,24fc <_fclose_r+0xa0>
-    24e8:	80801004 	addi	r2,r16,64
-    24ec:	28800226 	beq	r5,r2,24f8 <_fclose_r+0x9c>
-    24f0:	8809883a 	mov	r4,r17
-    24f4:	000292c0 	call	292c <_free_r>
-    24f8:	80000c15 	stw	zero,48(r16)
-    24fc:	81401117 	ldw	r5,68(r16)
-    2500:	28000326 	beq	r5,zero,2510 <_fclose_r+0xb4>
-    2504:	8809883a 	mov	r4,r17
-    2508:	000292c0 	call	292c <_free_r>
-    250c:	80001115 	stw	zero,68(r16)
-    2510:	00008140 	call	814 <__sfp_lock_acquire>
-    2514:	8000030d 	sth	zero,12(r16)
-    2518:	00008180 	call	818 <__sfp_lock_release>
-    251c:	9005883a 	mov	r2,r18
-    2520:	003fdc06 	br	2494 <__alt_data_end+0xfffe2494>
-    2524:	00008040 	call	804 <__sinit>
-    2528:	003fd706 	br	2488 <__alt_data_end+0xfffe2488>
-    252c:	04bfffc4 	movi	r18,-1
-    2530:	003fe806 	br	24d4 <__alt_data_end+0xfffe24d4>
-    2534:	81400417 	ldw	r5,16(r16)
-    2538:	8809883a 	mov	r4,r17
-    253c:	000292c0 	call	292c <_free_r>
-    2540:	003fe706 	br	24e0 <__alt_data_end+0xfffe24e0>
-    2544:	0005883a 	mov	r2,zero
-    2548:	f800283a 	ret
 
-0000254c <fclose>:
-    254c:	00800034 	movhi	r2,0
-    2550:	109ca504 	addi	r2,r2,29332
-    2554:	200b883a 	mov	r5,r4
-    2558:	11000017 	ldw	r4,0(r2)
-    255c:	000245c1 	jmpi	245c <_fclose_r>
+000024ac <__sflush_r>:
+    24ac:	2880030b 	ldhu	r2,12(r5)
+    24b0:	defffb04 	addi	sp,sp,-20
+    24b4:	dcc00315 	stw	r19,12(sp)
+    24b8:	dc000015 	stw	r16,0(sp)
+    24bc:	dfc00415 	stw	ra,16(sp)
+    24c0:	dc800215 	stw	r18,8(sp)
+    24c4:	dc400115 	stw	r17,4(sp)
+    24c8:	10c0020c 	andi	r3,r2,8
+    24cc:	2821883a 	mov	r16,r5
+    24d0:	2027883a 	mov	r19,r4
+    24d4:	18003f1e 	bne	r3,zero,25d4 <__sflush_r+0x128>
+    24d8:	28c00117 	ldw	r3,4(r5)
+    24dc:	10820014 	ori	r2,r2,2048
+    24e0:	2880030d 	sth	r2,12(r5)
+    24e4:	00c0550e 	bge	zero,r3,263c <__sflush_r+0x190>
+    24e8:	82000a17 	ldw	r8,40(r16)
+    24ec:	40003126 	beq	r8,zero,25b4 <__sflush_r+0x108>
+    24f0:	9c400017 	ldw	r17,0(r19)
+    24f4:	1104000c 	andi	r4,r2,4096
+    24f8:	98000015 	stw	zero,0(r19)
+    24fc:	81400717 	ldw	r5,28(r16)
+    2500:	1007883a 	mov	r3,r2
+    2504:	2000521e 	bne	r4,zero,2650 <__sflush_r+0x1a4>
+    2508:	01c00044 	movi	r7,1
+    250c:	000d883a 	mov	r6,zero
+    2510:	9809883a 	mov	r4,r19
+    2514:	403ee83a 	callr	r8
+    2518:	10ffffd8 	cmpnei	r3,r2,-1
+    251c:	18005826 	beq	r3,zero,2680 <__sflush_r+0x1d4>
+    2520:	80c0030b 	ldhu	r3,12(r16)
+    2524:	82000a17 	ldw	r8,40(r16)
+    2528:	81400717 	ldw	r5,28(r16)
+    252c:	18c0010c 	andi	r3,r3,4
+    2530:	18000626 	beq	r3,zero,254c <__sflush_r+0xa0>
+    2534:	81000117 	ldw	r4,4(r16)
+    2538:	80c00c17 	ldw	r3,48(r16)
+    253c:	1105c83a 	sub	r2,r2,r4
+    2540:	18000226 	beq	r3,zero,254c <__sflush_r+0xa0>
+    2544:	80c00f17 	ldw	r3,60(r16)
+    2548:	10c5c83a 	sub	r2,r2,r3
+    254c:	100d883a 	mov	r6,r2
+    2550:	000f883a 	mov	r7,zero
+    2554:	9809883a 	mov	r4,r19
+    2558:	403ee83a 	callr	r8
+    255c:	10ffffd8 	cmpnei	r3,r2,-1
+    2560:	18003d1e 	bne	r3,zero,2658 <__sflush_r+0x1ac>
+    2564:	99000017 	ldw	r4,0(r19)
+    2568:	80c0030b 	ldhu	r3,12(r16)
+    256c:	20004e26 	beq	r4,zero,26a8 <__sflush_r+0x1fc>
+    2570:	21400760 	cmpeqi	r5,r4,29
+    2574:	2800021e 	bne	r5,zero,2580 <__sflush_r+0xd4>
+    2578:	210005a0 	cmpeqi	r4,r4,22
+    257c:	20002c26 	beq	r4,zero,2630 <__sflush_r+0x184>
+    2580:	80800417 	ldw	r2,16(r16)
+    2584:	18fdffcc 	andi	r3,r3,63487
+    2588:	80c0030d 	sth	r3,12(r16)
+    258c:	80000115 	stw	zero,4(r16)
+    2590:	80800015 	stw	r2,0(r16)
+    2594:	81400c17 	ldw	r5,48(r16)
+    2598:	9c400015 	stw	r17,0(r19)
+    259c:	28000526 	beq	r5,zero,25b4 <__sflush_r+0x108>
+    25a0:	80801004 	addi	r2,r16,64
+    25a4:	28800226 	beq	r5,r2,25b0 <__sflush_r+0x104>
+    25a8:	9809883a 	mov	r4,r19
+    25ac:	00028d40 	call	28d4 <_free_r>
+    25b0:	80000c15 	stw	zero,48(r16)
+    25b4:	0005883a 	mov	r2,zero
+    25b8:	dfc00417 	ldw	ra,16(sp)
+    25bc:	dcc00317 	ldw	r19,12(sp)
+    25c0:	dc800217 	ldw	r18,8(sp)
+    25c4:	dc400117 	ldw	r17,4(sp)
+    25c8:	dc000017 	ldw	r16,0(sp)
+    25cc:	dec00504 	addi	sp,sp,20
+    25d0:	f800283a 	ret
+    25d4:	2c800417 	ldw	r18,16(r5)
+    25d8:	903ff626 	beq	r18,zero,25b4 <__sflush_r+0x108>
+    25dc:	2c400017 	ldw	r17,0(r5)
+    25e0:	108000cc 	andi	r2,r2,3
+    25e4:	2c800015 	stw	r18,0(r5)
+    25e8:	8ca3c83a 	sub	r17,r17,r18
+    25ec:	1000161e 	bne	r2,zero,2648 <__sflush_r+0x19c>
+    25f0:	28800517 	ldw	r2,20(r5)
+    25f4:	80800215 	stw	r2,8(r16)
+    25f8:	04400316 	blt	zero,r17,2608 <__sflush_r+0x15c>
+    25fc:	003fed06 	br	25b4 <__sflush_r+0x108>
+    2600:	90a5883a 	add	r18,r18,r2
+    2604:	047feb0e 	bge	zero,r17,25b4 <__sflush_r+0x108>
+    2608:	80800917 	ldw	r2,36(r16)
+    260c:	81400717 	ldw	r5,28(r16)
+    2610:	880f883a 	mov	r7,r17
+    2614:	900d883a 	mov	r6,r18
+    2618:	9809883a 	mov	r4,r19
+    261c:	103ee83a 	callr	r2
+    2620:	88a3c83a 	sub	r17,r17,r2
+    2624:	00bff616 	blt	zero,r2,2600 <__sflush_r+0x154>
+    2628:	80c0030b 	ldhu	r3,12(r16)
+    262c:	00bfffc4 	movi	r2,-1
+    2630:	18c01014 	ori	r3,r3,64
+    2634:	80c0030d 	sth	r3,12(r16)
+    2638:	003fdf06 	br	25b8 <__sflush_r+0x10c>
+    263c:	28c00f17 	ldw	r3,60(r5)
+    2640:	00ffa916 	blt	zero,r3,24e8 <__sflush_r+0x3c>
+    2644:	003fdb06 	br	25b4 <__sflush_r+0x108>
+    2648:	0005883a 	mov	r2,zero
+    264c:	003fe906 	br	25f4 <__sflush_r+0x148>
+    2650:	80801417 	ldw	r2,80(r16)
+    2654:	003fb506 	br	252c <__sflush_r+0x80>
+    2658:	80c0030b 	ldhu	r3,12(r16)
+    265c:	81000417 	ldw	r4,16(r16)
+    2660:	80000115 	stw	zero,4(r16)
+    2664:	197dffcc 	andi	r5,r3,63487
+    2668:	8140030d 	sth	r5,12(r16)
+    266c:	81000015 	stw	r4,0(r16)
+    2670:	18c4000c 	andi	r3,r3,4096
+    2674:	183fc726 	beq	r3,zero,2594 <__sflush_r+0xe8>
+    2678:	80801415 	stw	r2,80(r16)
+    267c:	003fc506 	br	2594 <__sflush_r+0xe8>
+    2680:	98c00017 	ldw	r3,0(r19)
+    2684:	183fa626 	beq	r3,zero,2520 <__sflush_r+0x74>
+    2688:	19000760 	cmpeqi	r4,r3,29
+    268c:	20000e1e 	bne	r4,zero,26c8 <__sflush_r+0x21c>
+    2690:	18c00598 	cmpnei	r3,r3,22
+    2694:	18000c26 	beq	r3,zero,26c8 <__sflush_r+0x21c>
+    2698:	80c0030b 	ldhu	r3,12(r16)
+    269c:	18c01014 	ori	r3,r3,64
+    26a0:	80c0030d 	sth	r3,12(r16)
+    26a4:	003fc406 	br	25b8 <__sflush_r+0x10c>
+    26a8:	81000417 	ldw	r4,16(r16)
+    26ac:	197dffcc 	andi	r5,r3,63487
+    26b0:	8140030d 	sth	r5,12(r16)
+    26b4:	80000115 	stw	zero,4(r16)
+    26b8:	81000015 	stw	r4,0(r16)
+    26bc:	18c4000c 	andi	r3,r3,4096
+    26c0:	183fb426 	beq	r3,zero,2594 <__sflush_r+0xe8>
+    26c4:	003fec06 	br	2678 <__sflush_r+0x1cc>
+    26c8:	9c400015 	stw	r17,0(r19)
+    26cc:	0005883a 	mov	r2,zero
+    26d0:	003fb906 	br	25b8 <__sflush_r+0x10c>
 
-00002560 <__sflush_r>:
-    2560:	2880030b 	ldhu	r2,12(r5)
-    2564:	defffb04 	addi	sp,sp,-20
-    2568:	dcc00315 	stw	r19,12(sp)
-    256c:	dc400115 	stw	r17,4(sp)
-    2570:	dfc00415 	stw	ra,16(sp)
-    2574:	dc800215 	stw	r18,8(sp)
-    2578:	dc000015 	stw	r16,0(sp)
-    257c:	10c0020c 	andi	r3,r2,8
-    2580:	2823883a 	mov	r17,r5
-    2584:	2027883a 	mov	r19,r4
-    2588:	1800311e 	bne	r3,zero,2650 <__sflush_r+0xf0>
-    258c:	28c00117 	ldw	r3,4(r5)
-    2590:	10820014 	ori	r2,r2,2048
-    2594:	2880030d 	sth	r2,12(r5)
-    2598:	00c04b0e 	bge	zero,r3,26c8 <__sflush_r+0x168>
-    259c:	8a000a17 	ldw	r8,40(r17)
-    25a0:	40002326 	beq	r8,zero,2630 <__sflush_r+0xd0>
-    25a4:	9c000017 	ldw	r16,0(r19)
-    25a8:	10c4000c 	andi	r3,r2,4096
-    25ac:	98000015 	stw	zero,0(r19)
-    25b0:	18004826 	beq	r3,zero,26d4 <__sflush_r+0x174>
-    25b4:	89801417 	ldw	r6,80(r17)
-    25b8:	10c0010c 	andi	r3,r2,4
-    25bc:	18000626 	beq	r3,zero,25d8 <__sflush_r+0x78>
-    25c0:	88c00117 	ldw	r3,4(r17)
-    25c4:	88800c17 	ldw	r2,48(r17)
-    25c8:	30cdc83a 	sub	r6,r6,r3
-    25cc:	10000226 	beq	r2,zero,25d8 <__sflush_r+0x78>
-    25d0:	88800f17 	ldw	r2,60(r17)
-    25d4:	308dc83a 	sub	r6,r6,r2
-    25d8:	89400717 	ldw	r5,28(r17)
-    25dc:	000f883a 	mov	r7,zero
-    25e0:	9809883a 	mov	r4,r19
-    25e4:	403ee83a 	callr	r8
-    25e8:	00ffffc4 	movi	r3,-1
-    25ec:	10c04426 	beq	r2,r3,2700 <__sflush_r+0x1a0>
-    25f0:	88c0030b 	ldhu	r3,12(r17)
-    25f4:	89000417 	ldw	r4,16(r17)
-    25f8:	88000115 	stw	zero,4(r17)
-    25fc:	197dffcc 	andi	r5,r3,63487
-    2600:	8940030d 	sth	r5,12(r17)
-    2604:	89000015 	stw	r4,0(r17)
-    2608:	18c4000c 	andi	r3,r3,4096
-    260c:	18002c1e 	bne	r3,zero,26c0 <__sflush_r+0x160>
-    2610:	89400c17 	ldw	r5,48(r17)
-    2614:	9c000015 	stw	r16,0(r19)
-    2618:	28000526 	beq	r5,zero,2630 <__sflush_r+0xd0>
-    261c:	88801004 	addi	r2,r17,64
-    2620:	28800226 	beq	r5,r2,262c <__sflush_r+0xcc>
-    2624:	9809883a 	mov	r4,r19
-    2628:	000292c0 	call	292c <_free_r>
-    262c:	88000c15 	stw	zero,48(r17)
-    2630:	0005883a 	mov	r2,zero
-    2634:	dfc00417 	ldw	ra,16(sp)
-    2638:	dcc00317 	ldw	r19,12(sp)
-    263c:	dc800217 	ldw	r18,8(sp)
-    2640:	dc400117 	ldw	r17,4(sp)
-    2644:	dc000017 	ldw	r16,0(sp)
-    2648:	dec00504 	addi	sp,sp,20
-    264c:	f800283a 	ret
-    2650:	2c800417 	ldw	r18,16(r5)
-    2654:	903ff626 	beq	r18,zero,2630 <__alt_data_end+0xfffe2630>
-    2658:	2c000017 	ldw	r16,0(r5)
-    265c:	108000cc 	andi	r2,r2,3
-    2660:	2c800015 	stw	r18,0(r5)
-    2664:	84a1c83a 	sub	r16,r16,r18
-    2668:	1000131e 	bne	r2,zero,26b8 <__sflush_r+0x158>
-    266c:	28800517 	ldw	r2,20(r5)
-    2670:	88800215 	stw	r2,8(r17)
-    2674:	04000316 	blt	zero,r16,2684 <__sflush_r+0x124>
-    2678:	003fed06 	br	2630 <__alt_data_end+0xfffe2630>
-    267c:	90a5883a 	add	r18,r18,r2
-    2680:	043feb0e 	bge	zero,r16,2630 <__alt_data_end+0xfffe2630>
-    2684:	88800917 	ldw	r2,36(r17)
-    2688:	89400717 	ldw	r5,28(r17)
-    268c:	800f883a 	mov	r7,r16
-    2690:	900d883a 	mov	r6,r18
-    2694:	9809883a 	mov	r4,r19
-    2698:	103ee83a 	callr	r2
-    269c:	80a1c83a 	sub	r16,r16,r2
-    26a0:	00bff616 	blt	zero,r2,267c <__alt_data_end+0xfffe267c>
-    26a4:	88c0030b 	ldhu	r3,12(r17)
-    26a8:	00bfffc4 	movi	r2,-1
-    26ac:	18c01014 	ori	r3,r3,64
-    26b0:	88c0030d 	sth	r3,12(r17)
-    26b4:	003fdf06 	br	2634 <__alt_data_end+0xfffe2634>
-    26b8:	0005883a 	mov	r2,zero
-    26bc:	003fec06 	br	2670 <__alt_data_end+0xfffe2670>
-    26c0:	88801415 	stw	r2,80(r17)
-    26c4:	003fd206 	br	2610 <__alt_data_end+0xfffe2610>
-    26c8:	28c00f17 	ldw	r3,60(r5)
-    26cc:	00ffb316 	blt	zero,r3,259c <__alt_data_end+0xfffe259c>
-    26d0:	003fd706 	br	2630 <__alt_data_end+0xfffe2630>
-    26d4:	89400717 	ldw	r5,28(r17)
-    26d8:	000d883a 	mov	r6,zero
-    26dc:	01c00044 	movi	r7,1
-    26e0:	9809883a 	mov	r4,r19
-    26e4:	403ee83a 	callr	r8
-    26e8:	100d883a 	mov	r6,r2
-    26ec:	00bfffc4 	movi	r2,-1
-    26f0:	30801426 	beq	r6,r2,2744 <__sflush_r+0x1e4>
-    26f4:	8880030b 	ldhu	r2,12(r17)
-    26f8:	8a000a17 	ldw	r8,40(r17)
-    26fc:	003fae06 	br	25b8 <__alt_data_end+0xfffe25b8>
-    2700:	98c00017 	ldw	r3,0(r19)
-    2704:	183fba26 	beq	r3,zero,25f0 <__alt_data_end+0xfffe25f0>
-    2708:	01000744 	movi	r4,29
-    270c:	19000626 	beq	r3,r4,2728 <__sflush_r+0x1c8>
-    2710:	01000584 	movi	r4,22
-    2714:	19000426 	beq	r3,r4,2728 <__sflush_r+0x1c8>
-    2718:	88c0030b 	ldhu	r3,12(r17)
-    271c:	18c01014 	ori	r3,r3,64
-    2720:	88c0030d 	sth	r3,12(r17)
-    2724:	003fc306 	br	2634 <__alt_data_end+0xfffe2634>
-    2728:	8880030b 	ldhu	r2,12(r17)
-    272c:	88c00417 	ldw	r3,16(r17)
-    2730:	88000115 	stw	zero,4(r17)
-    2734:	10bdffcc 	andi	r2,r2,63487
-    2738:	8880030d 	sth	r2,12(r17)
-    273c:	88c00015 	stw	r3,0(r17)
-    2740:	003fb306 	br	2610 <__alt_data_end+0xfffe2610>
-    2744:	98800017 	ldw	r2,0(r19)
-    2748:	103fea26 	beq	r2,zero,26f4 <__alt_data_end+0xfffe26f4>
-    274c:	00c00744 	movi	r3,29
-    2750:	10c00226 	beq	r2,r3,275c <__sflush_r+0x1fc>
-    2754:	00c00584 	movi	r3,22
-    2758:	10c0031e 	bne	r2,r3,2768 <__sflush_r+0x208>
-    275c:	9c000015 	stw	r16,0(r19)
-    2760:	0005883a 	mov	r2,zero
-    2764:	003fb306 	br	2634 <__alt_data_end+0xfffe2634>
-    2768:	88c0030b 	ldhu	r3,12(r17)
-    276c:	3005883a 	mov	r2,r6
-    2770:	18c01014 	ori	r3,r3,64
-    2774:	88c0030d 	sth	r3,12(r17)
-    2778:	003fae06 	br	2634 <__alt_data_end+0xfffe2634>
+000026d4 <_fflush_r>:
+    26d4:	defffd04 	addi	sp,sp,-12
+    26d8:	dc000115 	stw	r16,4(sp)
+    26dc:	dfc00215 	stw	ra,8(sp)
+    26e0:	2021883a 	mov	r16,r4
+    26e4:	20000226 	beq	r4,zero,26f0 <_fflush_r+0x1c>
+    26e8:	20800e17 	ldw	r2,56(r4)
+    26ec:	10000726 	beq	r2,zero,270c <_fflush_r+0x38>
+    26f0:	2880030f 	ldh	r2,12(r5)
+    26f4:	10000a1e 	bne	r2,zero,2720 <_fflush_r+0x4c>
+    26f8:	0005883a 	mov	r2,zero
+    26fc:	dfc00217 	ldw	ra,8(sp)
+    2700:	dc000117 	ldw	r16,4(sp)
+    2704:	dec00304 	addi	sp,sp,12
+    2708:	f800283a 	ret
+    270c:	d9400015 	stw	r5,0(sp)
+    2710:	00007d40 	call	7d4 <__sinit>
+    2714:	d9400017 	ldw	r5,0(sp)
+    2718:	2880030f 	ldh	r2,12(r5)
+    271c:	103ff626 	beq	r2,zero,26f8 <_fflush_r+0x24>
+    2720:	8009883a 	mov	r4,r16
+    2724:	dfc00217 	ldw	ra,8(sp)
+    2728:	dc000117 	ldw	r16,4(sp)
+    272c:	dec00304 	addi	sp,sp,12
+    2730:	00024ac1 	jmpi	24ac <__sflush_r>
 
-0000277c <_fflush_r>:
-    277c:	defffd04 	addi	sp,sp,-12
-    2780:	dc000115 	stw	r16,4(sp)
-    2784:	dfc00215 	stw	ra,8(sp)
-    2788:	2021883a 	mov	r16,r4
-    278c:	20000226 	beq	r4,zero,2798 <_fflush_r+0x1c>
-    2790:	20800e17 	ldw	r2,56(r4)
-    2794:	10000c26 	beq	r2,zero,27c8 <_fflush_r+0x4c>
-    2798:	2880030f 	ldh	r2,12(r5)
-    279c:	1000051e 	bne	r2,zero,27b4 <_fflush_r+0x38>
-    27a0:	0005883a 	mov	r2,zero
-    27a4:	dfc00217 	ldw	ra,8(sp)
-    27a8:	dc000117 	ldw	r16,4(sp)
-    27ac:	dec00304 	addi	sp,sp,12
-    27b0:	f800283a 	ret
-    27b4:	8009883a 	mov	r4,r16
-    27b8:	dfc00217 	ldw	ra,8(sp)
-    27bc:	dc000117 	ldw	r16,4(sp)
-    27c0:	dec00304 	addi	sp,sp,12
-    27c4:	00025601 	jmpi	2560 <__sflush_r>
-    27c8:	d9400015 	stw	r5,0(sp)
-    27cc:	00008040 	call	804 <__sinit>
-    27d0:	d9400017 	ldw	r5,0(sp)
-    27d4:	003ff006 	br	2798 <__alt_data_end+0xfffe2798>
+00002734 <fflush>:
+    2734:	20001726 	beq	r4,zero,2794 <fflush+0x60>
+    2738:	00800034 	movhi	r2,0
+    273c:	200b883a 	mov	r5,r4
+    2740:	111c7917 	ldw	r4,29156(r2)
+    2744:	20000226 	beq	r4,zero,2750 <fflush+0x1c>
+    2748:	20800e17 	ldw	r2,56(r4)
+    274c:	10000526 	beq	r2,zero,2764 <fflush+0x30>
+    2750:	2880030f 	ldh	r2,12(r5)
+    2754:	1000021e 	bne	r2,zero,2760 <fflush+0x2c>
+    2758:	0005883a 	mov	r2,zero
+    275c:	f800283a 	ret
+    2760:	00024ac1 	jmpi	24ac <__sflush_r>
+    2764:	defffd04 	addi	sp,sp,-12
+    2768:	d9400115 	stw	r5,4(sp)
+    276c:	d9000015 	stw	r4,0(sp)
+    2770:	dfc00215 	stw	ra,8(sp)
+    2774:	00007d40 	call	7d4 <__sinit>
+    2778:	d9400117 	ldw	r5,4(sp)
+    277c:	d9000017 	ldw	r4,0(sp)
+    2780:	2880030f 	ldh	r2,12(r5)
+    2784:	10000826 	beq	r2,zero,27a8 <fflush+0x74>
+    2788:	dfc00217 	ldw	ra,8(sp)
+    278c:	dec00304 	addi	sp,sp,12
+    2790:	00024ac1 	jmpi	24ac <__sflush_r>
+    2794:	00800034 	movhi	r2,0
+    2798:	111c7817 	ldw	r4,29152(r2)
+    279c:	01400034 	movhi	r5,0
+    27a0:	2949b504 	addi	r5,r5,9940
+    27a4:	0000d7c1 	jmpi	d7c <_fwalk_reent>
+    27a8:	0005883a 	mov	r2,zero
+    27ac:	dfc00217 	ldw	ra,8(sp)
+    27b0:	dec00304 	addi	sp,sp,12
+    27b4:	f800283a 	ret
 
-000027d8 <fflush>:
-    27d8:	20000526 	beq	r4,zero,27f0 <fflush+0x18>
-    27dc:	00800034 	movhi	r2,0
-    27e0:	109ca504 	addi	r2,r2,29332
-    27e4:	200b883a 	mov	r5,r4
-    27e8:	11000017 	ldw	r4,0(r2)
-    27ec:	000277c1 	jmpi	277c <_fflush_r>
-    27f0:	00800034 	movhi	r2,0
-    27f4:	109ca404 	addi	r2,r2,29328
-    27f8:	11000017 	ldw	r4,0(r2)
-    27fc:	01400034 	movhi	r5,0
-    2800:	2949df04 	addi	r5,r5,10108
-    2804:	0000de01 	jmpi	de0 <_fwalk_reent>
-
-00002808 <_malloc_trim_r>:
-    2808:	defffb04 	addi	sp,sp,-20
-    280c:	dcc00315 	stw	r19,12(sp)
-    2810:	04c00034 	movhi	r19,0
-    2814:	dc800215 	stw	r18,8(sp)
-    2818:	dc400115 	stw	r17,4(sp)
-    281c:	dc000015 	stw	r16,0(sp)
-    2820:	dfc00415 	stw	ra,16(sp)
-    2824:	2821883a 	mov	r16,r5
-    2828:	9cd72004 	addi	r19,r19,23680
-    282c:	2025883a 	mov	r18,r4
-    2830:	000361c0 	call	361c <__malloc_lock>
-    2834:	98800217 	ldw	r2,8(r19)
-    2838:	14400117 	ldw	r17,4(r2)
-    283c:	00bfff04 	movi	r2,-4
-    2840:	88a2703a 	and	r17,r17,r2
-    2844:	8c21c83a 	sub	r16,r17,r16
-    2848:	8403fbc4 	addi	r16,r16,4079
-    284c:	8020d33a 	srli	r16,r16,12
-    2850:	0083ffc4 	movi	r2,4095
-    2854:	843fffc4 	addi	r16,r16,-1
-    2858:	8020933a 	slli	r16,r16,12
-    285c:	1400060e 	bge	r2,r16,2878 <_malloc_trim_r+0x70>
-    2860:	000b883a 	mov	r5,zero
-    2864:	9009883a 	mov	r4,r18
-    2868:	00020c40 	call	20c4 <_sbrk_r>
+000027b8 <_malloc_trim_r>:
+    27b8:	defffb04 	addi	sp,sp,-20
+    27bc:	dcc00315 	stw	r19,12(sp)
+    27c0:	04c00034 	movhi	r19,0
+    27c4:	dc800215 	stw	r18,8(sp)
+    27c8:	dc400115 	stw	r17,4(sp)
+    27cc:	dc000015 	stw	r16,0(sp)
+    27d0:	dfc00415 	stw	ra,16(sp)
+    27d4:	2821883a 	mov	r16,r5
+    27d8:	9cd6f404 	addi	r19,r19,23504
+    27dc:	2025883a 	mov	r18,r4
+    27e0:	000365c0 	call	365c <__malloc_lock>
+    27e4:	98800217 	ldw	r2,8(r19)
+    27e8:	14400117 	ldw	r17,4(r2)
+    27ec:	00bfff04 	movi	r2,-4
+    27f0:	88a2703a 	and	r17,r17,r2
+    27f4:	8c21c83a 	sub	r16,r17,r16
+    27f8:	8403fbc4 	addi	r16,r16,4079
+    27fc:	8020d33a 	srli	r16,r16,12
+    2800:	843fffc4 	addi	r16,r16,-1
+    2804:	8020933a 	slli	r16,r16,12
+    2808:	80840008 	cmpgei	r2,r16,4096
+    280c:	10000626 	beq	r2,zero,2828 <_malloc_trim_r+0x70>
+    2810:	000b883a 	mov	r5,zero
+    2814:	9009883a 	mov	r4,r18
+    2818:	0001f540 	call	1f54 <_sbrk_r>
+    281c:	98c00217 	ldw	r3,8(r19)
+    2820:	1c47883a 	add	r3,r3,r17
+    2824:	10c00a26 	beq	r2,r3,2850 <_malloc_trim_r+0x98>
+    2828:	9009883a 	mov	r4,r18
+    282c:	00036800 	call	3680 <__malloc_unlock>
+    2830:	0005883a 	mov	r2,zero
+    2834:	dfc00417 	ldw	ra,16(sp)
+    2838:	dcc00317 	ldw	r19,12(sp)
+    283c:	dc800217 	ldw	r18,8(sp)
+    2840:	dc400117 	ldw	r17,4(sp)
+    2844:	dc000017 	ldw	r16,0(sp)
+    2848:	dec00504 	addi	sp,sp,20
+    284c:	f800283a 	ret
+    2850:	040bc83a 	sub	r5,zero,r16
+    2854:	9009883a 	mov	r4,r18
+    2858:	0001f540 	call	1f54 <_sbrk_r>
+    285c:	10bfffd8 	cmpnei	r2,r2,-1
+    2860:	10000d26 	beq	r2,zero,2898 <_malloc_trim_r+0xe0>
+    2864:	00800034 	movhi	r2,0
+    2868:	109c9117 	ldw	r2,29252(r2)
     286c:	98c00217 	ldw	r3,8(r19)
-    2870:	1c47883a 	add	r3,r3,r17
-    2874:	10c00a26 	beq	r2,r3,28a0 <_malloc_trim_r+0x98>
-    2878:	9009883a 	mov	r4,r18
-    287c:	00036400 	call	3640 <__malloc_unlock>
-    2880:	0005883a 	mov	r2,zero
-    2884:	dfc00417 	ldw	ra,16(sp)
-    2888:	dcc00317 	ldw	r19,12(sp)
-    288c:	dc800217 	ldw	r18,8(sp)
-    2890:	dc400117 	ldw	r17,4(sp)
-    2894:	dc000017 	ldw	r16,0(sp)
-    2898:	dec00504 	addi	sp,sp,20
-    289c:	f800283a 	ret
-    28a0:	040bc83a 	sub	r5,zero,r16
-    28a4:	9009883a 	mov	r4,r18
-    28a8:	00020c40 	call	20c4 <_sbrk_r>
-    28ac:	00ffffc4 	movi	r3,-1
-    28b0:	10c00d26 	beq	r2,r3,28e8 <_malloc_trim_r+0xe0>
-    28b4:	00c00034 	movhi	r3,0
-    28b8:	18dcbd04 	addi	r3,r3,29428
-    28bc:	18800017 	ldw	r2,0(r3)
-    28c0:	99000217 	ldw	r4,8(r19)
-    28c4:	8c23c83a 	sub	r17,r17,r16
-    28c8:	8c400054 	ori	r17,r17,1
-    28cc:	1421c83a 	sub	r16,r2,r16
-    28d0:	24400115 	stw	r17,4(r4)
-    28d4:	9009883a 	mov	r4,r18
-    28d8:	1c000015 	stw	r16,0(r3)
-    28dc:	00036400 	call	3640 <__malloc_unlock>
-    28e0:	00800044 	movi	r2,1
-    28e4:	003fe706 	br	2884 <__alt_data_end+0xfffe2884>
-    28e8:	000b883a 	mov	r5,zero
-    28ec:	9009883a 	mov	r4,r18
-    28f0:	00020c40 	call	20c4 <_sbrk_r>
-    28f4:	99000217 	ldw	r4,8(r19)
-    28f8:	014003c4 	movi	r5,15
-    28fc:	1107c83a 	sub	r3,r2,r4
-    2900:	28ffdd0e 	bge	r5,r3,2878 <__alt_data_end+0xfffe2878>
-    2904:	01400034 	movhi	r5,0
-    2908:	295ca604 	addi	r5,r5,29336
-    290c:	29400017 	ldw	r5,0(r5)
-    2910:	18c00054 	ori	r3,r3,1
-    2914:	20c00115 	stw	r3,4(r4)
-    2918:	00c00034 	movhi	r3,0
-    291c:	1145c83a 	sub	r2,r2,r5
-    2920:	18dcbd04 	addi	r3,r3,29428
-    2924:	18800015 	stw	r2,0(r3)
-    2928:	003fd306 	br	2878 <__alt_data_end+0xfffe2878>
+    2870:	8c23c83a 	sub	r17,r17,r16
+    2874:	8c400054 	ori	r17,r17,1
+    2878:	1421c83a 	sub	r16,r2,r16
+    287c:	1c400115 	stw	r17,4(r3)
+    2880:	00800034 	movhi	r2,0
+    2884:	9009883a 	mov	r4,r18
+    2888:	141c9115 	stw	r16,29252(r2)
+    288c:	00036800 	call	3680 <__malloc_unlock>
+    2890:	00800044 	movi	r2,1
+    2894:	003fe706 	br	2834 <_malloc_trim_r+0x7c>
+    2898:	000b883a 	mov	r5,zero
+    289c:	9009883a 	mov	r4,r18
+    28a0:	0001f540 	call	1f54 <_sbrk_r>
+    28a4:	99000217 	ldw	r4,8(r19)
+    28a8:	1107c83a 	sub	r3,r2,r4
+    28ac:	19400410 	cmplti	r5,r3,16
+    28b0:	283fdd1e 	bne	r5,zero,2828 <_malloc_trim_r+0x70>
+    28b4:	01400034 	movhi	r5,0
+    28b8:	295c7a17 	ldw	r5,29160(r5)
+    28bc:	18c00054 	ori	r3,r3,1
+    28c0:	20c00115 	stw	r3,4(r4)
+    28c4:	1145c83a 	sub	r2,r2,r5
+    28c8:	01400034 	movhi	r5,0
+    28cc:	289c9115 	stw	r2,29252(r5)
+    28d0:	003fd506 	br	2828 <_malloc_trim_r+0x70>
 
-0000292c <_free_r>:
-    292c:	28004126 	beq	r5,zero,2a34 <_free_r+0x108>
-    2930:	defffd04 	addi	sp,sp,-12
-    2934:	dc400115 	stw	r17,4(sp)
-    2938:	dc000015 	stw	r16,0(sp)
-    293c:	2023883a 	mov	r17,r4
-    2940:	2821883a 	mov	r16,r5
-    2944:	dfc00215 	stw	ra,8(sp)
-    2948:	000361c0 	call	361c <__malloc_lock>
-    294c:	81ffff17 	ldw	r7,-4(r16)
-    2950:	00bfff84 	movi	r2,-2
-    2954:	01000034 	movhi	r4,0
-    2958:	81bffe04 	addi	r6,r16,-8
-    295c:	3884703a 	and	r2,r7,r2
-    2960:	21172004 	addi	r4,r4,23680
-    2964:	308b883a 	add	r5,r6,r2
-    2968:	2a400117 	ldw	r9,4(r5)
-    296c:	22000217 	ldw	r8,8(r4)
-    2970:	00ffff04 	movi	r3,-4
-    2974:	48c6703a 	and	r3,r9,r3
-    2978:	2a005726 	beq	r5,r8,2ad8 <_free_r+0x1ac>
-    297c:	28c00115 	stw	r3,4(r5)
-    2980:	39c0004c 	andi	r7,r7,1
-    2984:	3800091e 	bne	r7,zero,29ac <_free_r+0x80>
-    2988:	823ffe17 	ldw	r8,-8(r16)
-    298c:	22400204 	addi	r9,r4,8
-    2990:	320dc83a 	sub	r6,r6,r8
-    2994:	31c00217 	ldw	r7,8(r6)
-    2998:	1205883a 	add	r2,r2,r8
-    299c:	3a406526 	beq	r7,r9,2b34 <_free_r+0x208>
-    29a0:	32000317 	ldw	r8,12(r6)
-    29a4:	3a000315 	stw	r8,12(r7)
-    29a8:	41c00215 	stw	r7,8(r8)
-    29ac:	28cf883a 	add	r7,r5,r3
-    29b0:	39c00117 	ldw	r7,4(r7)
-    29b4:	39c0004c 	andi	r7,r7,1
-    29b8:	38003a26 	beq	r7,zero,2aa4 <_free_r+0x178>
-    29bc:	10c00054 	ori	r3,r2,1
-    29c0:	30c00115 	stw	r3,4(r6)
-    29c4:	3087883a 	add	r3,r6,r2
-    29c8:	18800015 	stw	r2,0(r3)
-    29cc:	00c07fc4 	movi	r3,511
-    29d0:	18801936 	bltu	r3,r2,2a38 <_free_r+0x10c>
-    29d4:	1004d0fa 	srli	r2,r2,3
-    29d8:	01c00044 	movi	r7,1
-    29dc:	21400117 	ldw	r5,4(r4)
-    29e0:	10c00044 	addi	r3,r2,1
-    29e4:	18c7883a 	add	r3,r3,r3
-    29e8:	1005d0ba 	srai	r2,r2,2
-    29ec:	18c7883a 	add	r3,r3,r3
-    29f0:	18c7883a 	add	r3,r3,r3
-    29f4:	1907883a 	add	r3,r3,r4
-    29f8:	3884983a 	sll	r2,r7,r2
-    29fc:	19c00017 	ldw	r7,0(r3)
-    2a00:	1a3ffe04 	addi	r8,r3,-8
-    2a04:	1144b03a 	or	r2,r2,r5
-    2a08:	32000315 	stw	r8,12(r6)
-    2a0c:	31c00215 	stw	r7,8(r6)
-    2a10:	20800115 	stw	r2,4(r4)
-    2a14:	19800015 	stw	r6,0(r3)
-    2a18:	39800315 	stw	r6,12(r7)
-    2a1c:	8809883a 	mov	r4,r17
-    2a20:	dfc00217 	ldw	ra,8(sp)
-    2a24:	dc400117 	ldw	r17,4(sp)
-    2a28:	dc000017 	ldw	r16,0(sp)
-    2a2c:	dec00304 	addi	sp,sp,12
-    2a30:	00036401 	jmpi	3640 <__malloc_unlock>
-    2a34:	f800283a 	ret
-    2a38:	100ad27a 	srli	r5,r2,9
-    2a3c:	00c00104 	movi	r3,4
-    2a40:	19404a36 	bltu	r3,r5,2b6c <_free_r+0x240>
-    2a44:	100ad1ba 	srli	r5,r2,6
-    2a48:	28c00e44 	addi	r3,r5,57
-    2a4c:	18c7883a 	add	r3,r3,r3
-    2a50:	29400e04 	addi	r5,r5,56
-    2a54:	18c7883a 	add	r3,r3,r3
-    2a58:	18c7883a 	add	r3,r3,r3
-    2a5c:	1909883a 	add	r4,r3,r4
-    2a60:	20c00017 	ldw	r3,0(r4)
-    2a64:	01c00034 	movhi	r7,0
-    2a68:	213ffe04 	addi	r4,r4,-8
-    2a6c:	39d72004 	addi	r7,r7,23680
-    2a70:	20c04426 	beq	r4,r3,2b84 <_free_r+0x258>
-    2a74:	01ffff04 	movi	r7,-4
-    2a78:	19400117 	ldw	r5,4(r3)
-    2a7c:	29ca703a 	and	r5,r5,r7
-    2a80:	1140022e 	bgeu	r2,r5,2a8c <_free_r+0x160>
-    2a84:	18c00217 	ldw	r3,8(r3)
-    2a88:	20fffb1e 	bne	r4,r3,2a78 <__alt_data_end+0xfffe2a78>
-    2a8c:	19000317 	ldw	r4,12(r3)
-    2a90:	31000315 	stw	r4,12(r6)
-    2a94:	30c00215 	stw	r3,8(r6)
-    2a98:	21800215 	stw	r6,8(r4)
-    2a9c:	19800315 	stw	r6,12(r3)
-    2aa0:	003fde06 	br	2a1c <__alt_data_end+0xfffe2a1c>
-    2aa4:	29c00217 	ldw	r7,8(r5)
-    2aa8:	10c5883a 	add	r2,r2,r3
-    2aac:	00c00034 	movhi	r3,0
-    2ab0:	18d72204 	addi	r3,r3,23688
-    2ab4:	38c03b26 	beq	r7,r3,2ba4 <_free_r+0x278>
-    2ab8:	2a000317 	ldw	r8,12(r5)
-    2abc:	11400054 	ori	r5,r2,1
-    2ac0:	3087883a 	add	r3,r6,r2
-    2ac4:	3a000315 	stw	r8,12(r7)
-    2ac8:	41c00215 	stw	r7,8(r8)
-    2acc:	31400115 	stw	r5,4(r6)
-    2ad0:	18800015 	stw	r2,0(r3)
-    2ad4:	003fbd06 	br	29cc <__alt_data_end+0xfffe29cc>
-    2ad8:	39c0004c 	andi	r7,r7,1
-    2adc:	10c5883a 	add	r2,r2,r3
-    2ae0:	3800071e 	bne	r7,zero,2b00 <_free_r+0x1d4>
-    2ae4:	81fffe17 	ldw	r7,-8(r16)
-    2ae8:	31cdc83a 	sub	r6,r6,r7
-    2aec:	30c00317 	ldw	r3,12(r6)
-    2af0:	31400217 	ldw	r5,8(r6)
-    2af4:	11c5883a 	add	r2,r2,r7
-    2af8:	28c00315 	stw	r3,12(r5)
-    2afc:	19400215 	stw	r5,8(r3)
-    2b00:	10c00054 	ori	r3,r2,1
-    2b04:	30c00115 	stw	r3,4(r6)
-    2b08:	00c00034 	movhi	r3,0
-    2b0c:	18dca704 	addi	r3,r3,29340
-    2b10:	18c00017 	ldw	r3,0(r3)
-    2b14:	21800215 	stw	r6,8(r4)
-    2b18:	10ffc036 	bltu	r2,r3,2a1c <__alt_data_end+0xfffe2a1c>
-    2b1c:	00800034 	movhi	r2,0
-    2b20:	109cb404 	addi	r2,r2,29392
-    2b24:	11400017 	ldw	r5,0(r2)
-    2b28:	8809883a 	mov	r4,r17
-    2b2c:	00028080 	call	2808 <_malloc_trim_r>
-    2b30:	003fba06 	br	2a1c <__alt_data_end+0xfffe2a1c>
-    2b34:	28c9883a 	add	r4,r5,r3
-    2b38:	21000117 	ldw	r4,4(r4)
-    2b3c:	2100004c 	andi	r4,r4,1
-    2b40:	2000391e 	bne	r4,zero,2c28 <_free_r+0x2fc>
-    2b44:	29c00217 	ldw	r7,8(r5)
-    2b48:	29000317 	ldw	r4,12(r5)
-    2b4c:	1885883a 	add	r2,r3,r2
-    2b50:	10c00054 	ori	r3,r2,1
-    2b54:	39000315 	stw	r4,12(r7)
-    2b58:	21c00215 	stw	r7,8(r4)
-    2b5c:	30c00115 	stw	r3,4(r6)
-    2b60:	308d883a 	add	r6,r6,r2
-    2b64:	30800015 	stw	r2,0(r6)
-    2b68:	003fac06 	br	2a1c <__alt_data_end+0xfffe2a1c>
-    2b6c:	00c00504 	movi	r3,20
-    2b70:	19401536 	bltu	r3,r5,2bc8 <_free_r+0x29c>
-    2b74:	28c01704 	addi	r3,r5,92
-    2b78:	18c7883a 	add	r3,r3,r3
-    2b7c:	294016c4 	addi	r5,r5,91
-    2b80:	003fb406 	br	2a54 <__alt_data_end+0xfffe2a54>
-    2b84:	280bd0ba 	srai	r5,r5,2
-    2b88:	00c00044 	movi	r3,1
-    2b8c:	38800117 	ldw	r2,4(r7)
-    2b90:	194a983a 	sll	r5,r3,r5
-    2b94:	2007883a 	mov	r3,r4
-    2b98:	2884b03a 	or	r2,r5,r2
-    2b9c:	38800115 	stw	r2,4(r7)
-    2ba0:	003fbb06 	br	2a90 <__alt_data_end+0xfffe2a90>
-    2ba4:	21800515 	stw	r6,20(r4)
-    2ba8:	21800415 	stw	r6,16(r4)
-    2bac:	10c00054 	ori	r3,r2,1
-    2bb0:	31c00315 	stw	r7,12(r6)
-    2bb4:	31c00215 	stw	r7,8(r6)
-    2bb8:	30c00115 	stw	r3,4(r6)
-    2bbc:	308d883a 	add	r6,r6,r2
-    2bc0:	30800015 	stw	r2,0(r6)
-    2bc4:	003f9506 	br	2a1c <__alt_data_end+0xfffe2a1c>
-    2bc8:	00c01504 	movi	r3,84
-    2bcc:	19400536 	bltu	r3,r5,2be4 <_free_r+0x2b8>
-    2bd0:	100ad33a 	srli	r5,r2,12
-    2bd4:	28c01bc4 	addi	r3,r5,111
-    2bd8:	18c7883a 	add	r3,r3,r3
-    2bdc:	29401b84 	addi	r5,r5,110
-    2be0:	003f9c06 	br	2a54 <__alt_data_end+0xfffe2a54>
-    2be4:	00c05504 	movi	r3,340
-    2be8:	19400536 	bltu	r3,r5,2c00 <_free_r+0x2d4>
-    2bec:	100ad3fa 	srli	r5,r2,15
-    2bf0:	28c01e04 	addi	r3,r5,120
-    2bf4:	18c7883a 	add	r3,r3,r3
-    2bf8:	29401dc4 	addi	r5,r5,119
-    2bfc:	003f9506 	br	2a54 <__alt_data_end+0xfffe2a54>
-    2c00:	00c15504 	movi	r3,1364
-    2c04:	19400536 	bltu	r3,r5,2c1c <_free_r+0x2f0>
-    2c08:	100ad4ba 	srli	r5,r2,18
-    2c0c:	28c01f44 	addi	r3,r5,125
-    2c10:	18c7883a 	add	r3,r3,r3
-    2c14:	29401f04 	addi	r5,r5,124
-    2c18:	003f8e06 	br	2a54 <__alt_data_end+0xfffe2a54>
-    2c1c:	00c03f84 	movi	r3,254
-    2c20:	01401f84 	movi	r5,126
-    2c24:	003f8b06 	br	2a54 <__alt_data_end+0xfffe2a54>
-    2c28:	10c00054 	ori	r3,r2,1
-    2c2c:	30c00115 	stw	r3,4(r6)
-    2c30:	308d883a 	add	r6,r6,r2
-    2c34:	30800015 	stw	r2,0(r6)
-    2c38:	003f7806 	br	2a1c <__alt_data_end+0xfffe2a1c>
+000028d4 <_free_r>:
+    28d4:	28004f26 	beq	r5,zero,2a14 <_free_r+0x140>
+    28d8:	defffd04 	addi	sp,sp,-12
+    28dc:	dc400115 	stw	r17,4(sp)
+    28e0:	dc000015 	stw	r16,0(sp)
+    28e4:	2023883a 	mov	r17,r4
+    28e8:	2821883a 	mov	r16,r5
+    28ec:	dfc00215 	stw	ra,8(sp)
+    28f0:	000365c0 	call	365c <__malloc_lock>
+    28f4:	81ffff17 	ldw	r7,-4(r16)
+    28f8:	00bfff84 	movi	r2,-2
+    28fc:	80fffe04 	addi	r3,r16,-8
+    2900:	3884703a 	and	r2,r7,r2
+    2904:	01000034 	movhi	r4,0
+    2908:	188d883a 	add	r6,r3,r2
+    290c:	2116f404 	addi	r4,r4,23504
+    2910:	31400117 	ldw	r5,4(r6)
+    2914:	22000217 	ldw	r8,8(r4)
+    2918:	027fff04 	movi	r9,-4
+    291c:	2a4a703a 	and	r5,r5,r9
+    2920:	41806426 	beq	r8,r6,2ab4 <_free_r+0x1e0>
+    2924:	31400115 	stw	r5,4(r6)
+    2928:	39c0004c 	andi	r7,r7,1
+    292c:	3151883a 	add	r8,r6,r5
+    2930:	3800281e 	bne	r7,zero,29d4 <_free_r+0x100>
+    2934:	82bffe17 	ldw	r10,-8(r16)
+    2938:	42000117 	ldw	r8,4(r8)
+    293c:	01c00034 	movhi	r7,0
+    2940:	1a87c83a 	sub	r3,r3,r10
+    2944:	1a400217 	ldw	r9,8(r3)
+    2948:	39d6f604 	addi	r7,r7,23512
+    294c:	1285883a 	add	r2,r2,r10
+    2950:	4200004c 	andi	r8,r8,1
+    2954:	49c04c26 	beq	r9,r7,2a88 <_free_r+0x1b4>
+    2958:	1a800317 	ldw	r10,12(r3)
+    295c:	4a800315 	stw	r10,12(r9)
+    2960:	52400215 	stw	r9,8(r10)
+    2964:	40007126 	beq	r8,zero,2b2c <_free_r+0x258>
+    2968:	11400054 	ori	r5,r2,1
+    296c:	19400115 	stw	r5,4(r3)
+    2970:	30800015 	stw	r2,0(r6)
+    2974:	11408028 	cmpgeui	r5,r2,512
+    2978:	28002c1e 	bne	r5,zero,2a2c <_free_r+0x158>
+    297c:	100ad0fa 	srli	r5,r2,3
+    2980:	100cd17a 	srli	r6,r2,5
+    2984:	00800044 	movi	r2,1
+    2988:	29400044 	addi	r5,r5,1
+    298c:	280a90fa 	slli	r5,r5,3
+    2990:	21c00117 	ldw	r7,4(r4)
+    2994:	1184983a 	sll	r2,r2,r6
+    2998:	214b883a 	add	r5,r4,r5
+    299c:	29800017 	ldw	r6,0(r5)
+    29a0:	11c4b03a 	or	r2,r2,r7
+    29a4:	29fffe04 	addi	r7,r5,-8
+    29a8:	19c00315 	stw	r7,12(r3)
+    29ac:	19800215 	stw	r6,8(r3)
+    29b0:	20800115 	stw	r2,4(r4)
+    29b4:	28c00015 	stw	r3,0(r5)
+    29b8:	30c00315 	stw	r3,12(r6)
+    29bc:	8809883a 	mov	r4,r17
+    29c0:	dfc00217 	ldw	ra,8(sp)
+    29c4:	dc400117 	ldw	r17,4(sp)
+    29c8:	dc000017 	ldw	r16,0(sp)
+    29cc:	dec00304 	addi	sp,sp,12
+    29d0:	00036801 	jmpi	3680 <__malloc_unlock>
+    29d4:	41c00117 	ldw	r7,4(r8)
+    29d8:	39c0004c 	andi	r7,r7,1
+    29dc:	38000e1e 	bne	r7,zero,2a18 <_free_r+0x144>
+    29e0:	01c00034 	movhi	r7,0
+    29e4:	1145883a 	add	r2,r2,r5
+    29e8:	39d6f604 	addi	r7,r7,23512
+    29ec:	31400217 	ldw	r5,8(r6)
+    29f0:	12400054 	ori	r9,r2,1
+    29f4:	1891883a 	add	r8,r3,r2
+    29f8:	29c05226 	beq	r5,r7,2b44 <_free_r+0x270>
+    29fc:	31800317 	ldw	r6,12(r6)
+    2a00:	29800315 	stw	r6,12(r5)
+    2a04:	31400215 	stw	r5,8(r6)
+    2a08:	1a400115 	stw	r9,4(r3)
+    2a0c:	40800015 	stw	r2,0(r8)
+    2a10:	003fd806 	br	2974 <_free_r+0xa0>
+    2a14:	f800283a 	ret
+    2a18:	11400054 	ori	r5,r2,1
+    2a1c:	817fff15 	stw	r5,-4(r16)
+    2a20:	30800015 	stw	r2,0(r6)
+    2a24:	11408028 	cmpgeui	r5,r2,512
+    2a28:	283fd426 	beq	r5,zero,297c <_free_r+0xa8>
+    2a2c:	100ad27a 	srli	r5,r2,9
+    2a30:	29800168 	cmpgeui	r6,r5,5
+    2a34:	3000341e 	bne	r6,zero,2b08 <_free_r+0x234>
+    2a38:	100ad1ba 	srli	r5,r2,6
+    2a3c:	29800e44 	addi	r6,r5,57
+    2a40:	300c90fa 	slli	r6,r6,3
+    2a44:	29c00e04 	addi	r7,r5,56
+    2a48:	218d883a 	add	r6,r4,r6
+    2a4c:	31400017 	ldw	r5,0(r6)
+    2a50:	31bffe04 	addi	r6,r6,-8
+    2a54:	31404226 	beq	r6,r5,2b60 <_free_r+0x28c>
+    2a58:	01ffff04 	movi	r7,-4
+    2a5c:	29000117 	ldw	r4,4(r5)
+    2a60:	21c8703a 	and	r4,r4,r7
+    2a64:	1100022e 	bgeu	r2,r4,2a70 <_free_r+0x19c>
+    2a68:	29400217 	ldw	r5,8(r5)
+    2a6c:	317ffb1e 	bne	r6,r5,2a5c <_free_r+0x188>
+    2a70:	29800317 	ldw	r6,12(r5)
+    2a74:	19800315 	stw	r6,12(r3)
+    2a78:	19400215 	stw	r5,8(r3)
+    2a7c:	30c00215 	stw	r3,8(r6)
+    2a80:	28c00315 	stw	r3,12(r5)
+    2a84:	003fcd06 	br	29bc <_free_r+0xe8>
+    2a88:	40004d1e 	bne	r8,zero,2bc0 <_free_r+0x2ec>
+    2a8c:	31000317 	ldw	r4,12(r6)
+    2a90:	31800217 	ldw	r6,8(r6)
+    2a94:	2885883a 	add	r2,r5,r2
+    2a98:	11400054 	ori	r5,r2,1
+    2a9c:	31000315 	stw	r4,12(r6)
+    2aa0:	21800215 	stw	r6,8(r4)
+    2aa4:	19400115 	stw	r5,4(r3)
+    2aa8:	1887883a 	add	r3,r3,r2
+    2aac:	18800015 	stw	r2,0(r3)
+    2ab0:	003fc206 	br	29bc <_free_r+0xe8>
+    2ab4:	39c0004c 	andi	r7,r7,1
+    2ab8:	1145883a 	add	r2,r2,r5
+    2abc:	3800071e 	bne	r7,zero,2adc <_free_r+0x208>
+    2ac0:	81fffe17 	ldw	r7,-8(r16)
+    2ac4:	19c7c83a 	sub	r3,r3,r7
+    2ac8:	19400317 	ldw	r5,12(r3)
+    2acc:	19800217 	ldw	r6,8(r3)
+    2ad0:	11c5883a 	add	r2,r2,r7
+    2ad4:	31400315 	stw	r5,12(r6)
+    2ad8:	29800215 	stw	r6,8(r5)
+    2adc:	01400034 	movhi	r5,0
+    2ae0:	11800054 	ori	r6,r2,1
+    2ae4:	295c7b17 	ldw	r5,29164(r5)
+    2ae8:	19800115 	stw	r6,4(r3)
+    2aec:	20c00215 	stw	r3,8(r4)
+    2af0:	117fb236 	bltu	r2,r5,29bc <_free_r+0xe8>
+    2af4:	00800034 	movhi	r2,0
+    2af8:	115c8817 	ldw	r5,29216(r2)
+    2afc:	8809883a 	mov	r4,r17
+    2b00:	00027b80 	call	27b8 <_malloc_trim_r>
+    2b04:	003fad06 	br	29bc <_free_r+0xe8>
+    2b08:	29800568 	cmpgeui	r6,r5,21
+    2b0c:	30000926 	beq	r6,zero,2b34 <_free_r+0x260>
+    2b10:	29801568 	cmpgeui	r6,r5,85
+    2b14:	3000191e 	bne	r6,zero,2b7c <_free_r+0x2a8>
+    2b18:	100ad33a 	srli	r5,r2,12
+    2b1c:	29801bc4 	addi	r6,r5,111
+    2b20:	300c90fa 	slli	r6,r6,3
+    2b24:	29c01b84 	addi	r7,r5,110
+    2b28:	003fc706 	br	2a48 <_free_r+0x174>
+    2b2c:	1145883a 	add	r2,r2,r5
+    2b30:	003fae06 	br	29ec <_free_r+0x118>
+    2b34:	29801704 	addi	r6,r5,92
+    2b38:	300c90fa 	slli	r6,r6,3
+    2b3c:	29c016c4 	addi	r7,r5,91
+    2b40:	003fc106 	br	2a48 <_free_r+0x174>
+    2b44:	20c00515 	stw	r3,20(r4)
+    2b48:	20c00415 	stw	r3,16(r4)
+    2b4c:	19c00315 	stw	r7,12(r3)
+    2b50:	19c00215 	stw	r7,8(r3)
+    2b54:	1a400115 	stw	r9,4(r3)
+    2b58:	40800015 	stw	r2,0(r8)
+    2b5c:	003f9706 	br	29bc <_free_r+0xe8>
+    2b60:	380fd0ba 	srai	r7,r7,2
+    2b64:	00800044 	movi	r2,1
+    2b68:	22000117 	ldw	r8,4(r4)
+    2b6c:	11ce983a 	sll	r7,r2,r7
+    2b70:	3a0eb03a 	or	r7,r7,r8
+    2b74:	21c00115 	stw	r7,4(r4)
+    2b78:	003fbe06 	br	2a74 <_free_r+0x1a0>
+    2b7c:	29805568 	cmpgeui	r6,r5,341
+    2b80:	3000051e 	bne	r6,zero,2b98 <_free_r+0x2c4>
+    2b84:	100ad3fa 	srli	r5,r2,15
+    2b88:	29801e04 	addi	r6,r5,120
+    2b8c:	300c90fa 	slli	r6,r6,3
+    2b90:	29c01dc4 	addi	r7,r5,119
+    2b94:	003fac06 	br	2a48 <_free_r+0x174>
+    2b98:	29415568 	cmpgeui	r5,r5,1365
+    2b9c:	2800051e 	bne	r5,zero,2bb4 <_free_r+0x2e0>
+    2ba0:	100ad4ba 	srli	r5,r2,18
+    2ba4:	29801f44 	addi	r6,r5,125
+    2ba8:	300c90fa 	slli	r6,r6,3
+    2bac:	29c01f04 	addi	r7,r5,124
+    2bb0:	003fa506 	br	2a48 <_free_r+0x174>
+    2bb4:	0180fe04 	movi	r6,1016
+    2bb8:	01c01f84 	movi	r7,126
+    2bbc:	003fa206 	br	2a48 <_free_r+0x174>
+    2bc0:	11000054 	ori	r4,r2,1
+    2bc4:	19000115 	stw	r4,4(r3)
+    2bc8:	30800015 	stw	r2,0(r6)
+    2bcc:	003f7b06 	br	29bc <_free_r+0xe8>
 
-00002c3c <_lseek_r>:
-    2c3c:	defffd04 	addi	sp,sp,-12
-    2c40:	2805883a 	mov	r2,r5
-    2c44:	dc000015 	stw	r16,0(sp)
-    2c48:	04000034 	movhi	r16,0
-    2c4c:	dc400115 	stw	r17,4(sp)
-    2c50:	300b883a 	mov	r5,r6
-    2c54:	841cb504 	addi	r16,r16,29396
-    2c58:	2023883a 	mov	r17,r4
-    2c5c:	380d883a 	mov	r6,r7
-    2c60:	1009883a 	mov	r4,r2
-    2c64:	dfc00215 	stw	ra,8(sp)
-    2c68:	80000015 	stw	zero,0(r16)
-    2c6c:	00034c40 	call	34c4 <lseek>
-    2c70:	00ffffc4 	movi	r3,-1
-    2c74:	10c00526 	beq	r2,r3,2c8c <_lseek_r+0x50>
-    2c78:	dfc00217 	ldw	ra,8(sp)
-    2c7c:	dc400117 	ldw	r17,4(sp)
-    2c80:	dc000017 	ldw	r16,0(sp)
-    2c84:	dec00304 	addi	sp,sp,12
-    2c88:	f800283a 	ret
-    2c8c:	80c00017 	ldw	r3,0(r16)
-    2c90:	183ff926 	beq	r3,zero,2c78 <__alt_data_end+0xfffe2c78>
-    2c94:	88c00015 	stw	r3,0(r17)
-    2c98:	003ff706 	br	2c78 <__alt_data_end+0xfffe2c78>
+00002bd0 <_lseek_r>:
+    2bd0:	2807883a 	mov	r3,r5
+    2bd4:	defffe04 	addi	sp,sp,-8
+    2bd8:	dc000015 	stw	r16,0(sp)
+    2bdc:	300b883a 	mov	r5,r6
+    2be0:	00800034 	movhi	r2,0
+    2be4:	380d883a 	mov	r6,r7
+    2be8:	2021883a 	mov	r16,r4
+    2bec:	1809883a 	mov	r4,r3
+    2bf0:	dfc00115 	stw	ra,4(sp)
+    2bf4:	101c8915 	stw	zero,29220(r2)
+    2bf8:	00035000 	call	3500 <lseek>
+    2bfc:	10ffffd8 	cmpnei	r3,r2,-1
+    2c00:	18000426 	beq	r3,zero,2c14 <_lseek_r+0x44>
+    2c04:	dfc00117 	ldw	ra,4(sp)
+    2c08:	dc000017 	ldw	r16,0(sp)
+    2c0c:	dec00204 	addi	sp,sp,8
+    2c10:	f800283a 	ret
+    2c14:	00c00034 	movhi	r3,0
+    2c18:	18dc8917 	ldw	r3,29220(r3)
+    2c1c:	183ff926 	beq	r3,zero,2c04 <_lseek_r+0x34>
+    2c20:	80c00015 	stw	r3,0(r16)
+    2c24:	dfc00117 	ldw	ra,4(sp)
+    2c28:	dc000017 	ldw	r16,0(sp)
+    2c2c:	dec00204 	addi	sp,sp,8
+    2c30:	f800283a 	ret
 
-00002c9c <__smakebuf_r>:
-    2c9c:	2880030b 	ldhu	r2,12(r5)
-    2ca0:	10c0008c 	andi	r3,r2,2
-    2ca4:	1800411e 	bne	r3,zero,2dac <__smakebuf_r+0x110>
-    2ca8:	deffec04 	addi	sp,sp,-80
-    2cac:	dc000f15 	stw	r16,60(sp)
-    2cb0:	2821883a 	mov	r16,r5
-    2cb4:	2940038f 	ldh	r5,14(r5)
-    2cb8:	dc401015 	stw	r17,64(sp)
-    2cbc:	dfc01315 	stw	ra,76(sp)
-    2cc0:	dcc01215 	stw	r19,72(sp)
-    2cc4:	dc801115 	stw	r18,68(sp)
-    2cc8:	2023883a 	mov	r17,r4
-    2ccc:	28001c16 	blt	r5,zero,2d40 <__smakebuf_r+0xa4>
-    2cd0:	d80d883a 	mov	r6,sp
-    2cd4:	0002eb80 	call	2eb8 <_fstat_r>
-    2cd8:	10001816 	blt	r2,zero,2d3c <__smakebuf_r+0xa0>
-    2cdc:	d8800117 	ldw	r2,4(sp)
-    2ce0:	00e00014 	movui	r3,32768
-    2ce4:	10bc000c 	andi	r2,r2,61440
-    2ce8:	14c80020 	cmpeqi	r19,r2,8192
-    2cec:	10c03726 	beq	r2,r3,2dcc <__smakebuf_r+0x130>
-    2cf0:	80c0030b 	ldhu	r3,12(r16)
-    2cf4:	18c20014 	ori	r3,r3,2048
-    2cf8:	80c0030d 	sth	r3,12(r16)
-    2cfc:	00c80004 	movi	r3,8192
-    2d00:	10c0521e 	bne	r2,r3,2e4c <__smakebuf_r+0x1b0>
-    2d04:	8140038f 	ldh	r5,14(r16)
-    2d08:	8809883a 	mov	r4,r17
-    2d0c:	0002f140 	call	2f14 <_isatty_r>
-    2d10:	10004c26 	beq	r2,zero,2e44 <__smakebuf_r+0x1a8>
-    2d14:	8080030b 	ldhu	r2,12(r16)
-    2d18:	80c010c4 	addi	r3,r16,67
-    2d1c:	80c00015 	stw	r3,0(r16)
-    2d20:	10800054 	ori	r2,r2,1
-    2d24:	8080030d 	sth	r2,12(r16)
-    2d28:	00800044 	movi	r2,1
-    2d2c:	80c00415 	stw	r3,16(r16)
-    2d30:	80800515 	stw	r2,20(r16)
-    2d34:	04810004 	movi	r18,1024
-    2d38:	00000706 	br	2d58 <__smakebuf_r+0xbc>
+00002c34 <__smakebuf_r>:
+    2c34:	2880030b 	ldhu	r2,12(r5)
+    2c38:	deffe804 	addi	sp,sp,-96
+    2c3c:	dc001215 	stw	r16,72(sp)
+    2c40:	dfc01715 	stw	ra,92(sp)
+    2c44:	dd001615 	stw	r20,88(sp)
+    2c48:	dcc01515 	stw	r19,84(sp)
+    2c4c:	dc801415 	stw	r18,80(sp)
+    2c50:	dc401315 	stw	r17,76(sp)
+    2c54:	10c0008c 	andi	r3,r2,2
+    2c58:	2821883a 	mov	r16,r5
+    2c5c:	18000d26 	beq	r3,zero,2c94 <__smakebuf_r+0x60>
+    2c60:	288010c4 	addi	r2,r5,67
+    2c64:	28800015 	stw	r2,0(r5)
+    2c68:	28800415 	stw	r2,16(r5)
+    2c6c:	00800044 	movi	r2,1
+    2c70:	28800515 	stw	r2,20(r5)
+    2c74:	dfc01717 	ldw	ra,92(sp)
+    2c78:	dd001617 	ldw	r20,88(sp)
+    2c7c:	dcc01517 	ldw	r19,84(sp)
+    2c80:	dc801417 	ldw	r18,80(sp)
+    2c84:	dc401317 	ldw	r17,76(sp)
+    2c88:	dc001217 	ldw	r16,72(sp)
+    2c8c:	dec01804 	addi	sp,sp,96
+    2c90:	f800283a 	ret
+    2c94:	2940038f 	ldh	r5,14(r5)
+    2c98:	2023883a 	mov	r17,r4
+    2c9c:	28002816 	blt	r5,zero,2d40 <__smakebuf_r+0x10c>
+    2ca0:	d80d883a 	mov	r6,sp
+    2ca4:	0002ee00 	call	2ee0 <_fstat_r>
+    2ca8:	10002416 	blt	r2,zero,2d3c <__smakebuf_r+0x108>
+    2cac:	d8800117 	ldw	r2,4(sp)
+    2cb0:	10bc000c 	andi	r2,r2,61440
+    2cb4:	10880018 	cmpnei	r2,r2,8192
+    2cb8:	1000461e 	bne	r2,zero,2dd4 <__smakebuf_r+0x1a0>
+    2cbc:	8140038f 	ldh	r5,14(r16)
+    2cc0:	8809883a 	mov	r4,r17
+    2cc4:	0002f400 	call	2f40 <_isatty_r>
+    2cc8:	10003e26 	beq	r2,zero,2dc4 <__smakebuf_r+0x190>
+    2ccc:	8080030b 	ldhu	r2,12(r16)
+    2cd0:	80c010c4 	addi	r3,r16,67
+    2cd4:	80c00015 	stw	r3,0(r16)
+    2cd8:	10800054 	ori	r2,r2,1
+    2cdc:	8080030d 	sth	r2,12(r16)
+    2ce0:	00800044 	movi	r2,1
+    2ce4:	80c00415 	stw	r3,16(r16)
+    2ce8:	80800515 	stw	r2,20(r16)
+    2cec:	04c00044 	movi	r19,1
+    2cf0:	05010004 	movi	r20,1024
+    2cf4:	04820004 	movi	r18,2048
+    2cf8:	a00b883a 	mov	r5,r20
+    2cfc:	8809883a 	mov	r4,r17
+    2d00:	0000e240 	call	e24 <_malloc_r>
+    2d04:	10001726 	beq	r2,zero,2d64 <__smakebuf_r+0x130>
+    2d08:	80c0030b 	ldhu	r3,12(r16)
+    2d0c:	01000034 	movhi	r4,0
+    2d10:	21011e04 	addi	r4,r4,1144
+    2d14:	89000f15 	stw	r4,60(r17)
+    2d18:	18c02014 	ori	r3,r3,128
+    2d1c:	80c0030d 	sth	r3,12(r16)
+    2d20:	80800015 	stw	r2,0(r16)
+    2d24:	80800415 	stw	r2,16(r16)
+    2d28:	85000515 	stw	r20,20(r16)
+    2d2c:	98001d1e 	bne	r19,zero,2da4 <__smakebuf_r+0x170>
+    2d30:	90c6b03a 	or	r3,r18,r3
+    2d34:	80c0030d 	sth	r3,12(r16)
+    2d38:	003fce06 	br	2c74 <__smakebuf_r+0x40>
     2d3c:	8080030b 	ldhu	r2,12(r16)
-    2d40:	10c0200c 	andi	r3,r2,128
-    2d44:	18001f1e 	bne	r3,zero,2dc4 <__smakebuf_r+0x128>
-    2d48:	04810004 	movi	r18,1024
-    2d4c:	10820014 	ori	r2,r2,2048
-    2d50:	8080030d 	sth	r2,12(r16)
-    2d54:	0027883a 	mov	r19,zero
-    2d58:	900b883a 	mov	r5,r18
-    2d5c:	8809883a 	mov	r4,r17
-    2d60:	0000ea40 	call	ea4 <_malloc_r>
-    2d64:	10002c26 	beq	r2,zero,2e18 <__smakebuf_r+0x17c>
-    2d68:	80c0030b 	ldhu	r3,12(r16)
-    2d6c:	01000034 	movhi	r4,0
-    2d70:	21012b04 	addi	r4,r4,1196
-    2d74:	89000f15 	stw	r4,60(r17)
-    2d78:	18c02014 	ori	r3,r3,128
-    2d7c:	80c0030d 	sth	r3,12(r16)
-    2d80:	80800015 	stw	r2,0(r16)
-    2d84:	80800415 	stw	r2,16(r16)
-    2d88:	84800515 	stw	r18,20(r16)
-    2d8c:	98001a1e 	bne	r19,zero,2df8 <__smakebuf_r+0x15c>
-    2d90:	dfc01317 	ldw	ra,76(sp)
-    2d94:	dcc01217 	ldw	r19,72(sp)
-    2d98:	dc801117 	ldw	r18,68(sp)
-    2d9c:	dc401017 	ldw	r17,64(sp)
-    2da0:	dc000f17 	ldw	r16,60(sp)
-    2da4:	dec01404 	addi	sp,sp,80
-    2da8:	f800283a 	ret
-    2dac:	288010c4 	addi	r2,r5,67
-    2db0:	28800015 	stw	r2,0(r5)
-    2db4:	28800415 	stw	r2,16(r5)
-    2db8:	00800044 	movi	r2,1
-    2dbc:	28800515 	stw	r2,20(r5)
-    2dc0:	f800283a 	ret
-    2dc4:	04801004 	movi	r18,64
-    2dc8:	003fe006 	br	2d4c <__alt_data_end+0xfffe2d4c>
-    2dcc:	81000a17 	ldw	r4,40(r16)
-    2dd0:	00c00034 	movhi	r3,0
-    2dd4:	18c87c04 	addi	r3,r3,8688
-    2dd8:	20ffc51e 	bne	r4,r3,2cf0 <__alt_data_end+0xfffe2cf0>
-    2ddc:	8080030b 	ldhu	r2,12(r16)
-    2de0:	04810004 	movi	r18,1024
-    2de4:	84801315 	stw	r18,76(r16)
-    2de8:	1484b03a 	or	r2,r2,r18
-    2dec:	8080030d 	sth	r2,12(r16)
-    2df0:	0027883a 	mov	r19,zero
-    2df4:	003fd806 	br	2d58 <__alt_data_end+0xfffe2d58>
-    2df8:	8140038f 	ldh	r5,14(r16)
-    2dfc:	8809883a 	mov	r4,r17
-    2e00:	0002f140 	call	2f14 <_isatty_r>
-    2e04:	103fe226 	beq	r2,zero,2d90 <__alt_data_end+0xfffe2d90>
-    2e08:	8080030b 	ldhu	r2,12(r16)
-    2e0c:	10800054 	ori	r2,r2,1
-    2e10:	8080030d 	sth	r2,12(r16)
-    2e14:	003fde06 	br	2d90 <__alt_data_end+0xfffe2d90>
-    2e18:	8080030b 	ldhu	r2,12(r16)
-    2e1c:	10c0800c 	andi	r3,r2,512
-    2e20:	183fdb1e 	bne	r3,zero,2d90 <__alt_data_end+0xfffe2d90>
-    2e24:	10800094 	ori	r2,r2,2
-    2e28:	80c010c4 	addi	r3,r16,67
-    2e2c:	8080030d 	sth	r2,12(r16)
-    2e30:	00800044 	movi	r2,1
-    2e34:	80c00015 	stw	r3,0(r16)
-    2e38:	80c00415 	stw	r3,16(r16)
-    2e3c:	80800515 	stw	r2,20(r16)
-    2e40:	003fd306 	br	2d90 <__alt_data_end+0xfffe2d90>
-    2e44:	04810004 	movi	r18,1024
-    2e48:	003fc306 	br	2d58 <__alt_data_end+0xfffe2d58>
-    2e4c:	0027883a 	mov	r19,zero
-    2e50:	04810004 	movi	r18,1024
-    2e54:	003fc006 	br	2d58 <__alt_data_end+0xfffe2d58>
+    2d40:	1080200c 	andi	r2,r2,128
+    2d44:	0027883a 	mov	r19,zero
+    2d48:	10001326 	beq	r2,zero,2d98 <__smakebuf_r+0x164>
+    2d4c:	05001004 	movi	r20,64
+    2d50:	a00b883a 	mov	r5,r20
+    2d54:	8809883a 	mov	r4,r17
+    2d58:	0025883a 	mov	r18,zero
+    2d5c:	0000e240 	call	e24 <_malloc_r>
+    2d60:	103fe91e 	bne	r2,zero,2d08 <__smakebuf_r+0xd4>
+    2d64:	8080030b 	ldhu	r2,12(r16)
+    2d68:	10c0800c 	andi	r3,r2,512
+    2d6c:	183fc11e 	bne	r3,zero,2c74 <__smakebuf_r+0x40>
+    2d70:	00ffff04 	movi	r3,-4
+    2d74:	10c4703a 	and	r2,r2,r3
+    2d78:	10800094 	ori	r2,r2,2
+    2d7c:	80c010c4 	addi	r3,r16,67
+    2d80:	8080030d 	sth	r2,12(r16)
+    2d84:	00800044 	movi	r2,1
+    2d88:	80c00015 	stw	r3,0(r16)
+    2d8c:	80c00415 	stw	r3,16(r16)
+    2d90:	80800515 	stw	r2,20(r16)
+    2d94:	003fb706 	br	2c74 <__smakebuf_r+0x40>
+    2d98:	05010004 	movi	r20,1024
+    2d9c:	0025883a 	mov	r18,zero
+    2da0:	003fd506 	br	2cf8 <__smakebuf_r+0xc4>
+    2da4:	8140038f 	ldh	r5,14(r16)
+    2da8:	8809883a 	mov	r4,r17
+    2dac:	0002f400 	call	2f40 <_isatty_r>
+    2db0:	80c0030b 	ldhu	r3,12(r16)
+    2db4:	103fde26 	beq	r2,zero,2d30 <__smakebuf_r+0xfc>
+    2db8:	18ffff0c 	andi	r3,r3,65532
+    2dbc:	18c00054 	ori	r3,r3,1
+    2dc0:	003fdb06 	br	2d30 <__smakebuf_r+0xfc>
+    2dc4:	04c00044 	movi	r19,1
+    2dc8:	05010004 	movi	r20,1024
+    2dcc:	04820004 	movi	r18,2048
+    2dd0:	003fc906 	br	2cf8 <__smakebuf_r+0xc4>
+    2dd4:	0027883a 	mov	r19,zero
+    2dd8:	05010004 	movi	r20,1024
+    2ddc:	04820004 	movi	r18,2048
+    2de0:	003fc506 	br	2cf8 <__smakebuf_r+0xc4>
 
-00002e58 <_read_r>:
-    2e58:	defffd04 	addi	sp,sp,-12
-    2e5c:	2805883a 	mov	r2,r5
-    2e60:	dc000015 	stw	r16,0(sp)
-    2e64:	04000034 	movhi	r16,0
-    2e68:	dc400115 	stw	r17,4(sp)
-    2e6c:	300b883a 	mov	r5,r6
-    2e70:	841cb504 	addi	r16,r16,29396
-    2e74:	2023883a 	mov	r17,r4
-    2e78:	380d883a 	mov	r6,r7
-    2e7c:	1009883a 	mov	r4,r2
-    2e80:	dfc00215 	stw	ra,8(sp)
-    2e84:	80000015 	stw	zero,0(r16)
-    2e88:	00036a00 	call	36a0 <read>
-    2e8c:	00ffffc4 	movi	r3,-1
-    2e90:	10c00526 	beq	r2,r3,2ea8 <_read_r+0x50>
-    2e94:	dfc00217 	ldw	ra,8(sp)
-    2e98:	dc400117 	ldw	r17,4(sp)
-    2e9c:	dc000017 	ldw	r16,0(sp)
-    2ea0:	dec00304 	addi	sp,sp,12
-    2ea4:	f800283a 	ret
-    2ea8:	80c00017 	ldw	r3,0(r16)
-    2eac:	183ff926 	beq	r3,zero,2e94 <__alt_data_end+0xfffe2e94>
-    2eb0:	88c00015 	stw	r3,0(r17)
-    2eb4:	003ff706 	br	2e94 <__alt_data_end+0xfffe2e94>
+00002de4 <__swhatbuf_r>:
+    2de4:	deffea04 	addi	sp,sp,-88
+    2de8:	dc001215 	stw	r16,72(sp)
+    2dec:	2821883a 	mov	r16,r5
+    2df0:	2940038f 	ldh	r5,14(r5)
+    2df4:	dc801415 	stw	r18,80(sp)
+    2df8:	dc401315 	stw	r17,76(sp)
+    2dfc:	dfc01515 	stw	ra,84(sp)
+    2e00:	3023883a 	mov	r17,r6
+    2e04:	3825883a 	mov	r18,r7
+    2e08:	28001016 	blt	r5,zero,2e4c <__swhatbuf_r+0x68>
+    2e0c:	d80d883a 	mov	r6,sp
+    2e10:	0002ee00 	call	2ee0 <_fstat_r>
+    2e14:	10000d16 	blt	r2,zero,2e4c <__swhatbuf_r+0x68>
+    2e18:	d8c00117 	ldw	r3,4(sp)
+    2e1c:	00820004 	movi	r2,2048
+    2e20:	18fc000c 	andi	r3,r3,61440
+    2e24:	18c80020 	cmpeqi	r3,r3,8192
+    2e28:	90c00015 	stw	r3,0(r18)
+    2e2c:	00c10004 	movi	r3,1024
+    2e30:	88c00015 	stw	r3,0(r17)
+    2e34:	dfc01517 	ldw	ra,84(sp)
+    2e38:	dc801417 	ldw	r18,80(sp)
+    2e3c:	dc401317 	ldw	r17,76(sp)
+    2e40:	dc001217 	ldw	r16,72(sp)
+    2e44:	dec01604 	addi	sp,sp,88
+    2e48:	f800283a 	ret
+    2e4c:	8080030b 	ldhu	r2,12(r16)
+    2e50:	90000015 	stw	zero,0(r18)
+    2e54:	1080200c 	andi	r2,r2,128
+    2e58:	10000426 	beq	r2,zero,2e6c <__swhatbuf_r+0x88>
+    2e5c:	00801004 	movi	r2,64
+    2e60:	88800015 	stw	r2,0(r17)
+    2e64:	0005883a 	mov	r2,zero
+    2e68:	003ff206 	br	2e34 <__swhatbuf_r+0x50>
+    2e6c:	00810004 	movi	r2,1024
+    2e70:	88800015 	stw	r2,0(r17)
+    2e74:	0005883a 	mov	r2,zero
+    2e78:	003fee06 	br	2e34 <__swhatbuf_r+0x50>
 
-00002eb8 <_fstat_r>:
-    2eb8:	defffd04 	addi	sp,sp,-12
-    2ebc:	2805883a 	mov	r2,r5
-    2ec0:	dc000015 	stw	r16,0(sp)
-    2ec4:	04000034 	movhi	r16,0
-    2ec8:	dc400115 	stw	r17,4(sp)
-    2ecc:	841cb504 	addi	r16,r16,29396
-    2ed0:	2023883a 	mov	r17,r4
-    2ed4:	300b883a 	mov	r5,r6
-    2ed8:	1009883a 	mov	r4,r2
-    2edc:	dfc00215 	stw	ra,8(sp)
-    2ee0:	80000015 	stw	zero,0(r16)
-    2ee4:	00032e80 	call	32e8 <fstat>
-    2ee8:	00ffffc4 	movi	r3,-1
-    2eec:	10c00526 	beq	r2,r3,2f04 <_fstat_r+0x4c>
-    2ef0:	dfc00217 	ldw	ra,8(sp)
-    2ef4:	dc400117 	ldw	r17,4(sp)
-    2ef8:	dc000017 	ldw	r16,0(sp)
-    2efc:	dec00304 	addi	sp,sp,12
-    2f00:	f800283a 	ret
-    2f04:	80c00017 	ldw	r3,0(r16)
-    2f08:	183ff926 	beq	r3,zero,2ef0 <__alt_data_end+0xfffe2ef0>
-    2f0c:	88c00015 	stw	r3,0(r17)
-    2f10:	003ff706 	br	2ef0 <__alt_data_end+0xfffe2ef0>
+00002e7c <_read_r>:
+    2e7c:	2807883a 	mov	r3,r5
+    2e80:	defffe04 	addi	sp,sp,-8
+    2e84:	dc000015 	stw	r16,0(sp)
+    2e88:	300b883a 	mov	r5,r6
+    2e8c:	00800034 	movhi	r2,0
+    2e90:	380d883a 	mov	r6,r7
+    2e94:	2021883a 	mov	r16,r4
+    2e98:	1809883a 	mov	r4,r3
+    2e9c:	dfc00115 	stw	ra,4(sp)
+    2ea0:	101c8915 	stw	zero,29220(r2)
+    2ea4:	00036e00 	call	36e0 <read>
+    2ea8:	10ffffd8 	cmpnei	r3,r2,-1
+    2eac:	18000426 	beq	r3,zero,2ec0 <_read_r+0x44>
+    2eb0:	dfc00117 	ldw	ra,4(sp)
+    2eb4:	dc000017 	ldw	r16,0(sp)
+    2eb8:	dec00204 	addi	sp,sp,8
+    2ebc:	f800283a 	ret
+    2ec0:	00c00034 	movhi	r3,0
+    2ec4:	18dc8917 	ldw	r3,29220(r3)
+    2ec8:	183ff926 	beq	r3,zero,2eb0 <_read_r+0x34>
+    2ecc:	80c00015 	stw	r3,0(r16)
+    2ed0:	dfc00117 	ldw	ra,4(sp)
+    2ed4:	dc000017 	ldw	r16,0(sp)
+    2ed8:	dec00204 	addi	sp,sp,8
+    2edc:	f800283a 	ret
 
-00002f14 <_isatty_r>:
-    2f14:	defffd04 	addi	sp,sp,-12
-    2f18:	dc000015 	stw	r16,0(sp)
-    2f1c:	04000034 	movhi	r16,0
-    2f20:	dc400115 	stw	r17,4(sp)
-    2f24:	841cb504 	addi	r16,r16,29396
-    2f28:	2023883a 	mov	r17,r4
-    2f2c:	2809883a 	mov	r4,r5
-    2f30:	dfc00215 	stw	ra,8(sp)
-    2f34:	80000015 	stw	zero,0(r16)
-    2f38:	00033dc0 	call	33dc <isatty>
-    2f3c:	00ffffc4 	movi	r3,-1
-    2f40:	10c00526 	beq	r2,r3,2f58 <_isatty_r+0x44>
-    2f44:	dfc00217 	ldw	ra,8(sp)
-    2f48:	dc400117 	ldw	r17,4(sp)
-    2f4c:	dc000017 	ldw	r16,0(sp)
-    2f50:	dec00304 	addi	sp,sp,12
-    2f54:	f800283a 	ret
-    2f58:	80c00017 	ldw	r3,0(r16)
-    2f5c:	183ff926 	beq	r3,zero,2f44 <__alt_data_end+0xfffe2f44>
-    2f60:	88c00015 	stw	r3,0(r17)
-    2f64:	003ff706 	br	2f44 <__alt_data_end+0xfffe2f44>
+00002ee0 <_fstat_r>:
+    2ee0:	2807883a 	mov	r3,r5
+    2ee4:	defffe04 	addi	sp,sp,-8
+    2ee8:	dc000015 	stw	r16,0(sp)
+    2eec:	00800034 	movhi	r2,0
+    2ef0:	300b883a 	mov	r5,r6
+    2ef4:	2021883a 	mov	r16,r4
+    2ef8:	1809883a 	mov	r4,r3
+    2efc:	dfc00115 	stw	ra,4(sp)
+    2f00:	101c8915 	stw	zero,29220(r2)
+    2f04:	000331c0 	call	331c <fstat>
+    2f08:	10ffffd8 	cmpnei	r3,r2,-1
+    2f0c:	18000426 	beq	r3,zero,2f20 <_fstat_r+0x40>
+    2f10:	dfc00117 	ldw	ra,4(sp)
+    2f14:	dc000017 	ldw	r16,0(sp)
+    2f18:	dec00204 	addi	sp,sp,8
+    2f1c:	f800283a 	ret
+    2f20:	00c00034 	movhi	r3,0
+    2f24:	18dc8917 	ldw	r3,29220(r3)
+    2f28:	183ff926 	beq	r3,zero,2f10 <_fstat_r+0x30>
+    2f2c:	80c00015 	stw	r3,0(r16)
+    2f30:	dfc00117 	ldw	ra,4(sp)
+    2f34:	dc000017 	ldw	r16,0(sp)
+    2f38:	dec00204 	addi	sp,sp,8
+    2f3c:	f800283a 	ret
 
-00002f68 <__divsi3>:
-    2f68:	20001b16 	blt	r4,zero,2fd8 <__divsi3+0x70>
-    2f6c:	000f883a 	mov	r7,zero
-    2f70:	28001616 	blt	r5,zero,2fcc <__divsi3+0x64>
-    2f74:	200d883a 	mov	r6,r4
-    2f78:	29001a2e 	bgeu	r5,r4,2fe4 <__divsi3+0x7c>
-    2f7c:	00800804 	movi	r2,32
-    2f80:	00c00044 	movi	r3,1
-    2f84:	00000106 	br	2f8c <__divsi3+0x24>
-    2f88:	10000d26 	beq	r2,zero,2fc0 <__divsi3+0x58>
-    2f8c:	294b883a 	add	r5,r5,r5
-    2f90:	10bfffc4 	addi	r2,r2,-1
-    2f94:	18c7883a 	add	r3,r3,r3
-    2f98:	293ffb36 	bltu	r5,r4,2f88 <__alt_data_end+0xfffe2f88>
-    2f9c:	0005883a 	mov	r2,zero
-    2fa0:	18000726 	beq	r3,zero,2fc0 <__divsi3+0x58>
-    2fa4:	0005883a 	mov	r2,zero
-    2fa8:	31400236 	bltu	r6,r5,2fb4 <__divsi3+0x4c>
-    2fac:	314dc83a 	sub	r6,r6,r5
-    2fb0:	10c4b03a 	or	r2,r2,r3
-    2fb4:	1806d07a 	srli	r3,r3,1
-    2fb8:	280ad07a 	srli	r5,r5,1
-    2fbc:	183ffa1e 	bne	r3,zero,2fa8 <__alt_data_end+0xfffe2fa8>
-    2fc0:	38000126 	beq	r7,zero,2fc8 <__divsi3+0x60>
-    2fc4:	0085c83a 	sub	r2,zero,r2
-    2fc8:	f800283a 	ret
-    2fcc:	014bc83a 	sub	r5,zero,r5
-    2fd0:	39c0005c 	xori	r7,r7,1
-    2fd4:	003fe706 	br	2f74 <__alt_data_end+0xfffe2f74>
-    2fd8:	0109c83a 	sub	r4,zero,r4
-    2fdc:	01c00044 	movi	r7,1
-    2fe0:	003fe306 	br	2f70 <__alt_data_end+0xfffe2f70>
-    2fe4:	00c00044 	movi	r3,1
-    2fe8:	003fee06 	br	2fa4 <__alt_data_end+0xfffe2fa4>
+00002f40 <_isatty_r>:
+    2f40:	defffe04 	addi	sp,sp,-8
+    2f44:	dc000015 	stw	r16,0(sp)
+    2f48:	00800034 	movhi	r2,0
+    2f4c:	2021883a 	mov	r16,r4
+    2f50:	2809883a 	mov	r4,r5
+    2f54:	dfc00115 	stw	ra,4(sp)
+    2f58:	101c8915 	stw	zero,29220(r2)
+    2f5c:	00034140 	call	3414 <isatty>
+    2f60:	10ffffd8 	cmpnei	r3,r2,-1
+    2f64:	18000426 	beq	r3,zero,2f78 <_isatty_r+0x38>
+    2f68:	dfc00117 	ldw	ra,4(sp)
+    2f6c:	dc000017 	ldw	r16,0(sp)
+    2f70:	dec00204 	addi	sp,sp,8
+    2f74:	f800283a 	ret
+    2f78:	00c00034 	movhi	r3,0
+    2f7c:	18dc8917 	ldw	r3,29220(r3)
+    2f80:	183ff926 	beq	r3,zero,2f68 <_isatty_r+0x28>
+    2f84:	80c00015 	stw	r3,0(r16)
+    2f88:	dfc00117 	ldw	ra,4(sp)
+    2f8c:	dc000017 	ldw	r16,0(sp)
+    2f90:	dec00204 	addi	sp,sp,8
+    2f94:	f800283a 	ret
 
-00002fec <__modsi3>:
-    2fec:	20001716 	blt	r4,zero,304c <__modsi3+0x60>
-    2ff0:	000f883a 	mov	r7,zero
-    2ff4:	2005883a 	mov	r2,r4
-    2ff8:	28001216 	blt	r5,zero,3044 <__modsi3+0x58>
-    2ffc:	2900162e 	bgeu	r5,r4,3058 <__modsi3+0x6c>
-    3000:	01800804 	movi	r6,32
-    3004:	00c00044 	movi	r3,1
-    3008:	00000106 	br	3010 <__modsi3+0x24>
-    300c:	30000a26 	beq	r6,zero,3038 <__modsi3+0x4c>
-    3010:	294b883a 	add	r5,r5,r5
-    3014:	31bfffc4 	addi	r6,r6,-1
-    3018:	18c7883a 	add	r3,r3,r3
-    301c:	293ffb36 	bltu	r5,r4,300c <__alt_data_end+0xfffe300c>
-    3020:	18000526 	beq	r3,zero,3038 <__modsi3+0x4c>
-    3024:	1806d07a 	srli	r3,r3,1
-    3028:	11400136 	bltu	r2,r5,3030 <__modsi3+0x44>
-    302c:	1145c83a 	sub	r2,r2,r5
-    3030:	280ad07a 	srli	r5,r5,1
-    3034:	183ffb1e 	bne	r3,zero,3024 <__alt_data_end+0xfffe3024>
-    3038:	38000126 	beq	r7,zero,3040 <__modsi3+0x54>
-    303c:	0085c83a 	sub	r2,zero,r2
-    3040:	f800283a 	ret
-    3044:	014bc83a 	sub	r5,zero,r5
-    3048:	003fec06 	br	2ffc <__alt_data_end+0xfffe2ffc>
-    304c:	0109c83a 	sub	r4,zero,r4
-    3050:	01c00044 	movi	r7,1
-    3054:	003fe706 	br	2ff4 <__alt_data_end+0xfffe2ff4>
-    3058:	00c00044 	movi	r3,1
-    305c:	003ff106 	br	3024 <__alt_data_end+0xfffe3024>
+00002f98 <__divsi3>:
+    2f98:	20001a16 	blt	r4,zero,3004 <__divsi3+0x6c>
+    2f9c:	000f883a 	mov	r7,zero
+    2fa0:	2800020e 	bge	r5,zero,2fac <__divsi3+0x14>
+    2fa4:	014bc83a 	sub	r5,zero,r5
+    2fa8:	39c0005c 	xori	r7,r7,1
+    2fac:	200d883a 	mov	r6,r4
+    2fb0:	00c00044 	movi	r3,1
+    2fb4:	2900092e 	bgeu	r5,r4,2fdc <__divsi3+0x44>
+    2fb8:	00800804 	movi	r2,32
+    2fbc:	00c00044 	movi	r3,1
+    2fc0:	00000106 	br	2fc8 <__divsi3+0x30>
+    2fc4:	10001226 	beq	r2,zero,3010 <__divsi3+0x78>
+    2fc8:	294b883a 	add	r5,r5,r5
+    2fcc:	10bfffc4 	addi	r2,r2,-1
+    2fd0:	18c7883a 	add	r3,r3,r3
+    2fd4:	293ffb36 	bltu	r5,r4,2fc4 <__divsi3+0x2c>
+    2fd8:	18000d26 	beq	r3,zero,3010 <__divsi3+0x78>
+    2fdc:	0005883a 	mov	r2,zero
+    2fe0:	31400236 	bltu	r6,r5,2fec <__divsi3+0x54>
+    2fe4:	314dc83a 	sub	r6,r6,r5
+    2fe8:	10c4b03a 	or	r2,r2,r3
+    2fec:	1806d07a 	srli	r3,r3,1
+    2ff0:	280ad07a 	srli	r5,r5,1
+    2ff4:	183ffa1e 	bne	r3,zero,2fe0 <__divsi3+0x48>
+    2ff8:	38000126 	beq	r7,zero,3000 <__divsi3+0x68>
+    2ffc:	0085c83a 	sub	r2,zero,r2
+    3000:	f800283a 	ret
+    3004:	0109c83a 	sub	r4,zero,r4
+    3008:	01c00044 	movi	r7,1
+    300c:	003fe406 	br	2fa0 <__divsi3+0x8>
+    3010:	0005883a 	mov	r2,zero
+    3014:	003ff806 	br	2ff8 <__divsi3+0x60>
 
-00003060 <__udivsi3>:
-    3060:	200d883a 	mov	r6,r4
-    3064:	2900152e 	bgeu	r5,r4,30bc <__udivsi3+0x5c>
-    3068:	28001416 	blt	r5,zero,30bc <__udivsi3+0x5c>
-    306c:	00800804 	movi	r2,32
-    3070:	00c00044 	movi	r3,1
-    3074:	00000206 	br	3080 <__udivsi3+0x20>
-    3078:	10000e26 	beq	r2,zero,30b4 <__udivsi3+0x54>
-    307c:	28000516 	blt	r5,zero,3094 <__udivsi3+0x34>
-    3080:	294b883a 	add	r5,r5,r5
-    3084:	10bfffc4 	addi	r2,r2,-1
-    3088:	18c7883a 	add	r3,r3,r3
-    308c:	293ffa36 	bltu	r5,r4,3078 <__alt_data_end+0xfffe3078>
-    3090:	18000826 	beq	r3,zero,30b4 <__udivsi3+0x54>
-    3094:	0005883a 	mov	r2,zero
-    3098:	31400236 	bltu	r6,r5,30a4 <__udivsi3+0x44>
-    309c:	314dc83a 	sub	r6,r6,r5
-    30a0:	10c4b03a 	or	r2,r2,r3
-    30a4:	1806d07a 	srli	r3,r3,1
-    30a8:	280ad07a 	srli	r5,r5,1
-    30ac:	183ffa1e 	bne	r3,zero,3098 <__alt_data_end+0xfffe3098>
-    30b0:	f800283a 	ret
-    30b4:	0005883a 	mov	r2,zero
-    30b8:	f800283a 	ret
-    30bc:	00c00044 	movi	r3,1
-    30c0:	003ff406 	br	3094 <__alt_data_end+0xfffe3094>
+00003018 <__modsi3>:
+    3018:	20001916 	blt	r4,zero,3080 <__modsi3+0x68>
+    301c:	000f883a 	mov	r7,zero
+    3020:	2005883a 	mov	r2,r4
+    3024:	2800010e 	bge	r5,zero,302c <__modsi3+0x14>
+    3028:	014bc83a 	sub	r5,zero,r5
+    302c:	00c00044 	movi	r3,1
+    3030:	2900092e 	bgeu	r5,r4,3058 <__modsi3+0x40>
+    3034:	01800804 	movi	r6,32
+    3038:	00c00044 	movi	r3,1
+    303c:	00000106 	br	3044 <__modsi3+0x2c>
+    3040:	30000d26 	beq	r6,zero,3078 <__modsi3+0x60>
+    3044:	294b883a 	add	r5,r5,r5
+    3048:	31bfffc4 	addi	r6,r6,-1
+    304c:	18c7883a 	add	r3,r3,r3
+    3050:	293ffb36 	bltu	r5,r4,3040 <__modsi3+0x28>
+    3054:	18000826 	beq	r3,zero,3078 <__modsi3+0x60>
+    3058:	1806d07a 	srli	r3,r3,1
+    305c:	11400136 	bltu	r2,r5,3064 <__modsi3+0x4c>
+    3060:	1145c83a 	sub	r2,r2,r5
+    3064:	280ad07a 	srli	r5,r5,1
+    3068:	183ffb1e 	bne	r3,zero,3058 <__modsi3+0x40>
+    306c:	38000126 	beq	r7,zero,3074 <__modsi3+0x5c>
+    3070:	0085c83a 	sub	r2,zero,r2
+    3074:	f800283a 	ret
+    3078:	2005883a 	mov	r2,r4
+    307c:	003ffb06 	br	306c <__modsi3+0x54>
+    3080:	0109c83a 	sub	r4,zero,r4
+    3084:	01c00044 	movi	r7,1
+    3088:	003fe506 	br	3020 <__modsi3+0x8>
 
-000030c4 <__umodsi3>:
-    30c4:	2005883a 	mov	r2,r4
-    30c8:	2900122e 	bgeu	r5,r4,3114 <__umodsi3+0x50>
-    30cc:	28001116 	blt	r5,zero,3114 <__umodsi3+0x50>
-    30d0:	01800804 	movi	r6,32
-    30d4:	00c00044 	movi	r3,1
-    30d8:	00000206 	br	30e4 <__umodsi3+0x20>
-    30dc:	30000c26 	beq	r6,zero,3110 <__umodsi3+0x4c>
-    30e0:	28000516 	blt	r5,zero,30f8 <__umodsi3+0x34>
-    30e4:	294b883a 	add	r5,r5,r5
-    30e8:	31bfffc4 	addi	r6,r6,-1
-    30ec:	18c7883a 	add	r3,r3,r3
-    30f0:	293ffa36 	bltu	r5,r4,30dc <__alt_data_end+0xfffe30dc>
-    30f4:	18000626 	beq	r3,zero,3110 <__umodsi3+0x4c>
-    30f8:	1806d07a 	srli	r3,r3,1
-    30fc:	11400136 	bltu	r2,r5,3104 <__umodsi3+0x40>
-    3100:	1145c83a 	sub	r2,r2,r5
-    3104:	280ad07a 	srli	r5,r5,1
-    3108:	183ffb1e 	bne	r3,zero,30f8 <__alt_data_end+0xfffe30f8>
-    310c:	f800283a 	ret
-    3110:	f800283a 	ret
-    3114:	00c00044 	movi	r3,1
-    3118:	003ff706 	br	30f8 <__alt_data_end+0xfffe30f8>
+0000308c <__udivsi3>:
+    308c:	200d883a 	mov	r6,r4
+    3090:	2900152e 	bgeu	r5,r4,30e8 <__udivsi3+0x5c>
+    3094:	28001416 	blt	r5,zero,30e8 <__udivsi3+0x5c>
+    3098:	00800804 	movi	r2,32
+    309c:	00c00044 	movi	r3,1
+    30a0:	00000206 	br	30ac <__udivsi3+0x20>
+    30a4:	10000e26 	beq	r2,zero,30e0 <__udivsi3+0x54>
+    30a8:	28000516 	blt	r5,zero,30c0 <__udivsi3+0x34>
+    30ac:	294b883a 	add	r5,r5,r5
+    30b0:	10bfffc4 	addi	r2,r2,-1
+    30b4:	18c7883a 	add	r3,r3,r3
+    30b8:	293ffa36 	bltu	r5,r4,30a4 <__udivsi3+0x18>
+    30bc:	18000826 	beq	r3,zero,30e0 <__udivsi3+0x54>
+    30c0:	0005883a 	mov	r2,zero
+    30c4:	31400236 	bltu	r6,r5,30d0 <__udivsi3+0x44>
+    30c8:	314dc83a 	sub	r6,r6,r5
+    30cc:	10c4b03a 	or	r2,r2,r3
+    30d0:	1806d07a 	srli	r3,r3,1
+    30d4:	280ad07a 	srli	r5,r5,1
+    30d8:	183ffa1e 	bne	r3,zero,30c4 <__udivsi3+0x38>
+    30dc:	f800283a 	ret
+    30e0:	0005883a 	mov	r2,zero
+    30e4:	f800283a 	ret
+    30e8:	00c00044 	movi	r3,1
+    30ec:	003ff406 	br	30c0 <__udivsi3+0x34>
 
-0000311c <__mulsi3>:
-    311c:	0005883a 	mov	r2,zero
-    3120:	20000726 	beq	r4,zero,3140 <__mulsi3+0x24>
-    3124:	20c0004c 	andi	r3,r4,1
-    3128:	2008d07a 	srli	r4,r4,1
-    312c:	18000126 	beq	r3,zero,3134 <__mulsi3+0x18>
-    3130:	1145883a 	add	r2,r2,r5
-    3134:	294b883a 	add	r5,r5,r5
-    3138:	203ffa1e 	bne	r4,zero,3124 <__alt_data_end+0xfffe3124>
-    313c:	f800283a 	ret
+000030f0 <__umodsi3>:
+    30f0:	2005883a 	mov	r2,r4
+    30f4:	2900132e 	bgeu	r5,r4,3144 <__umodsi3+0x54>
+    30f8:	28001216 	blt	r5,zero,3144 <__umodsi3+0x54>
+    30fc:	01800804 	movi	r6,32
+    3100:	00c00044 	movi	r3,1
+    3104:	00000206 	br	3110 <__umodsi3+0x20>
+    3108:	30000c26 	beq	r6,zero,313c <__umodsi3+0x4c>
+    310c:	28000516 	blt	r5,zero,3124 <__umodsi3+0x34>
+    3110:	294b883a 	add	r5,r5,r5
+    3114:	31bfffc4 	addi	r6,r6,-1
+    3118:	18c7883a 	add	r3,r3,r3
+    311c:	293ffa36 	bltu	r5,r4,3108 <__umodsi3+0x18>
+    3120:	18000626 	beq	r3,zero,313c <__umodsi3+0x4c>
+    3124:	1806d07a 	srli	r3,r3,1
+    3128:	11400136 	bltu	r2,r5,3130 <__umodsi3+0x40>
+    312c:	1145c83a 	sub	r2,r2,r5
+    3130:	280ad07a 	srli	r5,r5,1
+    3134:	183ffb1e 	bne	r3,zero,3124 <__umodsi3+0x34>
+    3138:	f800283a 	ret
+    313c:	2005883a 	mov	r2,r4
     3140:	f800283a 	ret
+    3144:	00c00044 	movi	r3,1
+    3148:	003ff606 	br	3124 <__umodsi3+0x34>
 
-00003144 <alt_get_errno>:
+0000314c <__mulsi3>:
+    314c:	0005883a 	mov	r2,zero
+    3150:	20000726 	beq	r4,zero,3170 <__mulsi3+0x24>
+    3154:	20c0004c 	andi	r3,r4,1
+    3158:	2008d07a 	srli	r4,r4,1
+    315c:	18000126 	beq	r3,zero,3164 <__mulsi3+0x18>
+    3160:	1145883a 	add	r2,r2,r5
+    3164:	294b883a 	add	r5,r5,r5
+    3168:	203ffa1e 	bne	r4,zero,3154 <__mulsi3+0x8>
+    316c:	f800283a 	ret
+    3170:	f800283a 	ret
+
+00003174 <alt_get_errno>:
 #undef errno
 
 extern int errno;
 
 static ALT_INLINE int* alt_get_errno(void)
 {
-    3144:	defffe04 	addi	sp,sp,-8
-    3148:	dfc00115 	stw	ra,4(sp)
-    314c:	df000015 	stw	fp,0(sp)
-    3150:	d839883a 	mov	fp,sp
+    3174:	defffe04 	addi	sp,sp,-8
+    3178:	dfc00115 	stw	ra,4(sp)
+    317c:	df000015 	stw	fp,0(sp)
+    3180:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    3154:	d0a00917 	ldw	r2,-32732(gp)
-    3158:	10000326 	beq	r2,zero,3168 <alt_get_errno+0x24>
-    315c:	d0a00917 	ldw	r2,-32732(gp)
-    3160:	103ee83a 	callr	r2
-    3164:	00000106 	br	316c <alt_get_errno+0x28>
-    3168:	d0a01104 	addi	r2,gp,-32700
+    3184:	d0a00917 	ldw	r2,-32732(gp)
+    3188:	10000326 	beq	r2,zero,3198 <alt_get_errno+0x24>
+    318c:	d0a00917 	ldw	r2,-32732(gp)
+    3190:	103ee83a 	callr	r2
+    3194:	00000106 	br	319c <alt_get_errno+0x28>
+    3198:	d0a01104 	addi	r2,gp,-32700
 }
-    316c:	e037883a 	mov	sp,fp
-    3170:	dfc00117 	ldw	ra,4(sp)
-    3174:	df000017 	ldw	fp,0(sp)
-    3178:	dec00204 	addi	sp,sp,8
-    317c:	f800283a 	ret
+    319c:	e037883a 	mov	sp,fp
+    31a0:	dfc00117 	ldw	ra,4(sp)
+    31a4:	df000017 	ldw	fp,0(sp)
+    31a8:	dec00204 	addi	sp,sp,8
+    31ac:	f800283a 	ret
 
-00003180 <close>:
+000031b0 <close>:
  *
  * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h
  */
  
 int ALT_CLOSE (int fildes)
 {
-    3180:	defffb04 	addi	sp,sp,-20
-    3184:	dfc00415 	stw	ra,16(sp)
-    3188:	df000315 	stw	fp,12(sp)
-    318c:	df000304 	addi	fp,sp,12
-    3190:	e13fff15 	stw	r4,-4(fp)
+    31b0:	defffb04 	addi	sp,sp,-20
+    31b4:	dfc00415 	stw	ra,16(sp)
+    31b8:	df000315 	stw	fp,12(sp)
+    31bc:	df000304 	addi	fp,sp,12
+    31c0:	e13ffd15 	stw	r4,-12(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (fildes < 0) ? NULL : &alt_fd_list[fildes];
-    3194:	e0bfff17 	ldw	r2,-4(fp)
-    3198:	10000816 	blt	r2,zero,31bc <close+0x3c>
-    319c:	01400304 	movi	r5,12
-    31a0:	e13fff17 	ldw	r4,-4(fp)
-    31a4:	000311c0 	call	311c <__mulsi3>
-    31a8:	1007883a 	mov	r3,r2
-    31ac:	00800034 	movhi	r2,0
-    31b0:	10982c04 	addi	r2,r2,24752
-    31b4:	1885883a 	add	r2,r3,r2
-    31b8:	00000106 	br	31c0 <close+0x40>
-    31bc:	0005883a 	mov	r2,zero
-    31c0:	e0bffd15 	stw	r2,-12(fp)
+    31c4:	e0bffd17 	ldw	r2,-12(fp)
+    31c8:	10000916 	blt	r2,zero,31f0 <close+0x40>
+    31cc:	e0fffd17 	ldw	r3,-12(fp)
+    31d0:	1805883a 	mov	r2,r3
+    31d4:	1085883a 	add	r2,r2,r2
+    31d8:	10c5883a 	add	r2,r2,r3
+    31dc:	100490ba 	slli	r2,r2,2
+    31e0:	00c00034 	movhi	r3,0
+    31e4:	18d80004 	addi	r3,r3,24576
+    31e8:	10c5883a 	add	r2,r2,r3
+    31ec:	00000106 	br	31f4 <close+0x44>
+    31f0:	0005883a 	mov	r2,zero
+    31f4:	e0bfff15 	stw	r2,-4(fp)
 
   if (fd)
-    31c4:	e0bffd17 	ldw	r2,-12(fp)
-    31c8:	10001926 	beq	r2,zero,3230 <close+0xb0>
+    31f8:	e0bfff17 	ldw	r2,-4(fp)
+    31fc:	10001926 	beq	r2,zero,3264 <close+0xb4>
     /*
      * If the associated file system/device has a close function, call it so 
      * that any necessary cleanup code can run.
      */
 
     rval = (fd->dev->close) ? fd->dev->close(fd) : 0;
-    31cc:	e0bffd17 	ldw	r2,-12(fp)
-    31d0:	10800017 	ldw	r2,0(r2)
-    31d4:	10800417 	ldw	r2,16(r2)
-    31d8:	10000626 	beq	r2,zero,31f4 <close+0x74>
-    31dc:	e0bffd17 	ldw	r2,-12(fp)
-    31e0:	10800017 	ldw	r2,0(r2)
-    31e4:	10800417 	ldw	r2,16(r2)
-    31e8:	e13ffd17 	ldw	r4,-12(fp)
-    31ec:	103ee83a 	callr	r2
-    31f0:	00000106 	br	31f8 <close+0x78>
-    31f4:	0005883a 	mov	r2,zero
-    31f8:	e0bffe15 	stw	r2,-8(fp)
+    3200:	e0bfff17 	ldw	r2,-4(fp)
+    3204:	10800017 	ldw	r2,0(r2)
+    3208:	10800417 	ldw	r2,16(r2)
+    320c:	10000626 	beq	r2,zero,3228 <close+0x78>
+    3210:	e0bfff17 	ldw	r2,-4(fp)
+    3214:	10800017 	ldw	r2,0(r2)
+    3218:	10800417 	ldw	r2,16(r2)
+    321c:	e13fff17 	ldw	r4,-4(fp)
+    3220:	103ee83a 	callr	r2
+    3224:	00000106 	br	322c <close+0x7c>
+    3228:	0005883a 	mov	r2,zero
+    322c:	e0bffe15 	stw	r2,-8(fp)
 
     /* Free the file descriptor structure and return. */
 
     alt_release_fd (fildes);
-    31fc:	e13fff17 	ldw	r4,-4(fp)
-    3200:	00037a40 	call	37a4 <alt_release_fd>
+    3230:	e13ffd17 	ldw	r4,-12(fp)
+    3234:	00037e80 	call	37e8 <alt_release_fd>
     if (rval < 0)
-    3204:	e0bffe17 	ldw	r2,-8(fp)
-    3208:	1000070e 	bge	r2,zero,3228 <close+0xa8>
+    3238:	e0bffe17 	ldw	r2,-8(fp)
+    323c:	1000070e 	bge	r2,zero,325c <close+0xac>
     {
       ALT_ERRNO = -rval;
-    320c:	00031440 	call	3144 <alt_get_errno>
-    3210:	1007883a 	mov	r3,r2
-    3214:	e0bffe17 	ldw	r2,-8(fp)
-    3218:	0085c83a 	sub	r2,zero,r2
-    321c:	18800015 	stw	r2,0(r3)
+    3240:	00031740 	call	3174 <alt_get_errno>
+    3244:	1007883a 	mov	r3,r2
+    3248:	e0bffe17 	ldw	r2,-8(fp)
+    324c:	0085c83a 	sub	r2,zero,r2
+    3250:	18800015 	stw	r2,0(r3)
       return -1;
-    3220:	00bfffc4 	movi	r2,-1
-    3224:	00000706 	br	3244 <close+0xc4>
+    3254:	00bfffc4 	movi	r2,-1
+    3258:	00000706 	br	3278 <close+0xc8>
     }
     return 0;
-    3228:	0005883a 	mov	r2,zero
-    322c:	00000506 	br	3244 <close+0xc4>
+    325c:	0005883a 	mov	r2,zero
+    3260:	00000506 	br	3278 <close+0xc8>
   }
   else
   {
     ALT_ERRNO = EBADFD;
-    3230:	00031440 	call	3144 <alt_get_errno>
-    3234:	1007883a 	mov	r3,r2
-    3238:	00801444 	movi	r2,81
-    323c:	18800015 	stw	r2,0(r3)
+    3264:	00031740 	call	3174 <alt_get_errno>
+    3268:	1007883a 	mov	r3,r2
+    326c:	00801444 	movi	r2,81
+    3270:	18800015 	stw	r2,0(r3)
     return -1;
-    3240:	00bfffc4 	movi	r2,-1
+    3274:	00bfffc4 	movi	r2,-1
   }
 }
-    3244:	e037883a 	mov	sp,fp
-    3248:	dfc00117 	ldw	ra,4(sp)
-    324c:	df000017 	ldw	fp,0(sp)
-    3250:	dec00204 	addi	sp,sp,8
-    3254:	f800283a 	ret
+    3278:	e037883a 	mov	sp,fp
+    327c:	dfc00117 	ldw	ra,4(sp)
+    3280:	df000017 	ldw	fp,0(sp)
+    3284:	dec00204 	addi	sp,sp,8
+    3288:	f800283a 	ret
 
-00003258 <alt_dcache_flush>:
+0000328c <alt_dcache_flush>:
  *
  * Any dirty lines in the data cache are written back to memory.
  */
 
 void alt_dcache_flush (void* start, alt_u32 len)
 {
-    3258:	defffd04 	addi	sp,sp,-12
-    325c:	df000215 	stw	fp,8(sp)
-    3260:	df000204 	addi	fp,sp,8
-    3264:	e13ffe15 	stw	r4,-8(fp)
-    3268:	e17fff15 	stw	r5,-4(fp)
+    328c:	defffd04 	addi	sp,sp,-12
+    3290:	df000215 	stw	fp,8(sp)
+    3294:	df000204 	addi	fp,sp,8
+    3298:	e13fff15 	stw	r4,-4(fp)
+    329c:	e17ffe15 	stw	r5,-8(fp)
   {
     ALT_FLUSH_DATA(i);
   }
 
 #endif /* NIOS2_DCACHE_SIZE > 0 */
 }
-    326c:	0001883a 	nop
-    3270:	e037883a 	mov	sp,fp
-    3274:	df000017 	ldw	fp,0(sp)
-    3278:	dec00104 	addi	sp,sp,4
-    327c:	f800283a 	ret
+    32a0:	0001883a 	nop
+    32a4:	e037883a 	mov	sp,fp
+    32a8:	df000017 	ldw	fp,0(sp)
+    32ac:	dec00104 	addi	sp,sp,4
+    32b0:	f800283a 	ret
 
-00003280 <alt_dev_null_write>:
+000032b4 <alt_dev_null_write>:
  * by the alt_dev_null device. It simple discards all data passed to it, and
  * indicates that the data has been successfully transmitted.
  */
 
 static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len)
 {
-    3280:	defffc04 	addi	sp,sp,-16
-    3284:	df000315 	stw	fp,12(sp)
-    3288:	df000304 	addi	fp,sp,12
-    328c:	e13ffd15 	stw	r4,-12(fp)
-    3290:	e17ffe15 	stw	r5,-8(fp)
-    3294:	e1bfff15 	stw	r6,-4(fp)
+    32b4:	defffc04 	addi	sp,sp,-16
+    32b8:	df000315 	stw	fp,12(sp)
+    32bc:	df000304 	addi	fp,sp,12
+    32c0:	e13fff15 	stw	r4,-4(fp)
+    32c4:	e17ffe15 	stw	r5,-8(fp)
+    32c8:	e1bffd15 	stw	r6,-12(fp)
   return len;
-    3298:	e0bfff17 	ldw	r2,-4(fp)
+    32cc:	e0bffd17 	ldw	r2,-12(fp)
 }
-    329c:	e037883a 	mov	sp,fp
-    32a0:	df000017 	ldw	fp,0(sp)
-    32a4:	dec00104 	addi	sp,sp,4
-    32a8:	f800283a 	ret
+    32d0:	e037883a 	mov	sp,fp
+    32d4:	df000017 	ldw	fp,0(sp)
+    32d8:	dec00104 	addi	sp,sp,4
+    32dc:	f800283a 	ret
 
-000032ac <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
+000032e0 <alt_get_errno>:
 {
-    32ac:	defffe04 	addi	sp,sp,-8
-    32b0:	dfc00115 	stw	ra,4(sp)
-    32b4:	df000015 	stw	fp,0(sp)
-    32b8:	d839883a 	mov	fp,sp
+    32e0:	defffe04 	addi	sp,sp,-8
+    32e4:	dfc00115 	stw	ra,4(sp)
+    32e8:	df000015 	stw	fp,0(sp)
+    32ec:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    32bc:	d0a00917 	ldw	r2,-32732(gp)
-    32c0:	10000326 	beq	r2,zero,32d0 <alt_get_errno+0x24>
-    32c4:	d0a00917 	ldw	r2,-32732(gp)
-    32c8:	103ee83a 	callr	r2
-    32cc:	00000106 	br	32d4 <alt_get_errno+0x28>
-    32d0:	d0a01104 	addi	r2,gp,-32700
+    32f0:	d0a00917 	ldw	r2,-32732(gp)
+    32f4:	10000326 	beq	r2,zero,3304 <alt_get_errno+0x24>
+    32f8:	d0a00917 	ldw	r2,-32732(gp)
+    32fc:	103ee83a 	callr	r2
+    3300:	00000106 	br	3308 <alt_get_errno+0x28>
+    3304:	d0a01104 	addi	r2,gp,-32700
 }
-    32d4:	e037883a 	mov	sp,fp
-    32d8:	dfc00117 	ldw	ra,4(sp)
-    32dc:	df000017 	ldw	fp,0(sp)
-    32e0:	dec00204 	addi	sp,sp,8
-    32e4:	f800283a 	ret
+    3308:	e037883a 	mov	sp,fp
+    330c:	dfc00117 	ldw	ra,4(sp)
+    3310:	df000017 	ldw	fp,0(sp)
+    3314:	dec00204 	addi	sp,sp,8
+    3318:	f800283a 	ret
 
-000032e8 <fstat>:
+0000331c <fstat>:
 }
 
 #else /* !ALT_USE_DIRECT_DRIVERS */
 
 int ALT_FSTAT (int file, struct stat *st)
 {
-    32e8:	defffb04 	addi	sp,sp,-20
-    32ec:	dfc00415 	stw	ra,16(sp)
-    32f0:	df000315 	stw	fp,12(sp)
-    32f4:	df000304 	addi	fp,sp,12
-    32f8:	e13ffe15 	stw	r4,-8(fp)
-    32fc:	e17fff15 	stw	r5,-4(fp)
+    331c:	defffb04 	addi	sp,sp,-20
+    3320:	dfc00415 	stw	ra,16(sp)
+    3324:	df000315 	stw	fp,12(sp)
+    3328:	df000304 	addi	fp,sp,12
+    332c:	e13ffe15 	stw	r4,-8(fp)
+    3330:	e17ffd15 	stw	r5,-12(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (file < 0) ? NULL : &alt_fd_list[file];
-    3300:	e0bffe17 	ldw	r2,-8(fp)
-    3304:	10000816 	blt	r2,zero,3328 <fstat+0x40>
-    3308:	01400304 	movi	r5,12
-    330c:	e13ffe17 	ldw	r4,-8(fp)
-    3310:	000311c0 	call	311c <__mulsi3>
-    3314:	1007883a 	mov	r3,r2
-    3318:	00800034 	movhi	r2,0
-    331c:	10982c04 	addi	r2,r2,24752
-    3320:	1885883a 	add	r2,r3,r2
-    3324:	00000106 	br	332c <fstat+0x44>
-    3328:	0005883a 	mov	r2,zero
-    332c:	e0bffd15 	stw	r2,-12(fp)
+    3334:	e0bffe17 	ldw	r2,-8(fp)
+    3338:	10000916 	blt	r2,zero,3360 <fstat+0x44>
+    333c:	e0fffe17 	ldw	r3,-8(fp)
+    3340:	1805883a 	mov	r2,r3
+    3344:	1085883a 	add	r2,r2,r2
+    3348:	10c5883a 	add	r2,r2,r3
+    334c:	100490ba 	slli	r2,r2,2
+    3350:	00c00034 	movhi	r3,0
+    3354:	18d80004 	addi	r3,r3,24576
+    3358:	10c5883a 	add	r2,r2,r3
+    335c:	00000106 	br	3364 <fstat+0x48>
+    3360:	0005883a 	mov	r2,zero
+    3364:	e0bfff15 	stw	r2,-4(fp)
   
   if (fd)
-    3330:	e0bffd17 	ldw	r2,-12(fp)
-    3334:	10001026 	beq	r2,zero,3378 <fstat+0x90>
+    3368:	e0bfff17 	ldw	r2,-4(fp)
+    336c:	10001026 	beq	r2,zero,33b0 <fstat+0x94>
   {
     /* Call the drivers fstat() function to fill out the "st" structure. */
 
     if (fd->dev->fstat)
-    3338:	e0bffd17 	ldw	r2,-12(fp)
-    333c:	10800017 	ldw	r2,0(r2)
-    3340:	10800817 	ldw	r2,32(r2)
-    3344:	10000726 	beq	r2,zero,3364 <fstat+0x7c>
+    3370:	e0bfff17 	ldw	r2,-4(fp)
+    3374:	10800017 	ldw	r2,0(r2)
+    3378:	10800817 	ldw	r2,32(r2)
+    337c:	10000726 	beq	r2,zero,339c <fstat+0x80>
     {
       return fd->dev->fstat(fd, st);
-    3348:	e0bffd17 	ldw	r2,-12(fp)
-    334c:	10800017 	ldw	r2,0(r2)
-    3350:	10800817 	ldw	r2,32(r2)
-    3354:	e17fff17 	ldw	r5,-4(fp)
-    3358:	e13ffd17 	ldw	r4,-12(fp)
-    335c:	103ee83a 	callr	r2
-    3360:	00000a06 	br	338c <fstat+0xa4>
+    3380:	e0bfff17 	ldw	r2,-4(fp)
+    3384:	10800017 	ldw	r2,0(r2)
+    3388:	10800817 	ldw	r2,32(r2)
+    338c:	e17ffd17 	ldw	r5,-12(fp)
+    3390:	e13fff17 	ldw	r4,-4(fp)
+    3394:	103ee83a 	callr	r2
+    3398:	00000a06 	br	33c4 <fstat+0xa8>
      * device.
      */
  
     else
     {
       st->st_mode = _IFCHR;
-    3364:	e0bfff17 	ldw	r2,-4(fp)
-    3368:	00c80004 	movi	r3,8192
-    336c:	10c00115 	stw	r3,4(r2)
+    339c:	e0bffd17 	ldw	r2,-12(fp)
+    33a0:	00c80004 	movi	r3,8192
+    33a4:	10c00115 	stw	r3,4(r2)
       return 0;
-    3370:	0005883a 	mov	r2,zero
-    3374:	00000506 	br	338c <fstat+0xa4>
+    33a8:	0005883a 	mov	r2,zero
+    33ac:	00000506 	br	33c4 <fstat+0xa8>
     }
   }
   else
   {
     ALT_ERRNO = EBADFD;
-    3378:	00032ac0 	call	32ac <alt_get_errno>
-    337c:	1007883a 	mov	r3,r2
-    3380:	00801444 	movi	r2,81
-    3384:	18800015 	stw	r2,0(r3)
+    33b0:	00032e00 	call	32e0 <alt_get_errno>
+    33b4:	1007883a 	mov	r3,r2
+    33b8:	00801444 	movi	r2,81
+    33bc:	18800015 	stw	r2,0(r3)
     return -1;
-    3388:	00bfffc4 	movi	r2,-1
+    33c0:	00bfffc4 	movi	r2,-1
   }
 }
-    338c:	e037883a 	mov	sp,fp
-    3390:	dfc00117 	ldw	ra,4(sp)
-    3394:	df000017 	ldw	fp,0(sp)
-    3398:	dec00204 	addi	sp,sp,8
-    339c:	f800283a 	ret
+    33c4:	e037883a 	mov	sp,fp
+    33c8:	dfc00117 	ldw	ra,4(sp)
+    33cc:	df000017 	ldw	fp,0(sp)
+    33d0:	dec00204 	addi	sp,sp,8
+    33d4:	f800283a 	ret
 
-000033a0 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
+000033d8 <alt_get_errno>:
 {
-    33a0:	defffe04 	addi	sp,sp,-8
-    33a4:	dfc00115 	stw	ra,4(sp)
-    33a8:	df000015 	stw	fp,0(sp)
-    33ac:	d839883a 	mov	fp,sp
+    33d8:	defffe04 	addi	sp,sp,-8
+    33dc:	dfc00115 	stw	ra,4(sp)
+    33e0:	df000015 	stw	fp,0(sp)
+    33e4:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    33b0:	d0a00917 	ldw	r2,-32732(gp)
-    33b4:	10000326 	beq	r2,zero,33c4 <alt_get_errno+0x24>
-    33b8:	d0a00917 	ldw	r2,-32732(gp)
-    33bc:	103ee83a 	callr	r2
-    33c0:	00000106 	br	33c8 <alt_get_errno+0x28>
-    33c4:	d0a01104 	addi	r2,gp,-32700
+    33e8:	d0a00917 	ldw	r2,-32732(gp)
+    33ec:	10000326 	beq	r2,zero,33fc <alt_get_errno+0x24>
+    33f0:	d0a00917 	ldw	r2,-32732(gp)
+    33f4:	103ee83a 	callr	r2
+    33f8:	00000106 	br	3400 <alt_get_errno+0x28>
+    33fc:	d0a01104 	addi	r2,gp,-32700
 }
-    33c8:	e037883a 	mov	sp,fp
-    33cc:	dfc00117 	ldw	ra,4(sp)
-    33d0:	df000017 	ldw	fp,0(sp)
-    33d4:	dec00204 	addi	sp,sp,8
-    33d8:	f800283a 	ret
+    3400:	e037883a 	mov	sp,fp
+    3404:	dfc00117 	ldw	ra,4(sp)
+    3408:	df000017 	ldw	fp,0(sp)
+    340c:	dec00204 	addi	sp,sp,8
+    3410:	f800283a 	ret
 
-000033dc <isatty>:
+00003414 <isatty>:
  *
  * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h
  */
  
 int ALT_ISATTY (int file)
 {
-    33dc:	deffed04 	addi	sp,sp,-76
-    33e0:	dfc01215 	stw	ra,72(sp)
-    33e4:	df001115 	stw	fp,68(sp)
-    33e8:	df001104 	addi	fp,sp,68
-    33ec:	e13fff15 	stw	r4,-4(fp)
+    3414:	deffea04 	addi	sp,sp,-88
+    3418:	dfc01515 	stw	ra,84(sp)
+    341c:	df001415 	stw	fp,80(sp)
+    3420:	df001404 	addi	fp,sp,80
+    3424:	e13fec15 	stw	r4,-80(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (file < 0) ? NULL : &alt_fd_list[file];
-    33f0:	e0bfff17 	ldw	r2,-4(fp)
-    33f4:	10000816 	blt	r2,zero,3418 <isatty+0x3c>
-    33f8:	01400304 	movi	r5,12
-    33fc:	e13fff17 	ldw	r4,-4(fp)
-    3400:	000311c0 	call	311c <__mulsi3>
-    3404:	1007883a 	mov	r3,r2
-    3408:	00800034 	movhi	r2,0
-    340c:	10982c04 	addi	r2,r2,24752
-    3410:	1885883a 	add	r2,r3,r2
-    3414:	00000106 	br	341c <isatty+0x40>
-    3418:	0005883a 	mov	r2,zero
-    341c:	e0bfef15 	stw	r2,-68(fp)
+    3428:	e0bfec17 	ldw	r2,-80(fp)
+    342c:	10000916 	blt	r2,zero,3454 <isatty+0x40>
+    3430:	e0ffec17 	ldw	r3,-80(fp)
+    3434:	1805883a 	mov	r2,r3
+    3438:	1085883a 	add	r2,r2,r2
+    343c:	10c5883a 	add	r2,r2,r3
+    3440:	100490ba 	slli	r2,r2,2
+    3444:	00c00034 	movhi	r3,0
+    3448:	18d80004 	addi	r3,r3,24576
+    344c:	10c5883a 	add	r2,r2,r3
+    3450:	00000106 	br	3458 <isatty+0x44>
+    3454:	0005883a 	mov	r2,zero
+    3458:	e0bfff15 	stw	r2,-4(fp)
   
   if (fd)
-    3420:	e0bfef17 	ldw	r2,-68(fp)
-    3424:	10000e26 	beq	r2,zero,3460 <isatty+0x84>
+    345c:	e0bfff17 	ldw	r2,-4(fp)
+    3460:	10000e26 	beq	r2,zero,349c <isatty+0x88>
     /*
      * If a device driver does not provide an fstat() function, then it is 
      * treated as a terminal device by default.
      */
 
     if (!fd->dev->fstat)
-    3428:	e0bfef17 	ldw	r2,-68(fp)
-    342c:	10800017 	ldw	r2,0(r2)
-    3430:	10800817 	ldw	r2,32(r2)
-    3434:	1000021e 	bne	r2,zero,3440 <isatty+0x64>
+    3464:	e0bfff17 	ldw	r2,-4(fp)
+    3468:	10800017 	ldw	r2,0(r2)
+    346c:	10800817 	ldw	r2,32(r2)
+    3470:	1000021e 	bne	r2,zero,347c <isatty+0x68>
     {
       return 1;
-    3438:	00800044 	movi	r2,1
-    343c:	00000d06 	br	3474 <isatty+0x98>
+    3474:	00800044 	movi	r2,1
+    3478:	00000d06 	br	34b0 <isatty+0x9c>
      * this is called so that the device can identify itself.
      */ 
 
     else
     {
       fstat (file, &stat);
-    3440:	e0bff004 	addi	r2,fp,-64
-    3444:	100b883a 	mov	r5,r2
-    3448:	e13fff17 	ldw	r4,-4(fp)
-    344c:	00032e80 	call	32e8 <fstat>
+    347c:	e0bfed04 	addi	r2,fp,-76
+    3480:	100b883a 	mov	r5,r2
+    3484:	e13fec17 	ldw	r4,-80(fp)
+    3488:	000331c0 	call	331c <fstat>
       return (stat.st_mode == _IFCHR) ? 1 : 0;
-    3450:	e0bff117 	ldw	r2,-60(fp)
-    3454:	10880020 	cmpeqi	r2,r2,8192
-    3458:	10803fcc 	andi	r2,r2,255
-    345c:	00000506 	br	3474 <isatty+0x98>
+    348c:	e0bfee17 	ldw	r2,-72(fp)
+    3490:	10880020 	cmpeqi	r2,r2,8192
+    3494:	10803fcc 	andi	r2,r2,255
+    3498:	00000506 	br	34b0 <isatty+0x9c>
     }
   }
   else
   {
     ALT_ERRNO = EBADFD;
-    3460:	00033a00 	call	33a0 <alt_get_errno>
-    3464:	1007883a 	mov	r3,r2
-    3468:	00801444 	movi	r2,81
-    346c:	18800015 	stw	r2,0(r3)
+    349c:	00033d80 	call	33d8 <alt_get_errno>
+    34a0:	1007883a 	mov	r3,r2
+    34a4:	00801444 	movi	r2,81
+    34a8:	18800015 	stw	r2,0(r3)
     return 0;
-    3470:	0005883a 	mov	r2,zero
+    34ac:	0005883a 	mov	r2,zero
   }
-}
-    3474:	e037883a 	mov	sp,fp
-    3478:	dfc00117 	ldw	ra,4(sp)
-    347c:	df000017 	ldw	fp,0(sp)
-    3480:	dec00204 	addi	sp,sp,8
-    3484:	f800283a 	ret
-
-00003488 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
-{
-    3488:	defffe04 	addi	sp,sp,-8
-    348c:	dfc00115 	stw	ra,4(sp)
-    3490:	df000015 	stw	fp,0(sp)
-    3494:	d839883a 	mov	fp,sp
-  return ((alt_errno) ? alt_errno() : &errno);
-    3498:	d0a00917 	ldw	r2,-32732(gp)
-    349c:	10000326 	beq	r2,zero,34ac <alt_get_errno+0x24>
-    34a0:	d0a00917 	ldw	r2,-32732(gp)
-    34a4:	103ee83a 	callr	r2
-    34a8:	00000106 	br	34b0 <alt_get_errno+0x28>
-    34ac:	d0a01104 	addi	r2,gp,-32700
 }
     34b0:	e037883a 	mov	sp,fp
     34b4:	dfc00117 	ldw	ra,4(sp)
@@ -4315,4062 +4276,3734 @@ static ALT_INLINE int* alt_get_errno(void)
     34bc:	dec00204 	addi	sp,sp,8
     34c0:	f800283a 	ret
 
-000034c4 <lseek>:
+000034c4 <alt_get_errno>:
+{
+    34c4:	defffe04 	addi	sp,sp,-8
+    34c8:	dfc00115 	stw	ra,4(sp)
+    34cc:	df000015 	stw	fp,0(sp)
+    34d0:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    34d4:	d0a00917 	ldw	r2,-32732(gp)
+    34d8:	10000326 	beq	r2,zero,34e8 <alt_get_errno+0x24>
+    34dc:	d0a00917 	ldw	r2,-32732(gp)
+    34e0:	103ee83a 	callr	r2
+    34e4:	00000106 	br	34ec <alt_get_errno+0x28>
+    34e8:	d0a01104 	addi	r2,gp,-32700
+}
+    34ec:	e037883a 	mov	sp,fp
+    34f0:	dfc00117 	ldw	ra,4(sp)
+    34f4:	df000017 	ldw	fp,0(sp)
+    34f8:	dec00204 	addi	sp,sp,8
+    34fc:	f800283a 	ret
+
+00003500 <lseek>:
  * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h
  *
  */
 
 off_t ALT_LSEEK (int file, off_t ptr, int dir)
 {
-    34c4:	defff904 	addi	sp,sp,-28
-    34c8:	dfc00615 	stw	ra,24(sp)
-    34cc:	df000515 	stw	fp,20(sp)
-    34d0:	df000504 	addi	fp,sp,20
-    34d4:	e13ffd15 	stw	r4,-12(fp)
-    34d8:	e17ffe15 	stw	r5,-8(fp)
-    34dc:	e1bfff15 	stw	r6,-4(fp)
+    3500:	defff904 	addi	sp,sp,-28
+    3504:	dfc00615 	stw	ra,24(sp)
+    3508:	df000515 	stw	fp,20(sp)
+    350c:	df000504 	addi	fp,sp,20
+    3510:	e13ffd15 	stw	r4,-12(fp)
+    3514:	e17ffc15 	stw	r5,-16(fp)
+    3518:	e1bffb15 	stw	r6,-20(fp)
   alt_fd* fd;
   off_t   rc = 0; 
-    34e0:	e03ffb15 	stw	zero,-20(fp)
+    351c:	e03fff15 	stw	zero,-4(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (file < 0) ? NULL : &alt_fd_list[file];
-    34e4:	e0bffd17 	ldw	r2,-12(fp)
-    34e8:	10000816 	blt	r2,zero,350c <lseek+0x48>
-    34ec:	01400304 	movi	r5,12
-    34f0:	e13ffd17 	ldw	r4,-12(fp)
-    34f4:	000311c0 	call	311c <__mulsi3>
-    34f8:	1007883a 	mov	r3,r2
-    34fc:	00800034 	movhi	r2,0
-    3500:	10982c04 	addi	r2,r2,24752
-    3504:	1885883a 	add	r2,r3,r2
-    3508:	00000106 	br	3510 <lseek+0x4c>
-    350c:	0005883a 	mov	r2,zero
-    3510:	e0bffc15 	stw	r2,-16(fp)
+    3520:	e0bffd17 	ldw	r2,-12(fp)
+    3524:	10000916 	blt	r2,zero,354c <lseek+0x4c>
+    3528:	e0fffd17 	ldw	r3,-12(fp)
+    352c:	1805883a 	mov	r2,r3
+    3530:	1085883a 	add	r2,r2,r2
+    3534:	10c5883a 	add	r2,r2,r3
+    3538:	100490ba 	slli	r2,r2,2
+    353c:	00c00034 	movhi	r3,0
+    3540:	18d80004 	addi	r3,r3,24576
+    3544:	10c5883a 	add	r2,r2,r3
+    3548:	00000106 	br	3550 <lseek+0x50>
+    354c:	0005883a 	mov	r2,zero
+    3550:	e0bffe15 	stw	r2,-8(fp)
   
   if (fd) 
-    3514:	e0bffc17 	ldw	r2,-16(fp)
-    3518:	10001026 	beq	r2,zero,355c <lseek+0x98>
+    3554:	e0bffe17 	ldw	r2,-8(fp)
+    3558:	10001026 	beq	r2,zero,359c <lseek+0x9c>
     /*
      * If the device driver provides an implementation of the lseek() function,
      * then call that to process the request.
      */
  
     if (fd->dev->lseek)
-    351c:	e0bffc17 	ldw	r2,-16(fp)
-    3520:	10800017 	ldw	r2,0(r2)
-    3524:	10800717 	ldw	r2,28(r2)
-    3528:	10000926 	beq	r2,zero,3550 <lseek+0x8c>
+    355c:	e0bffe17 	ldw	r2,-8(fp)
+    3560:	10800017 	ldw	r2,0(r2)
+    3564:	10800717 	ldw	r2,28(r2)
+    3568:	10000926 	beq	r2,zero,3590 <lseek+0x90>
     {
       rc = fd->dev->lseek(fd, ptr, dir);
-    352c:	e0bffc17 	ldw	r2,-16(fp)
-    3530:	10800017 	ldw	r2,0(r2)
-    3534:	10800717 	ldw	r2,28(r2)
-    3538:	e1bfff17 	ldw	r6,-4(fp)
-    353c:	e17ffe17 	ldw	r5,-8(fp)
-    3540:	e13ffc17 	ldw	r4,-16(fp)
-    3544:	103ee83a 	callr	r2
-    3548:	e0bffb15 	stw	r2,-20(fp)
-    354c:	00000506 	br	3564 <lseek+0xa0>
+    356c:	e0bffe17 	ldw	r2,-8(fp)
+    3570:	10800017 	ldw	r2,0(r2)
+    3574:	10800717 	ldw	r2,28(r2)
+    3578:	e1bffb17 	ldw	r6,-20(fp)
+    357c:	e17ffc17 	ldw	r5,-16(fp)
+    3580:	e13ffe17 	ldw	r4,-8(fp)
+    3584:	103ee83a 	callr	r2
+    3588:	e0bfff15 	stw	r2,-4(fp)
+    358c:	00000506 	br	35a4 <lseek+0xa4>
      * Otherwise return an error.
      */
 
     else
     {
       rc = -ENOTSUP;
-    3550:	00bfde84 	movi	r2,-134
-    3554:	e0bffb15 	stw	r2,-20(fp)
-    3558:	00000206 	br	3564 <lseek+0xa0>
+    3590:	00bfde84 	movi	r2,-134
+    3594:	e0bfff15 	stw	r2,-4(fp)
+    3598:	00000206 	br	35a4 <lseek+0xa4>
     }
   }
   else  
   {
     rc = -EBADFD;
-    355c:	00bfebc4 	movi	r2,-81
-    3560:	e0bffb15 	stw	r2,-20(fp)
+    359c:	00bfebc4 	movi	r2,-81
+    35a0:	e0bfff15 	stw	r2,-4(fp)
   }
 
   if (rc < 0)
-    3564:	e0bffb17 	ldw	r2,-20(fp)
-    3568:	1000070e 	bge	r2,zero,3588 <lseek+0xc4>
+    35a4:	e0bfff17 	ldw	r2,-4(fp)
+    35a8:	1000070e 	bge	r2,zero,35c8 <lseek+0xc8>
   {
     ALT_ERRNO = -rc;
-    356c:	00034880 	call	3488 <alt_get_errno>
-    3570:	1007883a 	mov	r3,r2
-    3574:	e0bffb17 	ldw	r2,-20(fp)
-    3578:	0085c83a 	sub	r2,zero,r2
-    357c:	18800015 	stw	r2,0(r3)
+    35ac:	00034c40 	call	34c4 <alt_get_errno>
+    35b0:	1007883a 	mov	r3,r2
+    35b4:	e0bfff17 	ldw	r2,-4(fp)
+    35b8:	0085c83a 	sub	r2,zero,r2
+    35bc:	18800015 	stw	r2,0(r3)
     rc = -1;
-    3580:	00bfffc4 	movi	r2,-1
-    3584:	e0bffb15 	stw	r2,-20(fp)
+    35c0:	00bfffc4 	movi	r2,-1
+    35c4:	e0bfff15 	stw	r2,-4(fp)
   }
 
   return rc;
-    3588:	e0bffb17 	ldw	r2,-20(fp)
+    35c8:	e0bfff17 	ldw	r2,-4(fp)
 }
-    358c:	e037883a 	mov	sp,fp
-    3590:	dfc00117 	ldw	ra,4(sp)
-    3594:	df000017 	ldw	fp,0(sp)
-    3598:	dec00204 	addi	sp,sp,8
-    359c:	f800283a 	ret
+    35cc:	e037883a 	mov	sp,fp
+    35d0:	dfc00117 	ldw	ra,4(sp)
+    35d4:	df000017 	ldw	fp,0(sp)
+    35d8:	dec00204 	addi	sp,sp,8
+    35dc:	f800283a 	ret
 
-000035a0 <alt_main>:
+000035e0 <alt_main>:
  * devices/filesystems/components in the system; and call the entry point for
  * the users application, i.e. main().
  */
 
 void alt_main (void)
 {
-    35a0:	defffd04 	addi	sp,sp,-12
-    35a4:	dfc00215 	stw	ra,8(sp)
-    35a8:	df000115 	stw	fp,4(sp)
-    35ac:	df000104 	addi	fp,sp,4
+    35e0:	defffd04 	addi	sp,sp,-12
+    35e4:	dfc00215 	stw	ra,8(sp)
+    35e8:	df000115 	stw	fp,4(sp)
+    35ec:	df000104 	addi	fp,sp,4
 #endif
 
   /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
   ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
   /* Initialize the interrupt controller. */
   alt_irq_init (NULL);
-    35b0:	0009883a 	mov	r4,zero
-    35b4:	0003a480 	call	3a48 <alt_irq_init>
+    35f0:	0009883a 	mov	r4,zero
+    35f4:	0003a840 	call	3a84 <alt_irq_init>
 
   /* Initialize the operating system */
   ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n");
   ALT_OS_INIT();
-    35b8:	0001883a 	nop
+    35f8:	0001883a 	nop
   ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
   ALT_SEM_CREATE (&alt_fd_list_lock, 1);
 
   /* Initialize the device drivers/software components. */
   ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
   alt_sys_init();
-    35bc:	0003a800 	call	3a80 <alt_sys_init>
+    35fc:	0003ac00 	call	3ac0 <alt_sys_init>
    * devices be present (not equal to /dev/null) and if direct drivers
    * aren't being used.
    */
 
     ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n");
     alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR);
-    35c0:	01800034 	movhi	r6,0
-    35c4:	31960f04 	addi	r6,r6,22588
-    35c8:	01400034 	movhi	r5,0
-    35cc:	29560f04 	addi	r5,r5,22588
-    35d0:	01000034 	movhi	r4,0
-    35d4:	21160f04 	addi	r4,r4,22588
-    35d8:	0004c8c0 	call	4c8c <alt_io_redirect>
+    3600:	01800034 	movhi	r6,0
+    3604:	3195e304 	addi	r6,r6,22412
+    3608:	01400034 	movhi	r5,0
+    360c:	2955e304 	addi	r5,r5,22412
+    3610:	01000034 	movhi	r4,0
+    3614:	2115e304 	addi	r4,r4,22412
+    3618:	0004ce00 	call	4ce0 <alt_io_redirect>
   /* 
    * Call the C++ constructors 
    */
 
   ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n");
   _do_ctors ();
-    35dc:	00048480 	call	4848 <_do_ctors>
+    361c:	00048ac0 	call	48ac <_do_ctors>
    * redefined as _exit()). This is in the interest of reducing code footprint,
    * in that the atexit() overhead is removed when it's not needed.
    */
 
   ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n");
   atexit (_do_dtors);
-    35e0:	01000034 	movhi	r4,0
-    35e4:	21122a04 	addi	r4,r4,18600
-    35e8:	000544c0 	call	544c <atexit>
+    3620:	01000034 	movhi	r4,0
+    3624:	21124404 	addi	r4,r4,18704
+    3628:	000548c0 	call	548c <atexit>
   ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");
 
 #ifdef ALT_NO_EXIT
   main (alt_argc, alt_argv, alt_envp);
 #else
   result = main (alt_argc, alt_argv, alt_envp);
-    35ec:	d0a01217 	ldw	r2,-32696(gp)
-    35f0:	d0e01317 	ldw	r3,-32692(gp)
-    35f4:	d1201417 	ldw	r4,-32688(gp)
-    35f8:	200d883a 	mov	r6,r4
-    35fc:	180b883a 	mov	r5,r3
-    3600:	1009883a 	mov	r4,r2
-    3604:	00002480 	call	248 <main>
-    3608:	e0bfff15 	stw	r2,-4(fp)
+    362c:	d0a01217 	ldw	r2,-32696(gp)
+    3630:	d0e01317 	ldw	r3,-32692(gp)
+    3634:	d1201417 	ldw	r4,-32688(gp)
+    3638:	200d883a 	mov	r6,r4
+    363c:	180b883a 	mov	r5,r3
+    3640:	1009883a 	mov	r4,r2
+    3644:	000023c0 	call	23c <main>
+    3648:	e0bfff15 	stw	r2,-4(fp)
   close(STDOUT_FILENO);
-    360c:	01000044 	movi	r4,1
-    3610:	00031800 	call	3180 <close>
+    364c:	01000044 	movi	r4,1
+    3650:	00031b00 	call	31b0 <close>
   exit (result);
-    3614:	e13fff17 	ldw	r4,-4(fp)
-    3618:	00054600 	call	5460 <exit>
+    3654:	e13fff17 	ldw	r4,-4(fp)
+    3658:	00054a00 	call	54a0 <exit>
 
-0000361c <__malloc_lock>:
+0000365c <__malloc_lock>:
  * configuration is single threaded, so there is nothing to do here. Note that 
  * this requires that malloc is never called by an interrupt service routine.
  */
 
 void __malloc_lock ( struct _reent *_r )
 {
-    361c:	defffe04 	addi	sp,sp,-8
-    3620:	df000115 	stw	fp,4(sp)
-    3624:	df000104 	addi	fp,sp,4
-    3628:	e13fff15 	stw	r4,-4(fp)
+    365c:	defffe04 	addi	sp,sp,-8
+    3660:	df000115 	stw	fp,4(sp)
+    3664:	df000104 	addi	fp,sp,4
+    3668:	e13fff15 	stw	r4,-4(fp)
 }
-    362c:	0001883a 	nop
-    3630:	e037883a 	mov	sp,fp
-    3634:	df000017 	ldw	fp,0(sp)
-    3638:	dec00104 	addi	sp,sp,4
-    363c:	f800283a 	ret
+    366c:	0001883a 	nop
+    3670:	e037883a 	mov	sp,fp
+    3674:	df000017 	ldw	fp,0(sp)
+    3678:	dec00104 	addi	sp,sp,4
+    367c:	f800283a 	ret
 
-00003640 <__malloc_unlock>:
+00003680 <__malloc_unlock>:
 /*
  *
  */
 
 void __malloc_unlock ( struct _reent *_r )
 {
-    3640:	defffe04 	addi	sp,sp,-8
-    3644:	df000115 	stw	fp,4(sp)
-    3648:	df000104 	addi	fp,sp,4
-    364c:	e13fff15 	stw	r4,-4(fp)
+    3680:	defffe04 	addi	sp,sp,-8
+    3684:	df000115 	stw	fp,4(sp)
+    3688:	df000104 	addi	fp,sp,4
+    368c:	e13fff15 	stw	r4,-4(fp)
 }
-    3650:	0001883a 	nop
-    3654:	e037883a 	mov	sp,fp
-    3658:	df000017 	ldw	fp,0(sp)
-    365c:	dec00104 	addi	sp,sp,4
-    3660:	f800283a 	ret
+    3690:	0001883a 	nop
+    3694:	e037883a 	mov	sp,fp
+    3698:	df000017 	ldw	fp,0(sp)
+    369c:	dec00104 	addi	sp,sp,4
+    36a0:	f800283a 	ret
 
-00003664 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
+000036a4 <alt_get_errno>:
 {
-    3664:	defffe04 	addi	sp,sp,-8
-    3668:	dfc00115 	stw	ra,4(sp)
-    366c:	df000015 	stw	fp,0(sp)
-    3670:	d839883a 	mov	fp,sp
+    36a4:	defffe04 	addi	sp,sp,-8
+    36a8:	dfc00115 	stw	ra,4(sp)
+    36ac:	df000015 	stw	fp,0(sp)
+    36b0:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    3674:	d0a00917 	ldw	r2,-32732(gp)
-    3678:	10000326 	beq	r2,zero,3688 <alt_get_errno+0x24>
-    367c:	d0a00917 	ldw	r2,-32732(gp)
-    3680:	103ee83a 	callr	r2
-    3684:	00000106 	br	368c <alt_get_errno+0x28>
-    3688:	d0a01104 	addi	r2,gp,-32700
+    36b4:	d0a00917 	ldw	r2,-32732(gp)
+    36b8:	10000326 	beq	r2,zero,36c8 <alt_get_errno+0x24>
+    36bc:	d0a00917 	ldw	r2,-32732(gp)
+    36c0:	103ee83a 	callr	r2
+    36c4:	00000106 	br	36cc <alt_get_errno+0x28>
+    36c8:	d0a01104 	addi	r2,gp,-32700
 }
-    368c:	e037883a 	mov	sp,fp
-    3690:	dfc00117 	ldw	ra,4(sp)
-    3694:	df000017 	ldw	fp,0(sp)
-    3698:	dec00204 	addi	sp,sp,8
-    369c:	f800283a 	ret
+    36cc:	e037883a 	mov	sp,fp
+    36d0:	dfc00117 	ldw	ra,4(sp)
+    36d4:	df000017 	ldw	fp,0(sp)
+    36d8:	dec00204 	addi	sp,sp,8
+    36dc:	f800283a 	ret
 
-000036a0 <read>:
+000036e0 <read>:
 }
 
 #else /* !ALT_USE_DIRECT_DRIVERS */
 
 int ALT_READ (int file, void *ptr, size_t len)
 {
-    36a0:	defff904 	addi	sp,sp,-28
-    36a4:	dfc00615 	stw	ra,24(sp)
-    36a8:	df000515 	stw	fp,20(sp)
-    36ac:	df000504 	addi	fp,sp,20
-    36b0:	e13ffd15 	stw	r4,-12(fp)
-    36b4:	e17ffe15 	stw	r5,-8(fp)
-    36b8:	e1bfff15 	stw	r6,-4(fp)
+    36e0:	defff904 	addi	sp,sp,-28
+    36e4:	dfc00615 	stw	ra,24(sp)
+    36e8:	df000515 	stw	fp,20(sp)
+    36ec:	df000504 	addi	fp,sp,20
+    36f0:	e13ffd15 	stw	r4,-12(fp)
+    36f4:	e17ffc15 	stw	r5,-16(fp)
+    36f8:	e1bffb15 	stw	r6,-20(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (file < 0) ? NULL : &alt_fd_list[file];
-    36bc:	e0bffd17 	ldw	r2,-12(fp)
-    36c0:	10000816 	blt	r2,zero,36e4 <read+0x44>
-    36c4:	01400304 	movi	r5,12
-    36c8:	e13ffd17 	ldw	r4,-12(fp)
-    36cc:	000311c0 	call	311c <__mulsi3>
-    36d0:	1007883a 	mov	r3,r2
-    36d4:	00800034 	movhi	r2,0
-    36d8:	10982c04 	addi	r2,r2,24752
-    36dc:	1885883a 	add	r2,r3,r2
-    36e0:	00000106 	br	36e8 <read+0x48>
-    36e4:	0005883a 	mov	r2,zero
-    36e8:	e0bffb15 	stw	r2,-20(fp)
+    36fc:	e0bffd17 	ldw	r2,-12(fp)
+    3700:	10000916 	blt	r2,zero,3728 <read+0x48>
+    3704:	e0fffd17 	ldw	r3,-12(fp)
+    3708:	1805883a 	mov	r2,r3
+    370c:	1085883a 	add	r2,r2,r2
+    3710:	10c5883a 	add	r2,r2,r3
+    3714:	100490ba 	slli	r2,r2,2
+    3718:	00c00034 	movhi	r3,0
+    371c:	18d80004 	addi	r3,r3,24576
+    3720:	10c5883a 	add	r2,r2,r3
+    3724:	00000106 	br	372c <read+0x4c>
+    3728:	0005883a 	mov	r2,zero
+    372c:	e0bfff15 	stw	r2,-4(fp)
   
   if (fd)
-    36ec:	e0bffb17 	ldw	r2,-20(fp)
-    36f0:	10002226 	beq	r2,zero,377c <read+0xdc>
+    3730:	e0bfff17 	ldw	r2,-4(fp)
+    3734:	10002226 	beq	r2,zero,37c0 <read+0xe0>
      * If the file has not been opened with read access, or if the driver does
      * not provide an implementation of read(), generate an error. Otherwise
      * call the drivers read() function to process the request.
      */
 
     if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
-    36f4:	e0bffb17 	ldw	r2,-20(fp)
-    36f8:	10800217 	ldw	r2,8(r2)
-    36fc:	108000cc 	andi	r2,r2,3
-    3700:	10800060 	cmpeqi	r2,r2,1
-    3704:	1000181e 	bne	r2,zero,3768 <read+0xc8>
+    3738:	e0bfff17 	ldw	r2,-4(fp)
+    373c:	10800217 	ldw	r2,8(r2)
+    3740:	108000cc 	andi	r2,r2,3
+    3744:	10800060 	cmpeqi	r2,r2,1
+    3748:	1000181e 	bne	r2,zero,37ac <read+0xcc>
         (fd->dev->read))
-    3708:	e0bffb17 	ldw	r2,-20(fp)
-    370c:	10800017 	ldw	r2,0(r2)
-    3710:	10800517 	ldw	r2,20(r2)
-     * If the file has not been opened with read access, or if the driver does
-     * not provide an implementation of read(), generate an error. Otherwise
-     * call the drivers read() function to process the request.
-     */
-
+    374c:	e0bfff17 	ldw	r2,-4(fp)
+    3750:	10800017 	ldw	r2,0(r2)
+    3754:	10800517 	ldw	r2,20(r2)
     if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
-    3714:	10001426 	beq	r2,zero,3768 <read+0xc8>
-        (fd->dev->read))
+    3758:	10001426 	beq	r2,zero,37ac <read+0xcc>
       {
         if ((rval = fd->dev->read(fd, ptr, len)) < 0)
-    3718:	e0bffb17 	ldw	r2,-20(fp)
-    371c:	10800017 	ldw	r2,0(r2)
-    3720:	10800517 	ldw	r2,20(r2)
-    3724:	e0ffff17 	ldw	r3,-4(fp)
-    3728:	180d883a 	mov	r6,r3
-    372c:	e17ffe17 	ldw	r5,-8(fp)
-    3730:	e13ffb17 	ldw	r4,-20(fp)
-    3734:	103ee83a 	callr	r2
-    3738:	e0bffc15 	stw	r2,-16(fp)
-    373c:	e0bffc17 	ldw	r2,-16(fp)
-    3740:	1000070e 	bge	r2,zero,3760 <read+0xc0>
+    375c:	e0bfff17 	ldw	r2,-4(fp)
+    3760:	10800017 	ldw	r2,0(r2)
+    3764:	10800517 	ldw	r2,20(r2)
+    3768:	e0fffb17 	ldw	r3,-20(fp)
+    376c:	180d883a 	mov	r6,r3
+    3770:	e17ffc17 	ldw	r5,-16(fp)
+    3774:	e13fff17 	ldw	r4,-4(fp)
+    3778:	103ee83a 	callr	r2
+    377c:	e0bffe15 	stw	r2,-8(fp)
+    3780:	e0bffe17 	ldw	r2,-8(fp)
+    3784:	1000070e 	bge	r2,zero,37a4 <read+0xc4>
         {
           ALT_ERRNO = -rval;
-    3744:	00036640 	call	3664 <alt_get_errno>
-    3748:	1007883a 	mov	r3,r2
-    374c:	e0bffc17 	ldw	r2,-16(fp)
-    3750:	0085c83a 	sub	r2,zero,r2
-    3754:	18800015 	stw	r2,0(r3)
+    3788:	00036a40 	call	36a4 <alt_get_errno>
+    378c:	1007883a 	mov	r3,r2
+    3790:	e0bffe17 	ldw	r2,-8(fp)
+    3794:	0085c83a 	sub	r2,zero,r2
+    3798:	18800015 	stw	r2,0(r3)
           return -1;
-    3758:	00bfffc4 	movi	r2,-1
-    375c:	00000c06 	br	3790 <read+0xf0>
+    379c:	00bfffc4 	movi	r2,-1
+    37a0:	00000c06 	br	37d4 <read+0xf4>
         }
         return rval;
-    3760:	e0bffc17 	ldw	r2,-16(fp)
-    3764:	00000a06 	br	3790 <read+0xf0>
+    37a4:	e0bffe17 	ldw	r2,-8(fp)
+    37a8:	00000a06 	br	37d4 <read+0xf4>
       }
       else
       {
         ALT_ERRNO = EACCES;
-    3768:	00036640 	call	3664 <alt_get_errno>
-    376c:	1007883a 	mov	r3,r2
-    3770:	00800344 	movi	r2,13
-    3774:	18800015 	stw	r2,0(r3)
-    3778:	00000406 	br	378c <read+0xec>
+    37ac:	00036a40 	call	36a4 <alt_get_errno>
+    37b0:	1007883a 	mov	r3,r2
+    37b4:	00800344 	movi	r2,13
+    37b8:	18800015 	stw	r2,0(r3)
+    37bc:	00000406 	br	37d0 <read+0xf0>
       }
     }
   else
   {
     ALT_ERRNO = EBADFD;
-    377c:	00036640 	call	3664 <alt_get_errno>
-    3780:	1007883a 	mov	r3,r2
-    3784:	00801444 	movi	r2,81
-    3788:	18800015 	stw	r2,0(r3)
+    37c0:	00036a40 	call	36a4 <alt_get_errno>
+    37c4:	1007883a 	mov	r3,r2
+    37c8:	00801444 	movi	r2,81
+    37cc:	18800015 	stw	r2,0(r3)
   }
   return -1;
-    378c:	00bfffc4 	movi	r2,-1
+    37d0:	00bfffc4 	movi	r2,-1
 }
-    3790:	e037883a 	mov	sp,fp
-    3794:	dfc00117 	ldw	ra,4(sp)
-    3798:	df000017 	ldw	fp,0(sp)
-    379c:	dec00204 	addi	sp,sp,8
-    37a0:	f800283a 	ret
+    37d4:	e037883a 	mov	sp,fp
+    37d8:	dfc00117 	ldw	ra,4(sp)
+    37dc:	df000017 	ldw	fp,0(sp)
+    37e0:	dec00204 	addi	sp,sp,8
+    37e4:	f800283a 	ret
 
-000037a4 <alt_release_fd>:
+000037e8 <alt_release_fd>:
  * File descriptors correcponding to standard in, standard out and standard 
  * error cannont be released backed to the pool. They are always reserved.
  */
 
 void alt_release_fd (int fd)
 {
-    37a4:	defffc04 	addi	sp,sp,-16
-    37a8:	dfc00315 	stw	ra,12(sp)
-    37ac:	df000215 	stw	fp,8(sp)
-    37b0:	dc000115 	stw	r16,4(sp)
-    37b4:	df000204 	addi	fp,sp,8
-    37b8:	e13ffe15 	stw	r4,-8(fp)
+    37e8:	defffe04 	addi	sp,sp,-8
+    37ec:	df000115 	stw	fp,4(sp)
+    37f0:	df000104 	addi	fp,sp,4
+    37f4:	e13fff15 	stw	r4,-4(fp)
   if (fd > 2)
-    37bc:	e0bffe17 	ldw	r2,-8(fp)
-    37c0:	108000d0 	cmplti	r2,r2,3
-    37c4:	1000111e 	bne	r2,zero,380c <alt_release_fd+0x68>
+    37f8:	e0bfff17 	ldw	r2,-4(fp)
+    37fc:	108000d0 	cmplti	r2,r2,3
+    3800:	1000101e 	bne	r2,zero,3844 <alt_release_fd+0x5c>
   {
     alt_fd_list[fd].fd_flags = 0;
-    37c8:	04000034 	movhi	r16,0
-    37cc:	84182c04 	addi	r16,r16,24752
-    37d0:	e0bffe17 	ldw	r2,-8(fp)
-    37d4:	01400304 	movi	r5,12
-    37d8:	1009883a 	mov	r4,r2
-    37dc:	000311c0 	call	311c <__mulsi3>
-    37e0:	8085883a 	add	r2,r16,r2
-    37e4:	10800204 	addi	r2,r2,8
-    37e8:	10000015 	stw	zero,0(r2)
+    3804:	e0ffff17 	ldw	r3,-4(fp)
+    3808:	1805883a 	mov	r2,r3
+    380c:	1085883a 	add	r2,r2,r2
+    3810:	10c5883a 	add	r2,r2,r3
+    3814:	100490ba 	slli	r2,r2,2
+    3818:	00c00034 	movhi	r3,0
+    381c:	10c7883a 	add	r3,r2,r3
+    3820:	18180215 	stw	zero,24584(r3)
     alt_fd_list[fd].dev      = 0;
-    37ec:	04000034 	movhi	r16,0
-    37f0:	84182c04 	addi	r16,r16,24752
-    37f4:	e0bffe17 	ldw	r2,-8(fp)
-    37f8:	01400304 	movi	r5,12
-    37fc:	1009883a 	mov	r4,r2
-    3800:	000311c0 	call	311c <__mulsi3>
-    3804:	8085883a 	add	r2,r16,r2
-    3808:	10000015 	stw	zero,0(r2)
+    3824:	e0ffff17 	ldw	r3,-4(fp)
+    3828:	1805883a 	mov	r2,r3
+    382c:	1085883a 	add	r2,r2,r2
+    3830:	10c5883a 	add	r2,r2,r3
+    3834:	100490ba 	slli	r2,r2,2
+    3838:	00c00034 	movhi	r3,0
+    383c:	10c7883a 	add	r3,r2,r3
+    3840:	18180015 	stw	zero,24576(r3)
   }
 }
-    380c:	0001883a 	nop
-    3810:	e6ffff04 	addi	sp,fp,-4
-    3814:	dfc00217 	ldw	ra,8(sp)
-    3818:	df000117 	ldw	fp,4(sp)
-    381c:	dc000017 	ldw	r16,0(sp)
-    3820:	dec00304 	addi	sp,sp,12
-    3824:	f800283a 	ret
+    3844:	0001883a 	nop
+    3848:	e037883a 	mov	sp,fp
+    384c:	df000017 	ldw	fp,0(sp)
+    3850:	dec00104 	addi	sp,sp,4
+    3854:	f800283a 	ret
 
-00003828 <sbrk>:
+00003858 <sbrk>:
 #endif
  
 caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function ));
 
 caddr_t ALT_SBRK (int incr)
 { 
-    3828:	defff904 	addi	sp,sp,-28
-    382c:	df000615 	stw	fp,24(sp)
-    3830:	df000604 	addi	fp,sp,24
-    3834:	e13fff15 	stw	r4,-4(fp)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    3858:	defff904 	addi	sp,sp,-28
+    385c:	df000615 	stw	fp,24(sp)
+    3860:	df000604 	addi	fp,sp,24
+    3864:	e13ffa15 	stw	r4,-24(fp)
   NIOS2_READ_STATUS (context);
-    3838:	0005303a 	rdctl	r2,status
-    383c:	e0bffe15 	stw	r2,-8(fp)
-
+    3868:	0005303a 	rdctl	r2,status
+    386c:	e0bffd15 	stw	r2,-12(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    3840:	e0fffe17 	ldw	r3,-8(fp)
-    3844:	00bfff84 	movi	r2,-2
-    3848:	1884703a 	and	r2,r3,r2
-    384c:	1001703a 	wrctl	status,r2
-  
+    3870:	e0fffd17 	ldw	r3,-12(fp)
+    3874:	00bfff84 	movi	r2,-2
+    3878:	1884703a 	and	r2,r3,r2
+    387c:	1001703a 	wrctl	status,r2
   return context;
-    3850:	e0bffe17 	ldw	r2,-8(fp)
+    3880:	e0bffd17 	ldw	r2,-12(fp)
   alt_irq_context context;
   char *prev_heap_end; 
 
   context = alt_irq_disable_all();
-    3854:	e0bffb15 	stw	r2,-20(fp)
+    3884:	e0bfff15 	stw	r2,-4(fp)
 
   /* Always return data aligned on a word boundary */
   heap_end = (char *)(((unsigned int)heap_end + 3) & ~3);
-    3858:	d0a00a17 	ldw	r2,-32728(gp)
-    385c:	10c000c4 	addi	r3,r2,3
-    3860:	00bfff04 	movi	r2,-4
-    3864:	1884703a 	and	r2,r3,r2
-    3868:	d0a00a15 	stw	r2,-32728(gp)
+    3888:	d0a00a17 	ldw	r2,-32728(gp)
+    388c:	10c000c4 	addi	r3,r2,3
+    3890:	00bfff04 	movi	r2,-4
+    3894:	1884703a 	and	r2,r3,r2
+    3898:	d0a00a15 	stw	r2,-32728(gp)
   if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) {
     alt_irq_enable_all(context);
     return (caddr_t)-1;
   }
 #else
   if ((heap_end + incr) > __alt_heap_limit) {
-    386c:	d0e00a17 	ldw	r3,-32728(gp)
-    3870:	e0bfff17 	ldw	r2,-4(fp)
-    3874:	1887883a 	add	r3,r3,r2
-    3878:	008000b4 	movhi	r2,2
-    387c:	10800004 	addi	r2,r2,0
-    3880:	10c0062e 	bgeu	r2,r3,389c <sbrk+0x74>
-    3884:	e0bffb17 	ldw	r2,-20(fp)
-    3888:	e0bffa15 	stw	r2,-24(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    389c:	d0e00a17 	ldw	r3,-32728(gp)
+    38a0:	e0bffa17 	ldw	r2,-24(fp)
+    38a4:	1887883a 	add	r3,r3,r2
+    38a8:	008000b4 	movhi	r2,2
+    38ac:	10800004 	addi	r2,r2,0
+    38b0:	10c0072e 	bgeu	r2,r3,38d0 <sbrk+0x78>
+    38b4:	e0bfff17 	ldw	r2,-4(fp)
+    38b8:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context);
-    388c:	e0bffa17 	ldw	r2,-24(fp)
-    3890:	1001703a 	wrctl	status,r2
+    38bc:	e0bffc17 	ldw	r2,-16(fp)
+    38c0:	1001703a 	wrctl	status,r2
+}
+    38c4:	0001883a 	nop
     alt_irq_enable_all(context);
     return (caddr_t)-1;
-    3894:	00bfffc4 	movi	r2,-1
-    3898:	00000b06 	br	38c8 <sbrk+0xa0>
+    38c8:	00bfffc4 	movi	r2,-1
+    38cc:	00000c06 	br	3900 <sbrk+0xa8>
   }
 #endif
 
   prev_heap_end = heap_end; 
-    389c:	d0a00a17 	ldw	r2,-32728(gp)
-    38a0:	e0bffd15 	stw	r2,-12(fp)
+    38d0:	d0a00a17 	ldw	r2,-32728(gp)
+    38d4:	e0bffe15 	stw	r2,-8(fp)
   heap_end += incr; 
-    38a4:	d0e00a17 	ldw	r3,-32728(gp)
-    38a8:	e0bfff17 	ldw	r2,-4(fp)
-    38ac:	1885883a 	add	r2,r3,r2
-    38b0:	d0a00a15 	stw	r2,-32728(gp)
-    38b4:	e0bffb17 	ldw	r2,-20(fp)
-    38b8:	e0bffc15 	stw	r2,-16(fp)
-    38bc:	e0bffc17 	ldw	r2,-16(fp)
-    38c0:	1001703a 	wrctl	status,r2
+    38d8:	d0e00a17 	ldw	r3,-32728(gp)
+    38dc:	e0bffa17 	ldw	r2,-24(fp)
+    38e0:	1885883a 	add	r2,r3,r2
+    38e4:	d0a00a15 	stw	r2,-32728(gp)
+    38e8:	e0bfff17 	ldw	r2,-4(fp)
+    38ec:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+    38f0:	e0bffb17 	ldw	r2,-20(fp)
+    38f4:	1001703a 	wrctl	status,r2
+}
+    38f8:	0001883a 	nop
 
 #endif
 
   alt_irq_enable_all(context);
 
   return (caddr_t) prev_heap_end; 
-    38c4:	e0bffd17 	ldw	r2,-12(fp)
+    38fc:	e0bffe17 	ldw	r2,-8(fp)
 } 
-    38c8:	e037883a 	mov	sp,fp
-    38cc:	df000017 	ldw	fp,0(sp)
-    38d0:	dec00104 	addi	sp,sp,4
-    38d4:	f800283a 	ret
-
-000038d8 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
-{
-    38d8:	defffe04 	addi	sp,sp,-8
-    38dc:	dfc00115 	stw	ra,4(sp)
-    38e0:	df000015 	stw	fp,0(sp)
-    38e4:	d839883a 	mov	fp,sp
-  return ((alt_errno) ? alt_errno() : &errno);
-    38e8:	d0a00917 	ldw	r2,-32732(gp)
-    38ec:	10000326 	beq	r2,zero,38fc <alt_get_errno+0x24>
-    38f0:	d0a00917 	ldw	r2,-32732(gp)
-    38f4:	103ee83a 	callr	r2
-    38f8:	00000106 	br	3900 <alt_get_errno+0x28>
-    38fc:	d0a01104 	addi	r2,gp,-32700
-}
     3900:	e037883a 	mov	sp,fp
-    3904:	dfc00117 	ldw	ra,4(sp)
-    3908:	df000017 	ldw	fp,0(sp)
-    390c:	dec00204 	addi	sp,sp,8
-    3910:	f800283a 	ret
+    3904:	df000017 	ldw	fp,0(sp)
+    3908:	dec00104 	addi	sp,sp,4
+    390c:	f800283a 	ret
 
-00003914 <write>:
+00003910 <alt_get_errno>:
+{
+    3910:	defffe04 	addi	sp,sp,-8
+    3914:	dfc00115 	stw	ra,4(sp)
+    3918:	df000015 	stw	fp,0(sp)
+    391c:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    3920:	d0a00917 	ldw	r2,-32732(gp)
+    3924:	10000326 	beq	r2,zero,3934 <alt_get_errno+0x24>
+    3928:	d0a00917 	ldw	r2,-32732(gp)
+    392c:	103ee83a 	callr	r2
+    3930:	00000106 	br	3938 <alt_get_errno+0x28>
+    3934:	d0a01104 	addi	r2,gp,-32700
+}
+    3938:	e037883a 	mov	sp,fp
+    393c:	dfc00117 	ldw	ra,4(sp)
+    3940:	df000017 	ldw	fp,0(sp)
+    3944:	dec00204 	addi	sp,sp,8
+    3948:	f800283a 	ret
+
+0000394c <write>:
 }
 
 #else /* !ALT_USE_DIRECT_DRIVERS */
 
 int ALT_WRITE (int file, const void *ptr, size_t len)
 {
-    3914:	defff904 	addi	sp,sp,-28
-    3918:	dfc00615 	stw	ra,24(sp)
-    391c:	df000515 	stw	fp,20(sp)
-    3920:	df000504 	addi	fp,sp,20
-    3924:	e13ffd15 	stw	r4,-12(fp)
-    3928:	e17ffe15 	stw	r5,-8(fp)
-    392c:	e1bfff15 	stw	r6,-4(fp)
+    394c:	defff904 	addi	sp,sp,-28
+    3950:	dfc00615 	stw	ra,24(sp)
+    3954:	df000515 	stw	fp,20(sp)
+    3958:	df000504 	addi	fp,sp,20
+    395c:	e13ffd15 	stw	r4,-12(fp)
+    3960:	e17ffc15 	stw	r5,-16(fp)
+    3964:	e1bffb15 	stw	r6,-20(fp)
    * A common error case is that when the file descriptor was created, the call
    * to open() failed resulting in a negative file descriptor. This is trapped
    * below so that we don't try and process an invalid file descriptor.
    */
 
   fd = (file < 0) ? NULL : &alt_fd_list[file];
-    3930:	e0bffd17 	ldw	r2,-12(fp)
-    3934:	10000816 	blt	r2,zero,3958 <write+0x44>
-    3938:	01400304 	movi	r5,12
-    393c:	e13ffd17 	ldw	r4,-12(fp)
-    3940:	000311c0 	call	311c <__mulsi3>
-    3944:	1007883a 	mov	r3,r2
-    3948:	00800034 	movhi	r2,0
-    394c:	10982c04 	addi	r2,r2,24752
-    3950:	1885883a 	add	r2,r3,r2
-    3954:	00000106 	br	395c <write+0x48>
-    3958:	0005883a 	mov	r2,zero
-    395c:	e0bffb15 	stw	r2,-20(fp)
+    3968:	e0bffd17 	ldw	r2,-12(fp)
+    396c:	10000916 	blt	r2,zero,3994 <write+0x48>
+    3970:	e0fffd17 	ldw	r3,-12(fp)
+    3974:	1805883a 	mov	r2,r3
+    3978:	1085883a 	add	r2,r2,r2
+    397c:	10c5883a 	add	r2,r2,r3
+    3980:	100490ba 	slli	r2,r2,2
+    3984:	00c00034 	movhi	r3,0
+    3988:	18d80004 	addi	r3,r3,24576
+    398c:	10c5883a 	add	r2,r2,r3
+    3990:	00000106 	br	3998 <write+0x4c>
+    3994:	0005883a 	mov	r2,zero
+    3998:	e0bfff15 	stw	r2,-4(fp)
   
   if (fd)
-    3960:	e0bffb17 	ldw	r2,-20(fp)
-    3964:	10002126 	beq	r2,zero,39ec <write+0xd8>
+    399c:	e0bfff17 	ldw	r2,-4(fp)
+    39a0:	10002126 	beq	r2,zero,3a28 <write+0xdc>
      * If the file has not been opened with write access, or if the driver does
      * not provide an implementation of write(), generate an error. Otherwise
      * call the drivers write() function to process the request.
      */
 
     if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write)
-    3968:	e0bffb17 	ldw	r2,-20(fp)
-    396c:	10800217 	ldw	r2,8(r2)
-    3970:	108000cc 	andi	r2,r2,3
-    3974:	10001826 	beq	r2,zero,39d8 <write+0xc4>
-    3978:	e0bffb17 	ldw	r2,-20(fp)
-    397c:	10800017 	ldw	r2,0(r2)
-    3980:	10800617 	ldw	r2,24(r2)
-    3984:	10001426 	beq	r2,zero,39d8 <write+0xc4>
+    39a4:	e0bfff17 	ldw	r2,-4(fp)
+    39a8:	10800217 	ldw	r2,8(r2)
+    39ac:	108000cc 	andi	r2,r2,3
+    39b0:	10001826 	beq	r2,zero,3a14 <write+0xc8>
+    39b4:	e0bfff17 	ldw	r2,-4(fp)
+    39b8:	10800017 	ldw	r2,0(r2)
+    39bc:	10800617 	ldw	r2,24(r2)
+    39c0:	10001426 	beq	r2,zero,3a14 <write+0xc8>
     {
       
       /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
       ALT_LOG_WRITE_FUNCTION(ptr,len);
 
       if ((rval = fd->dev->write(fd, ptr, len)) < 0)
-    3988:	e0bffb17 	ldw	r2,-20(fp)
-    398c:	10800017 	ldw	r2,0(r2)
-    3990:	10800617 	ldw	r2,24(r2)
-    3994:	e0ffff17 	ldw	r3,-4(fp)
-    3998:	180d883a 	mov	r6,r3
-    399c:	e17ffe17 	ldw	r5,-8(fp)
-    39a0:	e13ffb17 	ldw	r4,-20(fp)
-    39a4:	103ee83a 	callr	r2
-    39a8:	e0bffc15 	stw	r2,-16(fp)
-    39ac:	e0bffc17 	ldw	r2,-16(fp)
-    39b0:	1000070e 	bge	r2,zero,39d0 <write+0xbc>
+    39c4:	e0bfff17 	ldw	r2,-4(fp)
+    39c8:	10800017 	ldw	r2,0(r2)
+    39cc:	10800617 	ldw	r2,24(r2)
+    39d0:	e0fffb17 	ldw	r3,-20(fp)
+    39d4:	180d883a 	mov	r6,r3
+    39d8:	e17ffc17 	ldw	r5,-16(fp)
+    39dc:	e13fff17 	ldw	r4,-4(fp)
+    39e0:	103ee83a 	callr	r2
+    39e4:	e0bffe15 	stw	r2,-8(fp)
+    39e8:	e0bffe17 	ldw	r2,-8(fp)
+    39ec:	1000070e 	bge	r2,zero,3a0c <write+0xc0>
       {
         ALT_ERRNO = -rval;
-    39b4:	00038d80 	call	38d8 <alt_get_errno>
-    39b8:	1007883a 	mov	r3,r2
-    39bc:	e0bffc17 	ldw	r2,-16(fp)
-    39c0:	0085c83a 	sub	r2,zero,r2
-    39c4:	18800015 	stw	r2,0(r3)
+    39f0:	00039100 	call	3910 <alt_get_errno>
+    39f4:	1007883a 	mov	r3,r2
+    39f8:	e0bffe17 	ldw	r2,-8(fp)
+    39fc:	0085c83a 	sub	r2,zero,r2
+    3a00:	18800015 	stw	r2,0(r3)
         return -1;
-    39c8:	00bfffc4 	movi	r2,-1
-    39cc:	00000c06 	br	3a00 <write+0xec>
+    3a04:	00bfffc4 	movi	r2,-1
+    3a08:	00000c06 	br	3a3c <write+0xf0>
       }
       return rval;
-    39d0:	e0bffc17 	ldw	r2,-16(fp)
-    39d4:	00000a06 	br	3a00 <write+0xec>
+    3a0c:	e0bffe17 	ldw	r2,-8(fp)
+    3a10:	00000a06 	br	3a3c <write+0xf0>
     }
     else
     {
       ALT_ERRNO = EACCES;
-    39d8:	00038d80 	call	38d8 <alt_get_errno>
-    39dc:	1007883a 	mov	r3,r2
-    39e0:	00800344 	movi	r2,13
-    39e4:	18800015 	stw	r2,0(r3)
-    39e8:	00000406 	br	39fc <write+0xe8>
+    3a14:	00039100 	call	3910 <alt_get_errno>
+    3a18:	1007883a 	mov	r3,r2
+    3a1c:	00800344 	movi	r2,13
+    3a20:	18800015 	stw	r2,0(r3)
+    3a24:	00000406 	br	3a38 <write+0xec>
     }
   }
   else  
   {
     ALT_ERRNO = EBADFD;
-    39ec:	00038d80 	call	38d8 <alt_get_errno>
-    39f0:	1007883a 	mov	r3,r2
-    39f4:	00801444 	movi	r2,81
-    39f8:	18800015 	stw	r2,0(r3)
+    3a28:	00039100 	call	3910 <alt_get_errno>
+    3a2c:	1007883a 	mov	r3,r2
+    3a30:	00801444 	movi	r2,81
+    3a34:	18800015 	stw	r2,0(r3)
   }
   return -1;
-    39fc:	00bfffc4 	movi	r2,-1
+    3a38:	00bfffc4 	movi	r2,-1
 }
-    3a00:	e037883a 	mov	sp,fp
-    3a04:	dfc00117 	ldw	ra,4(sp)
-    3a08:	df000017 	ldw	fp,0(sp)
-    3a0c:	dec00204 	addi	sp,sp,8
-    3a10:	f800283a 	ret
+    3a3c:	e037883a 	mov	sp,fp
+    3a40:	dfc00117 	ldw	ra,4(sp)
+    3a44:	df000017 	ldw	fp,0(sp)
+    3a48:	dec00204 	addi	sp,sp,8
+    3a4c:	f800283a 	ret
 
-00003a14 <alt_dev_reg>:
+00003a50 <alt_dev_reg>:
  */
 
 extern int alt_fs_reg  (alt_dev* dev); 
 
 static ALT_INLINE int alt_dev_reg (alt_dev* dev)
 {
-    3a14:	defffd04 	addi	sp,sp,-12
-    3a18:	dfc00215 	stw	ra,8(sp)
-    3a1c:	df000115 	stw	fp,4(sp)
-    3a20:	df000104 	addi	fp,sp,4
-    3a24:	e13fff15 	stw	r4,-4(fp)
+    3a50:	defffd04 	addi	sp,sp,-12
+    3a54:	dfc00215 	stw	ra,8(sp)
+    3a58:	df000115 	stw	fp,4(sp)
+    3a5c:	df000104 	addi	fp,sp,4
+    3a60:	e13fff15 	stw	r4,-4(fp)
   extern alt_llist alt_dev_list;
 
   return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list);
-    3a28:	d1600604 	addi	r5,gp,-32744
-    3a2c:	e13fff17 	ldw	r4,-4(fp)
-    3a30:	00047a40 	call	47a4 <alt_dev_llist_insert>
+    3a64:	d1600604 	addi	r5,gp,-32744
+    3a68:	e13fff17 	ldw	r4,-4(fp)
+    3a6c:	00048040 	call	4804 <alt_dev_llist_insert>
 }
-    3a34:	e037883a 	mov	sp,fp
-    3a38:	dfc00117 	ldw	ra,4(sp)
-    3a3c:	df000017 	ldw	fp,0(sp)
-    3a40:	dec00204 	addi	sp,sp,8
-    3a44:	f800283a 	ret
+    3a70:	e037883a 	mov	sp,fp
+    3a74:	dfc00117 	ldw	ra,4(sp)
+    3a78:	df000017 	ldw	fp,0(sp)
+    3a7c:	dec00204 	addi	sp,sp,8
+    3a80:	f800283a 	ret
 
-00003a48 <alt_irq_init>:
+00003a84 <alt_irq_init>:
  * The "base" parameter is ignored and only
  * present for backwards-compatibility.
  */
 
 void alt_irq_init ( const void* base )
 {
-    3a48:	defffd04 	addi	sp,sp,-12
-    3a4c:	dfc00215 	stw	ra,8(sp)
-    3a50:	df000115 	stw	fp,4(sp)
-    3a54:	df000104 	addi	fp,sp,4
-    3a58:	e13fff15 	stw	r4,-4(fp)
+    3a84:	defffd04 	addi	sp,sp,-12
+    3a88:	dfc00215 	stw	ra,8(sp)
+    3a8c:	df000115 	stw	fp,4(sp)
+    3a90:	df000104 	addi	fp,sp,4
+    3a94:	e13fff15 	stw	r4,-4(fp)
     ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu);
-    3a5c:	00051300 	call	5130 <altera_nios2_gen2_irq_init>
- * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts.
- */
-static ALT_INLINE void ALT_ALWAYS_INLINE 
-       alt_irq_cpu_enable_interrupts (void)
-{
+    3a98:	00051800 	call	5180 <altera_nios2_gen2_irq_init>
     NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
-    3a60:	00800044 	movi	r2,1
-    3a64:	1001703a 	wrctl	status,r2
+    3a9c:	00800044 	movi	r2,1
+    3aa0:	1001703a 	wrctl	status,r2
+}
+    3aa4:	0001883a 	nop
     alt_irq_cpu_enable_interrupts();
 }
-    3a68:	0001883a 	nop
-    3a6c:	e037883a 	mov	sp,fp
-    3a70:	dfc00117 	ldw	ra,4(sp)
-    3a74:	df000017 	ldw	fp,0(sp)
-    3a78:	dec00204 	addi	sp,sp,8
-    3a7c:	f800283a 	ret
+    3aa8:	0001883a 	nop
+    3aac:	e037883a 	mov	sp,fp
+    3ab0:	dfc00117 	ldw	ra,4(sp)
+    3ab4:	df000017 	ldw	fp,0(sp)
+    3ab8:	dec00204 	addi	sp,sp,8
+    3abc:	f800283a 	ret
 
-00003a80 <alt_sys_init>:
+00003ac0 <alt_sys_init>:
  * Initialize the non-interrupt controller devices.
  * Called after alt_irq_init().
  */
 
 void alt_sys_init( void )
 {
-    3a80:	defffe04 	addi	sp,sp,-8
-    3a84:	dfc00115 	stw	ra,4(sp)
-    3a88:	df000015 	stw	fp,0(sp)
-    3a8c:	d839883a 	mov	fp,sp
+    3ac0:	defffe04 	addi	sp,sp,-8
+    3ac4:	dfc00115 	stw	ra,4(sp)
+    3ac8:	df000015 	stw	fp,0(sp)
+    3acc:	d839883a 	mov	fp,sp
     ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
-    3a90:	01c0fa04 	movi	r7,1000
-    3a94:	000d883a 	mov	r6,zero
-    3a98:	000b883a 	mov	r5,zero
-    3a9c:	010000b4 	movhi	r4,2
-    3aa0:	21041004 	addi	r4,r4,4160
-    3aa4:	00045c00 	call	45c0 <alt_avalon_timer_sc_init>
+    3ad0:	01c0fa04 	movi	r7,1000
+    3ad4:	000d883a 	mov	r6,zero
+    3ad8:	000b883a 	mov	r5,zero
+    3adc:	010000b4 	movhi	r4,2
+    3ae0:	21041004 	addi	r4,r4,4160
+    3ae4:	00046100 	call	4610 <alt_avalon_timer_sc_init>
     ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
-    3aa8:	01800044 	movi	r6,1
-    3aac:	000b883a 	mov	r5,zero
-    3ab0:	01000034 	movhi	r4,0
-    3ab4:	21189604 	addi	r4,r4,25176
-    3ab8:	0003c440 	call	3c44 <altera_avalon_jtag_uart_init>
-    3abc:	01000034 	movhi	r4,0
-    3ac0:	21188c04 	addi	r4,r4,25136
-    3ac4:	0003a140 	call	3a14 <alt_dev_reg>
+    3ae8:	01800044 	movi	r6,1
+    3aec:	000b883a 	mov	r5,zero
+    3af0:	01000034 	movhi	r4,0
+    3af4:	21186a04 	addi	r4,r4,25000
+    3af8:	0003c840 	call	3c84 <altera_avalon_jtag_uart_init>
+    3afc:	01000034 	movhi	r4,0
+    3b00:	21186004 	addi	r4,r4,24960
+    3b04:	0003a500 	call	3a50 <alt_dev_reg>
 }
-    3ac8:	0001883a 	nop
-    3acc:	e037883a 	mov	sp,fp
-    3ad0:	dfc00117 	ldw	ra,4(sp)
-    3ad4:	df000017 	ldw	fp,0(sp)
-    3ad8:	dec00204 	addi	sp,sp,8
-    3adc:	f800283a 	ret
+    3b08:	0001883a 	nop
+    3b0c:	e037883a 	mov	sp,fp
+    3b10:	dfc00117 	ldw	ra,4(sp)
+    3b14:	df000017 	ldw	fp,0(sp)
+    3b18:	dec00204 	addi	sp,sp,8
+    3b1c:	f800283a 	ret
 
-00003ae0 <altera_avalon_jtag_uart_read_fd>:
+00003b20 <altera_avalon_jtag_uart_read_fd>:
  *
  */
 
 int 
 altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space)
 {
-    3ae0:	defffa04 	addi	sp,sp,-24
-    3ae4:	dfc00515 	stw	ra,20(sp)
-    3ae8:	df000415 	stw	fp,16(sp)
-    3aec:	df000404 	addi	fp,sp,16
-    3af0:	e13ffd15 	stw	r4,-12(fp)
-    3af4:	e17ffe15 	stw	r5,-8(fp)
-    3af8:	e1bfff15 	stw	r6,-4(fp)
+    3b20:	defffa04 	addi	sp,sp,-24
+    3b24:	dfc00515 	stw	ra,20(sp)
+    3b28:	df000415 	stw	fp,16(sp)
+    3b2c:	df000404 	addi	fp,sp,16
+    3b30:	e13ffe15 	stw	r4,-8(fp)
+    3b34:	e17ffd15 	stw	r5,-12(fp)
+    3b38:	e1bffc15 	stw	r6,-16(fp)
     altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
-    3afc:	e0bffd17 	ldw	r2,-12(fp)
-    3b00:	10800017 	ldw	r2,0(r2)
-    3b04:	e0bffc15 	stw	r2,-16(fp)
+    3b3c:	e0bffe17 	ldw	r2,-8(fp)
+    3b40:	10800017 	ldw	r2,0(r2)
+    3b44:	e0bfff15 	stw	r2,-4(fp)
 
     return altera_avalon_jtag_uart_read(&dev->state, buffer, space,
-    3b08:	e0bffc17 	ldw	r2,-16(fp)
-    3b0c:	10c00a04 	addi	r3,r2,40
-    3b10:	e0bffd17 	ldw	r2,-12(fp)
-    3b14:	10800217 	ldw	r2,8(r2)
-    3b18:	100f883a 	mov	r7,r2
-    3b1c:	e1bfff17 	ldw	r6,-4(fp)
-    3b20:	e17ffe17 	ldw	r5,-8(fp)
-    3b24:	1809883a 	mov	r4,r3
-    3b28:	00041080 	call	4108 <altera_avalon_jtag_uart_read>
+    3b48:	e0bfff17 	ldw	r2,-4(fp)
+    3b4c:	10c00a04 	addi	r3,r2,40
+    3b50:	e0bffe17 	ldw	r2,-8(fp)
+    3b54:	10800217 	ldw	r2,8(r2)
+    3b58:	100f883a 	mov	r7,r2
+    3b5c:	e1bffc17 	ldw	r6,-16(fp)
+    3b60:	e17ffd17 	ldw	r5,-12(fp)
+    3b64:	1809883a 	mov	r4,r3
+    3b68:	000414c0 	call	414c <altera_avalon_jtag_uart_read>
       fd->fd_flags);
 }
-    3b2c:	e037883a 	mov	sp,fp
-    3b30:	dfc00117 	ldw	ra,4(sp)
-    3b34:	df000017 	ldw	fp,0(sp)
-    3b38:	dec00204 	addi	sp,sp,8
-    3b3c:	f800283a 	ret
+    3b6c:	e037883a 	mov	sp,fp
+    3b70:	dfc00117 	ldw	ra,4(sp)
+    3b74:	df000017 	ldw	fp,0(sp)
+    3b78:	dec00204 	addi	sp,sp,8
+    3b7c:	f800283a 	ret
 
-00003b40 <altera_avalon_jtag_uart_write_fd>:
+00003b80 <altera_avalon_jtag_uart_write_fd>:
 
 int 
 altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space)
 {
-    3b40:	defffa04 	addi	sp,sp,-24
-    3b44:	dfc00515 	stw	ra,20(sp)
-    3b48:	df000415 	stw	fp,16(sp)
-    3b4c:	df000404 	addi	fp,sp,16
-    3b50:	e13ffd15 	stw	r4,-12(fp)
-    3b54:	e17ffe15 	stw	r5,-8(fp)
-    3b58:	e1bfff15 	stw	r6,-4(fp)
+    3b80:	defffa04 	addi	sp,sp,-24
+    3b84:	dfc00515 	stw	ra,20(sp)
+    3b88:	df000415 	stw	fp,16(sp)
+    3b8c:	df000404 	addi	fp,sp,16
+    3b90:	e13ffe15 	stw	r4,-8(fp)
+    3b94:	e17ffd15 	stw	r5,-12(fp)
+    3b98:	e1bffc15 	stw	r6,-16(fp)
     altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
-    3b5c:	e0bffd17 	ldw	r2,-12(fp)
-    3b60:	10800017 	ldw	r2,0(r2)
-    3b64:	e0bffc15 	stw	r2,-16(fp)
+    3b9c:	e0bffe17 	ldw	r2,-8(fp)
+    3ba0:	10800017 	ldw	r2,0(r2)
+    3ba4:	e0bfff15 	stw	r2,-4(fp)
 
     return altera_avalon_jtag_uart_write(&dev->state, buffer, space,
-    3b68:	e0bffc17 	ldw	r2,-16(fp)
-    3b6c:	10c00a04 	addi	r3,r2,40
-    3b70:	e0bffd17 	ldw	r2,-12(fp)
-    3b74:	10800217 	ldw	r2,8(r2)
-    3b78:	100f883a 	mov	r7,r2
-    3b7c:	e1bfff17 	ldw	r6,-4(fp)
-    3b80:	e17ffe17 	ldw	r5,-8(fp)
-    3b84:	1809883a 	mov	r4,r3
-    3b88:	00043240 	call	4324 <altera_avalon_jtag_uart_write>
+    3ba8:	e0bfff17 	ldw	r2,-4(fp)
+    3bac:	10c00a04 	addi	r3,r2,40
+    3bb0:	e0bffe17 	ldw	r2,-8(fp)
+    3bb4:	10800217 	ldw	r2,8(r2)
+    3bb8:	100f883a 	mov	r7,r2
+    3bbc:	e1bffc17 	ldw	r6,-16(fp)
+    3bc0:	e17ffd17 	ldw	r5,-12(fp)
+    3bc4:	1809883a 	mov	r4,r3
+    3bc8:	000436c0 	call	436c <altera_avalon_jtag_uart_write>
       fd->fd_flags);
 }
-    3b8c:	e037883a 	mov	sp,fp
-    3b90:	dfc00117 	ldw	ra,4(sp)
-    3b94:	df000017 	ldw	fp,0(sp)
-    3b98:	dec00204 	addi	sp,sp,8
-    3b9c:	f800283a 	ret
+    3bcc:	e037883a 	mov	sp,fp
+    3bd0:	dfc00117 	ldw	ra,4(sp)
+    3bd4:	df000017 	ldw	fp,0(sp)
+    3bd8:	dec00204 	addi	sp,sp,8
+    3bdc:	f800283a 	ret
 
-00003ba0 <altera_avalon_jtag_uart_close_fd>:
+00003be0 <altera_avalon_jtag_uart_close_fd>:
 
 #ifndef ALTERA_AVALON_JTAG_UART_SMALL
 
 int 
 altera_avalon_jtag_uart_close_fd(alt_fd* fd)
 {
-    3ba0:	defffc04 	addi	sp,sp,-16
-    3ba4:	dfc00315 	stw	ra,12(sp)
-    3ba8:	df000215 	stw	fp,8(sp)
-    3bac:	df000204 	addi	fp,sp,8
-    3bb0:	e13fff15 	stw	r4,-4(fp)
+    3be0:	defffc04 	addi	sp,sp,-16
+    3be4:	dfc00315 	stw	ra,12(sp)
+    3be8:	df000215 	stw	fp,8(sp)
+    3bec:	df000204 	addi	fp,sp,8
+    3bf0:	e13ffe15 	stw	r4,-8(fp)
     altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
-    3bb4:	e0bfff17 	ldw	r2,-4(fp)
-    3bb8:	10800017 	ldw	r2,0(r2)
-    3bbc:	e0bffe15 	stw	r2,-8(fp)
+    3bf4:	e0bffe17 	ldw	r2,-8(fp)
+    3bf8:	10800017 	ldw	r2,0(r2)
+    3bfc:	e0bfff15 	stw	r2,-4(fp)
 
     return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags);
-    3bc0:	e0bffe17 	ldw	r2,-8(fp)
-    3bc4:	10c00a04 	addi	r3,r2,40
-    3bc8:	e0bfff17 	ldw	r2,-4(fp)
-    3bcc:	10800217 	ldw	r2,8(r2)
-    3bd0:	100b883a 	mov	r5,r2
-    3bd4:	1809883a 	mov	r4,r3
-    3bd8:	0003fb00 	call	3fb0 <altera_avalon_jtag_uart_close>
+    3c00:	e0bfff17 	ldw	r2,-4(fp)
+    3c04:	10c00a04 	addi	r3,r2,40
+    3c08:	e0bffe17 	ldw	r2,-8(fp)
+    3c0c:	10800217 	ldw	r2,8(r2)
+    3c10:	100b883a 	mov	r5,r2
+    3c14:	1809883a 	mov	r4,r3
+    3c18:	0003ff00 	call	3ff0 <altera_avalon_jtag_uart_close>
 }
-    3bdc:	e037883a 	mov	sp,fp
-    3be0:	dfc00117 	ldw	ra,4(sp)
-    3be4:	df000017 	ldw	fp,0(sp)
-    3be8:	dec00204 	addi	sp,sp,8
-    3bec:	f800283a 	ret
+    3c1c:	e037883a 	mov	sp,fp
+    3c20:	dfc00117 	ldw	ra,4(sp)
+    3c24:	df000017 	ldw	fp,0(sp)
+    3c28:	dec00204 	addi	sp,sp,8
+    3c2c:	f800283a 	ret
 
-00003bf0 <altera_avalon_jtag_uart_ioctl_fd>:
+00003c30 <altera_avalon_jtag_uart_ioctl_fd>:
 
 int 
 altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg)
 {
-    3bf0:	defffa04 	addi	sp,sp,-24
-    3bf4:	dfc00515 	stw	ra,20(sp)
-    3bf8:	df000415 	stw	fp,16(sp)
-    3bfc:	df000404 	addi	fp,sp,16
-    3c00:	e13ffd15 	stw	r4,-12(fp)
-    3c04:	e17ffe15 	stw	r5,-8(fp)
-    3c08:	e1bfff15 	stw	r6,-4(fp)
+    3c30:	defffa04 	addi	sp,sp,-24
+    3c34:	dfc00515 	stw	ra,20(sp)
+    3c38:	df000415 	stw	fp,16(sp)
+    3c3c:	df000404 	addi	fp,sp,16
+    3c40:	e13ffe15 	stw	r4,-8(fp)
+    3c44:	e17ffd15 	stw	r5,-12(fp)
+    3c48:	e1bffc15 	stw	r6,-16(fp)
     altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev;
-    3c0c:	e0bffd17 	ldw	r2,-12(fp)
-    3c10:	10800017 	ldw	r2,0(r2)
-    3c14:	e0bffc15 	stw	r2,-16(fp)
+    3c4c:	e0bffe17 	ldw	r2,-8(fp)
+    3c50:	10800017 	ldw	r2,0(r2)
+    3c54:	e0bfff15 	stw	r2,-4(fp)
 
     return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg);
-    3c18:	e0bffc17 	ldw	r2,-16(fp)
-    3c1c:	10800a04 	addi	r2,r2,40
-    3c20:	e1bfff17 	ldw	r6,-4(fp)
-    3c24:	e17ffe17 	ldw	r5,-8(fp)
-    3c28:	1009883a 	mov	r4,r2
-    3c2c:	00040180 	call	4018 <altera_avalon_jtag_uart_ioctl>
+    3c58:	e0bfff17 	ldw	r2,-4(fp)
+    3c5c:	10800a04 	addi	r2,r2,40
+    3c60:	e1bffc17 	ldw	r6,-16(fp)
+    3c64:	e17ffd17 	ldw	r5,-12(fp)
+    3c68:	1009883a 	mov	r4,r2
+    3c6c:	00040580 	call	4058 <altera_avalon_jtag_uart_ioctl>
 }
-    3c30:	e037883a 	mov	sp,fp
-    3c34:	dfc00117 	ldw	ra,4(sp)
-    3c38:	df000017 	ldw	fp,0(sp)
-    3c3c:	dec00204 	addi	sp,sp,8
-    3c40:	f800283a 	ret
+    3c70:	e037883a 	mov	sp,fp
+    3c74:	dfc00117 	ldw	ra,4(sp)
+    3c78:	df000017 	ldw	fp,0(sp)
+    3c7c:	dec00204 	addi	sp,sp,8
+    3c80:	f800283a 	ret
 
-00003c44 <altera_avalon_jtag_uart_init>:
+00003c84 <altera_avalon_jtag_uart_init>:
  * Return 1 on sucessful IRQ register and 0 on failure.
  */
 
 void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, 
                                   int irq_controller_id, int irq)
 {
-    3c44:	defffa04 	addi	sp,sp,-24
-    3c48:	dfc00515 	stw	ra,20(sp)
-    3c4c:	df000415 	stw	fp,16(sp)
-    3c50:	df000404 	addi	fp,sp,16
-    3c54:	e13ffd15 	stw	r4,-12(fp)
-    3c58:	e17ffe15 	stw	r5,-8(fp)
-    3c5c:	e1bfff15 	stw	r6,-4(fp)
+    3c84:	defffa04 	addi	sp,sp,-24
+    3c88:	dfc00515 	stw	ra,20(sp)
+    3c8c:	df000415 	stw	fp,16(sp)
+    3c90:	df000404 	addi	fp,sp,16
+    3c94:	e13fff15 	stw	r4,-4(fp)
+    3c98:	e17ffe15 	stw	r5,-8(fp)
+    3c9c:	e1bffd15 	stw	r6,-12(fp)
   ALT_FLAG_CREATE(&sp->events, 0);
   ALT_SEM_CREATE(&sp->read_lock, 1);
   ALT_SEM_CREATE(&sp->write_lock, 1);
 
   /* enable read interrupts at the device */
   sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
-    3c60:	e0bffd17 	ldw	r2,-12(fp)
-    3c64:	00c00044 	movi	r3,1
-    3c68:	10c00815 	stw	r3,32(r2)
+    3ca0:	e0bfff17 	ldw	r2,-4(fp)
+    3ca4:	00c00044 	movi	r3,1
+    3ca8:	10c00815 	stw	r3,32(r2)
 
   IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); 
-    3c6c:	e0bffd17 	ldw	r2,-12(fp)
-    3c70:	10800017 	ldw	r2,0(r2)
-    3c74:	10800104 	addi	r2,r2,4
-    3c78:	1007883a 	mov	r3,r2
-    3c7c:	e0bffd17 	ldw	r2,-12(fp)
-    3c80:	10800817 	ldw	r2,32(r2)
-    3c84:	18800035 	stwio	r2,0(r3)
+    3cac:	e0bfff17 	ldw	r2,-4(fp)
+    3cb0:	10800017 	ldw	r2,0(r2)
+    3cb4:	10800104 	addi	r2,r2,4
+    3cb8:	1007883a 	mov	r3,r2
+    3cbc:	e0bfff17 	ldw	r2,-4(fp)
+    3cc0:	10800817 	ldw	r2,32(r2)
+    3cc4:	18800035 	stwio	r2,0(r3)
   
   /* register the interrupt handler */
 #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
   alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, 
-    3c88:	e0bffe17 	ldw	r2,-8(fp)
-    3c8c:	e0ffff17 	ldw	r3,-4(fp)
-    3c90:	d8000015 	stw	zero,0(sp)
-    3c94:	e1fffd17 	ldw	r7,-12(fp)
-    3c98:	01800034 	movhi	r6,0
-    3c9c:	318f4104 	addi	r6,r6,15620
-    3ca0:	180b883a 	mov	r5,r3
-    3ca4:	1009883a 	mov	r4,r2
-    3ca8:	00049080 	call	4908 <alt_ic_isr_register>
+    3cc8:	e0bffe17 	ldw	r2,-8(fp)
+    3ccc:	e0fffd17 	ldw	r3,-12(fp)
+    3cd0:	d8000015 	stw	zero,0(sp)
+    3cd4:	e1ffff17 	ldw	r7,-4(fp)
+    3cd8:	01800034 	movhi	r6,0
+    3cdc:	318f5104 	addi	r6,r6,15684
+    3ce0:	180b883a 	mov	r5,r3
+    3ce4:	1009883a 	mov	r4,r2
+    3ce8:	00049740 	call	4974 <alt_ic_isr_register>
 #else
   alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq);
 #endif  
 
   /* Register an alarm to go off every second to check for presence of host */
   sp->host_inactive = 0;
-    3cac:	e0bffd17 	ldw	r2,-12(fp)
-    3cb0:	10000915 	stw	zero,36(r2)
+    3cec:	e0bfff17 	ldw	r2,-4(fp)
+    3cf0:	10000915 	stw	zero,36(r2)
 
   if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), 
-    3cb4:	e0bffd17 	ldw	r2,-12(fp)
-    3cb8:	10800204 	addi	r2,r2,8
+    3cf4:	e0bfff17 	ldw	r2,-4(fp)
+    3cf8:	10800204 	addi	r2,r2,8
  * Obtain the system clock rate in ticks/s. 
  */
 
 static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void)
 {
   return _alt_tick_rate;
-    3cbc:	d0e01617 	ldw	r3,-32680(gp)
-    3cc0:	e1fffd17 	ldw	r7,-12(fp)
-    3cc4:	01800034 	movhi	r6,0
-    3cc8:	318fc404 	addi	r6,r6,16144
-    3ccc:	180b883a 	mov	r5,r3
-    3cd0:	1009883a 	mov	r4,r2
-    3cd4:	000463c0 	call	463c <alt_alarm_start>
-    3cd8:	1000040e 	bge	r2,zero,3cec <altera_avalon_jtag_uart_init+0xa8>
+    3cfc:	d0e01617 	ldw	r3,-32680(gp)
+    3d00:	e1ffff17 	ldw	r7,-4(fp)
+    3d04:	01800034 	movhi	r6,0
+    3d08:	318fd404 	addi	r6,r6,16208
+    3d0c:	180b883a 	mov	r5,r3
+    3d10:	1009883a 	mov	r4,r2
+    3d14:	00046940 	call	4694 <alt_alarm_start>
+    3d18:	1000040e 	bge	r2,zero,3d2c <altera_avalon_jtag_uart_init+0xa8>
     &altera_avalon_jtag_uart_timeout, sp) < 0)
   {
     /* If we can't set the alarm then record "don't know if host present" 
      * and behave as though the host is present.
      */
     sp->timeout = INT_MAX;
-    3cdc:	e0fffd17 	ldw	r3,-12(fp)
-    3ce0:	00a00034 	movhi	r2,32768
-    3ce4:	10bfffc4 	addi	r2,r2,-1
-    3ce8:	18800115 	stw	r2,4(r3)
+    3d1c:	e0ffff17 	ldw	r3,-4(fp)
+    3d20:	00a00034 	movhi	r2,32768
+    3d24:	10bfffc4 	addi	r2,r2,-1
+    3d28:	18800115 	stw	r2,4(r3)
   }
 
   /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ 
   ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base);
 }
-    3cec:	0001883a 	nop
-    3cf0:	e037883a 	mov	sp,fp
-    3cf4:	dfc00117 	ldw	ra,4(sp)
-    3cf8:	df000017 	ldw	fp,0(sp)
-    3cfc:	dec00204 	addi	sp,sp,8
-    3d00:	f800283a 	ret
+    3d2c:	0001883a 	nop
+    3d30:	e037883a 	mov	sp,fp
+    3d34:	dfc00117 	ldw	ra,4(sp)
+    3d38:	df000017 	ldw	fp,0(sp)
+    3d3c:	dec00204 	addi	sp,sp,8
+    3d40:	f800283a 	ret
 
-00003d04 <altera_avalon_jtag_uart_irq>:
+00003d44 <altera_avalon_jtag_uart_irq>:
 #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
 static void altera_avalon_jtag_uart_irq(void* context)
 #else
 static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id)
 #endif
 {
-    3d04:	defff804 	addi	sp,sp,-32
-    3d08:	df000715 	stw	fp,28(sp)
-    3d0c:	df000704 	addi	fp,sp,28
-    3d10:	e13fff15 	stw	r4,-4(fp)
+    3d44:	defff804 	addi	sp,sp,-32
+    3d48:	df000715 	stw	fp,28(sp)
+    3d4c:	df000704 	addi	fp,sp,28
+    3d50:	e13ff915 	stw	r4,-28(fp)
   altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context;
-    3d14:	e0bfff17 	ldw	r2,-4(fp)
-    3d18:	e0bffb15 	stw	r2,-20(fp)
+    3d54:	e0bff917 	ldw	r2,-28(fp)
+    3d58:	e0bffd15 	stw	r2,-12(fp)
   unsigned int base = sp->base;
-    3d1c:	e0bffb17 	ldw	r2,-20(fp)
-    3d20:	10800017 	ldw	r2,0(r2)
-    3d24:	e0bffc15 	stw	r2,-16(fp)
+    3d5c:	e0bffd17 	ldw	r2,-12(fp)
+    3d60:	10800017 	ldw	r2,0(r2)
+    3d64:	e0bffc15 	stw	r2,-16(fp)
   /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ 
   ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp);
 
   for ( ; ; )
   {
     unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
-    3d28:	e0bffc17 	ldw	r2,-16(fp)
-    3d2c:	10800104 	addi	r2,r2,4
-    3d30:	10800037 	ldwio	r2,0(r2)
-    3d34:	e0bffd15 	stw	r2,-12(fp)
+    3d68:	e0bffc17 	ldw	r2,-16(fp)
+    3d6c:	10800104 	addi	r2,r2,4
+    3d70:	10800037 	ldwio	r2,0(r2)
+    3d74:	e0bffb15 	stw	r2,-20(fp)
 
     /* Return once nothing more to do */
     if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0)
-    3d38:	e0bffd17 	ldw	r2,-12(fp)
-    3d3c:	1080c00c 	andi	r2,r2,768
-    3d40:	10006d26 	beq	r2,zero,3ef8 <altera_avalon_jtag_uart_irq+0x1f4>
+    3d78:	e0bffb17 	ldw	r2,-20(fp)
+    3d7c:	1080c00c 	andi	r2,r2,768
+    3d80:	10006d26 	beq	r2,zero,3f38 <altera_avalon_jtag_uart_irq+0x1f4>
       break;
 
     if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK)
-    3d44:	e0bffd17 	ldw	r2,-12(fp)
-    3d48:	1080400c 	andi	r2,r2,256
-    3d4c:	10003526 	beq	r2,zero,3e24 <altera_avalon_jtag_uart_irq+0x120>
+    3d84:	e0bffb17 	ldw	r2,-20(fp)
+    3d88:	1080400c 	andi	r2,r2,256
+    3d8c:	10003526 	beq	r2,zero,3e64 <altera_avalon_jtag_uart_irq+0x120>
     {
       /* process a read irq.  Start by assuming that there is data in the
        * receive FIFO (otherwise why would we have been interrupted?)
        */
       unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST;
-    3d50:	00800074 	movhi	r2,1
-    3d54:	e0bff915 	stw	r2,-28(fp)
+    3d90:	00800074 	movhi	r2,1
+    3d94:	e0bfff15 	stw	r2,-4(fp)
       for ( ; ; )
       {
         /* Check whether there is space in the buffer.  If not then we must not
          * read any characters from the buffer as they will be lost.
          */
         unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    3d58:	e0bffb17 	ldw	r2,-20(fp)
-    3d5c:	10800a17 	ldw	r2,40(r2)
-    3d60:	10800044 	addi	r2,r2,1
-    3d64:	1081ffcc 	andi	r2,r2,2047
-    3d68:	e0bffe15 	stw	r2,-8(fp)
+    3d98:	e0bffd17 	ldw	r2,-12(fp)
+    3d9c:	10800a17 	ldw	r2,40(r2)
+    3da0:	10800044 	addi	r2,r2,1
+    3da4:	1081ffcc 	andi	r2,r2,2047
+    3da8:	e0bffa15 	stw	r2,-24(fp)
         if (next == sp->rx_out)
-    3d6c:	e0bffb17 	ldw	r2,-20(fp)
-    3d70:	10c00b17 	ldw	r3,44(r2)
-    3d74:	e0bffe17 	ldw	r2,-8(fp)
-    3d78:	18801526 	beq	r3,r2,3dd0 <altera_avalon_jtag_uart_irq+0xcc>
+    3dac:	e0bffd17 	ldw	r2,-12(fp)
+    3db0:	10800b17 	ldw	r2,44(r2)
+    3db4:	e0fffa17 	ldw	r3,-24(fp)
+    3db8:	18801526 	beq	r3,r2,3e10 <altera_avalon_jtag_uart_irq+0xcc>
           break;
 
         /* Try to remove a character from the FIFO and find out whether there
          * are any more characters remaining.
          */
         data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base);
-    3d7c:	e0bffc17 	ldw	r2,-16(fp)
-    3d80:	10800037 	ldwio	r2,0(r2)
-    3d84:	e0bff915 	stw	r2,-28(fp)
+    3dbc:	e0bffc17 	ldw	r2,-16(fp)
+    3dc0:	10800037 	ldwio	r2,0(r2)
+    3dc4:	e0bfff15 	stw	r2,-4(fp)
         
         if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0)
-    3d88:	e0bff917 	ldw	r2,-28(fp)
-    3d8c:	10a0000c 	andi	r2,r2,32768
-    3d90:	10001126 	beq	r2,zero,3dd8 <altera_avalon_jtag_uart_irq+0xd4>
+    3dc8:	e0bfff17 	ldw	r2,-4(fp)
+    3dcc:	10a0000c 	andi	r2,r2,32768
+    3dd0:	10001126 	beq	r2,zero,3e18 <altera_avalon_jtag_uart_irq+0xd4>
           break;
 
         sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST;
-    3d94:	e0bffb17 	ldw	r2,-20(fp)
-    3d98:	10800a17 	ldw	r2,40(r2)
-    3d9c:	e0fff917 	ldw	r3,-28(fp)
-    3da0:	1809883a 	mov	r4,r3
-    3da4:	e0fffb17 	ldw	r3,-20(fp)
-    3da8:	1885883a 	add	r2,r3,r2
-    3dac:	10800e04 	addi	r2,r2,56
-    3db0:	11000005 	stb	r4,0(r2)
+    3dd4:	e0bffd17 	ldw	r2,-12(fp)
+    3dd8:	10800a17 	ldw	r2,40(r2)
+    3ddc:	e0ffff17 	ldw	r3,-4(fp)
+    3de0:	1809883a 	mov	r4,r3
+    3de4:	e0fffd17 	ldw	r3,-12(fp)
+    3de8:	1885883a 	add	r2,r3,r2
+    3dec:	11000e05 	stb	r4,56(r2)
         sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    3db4:	e0bffb17 	ldw	r2,-20(fp)
-    3db8:	10800a17 	ldw	r2,40(r2)
-    3dbc:	10800044 	addi	r2,r2,1
-    3dc0:	10c1ffcc 	andi	r3,r2,2047
-    3dc4:	e0bffb17 	ldw	r2,-20(fp)
-    3dc8:	10c00a15 	stw	r3,40(r2)
+    3df0:	e0bffd17 	ldw	r2,-12(fp)
+    3df4:	10800a17 	ldw	r2,40(r2)
+    3df8:	10800044 	addi	r2,r2,1
+    3dfc:	10c1ffcc 	andi	r3,r2,2047
+    3e00:	e0bffd17 	ldw	r2,-12(fp)
+    3e04:	10c00a15 	stw	r3,40(r2)
+ * HAL.
+ */
 
-        /* Post an event to notify jtag_uart_read that a character has been read */
-        ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET);
-      }
-    3dcc:	003fe206 	br	3d58 <__alt_data_end+0xfffe3d58>
-        /* Check whether there is space in the buffer.  If not then we must not
-         * read any characters from the buffer as they will be lost.
-         */
-        unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-        if (next == sp->rx_out)
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void)
+{
+  return 0;
+    3e08:	0001883a 	nop
+      {
+    3e0c:	003fe206 	br	3d98 <altera_avalon_jtag_uart_irq+0x54>
           break;
-    3dd0:	0001883a 	nop
-    3dd4:	00000106 	br	3ddc <altera_avalon_jtag_uart_irq+0xd8>
-         * are any more characters remaining.
-         */
-        data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base);
-        
-        if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0)
+    3e10:	0001883a 	nop
+    3e14:	00000106 	br	3e1c <altera_avalon_jtag_uart_irq+0xd8>
           break;
-    3dd8:	0001883a 	nop
+    3e18:	0001883a 	nop
 
         /* Post an event to notify jtag_uart_read that a character has been read */
         ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET);
       }
 
       if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK)
-    3ddc:	e0bff917 	ldw	r2,-28(fp)
-    3de0:	10bfffec 	andhi	r2,r2,65535
-    3de4:	10000f26 	beq	r2,zero,3e24 <altera_avalon_jtag_uart_irq+0x120>
+    3e1c:	e0bfff17 	ldw	r2,-4(fp)
+    3e20:	10bfffec 	andhi	r2,r2,65535
+    3e24:	10000f26 	beq	r2,zero,3e64 <altera_avalon_jtag_uart_irq+0x120>
       {
         /* If there is still data available here then the buffer is full 
          * so turn off receive interrupts until some space becomes available.
          */
         sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
-    3de8:	e0bffb17 	ldw	r2,-20(fp)
-    3dec:	10c00817 	ldw	r3,32(r2)
-    3df0:	00bfff84 	movi	r2,-2
-    3df4:	1886703a 	and	r3,r3,r2
-    3df8:	e0bffb17 	ldw	r2,-20(fp)
-    3dfc:	10c00815 	stw	r3,32(r2)
+    3e28:	e0bffd17 	ldw	r2,-12(fp)
+    3e2c:	10c00817 	ldw	r3,32(r2)
+    3e30:	00bfff84 	movi	r2,-2
+    3e34:	1886703a 	and	r3,r3,r2
+    3e38:	e0bffd17 	ldw	r2,-12(fp)
+    3e3c:	10c00815 	stw	r3,32(r2)
         IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable);
-    3e00:	e0bffc17 	ldw	r2,-16(fp)
-    3e04:	10800104 	addi	r2,r2,4
-    3e08:	1007883a 	mov	r3,r2
-    3e0c:	e0bffb17 	ldw	r2,-20(fp)
-    3e10:	10800817 	ldw	r2,32(r2)
-    3e14:	18800035 	stwio	r2,0(r3)
+    3e40:	e0bffc17 	ldw	r2,-16(fp)
+    3e44:	10800104 	addi	r2,r2,4
+    3e48:	1007883a 	mov	r3,r2
+    3e4c:	e0bffd17 	ldw	r2,-12(fp)
+    3e50:	10800817 	ldw	r2,32(r2)
+    3e54:	18800035 	stwio	r2,0(r3)
         
         /* Dummy read to ensure IRQ is cleared prior to ISR completion */
         IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
-    3e18:	e0bffc17 	ldw	r2,-16(fp)
-    3e1c:	10800104 	addi	r2,r2,4
-    3e20:	10800037 	ldwio	r2,0(r2)
+    3e58:	e0bffc17 	ldw	r2,-16(fp)
+    3e5c:	10800104 	addi	r2,r2,4
+    3e60:	10800037 	ldwio	r2,0(r2)
       }
     }
 
     if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)
-    3e24:	e0bffd17 	ldw	r2,-12(fp)
-    3e28:	1080800c 	andi	r2,r2,512
-    3e2c:	103fbe26 	beq	r2,zero,3d28 <__alt_data_end+0xfffe3d28>
+    3e64:	e0bffb17 	ldw	r2,-20(fp)
+    3e68:	1080800c 	andi	r2,r2,512
+    3e6c:	103fbe26 	beq	r2,zero,3d68 <altera_avalon_jtag_uart_irq+0x24>
     {
       /* process a write irq */
       unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST;
-    3e30:	e0bffd17 	ldw	r2,-12(fp)
-    3e34:	1004d43a 	srli	r2,r2,16
-    3e38:	e0bffa15 	stw	r2,-24(fp)
+    3e70:	e0bffb17 	ldw	r2,-20(fp)
+    3e74:	1004d43a 	srli	r2,r2,16
+    3e78:	e0bffe15 	stw	r2,-8(fp)
 
       while (space > 0 && sp->tx_out != sp->tx_in)
-    3e3c:	00001406 	br	3e90 <altera_avalon_jtag_uart_irq+0x18c>
+    3e7c:	00001406 	br	3ed0 <altera_avalon_jtag_uart_irq+0x18c>
       {
         IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]);
-    3e40:	e0bffc17 	ldw	r2,-16(fp)
-    3e44:	e0fffb17 	ldw	r3,-20(fp)
-    3e48:	18c00d17 	ldw	r3,52(r3)
-    3e4c:	e13ffb17 	ldw	r4,-20(fp)
-    3e50:	20c7883a 	add	r3,r4,r3
-    3e54:	18c20e04 	addi	r3,r3,2104
-    3e58:	18c00003 	ldbu	r3,0(r3)
-    3e5c:	18c03fcc 	andi	r3,r3,255
-    3e60:	18c0201c 	xori	r3,r3,128
-    3e64:	18ffe004 	addi	r3,r3,-128
-    3e68:	10c00035 	stwio	r3,0(r2)
+    3e80:	e0bffc17 	ldw	r2,-16(fp)
+    3e84:	e0fffd17 	ldw	r3,-12(fp)
+    3e88:	18c00d17 	ldw	r3,52(r3)
+    3e8c:	e13ffd17 	ldw	r4,-12(fp)
+    3e90:	20c7883a 	add	r3,r4,r3
+    3e94:	18c20e03 	ldbu	r3,2104(r3)
+    3e98:	18c03fcc 	andi	r3,r3,255
+    3e9c:	18c0201c 	xori	r3,r3,128
+    3ea0:	18ffe004 	addi	r3,r3,-128
+    3ea4:	10c00035 	stwio	r3,0(r2)
 
         sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    3e6c:	e0bffb17 	ldw	r2,-20(fp)
-    3e70:	10800d17 	ldw	r2,52(r2)
-    3e74:	10800044 	addi	r2,r2,1
-    3e78:	10c1ffcc 	andi	r3,r2,2047
-    3e7c:	e0bffb17 	ldw	r2,-20(fp)
-    3e80:	10c00d15 	stw	r3,52(r2)
+    3ea8:	e0bffd17 	ldw	r2,-12(fp)
+    3eac:	10800d17 	ldw	r2,52(r2)
+    3eb0:	10800044 	addi	r2,r2,1
+    3eb4:	10c1ffcc 	andi	r3,r2,2047
+    3eb8:	e0bffd17 	ldw	r2,-12(fp)
+    3ebc:	10c00d15 	stw	r3,52(r2)
+    3ec0:	0001883a 	nop
 
         /* Post an event to notify jtag_uart_write that a character has been written */
         ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET);
 
         space--;
-    3e84:	e0bffa17 	ldw	r2,-24(fp)
-    3e88:	10bfffc4 	addi	r2,r2,-1
-    3e8c:	e0bffa15 	stw	r2,-24(fp)
-    if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)
-    {
-      /* process a write irq */
-      unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST;
-
+    3ec4:	e0bffe17 	ldw	r2,-8(fp)
+    3ec8:	10bfffc4 	addi	r2,r2,-1
+    3ecc:	e0bffe15 	stw	r2,-8(fp)
       while (space > 0 && sp->tx_out != sp->tx_in)
-    3e90:	e0bffa17 	ldw	r2,-24(fp)
-    3e94:	10000526 	beq	r2,zero,3eac <altera_avalon_jtag_uart_irq+0x1a8>
-    3e98:	e0bffb17 	ldw	r2,-20(fp)
-    3e9c:	10c00d17 	ldw	r3,52(r2)
-    3ea0:	e0bffb17 	ldw	r2,-20(fp)
-    3ea4:	10800c17 	ldw	r2,48(r2)
-    3ea8:	18bfe51e 	bne	r3,r2,3e40 <__alt_data_end+0xfffe3e40>
-        ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET);
-
-        space--;
+    3ed0:	e0bffe17 	ldw	r2,-8(fp)
+    3ed4:	10000526 	beq	r2,zero,3eec <altera_avalon_jtag_uart_irq+0x1a8>
+    3ed8:	e0bffd17 	ldw	r2,-12(fp)
+    3edc:	10c00d17 	ldw	r3,52(r2)
+    3ee0:	e0bffd17 	ldw	r2,-12(fp)
+    3ee4:	10800c17 	ldw	r2,48(r2)
+    3ee8:	18bfe51e 	bne	r3,r2,3e80 <altera_avalon_jtag_uart_irq+0x13c>
       }
 
       if (space > 0)
-    3eac:	e0bffa17 	ldw	r2,-24(fp)
-    3eb0:	103f9d26 	beq	r2,zero,3d28 <__alt_data_end+0xfffe3d28>
+    3eec:	e0bffe17 	ldw	r2,-8(fp)
+    3ef0:	103f9d26 	beq	r2,zero,3d68 <altera_avalon_jtag_uart_irq+0x24>
       {
         /* If we don't have any more data available then turn off the TX interrupt */
         sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK;
-    3eb4:	e0bffb17 	ldw	r2,-20(fp)
-    3eb8:	10c00817 	ldw	r3,32(r2)
-    3ebc:	00bfff44 	movi	r2,-3
-    3ec0:	1886703a 	and	r3,r3,r2
-    3ec4:	e0bffb17 	ldw	r2,-20(fp)
-    3ec8:	10c00815 	stw	r3,32(r2)
+    3ef4:	e0bffd17 	ldw	r2,-12(fp)
+    3ef8:	10c00817 	ldw	r3,32(r2)
+    3efc:	00bfff44 	movi	r2,-3
+    3f00:	1886703a 	and	r3,r3,r2
+    3f04:	e0bffd17 	ldw	r2,-12(fp)
+    3f08:	10c00815 	stw	r3,32(r2)
         IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
-    3ecc:	e0bffb17 	ldw	r2,-20(fp)
-    3ed0:	10800017 	ldw	r2,0(r2)
-    3ed4:	10800104 	addi	r2,r2,4
-    3ed8:	1007883a 	mov	r3,r2
-    3edc:	e0bffb17 	ldw	r2,-20(fp)
-    3ee0:	10800817 	ldw	r2,32(r2)
-    3ee4:	18800035 	stwio	r2,0(r3)
+    3f0c:	e0bffd17 	ldw	r2,-12(fp)
+    3f10:	10800017 	ldw	r2,0(r2)
+    3f14:	10800104 	addi	r2,r2,4
+    3f18:	1007883a 	mov	r3,r2
+    3f1c:	e0bffd17 	ldw	r2,-12(fp)
+    3f20:	10800817 	ldw	r2,32(r2)
+    3f24:	18800035 	stwio	r2,0(r3)
         
         /* Dummy read to ensure IRQ is cleared prior to ISR completion */
         IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
-    3ee8:	e0bffc17 	ldw	r2,-16(fp)
-    3eec:	10800104 	addi	r2,r2,4
-    3ef0:	10800037 	ldwio	r2,0(r2)
-      }
-    }
-  }
-    3ef4:	003f8c06 	br	3d28 <__alt_data_end+0xfffe3d28>
+    3f28:	e0bffc17 	ldw	r2,-16(fp)
+    3f2c:	10800104 	addi	r2,r2,4
+    3f30:	10800037 	ldwio	r2,0(r2)
   {
-    unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
-
-    /* Return once nothing more to do */
-    if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0)
+    3f34:	003f8c06 	br	3d68 <altera_avalon_jtag_uart_irq+0x24>
       break;
-    3ef8:	0001883a 	nop
-        /* Dummy read to ensure IRQ is cleared prior to ISR completion */
-        IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
+    3f38:	0001883a 	nop
       }
     }
   }
 }
-    3efc:	0001883a 	nop
-    3f00:	e037883a 	mov	sp,fp
-    3f04:	df000017 	ldw	fp,0(sp)
-    3f08:	dec00104 	addi	sp,sp,4
-    3f0c:	f800283a 	ret
+    3f3c:	0001883a 	nop
+    3f40:	e037883a 	mov	sp,fp
+    3f44:	df000017 	ldw	fp,0(sp)
+    3f48:	dec00104 	addi	sp,sp,4
+    3f4c:	f800283a 	ret
 
-00003f10 <altera_avalon_jtag_uart_timeout>:
+00003f50 <altera_avalon_jtag_uart_timeout>:
  * Timeout routine is called every second
  */
 
 static alt_u32 
 altera_avalon_jtag_uart_timeout(void* context) 
 {
-    3f10:	defff804 	addi	sp,sp,-32
-    3f14:	df000715 	stw	fp,28(sp)
-    3f18:	df000704 	addi	fp,sp,28
-    3f1c:	e13ffb15 	stw	r4,-20(fp)
+    3f50:	defffc04 	addi	sp,sp,-16
+    3f54:	df000315 	stw	fp,12(sp)
+    3f58:	df000304 	addi	fp,sp,12
+    3f5c:	e13ffd15 	stw	r4,-12(fp)
   altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context;
-    3f20:	e0bffb17 	ldw	r2,-20(fp)
-    3f24:	e0bff915 	stw	r2,-28(fp)
+    3f60:	e0bffd17 	ldw	r2,-12(fp)
+    3f64:	e0bfff15 	stw	r2,-4(fp)
 
   unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base);
-    3f28:	e0bff917 	ldw	r2,-28(fp)
-    3f2c:	10800017 	ldw	r2,0(r2)
-    3f30:	10800104 	addi	r2,r2,4
-    3f34:	10800037 	ldwio	r2,0(r2)
-    3f38:	e0bffa15 	stw	r2,-24(fp)
+    3f68:	e0bfff17 	ldw	r2,-4(fp)
+    3f6c:	10800017 	ldw	r2,0(r2)
+    3f70:	10800104 	addi	r2,r2,4
+    3f74:	10800037 	ldwio	r2,0(r2)
+    3f78:	e0bffe15 	stw	r2,-8(fp)
 
   if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK)
-    3f3c:	e0bffa17 	ldw	r2,-24(fp)
-    3f40:	1081000c 	andi	r2,r2,1024
-    3f44:	10000b26 	beq	r2,zero,3f74 <altera_avalon_jtag_uart_timeout+0x64>
+    3f7c:	e0bffe17 	ldw	r2,-8(fp)
+    3f80:	1081000c 	andi	r2,r2,1024
+    3f84:	10000b26 	beq	r2,zero,3fb4 <altera_avalon_jtag_uart_timeout+0x64>
   {
     IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK);
-    3f48:	e0bff917 	ldw	r2,-28(fp)
-    3f4c:	10800017 	ldw	r2,0(r2)
-    3f50:	10800104 	addi	r2,r2,4
-    3f54:	1007883a 	mov	r3,r2
-    3f58:	e0bff917 	ldw	r2,-28(fp)
-    3f5c:	10800817 	ldw	r2,32(r2)
-    3f60:	10810014 	ori	r2,r2,1024
-    3f64:	18800035 	stwio	r2,0(r3)
+    3f88:	e0bfff17 	ldw	r2,-4(fp)
+    3f8c:	10800017 	ldw	r2,0(r2)
+    3f90:	10800104 	addi	r2,r2,4
+    3f94:	1007883a 	mov	r3,r2
+    3f98:	e0bfff17 	ldw	r2,-4(fp)
+    3f9c:	10800817 	ldw	r2,32(r2)
+    3fa0:	10810014 	ori	r2,r2,1024
+    3fa4:	18800035 	stwio	r2,0(r3)
     sp->host_inactive = 0;
-    3f68:	e0bff917 	ldw	r2,-28(fp)
-    3f6c:	10000915 	stw	zero,36(r2)
-    3f70:	00000a06 	br	3f9c <altera_avalon_jtag_uart_timeout+0x8c>
+    3fa8:	e0bfff17 	ldw	r2,-4(fp)
+    3fac:	10000915 	stw	zero,36(r2)
+    3fb0:	00000a06 	br	3fdc <altera_avalon_jtag_uart_timeout+0x8c>
   }
   else if (sp->host_inactive < INT_MAX - 2) {
-    3f74:	e0bff917 	ldw	r2,-28(fp)
-    3f78:	10c00917 	ldw	r3,36(r2)
-    3f7c:	00a00034 	movhi	r2,32768
-    3f80:	10bfff04 	addi	r2,r2,-4
-    3f84:	10c00536 	bltu	r2,r3,3f9c <altera_avalon_jtag_uart_timeout+0x8c>
+    3fb4:	e0bfff17 	ldw	r2,-4(fp)
+    3fb8:	10c00917 	ldw	r3,36(r2)
+    3fbc:	00a00034 	movhi	r2,32768
+    3fc0:	10bfff04 	addi	r2,r2,-4
+    3fc4:	10c00536 	bltu	r2,r3,3fdc <altera_avalon_jtag_uart_timeout+0x8c>
     sp->host_inactive++;
-    3f88:	e0bff917 	ldw	r2,-28(fp)
-    3f8c:	10800917 	ldw	r2,36(r2)
-    3f90:	10c00044 	addi	r3,r2,1
-    3f94:	e0bff917 	ldw	r2,-28(fp)
-    3f98:	10c00915 	stw	r3,36(r2)
-    3f9c:	d0a01617 	ldw	r2,-32680(gp)
+    3fc8:	e0bfff17 	ldw	r2,-4(fp)
+    3fcc:	10800917 	ldw	r2,36(r2)
+    3fd0:	10c00044 	addi	r3,r2,1
+    3fd4:	e0bfff17 	ldw	r2,-4(fp)
+    3fd8:	10c00915 	stw	r3,36(r2)
+    3fdc:	d0a01617 	ldw	r2,-32680(gp)
       ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET);
     }
   }
 
   return alt_ticks_per_second();
 }
-    3fa0:	e037883a 	mov	sp,fp
-    3fa4:	df000017 	ldw	fp,0(sp)
-    3fa8:	dec00104 	addi	sp,sp,4
-    3fac:	f800283a 	ret
+    3fe0:	e037883a 	mov	sp,fp
+    3fe4:	df000017 	ldw	fp,0(sp)
+    3fe8:	dec00104 	addi	sp,sp,4
+    3fec:	f800283a 	ret
 
-00003fb0 <altera_avalon_jtag_uart_close>:
+00003ff0 <altera_avalon_jtag_uart_close>:
  * The close routine is not implemented for the small driver; instead it will
  * map to null. This is because the small driver simply waits while characters
  * are transmitted; there is no interrupt-serviced buffer to empty 
  */
 int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags)
 {
-    3fb0:	defffd04 	addi	sp,sp,-12
-    3fb4:	df000215 	stw	fp,8(sp)
-    3fb8:	df000204 	addi	fp,sp,8
-    3fbc:	e13ffe15 	stw	r4,-8(fp)
-    3fc0:	e17fff15 	stw	r5,-4(fp)
+    3ff0:	defffd04 	addi	sp,sp,-12
+    3ff4:	df000215 	stw	fp,8(sp)
+    3ff8:	df000204 	addi	fp,sp,8
+    3ffc:	e13fff15 	stw	r4,-4(fp)
+    4000:	e17ffe15 	stw	r5,-8(fp)
   /* 
    * Wait for all transmit data to be emptied by the JTAG UART ISR, or
    * for a host-inactivity timeout, in which case transmit data will be lost
    */
   while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) {
-    3fc4:	00000506 	br	3fdc <altera_avalon_jtag_uart_close+0x2c>
+    4004:	00000506 	br	401c <altera_avalon_jtag_uart_close+0x2c>
     if (flags & O_NONBLOCK) {
-    3fc8:	e0bfff17 	ldw	r2,-4(fp)
-    3fcc:	1090000c 	andi	r2,r2,16384
-    3fd0:	10000226 	beq	r2,zero,3fdc <altera_avalon_jtag_uart_close+0x2c>
+    4008:	e0bffe17 	ldw	r2,-8(fp)
+    400c:	1090000c 	andi	r2,r2,16384
+    4010:	10000226 	beq	r2,zero,401c <altera_avalon_jtag_uart_close+0x2c>
       return -EWOULDBLOCK; 
-    3fd4:	00bffd44 	movi	r2,-11
-    3fd8:	00000b06 	br	4008 <altera_avalon_jtag_uart_close+0x58>
-{
-  /* 
-   * Wait for all transmit data to be emptied by the JTAG UART ISR, or
-   * for a host-inactivity timeout, in which case transmit data will be lost
-   */
+    4014:	00bffd44 	movi	r2,-11
+    4018:	00000b06 	br	4048 <altera_avalon_jtag_uart_close+0x58>
   while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) {
-    3fdc:	e0bffe17 	ldw	r2,-8(fp)
-    3fe0:	10c00d17 	ldw	r3,52(r2)
-    3fe4:	e0bffe17 	ldw	r2,-8(fp)
-    3fe8:	10800c17 	ldw	r2,48(r2)
-    3fec:	18800526 	beq	r3,r2,4004 <altera_avalon_jtag_uart_close+0x54>
-    3ff0:	e0bffe17 	ldw	r2,-8(fp)
-    3ff4:	10c00917 	ldw	r3,36(r2)
-    3ff8:	e0bffe17 	ldw	r2,-8(fp)
-    3ffc:	10800117 	ldw	r2,4(r2)
-    4000:	18bff136 	bltu	r3,r2,3fc8 <__alt_data_end+0xfffe3fc8>
-    if (flags & O_NONBLOCK) {
-      return -EWOULDBLOCK; 
+    401c:	e0bfff17 	ldw	r2,-4(fp)
+    4020:	10c00d17 	ldw	r3,52(r2)
+    4024:	e0bfff17 	ldw	r2,-4(fp)
+    4028:	10800c17 	ldw	r2,48(r2)
+    402c:	18800526 	beq	r3,r2,4044 <altera_avalon_jtag_uart_close+0x54>
+    4030:	e0bfff17 	ldw	r2,-4(fp)
+    4034:	10c00917 	ldw	r3,36(r2)
+    4038:	e0bfff17 	ldw	r2,-4(fp)
+    403c:	10800117 	ldw	r2,4(r2)
+    4040:	18bff136 	bltu	r3,r2,4008 <altera_avalon_jtag_uart_close+0x18>
     }
   }
 
   return 0;
-    4004:	0005883a 	mov	r2,zero
+    4044:	0005883a 	mov	r2,zero
 }
-    4008:	e037883a 	mov	sp,fp
-    400c:	df000017 	ldw	fp,0(sp)
-    4010:	dec00104 	addi	sp,sp,4
-    4014:	f800283a 	ret
+    4048:	e037883a 	mov	sp,fp
+    404c:	df000017 	ldw	fp,0(sp)
+    4050:	dec00104 	addi	sp,sp,4
+    4054:	f800283a 	ret
 
-00004018 <altera_avalon_jtag_uart_ioctl>:
+00004058 <altera_avalon_jtag_uart_ioctl>:
 /* ----------------------------------------------------------- */
 
 int 
 altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req,
   void* arg)
 {
-    4018:	defffa04 	addi	sp,sp,-24
-    401c:	df000515 	stw	fp,20(sp)
-    4020:	df000504 	addi	fp,sp,20
-    4024:	e13ffd15 	stw	r4,-12(fp)
-    4028:	e17ffe15 	stw	r5,-8(fp)
-    402c:	e1bfff15 	stw	r6,-4(fp)
+    4058:	defffa04 	addi	sp,sp,-24
+    405c:	df000515 	stw	fp,20(sp)
+    4060:	df000504 	addi	fp,sp,20
+    4064:	e13ffd15 	stw	r4,-12(fp)
+    4068:	e17ffc15 	stw	r5,-16(fp)
+    406c:	e1bffb15 	stw	r6,-20(fp)
   int rc = -ENOTTY;
-    4030:	00bff9c4 	movi	r2,-25
-    4034:	e0bffb15 	stw	r2,-20(fp)
+    4070:	00bff9c4 	movi	r2,-25
+    4074:	e0bfff15 	stw	r2,-4(fp)
 
   switch (req)
-    4038:	e0bffe17 	ldw	r2,-8(fp)
-    403c:	10da8060 	cmpeqi	r3,r2,27137
-    4040:	1800031e 	bne	r3,zero,4050 <altera_avalon_jtag_uart_ioctl+0x38>
-    4044:	109a80a0 	cmpeqi	r2,r2,27138
-    4048:	1000181e 	bne	r2,zero,40ac <altera_avalon_jtag_uart_ioctl+0x94>
+    4078:	e0bffc17 	ldw	r2,-16(fp)
+    407c:	109a8060 	cmpeqi	r2,r2,27137
+    4080:	1000041e 	bne	r2,zero,4094 <altera_avalon_jtag_uart_ioctl+0x3c>
+    4084:	e0bffc17 	ldw	r2,-16(fp)
+    4088:	109a80a0 	cmpeqi	r2,r2,27138
+    408c:	1000181e 	bne	r2,zero,40f0 <altera_avalon_jtag_uart_ioctl+0x98>
       rc = 0;
     }
     break;
 
   default:
     break;
-    404c:	00002906 	br	40f4 <altera_avalon_jtag_uart_ioctl+0xdc>
-
-  switch (req)
-  {
-  case TIOCSTIMEOUT:
-    /* Set the time to wait until assuming host is not connected */
+    4090:	00002906 	br	4138 <altera_avalon_jtag_uart_ioctl+0xe0>
     if (sp->timeout != INT_MAX)
-    4050:	e0bffd17 	ldw	r2,-12(fp)
-    4054:	10c00117 	ldw	r3,4(r2)
-    4058:	00a00034 	movhi	r2,32768
-    405c:	10bfffc4 	addi	r2,r2,-1
-    4060:	18802126 	beq	r3,r2,40e8 <altera_avalon_jtag_uart_ioctl+0xd0>
-    {
+    4094:	e0bffd17 	ldw	r2,-12(fp)
+    4098:	10c00117 	ldw	r3,4(r2)
+    409c:	00a00034 	movhi	r2,32768
+    40a0:	10bfffc4 	addi	r2,r2,-1
+    40a4:	18802126 	beq	r3,r2,412c <altera_avalon_jtag_uart_ioctl+0xd4>
       int timeout = *((int *)arg);
-    4064:	e0bfff17 	ldw	r2,-4(fp)
-    4068:	10800017 	ldw	r2,0(r2)
-    406c:	e0bffc15 	stw	r2,-16(fp)
+    40a8:	e0bffb17 	ldw	r2,-20(fp)
+    40ac:	10800017 	ldw	r2,0(r2)
+    40b0:	e0bffe15 	stw	r2,-8(fp)
       sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1;
-    4070:	e0bffc17 	ldw	r2,-16(fp)
-    4074:	10800090 	cmplti	r2,r2,2
-    4078:	1000061e 	bne	r2,zero,4094 <altera_avalon_jtag_uart_ioctl+0x7c>
-    407c:	e0fffc17 	ldw	r3,-16(fp)
-    4080:	00a00034 	movhi	r2,32768
-    4084:	10bfffc4 	addi	r2,r2,-1
-    4088:	18800226 	beq	r3,r2,4094 <altera_avalon_jtag_uart_ioctl+0x7c>
-    408c:	e0bffc17 	ldw	r2,-16(fp)
-    4090:	00000206 	br	409c <altera_avalon_jtag_uart_ioctl+0x84>
-    4094:	00a00034 	movhi	r2,32768
-    4098:	10bfff84 	addi	r2,r2,-2
-    409c:	e0fffd17 	ldw	r3,-12(fp)
-    40a0:	18800115 	stw	r2,4(r3)
+    40b4:	e0bffe17 	ldw	r2,-8(fp)
+    40b8:	10800090 	cmplti	r2,r2,2
+    40bc:	1000061e 	bne	r2,zero,40d8 <altera_avalon_jtag_uart_ioctl+0x80>
+    40c0:	e0fffe17 	ldw	r3,-8(fp)
+    40c4:	00a00034 	movhi	r2,32768
+    40c8:	10bfffc4 	addi	r2,r2,-1
+    40cc:	18800226 	beq	r3,r2,40d8 <altera_avalon_jtag_uart_ioctl+0x80>
+    40d0:	e0bffe17 	ldw	r2,-8(fp)
+    40d4:	00000206 	br	40e0 <altera_avalon_jtag_uart_ioctl+0x88>
+    40d8:	00a00034 	movhi	r2,32768
+    40dc:	10bfff84 	addi	r2,r2,-2
+    40e0:	e0fffd17 	ldw	r3,-12(fp)
+    40e4:	18800115 	stw	r2,4(r3)
       rc = 0;
-    40a4:	e03ffb15 	stw	zero,-20(fp)
-    }
+    40e8:	e03fff15 	stw	zero,-4(fp)
     break;
-    40a8:	00000f06 	br	40e8 <altera_avalon_jtag_uart_ioctl+0xd0>
-
-  case TIOCGCONNECTED:
-    /* Find out whether host is connected */
+    40ec:	00000f06 	br	412c <altera_avalon_jtag_uart_ioctl+0xd4>
     if (sp->timeout != INT_MAX)
-    40ac:	e0bffd17 	ldw	r2,-12(fp)
-    40b0:	10c00117 	ldw	r3,4(r2)
-    40b4:	00a00034 	movhi	r2,32768
-    40b8:	10bfffc4 	addi	r2,r2,-1
-    40bc:	18800c26 	beq	r3,r2,40f0 <altera_avalon_jtag_uart_ioctl+0xd8>
-    {
+    40f0:	e0bffd17 	ldw	r2,-12(fp)
+    40f4:	10c00117 	ldw	r3,4(r2)
+    40f8:	00a00034 	movhi	r2,32768
+    40fc:	10bfffc4 	addi	r2,r2,-1
+    4100:	18800c26 	beq	r3,r2,4134 <altera_avalon_jtag_uart_ioctl+0xdc>
       *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0;
-    40c0:	e0bffd17 	ldw	r2,-12(fp)
-    40c4:	10c00917 	ldw	r3,36(r2)
-    40c8:	e0bffd17 	ldw	r2,-12(fp)
-    40cc:	10800117 	ldw	r2,4(r2)
-    40d0:	1885803a 	cmpltu	r2,r3,r2
-    40d4:	10c03fcc 	andi	r3,r2,255
-    40d8:	e0bfff17 	ldw	r2,-4(fp)
-    40dc:	10c00015 	stw	r3,0(r2)
+    4104:	e0bffd17 	ldw	r2,-12(fp)
+    4108:	10c00917 	ldw	r3,36(r2)
+    410c:	e0bffd17 	ldw	r2,-12(fp)
+    4110:	10800117 	ldw	r2,4(r2)
+    4114:	1885803a 	cmpltu	r2,r3,r2
+    4118:	10c03fcc 	andi	r3,r2,255
+    411c:	e0bffb17 	ldw	r2,-20(fp)
+    4120:	10c00015 	stw	r3,0(r2)
       rc = 0;
-    40e0:	e03ffb15 	stw	zero,-20(fp)
-    }
+    4124:	e03fff15 	stw	zero,-4(fp)
     break;
-    40e4:	00000206 	br	40f0 <altera_avalon_jtag_uart_ioctl+0xd8>
-    {
-      int timeout = *((int *)arg);
-      sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1;
-      rc = 0;
-    }
+    4128:	00000206 	br	4134 <altera_avalon_jtag_uart_ioctl+0xdc>
     break;
-    40e8:	0001883a 	nop
-    40ec:	00000106 	br	40f4 <altera_avalon_jtag_uart_ioctl+0xdc>
-    if (sp->timeout != INT_MAX)
-    {
-      *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0;
-      rc = 0;
-    }
-    break;
-    40f0:	0001883a 	nop
-
-  default:
+    412c:	0001883a 	nop
+    4130:	00000106 	br	4138 <altera_avalon_jtag_uart_ioctl+0xe0>
     break;
+    4134:	0001883a 	nop
   }
 
   return rc;
-    40f4:	e0bffb17 	ldw	r2,-20(fp)
+    4138:	e0bfff17 	ldw	r2,-4(fp)
 }
-    40f8:	e037883a 	mov	sp,fp
-    40fc:	df000017 	ldw	fp,0(sp)
-    4100:	dec00104 	addi	sp,sp,4
-    4104:	f800283a 	ret
+    413c:	e037883a 	mov	sp,fp
+    4140:	df000017 	ldw	fp,0(sp)
+    4144:	dec00104 	addi	sp,sp,4
+    4148:	f800283a 	ret
 
-00004108 <altera_avalon_jtag_uart_read>:
+0000414c <altera_avalon_jtag_uart_read>:
 /* ----------------------------------------------------------- */
 
 int 
 altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, 
   char * buffer, int space, int flags)
 {
-    4108:	defff304 	addi	sp,sp,-52
-    410c:	dfc00c15 	stw	ra,48(sp)
-    4110:	df000b15 	stw	fp,44(sp)
-    4114:	df000b04 	addi	fp,sp,44
-    4118:	e13ffc15 	stw	r4,-16(fp)
-    411c:	e17ffd15 	stw	r5,-12(fp)
-    4120:	e1bffe15 	stw	r6,-8(fp)
-    4124:	e1ffff15 	stw	r7,-4(fp)
+    414c:	defff304 	addi	sp,sp,-52
+    4150:	dfc00c15 	stw	ra,48(sp)
+    4154:	df000b15 	stw	fp,44(sp)
+    4158:	df000b04 	addi	fp,sp,44
+    415c:	e13ff815 	stw	r4,-32(fp)
+    4160:	e17ff715 	stw	r5,-36(fp)
+    4164:	e1bff615 	stw	r6,-40(fp)
+    4168:	e1fff515 	stw	r7,-44(fp)
   char * ptr = buffer;
-    4128:	e0bffd17 	ldw	r2,-12(fp)
-    412c:	e0bff515 	stw	r2,-44(fp)
+    416c:	e0bff717 	ldw	r2,-36(fp)
+    4170:	e0bfff15 	stw	r2,-4(fp)
    * When running in a multi threaded environment, obtain the "read_lock"
    * semaphore. This ensures that reading from the device is thread-safe.
    */
   ALT_SEM_PEND (sp->read_lock, 0);
 
   while (space > 0)
-    4130:	00004706 	br	4250 <altera_avalon_jtag_uart_read+0x148>
+    4174:	00004706 	br	4294 <altera_avalon_jtag_uart_read+0x148>
     unsigned int in, out;
 
     /* Read as much data as possible */
     do
     {
       in  = sp->rx_in;
-    4134:	e0bffc17 	ldw	r2,-16(fp)
-    4138:	10800a17 	ldw	r2,40(r2)
-    413c:	e0bff715 	stw	r2,-36(fp)
+    4178:	e0bff817 	ldw	r2,-32(fp)
+    417c:	10800a17 	ldw	r2,40(r2)
+    4180:	e0bffd15 	stw	r2,-12(fp)
       out = sp->rx_out;
-    4140:	e0bffc17 	ldw	r2,-16(fp)
-    4144:	10800b17 	ldw	r2,44(r2)
-    4148:	e0bff815 	stw	r2,-32(fp)
+    4184:	e0bff817 	ldw	r2,-32(fp)
+    4188:	10800b17 	ldw	r2,44(r2)
+    418c:	e0bffc15 	stw	r2,-16(fp)
 
       if (in >= out)
-    414c:	e0fff717 	ldw	r3,-36(fp)
-    4150:	e0bff817 	ldw	r2,-32(fp)
-    4154:	18800536 	bltu	r3,r2,416c <altera_avalon_jtag_uart_read+0x64>
+    4190:	e0fffd17 	ldw	r3,-12(fp)
+    4194:	e0bffc17 	ldw	r2,-16(fp)
+    4198:	18800536 	bltu	r3,r2,41b0 <altera_avalon_jtag_uart_read+0x64>
         n = in - out;
-    4158:	e0fff717 	ldw	r3,-36(fp)
-    415c:	e0bff817 	ldw	r2,-32(fp)
-    4160:	1885c83a 	sub	r2,r3,r2
-    4164:	e0bff615 	stw	r2,-40(fp)
-    4168:	00000406 	br	417c <altera_avalon_jtag_uart_read+0x74>
+    419c:	e0fffd17 	ldw	r3,-12(fp)
+    41a0:	e0bffc17 	ldw	r2,-16(fp)
+    41a4:	1885c83a 	sub	r2,r3,r2
+    41a8:	e0bffe15 	stw	r2,-8(fp)
+    41ac:	00000406 	br	41c0 <altera_avalon_jtag_uart_read+0x74>
       else
         n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out;
-    416c:	00c20004 	movi	r3,2048
-    4170:	e0bff817 	ldw	r2,-32(fp)
-    4174:	1885c83a 	sub	r2,r3,r2
-    4178:	e0bff615 	stw	r2,-40(fp)
+    41b0:	00c20004 	movi	r3,2048
+    41b4:	e0bffc17 	ldw	r2,-16(fp)
+    41b8:	1885c83a 	sub	r2,r3,r2
+    41bc:	e0bffe15 	stw	r2,-8(fp)
 
       if (n == 0)
-    417c:	e0bff617 	ldw	r2,-40(fp)
-    4180:	10001e26 	beq	r2,zero,41fc <altera_avalon_jtag_uart_read+0xf4>
+    41c0:	e0bffe17 	ldw	r2,-8(fp)
+    41c4:	10001e26 	beq	r2,zero,4240 <altera_avalon_jtag_uart_read+0xf4>
         break; /* No more data available */
 
       if (n > space)
-    4184:	e0fffe17 	ldw	r3,-8(fp)
-    4188:	e0bff617 	ldw	r2,-40(fp)
-    418c:	1880022e 	bgeu	r3,r2,4198 <altera_avalon_jtag_uart_read+0x90>
+    41c8:	e0fff617 	ldw	r3,-40(fp)
+    41cc:	e0bffe17 	ldw	r2,-8(fp)
+    41d0:	1880022e 	bgeu	r3,r2,41dc <altera_avalon_jtag_uart_read+0x90>
         n = space;
-    4190:	e0bffe17 	ldw	r2,-8(fp)
-    4194:	e0bff615 	stw	r2,-40(fp)
+    41d4:	e0bff617 	ldw	r2,-40(fp)
+    41d8:	e0bffe15 	stw	r2,-8(fp)
 
       memcpy(ptr, sp->rx_buf + out, n);
-    4198:	e0bffc17 	ldw	r2,-16(fp)
-    419c:	10c00e04 	addi	r3,r2,56
-    41a0:	e0bff817 	ldw	r2,-32(fp)
-    41a4:	1885883a 	add	r2,r3,r2
-    41a8:	e1bff617 	ldw	r6,-40(fp)
-    41ac:	100b883a 	mov	r5,r2
-    41b0:	e13ff517 	ldw	r4,-44(fp)
-    41b4:	00017940 	call	1794 <memcpy>
+    41dc:	e0bff817 	ldw	r2,-32(fp)
+    41e0:	10c00e04 	addi	r3,r2,56
+    41e4:	e0bffc17 	ldw	r2,-16(fp)
+    41e8:	1885883a 	add	r2,r3,r2
+    41ec:	e1bffe17 	ldw	r6,-8(fp)
+    41f0:	100b883a 	mov	r5,r2
+    41f4:	e13fff17 	ldw	r4,-4(fp)
+    41f8:	00016d40 	call	16d4 <memcpy>
       ptr   += n;
-    41b8:	e0fff517 	ldw	r3,-44(fp)
-    41bc:	e0bff617 	ldw	r2,-40(fp)
-    41c0:	1885883a 	add	r2,r3,r2
-    41c4:	e0bff515 	stw	r2,-44(fp)
+    41fc:	e0ffff17 	ldw	r3,-4(fp)
+    4200:	e0bffe17 	ldw	r2,-8(fp)
+    4204:	1885883a 	add	r2,r3,r2
+    4208:	e0bfff15 	stw	r2,-4(fp)
       space -= n;
-    41c8:	e0fffe17 	ldw	r3,-8(fp)
-    41cc:	e0bff617 	ldw	r2,-40(fp)
-    41d0:	1885c83a 	sub	r2,r3,r2
-    41d4:	e0bffe15 	stw	r2,-8(fp)
+    420c:	e0fff617 	ldw	r3,-40(fp)
+    4210:	e0bffe17 	ldw	r2,-8(fp)
+    4214:	1885c83a 	sub	r2,r3,r2
+    4218:	e0bff615 	stw	r2,-40(fp)
 
       sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    41d8:	e0fff817 	ldw	r3,-32(fp)
-    41dc:	e0bff617 	ldw	r2,-40(fp)
-    41e0:	1885883a 	add	r2,r3,r2
-    41e4:	10c1ffcc 	andi	r3,r2,2047
-    41e8:	e0bffc17 	ldw	r2,-16(fp)
-    41ec:	10c00b15 	stw	r3,44(r2)
+    421c:	e0fffc17 	ldw	r3,-16(fp)
+    4220:	e0bffe17 	ldw	r2,-8(fp)
+    4224:	1885883a 	add	r2,r3,r2
+    4228:	10c1ffcc 	andi	r3,r2,2047
+    422c:	e0bff817 	ldw	r2,-32(fp)
+    4230:	10c00b15 	stw	r3,44(r2)
     }
     while (space > 0);
-    41f0:	e0bffe17 	ldw	r2,-8(fp)
-    41f4:	00bfcf16 	blt	zero,r2,4134 <__alt_data_end+0xfffe4134>
-    41f8:	00000106 	br	4200 <altera_avalon_jtag_uart_read+0xf8>
-        n = in - out;
-      else
-        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out;
-
-      if (n == 0)
+    4234:	e0bff617 	ldw	r2,-40(fp)
+    4238:	00bfcf16 	blt	zero,r2,4178 <altera_avalon_jtag_uart_read+0x2c>
+    423c:	00000106 	br	4244 <altera_avalon_jtag_uart_read+0xf8>
         break; /* No more data available */
-    41fc:	0001883a 	nop
-      sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    }
-    while (space > 0);
+    4240:	0001883a 	nop
 
     /* If we read any data then return it */
     if (ptr != buffer)
-    4200:	e0fff517 	ldw	r3,-44(fp)
-    4204:	e0bffd17 	ldw	r2,-12(fp)
-    4208:	1880141e 	bne	r3,r2,425c <altera_avalon_jtag_uart_read+0x154>
+    4244:	e0ffff17 	ldw	r3,-4(fp)
+    4248:	e0bff717 	ldw	r2,-36(fp)
+    424c:	1880141e 	bne	r3,r2,42a0 <altera_avalon_jtag_uart_read+0x154>
       break;
 
     /* If in non-blocking mode then return error */
     if (flags & O_NONBLOCK)
-    420c:	e0bfff17 	ldw	r2,-4(fp)
-    4210:	1090000c 	andi	r2,r2,16384
-    4214:	1000131e 	bne	r2,zero,4264 <altera_avalon_jtag_uart_read+0x15c>
+    4250:	e0bff517 	ldw	r2,-44(fp)
+    4254:	1090000c 	andi	r2,r2,16384
+    4258:	1000131e 	bne	r2,zero,42a8 <altera_avalon_jtag_uart_read+0x15c>
       while (in == sp->rx_in && sp->host_inactive < sp->timeout)
         ;
     }
 #else
     /* No OS: Always spin */
     while (in == sp->rx_in && sp->host_inactive < sp->timeout)
-    4218:	0001883a 	nop
-    421c:	e0bffc17 	ldw	r2,-16(fp)
-    4220:	10c00a17 	ldw	r3,40(r2)
-    4224:	e0bff717 	ldw	r2,-36(fp)
-    4228:	1880051e 	bne	r3,r2,4240 <altera_avalon_jtag_uart_read+0x138>
-    422c:	e0bffc17 	ldw	r2,-16(fp)
-    4230:	10c00917 	ldw	r3,36(r2)
-    4234:	e0bffc17 	ldw	r2,-16(fp)
-    4238:	10800117 	ldw	r2,4(r2)
-    423c:	18bff736 	bltu	r3,r2,421c <__alt_data_end+0xfffe421c>
-      ;
-#endif /* __ucosii__ */
-
-    if (in == sp->rx_in)
-    4240:	e0bffc17 	ldw	r2,-16(fp)
-    4244:	10c00a17 	ldw	r3,40(r2)
-    4248:	e0bff717 	ldw	r2,-36(fp)
-    424c:	18800726 	beq	r3,r2,426c <altera_avalon_jtag_uart_read+0x164>
-   * When running in a multi threaded environment, obtain the "read_lock"
-   * semaphore. This ensures that reading from the device is thread-safe.
-   */
-  ALT_SEM_PEND (sp->read_lock, 0);
-
-  while (space > 0)
-    4250:	e0bffe17 	ldw	r2,-8(fp)
-    4254:	00bfb716 	blt	zero,r2,4134 <__alt_data_end+0xfffe4134>
-    4258:	00000506 	br	4270 <altera_avalon_jtag_uart_read+0x168>
-    }
-    while (space > 0);
-
-    /* If we read any data then return it */
-    if (ptr != buffer)
-      break;
     425c:	0001883a 	nop
-    4260:	00000306 	br	4270 <altera_avalon_jtag_uart_read+0x168>
-
-    /* If in non-blocking mode then return error */
-    if (flags & O_NONBLOCK)
-      break;
-    4264:	0001883a 	nop
-    4268:	00000106 	br	4270 <altera_avalon_jtag_uart_read+0x168>
-    while (in == sp->rx_in && sp->host_inactive < sp->timeout)
+    4260:	e0bff817 	ldw	r2,-32(fp)
+    4264:	10800a17 	ldw	r2,40(r2)
+    4268:	e0fffd17 	ldw	r3,-12(fp)
+    426c:	1880051e 	bne	r3,r2,4284 <altera_avalon_jtag_uart_read+0x138>
+    4270:	e0bff817 	ldw	r2,-32(fp)
+    4274:	10c00917 	ldw	r3,36(r2)
+    4278:	e0bff817 	ldw	r2,-32(fp)
+    427c:	10800117 	ldw	r2,4(r2)
+    4280:	18bff736 	bltu	r3,r2,4260 <altera_avalon_jtag_uart_read+0x114>
       ;
 #endif /* __ucosii__ */
 
     if (in == sp->rx_in)
+    4284:	e0bff817 	ldw	r2,-32(fp)
+    4288:	10800a17 	ldw	r2,40(r2)
+    428c:	e0fffd17 	ldw	r3,-12(fp)
+    4290:	18800726 	beq	r3,r2,42b0 <altera_avalon_jtag_uart_read+0x164>
+  while (space > 0)
+    4294:	e0bff617 	ldw	r2,-40(fp)
+    4298:	00bfb716 	blt	zero,r2,4178 <altera_avalon_jtag_uart_read+0x2c>
+    429c:	00000506 	br	42b4 <altera_avalon_jtag_uart_read+0x168>
       break;
-    426c:	0001883a 	nop
+    42a0:	0001883a 	nop
+    42a4:	00000306 	br	42b4 <altera_avalon_jtag_uart_read+0x168>
+      break;
+    42a8:	0001883a 	nop
+    42ac:	00000106 	br	42b4 <altera_avalon_jtag_uart_read+0x168>
+      break;
+    42b0:	0001883a 	nop
    * semaphore so that other threads can access the buffer.
    */
 
   ALT_SEM_POST (sp->read_lock);
 
   if (ptr != buffer)
-    4270:	e0fff517 	ldw	r3,-44(fp)
-    4274:	e0bffd17 	ldw	r2,-12(fp)
-    4278:	18801826 	beq	r3,r2,42dc <altera_avalon_jtag_uart_read+0x1d4>
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    42b4:	e0ffff17 	ldw	r3,-4(fp)
+    42b8:	e0bff717 	ldw	r2,-36(fp)
+    42bc:	18801926 	beq	r3,r2,4324 <altera_avalon_jtag_uart_read+0x1d8>
   NIOS2_READ_STATUS (context);
-    427c:	0005303a 	rdctl	r2,status
-    4280:	e0bffb15 	stw	r2,-20(fp)
-
+    42c0:	0005303a 	rdctl	r2,status
+    42c4:	e0bff915 	stw	r2,-28(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    4284:	e0fffb17 	ldw	r3,-20(fp)
-    4288:	00bfff84 	movi	r2,-2
-    428c:	1884703a 	and	r2,r3,r2
-    4290:	1001703a 	wrctl	status,r2
-  
+    42c8:	e0fff917 	ldw	r3,-28(fp)
+    42cc:	00bfff84 	movi	r2,-2
+    42d0:	1884703a 	and	r2,r3,r2
+    42d4:	1001703a 	wrctl	status,r2
   return context;
-    4294:	e0bffb17 	ldw	r2,-20(fp)
+    42d8:	e0bff917 	ldw	r2,-28(fp)
   {
     /* If we read any data then there is space in the buffer so enable interrupts */
     context = alt_irq_disable_all();
-    4298:	e0bffa15 	stw	r2,-24(fp)
+    42dc:	e0bffb15 	stw	r2,-20(fp)
     sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
-    429c:	e0bffc17 	ldw	r2,-16(fp)
-    42a0:	10800817 	ldw	r2,32(r2)
-    42a4:	10c00054 	ori	r3,r2,1
-    42a8:	e0bffc17 	ldw	r2,-16(fp)
-    42ac:	10c00815 	stw	r3,32(r2)
+    42e0:	e0bff817 	ldw	r2,-32(fp)
+    42e4:	10800817 	ldw	r2,32(r2)
+    42e8:	10c00054 	ori	r3,r2,1
+    42ec:	e0bff817 	ldw	r2,-32(fp)
+    42f0:	10c00815 	stw	r3,32(r2)
     IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
-    42b0:	e0bffc17 	ldw	r2,-16(fp)
-    42b4:	10800017 	ldw	r2,0(r2)
-    42b8:	10800104 	addi	r2,r2,4
-    42bc:	1007883a 	mov	r3,r2
-    42c0:	e0bffc17 	ldw	r2,-16(fp)
-    42c4:	10800817 	ldw	r2,32(r2)
-    42c8:	18800035 	stwio	r2,0(r3)
-    42cc:	e0bffa17 	ldw	r2,-24(fp)
-    42d0:	e0bff915 	stw	r2,-28(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    42f4:	e0bff817 	ldw	r2,-32(fp)
+    42f8:	10800017 	ldw	r2,0(r2)
+    42fc:	10800104 	addi	r2,r2,4
+    4300:	1007883a 	mov	r3,r2
+    4304:	e0bff817 	ldw	r2,-32(fp)
+    4308:	10800817 	ldw	r2,32(r2)
+    430c:	18800035 	stwio	r2,0(r3)
+    4310:	e0bffb17 	ldw	r2,-20(fp)
+    4314:	e0bffa15 	stw	r2,-24(fp)
   NIOS2_WRITE_STATUS (context);
-    42d4:	e0bff917 	ldw	r2,-28(fp)
-    42d8:	1001703a 	wrctl	status,r2
+    4318:	e0bffa17 	ldw	r2,-24(fp)
+    431c:	1001703a 	wrctl	status,r2
+}
+    4320:	0001883a 	nop
     alt_irq_enable_all(context);
   }
 
   if (ptr != buffer)
-    42dc:	e0fff517 	ldw	r3,-44(fp)
-    42e0:	e0bffd17 	ldw	r2,-12(fp)
-    42e4:	18800426 	beq	r3,r2,42f8 <altera_avalon_jtag_uart_read+0x1f0>
+    4324:	e0ffff17 	ldw	r3,-4(fp)
+    4328:	e0bff717 	ldw	r2,-36(fp)
+    432c:	18800426 	beq	r3,r2,4340 <altera_avalon_jtag_uart_read+0x1f4>
     return ptr - buffer;
-    42e8:	e0fff517 	ldw	r3,-44(fp)
-    42ec:	e0bffd17 	ldw	r2,-12(fp)
-    42f0:	1885c83a 	sub	r2,r3,r2
-    42f4:	00000606 	br	4310 <altera_avalon_jtag_uart_read+0x208>
+    4330:	e0ffff17 	ldw	r3,-4(fp)
+    4334:	e0bff717 	ldw	r2,-36(fp)
+    4338:	1885c83a 	sub	r2,r3,r2
+    433c:	00000606 	br	4358 <altera_avalon_jtag_uart_read+0x20c>
   else if (flags & O_NONBLOCK)
-    42f8:	e0bfff17 	ldw	r2,-4(fp)
-    42fc:	1090000c 	andi	r2,r2,16384
-    4300:	10000226 	beq	r2,zero,430c <altera_avalon_jtag_uart_read+0x204>
+    4340:	e0bff517 	ldw	r2,-44(fp)
+    4344:	1090000c 	andi	r2,r2,16384
+    4348:	10000226 	beq	r2,zero,4354 <altera_avalon_jtag_uart_read+0x208>
     return -EWOULDBLOCK;
-    4304:	00bffd44 	movi	r2,-11
-    4308:	00000106 	br	4310 <altera_avalon_jtag_uart_read+0x208>
+    434c:	00bffd44 	movi	r2,-11
+    4350:	00000106 	br	4358 <altera_avalon_jtag_uart_read+0x20c>
   else
     return -EIO;
-    430c:	00bffec4 	movi	r2,-5
+    4354:	00bffec4 	movi	r2,-5
 }
-    4310:	e037883a 	mov	sp,fp
-    4314:	dfc00117 	ldw	ra,4(sp)
-    4318:	df000017 	ldw	fp,0(sp)
-    431c:	dec00204 	addi	sp,sp,8
-    4320:	f800283a 	ret
+    4358:	e037883a 	mov	sp,fp
+    435c:	dfc00117 	ldw	ra,4(sp)
+    4360:	df000017 	ldw	fp,0(sp)
+    4364:	dec00204 	addi	sp,sp,8
+    4368:	f800283a 	ret
 
-00004324 <altera_avalon_jtag_uart_write>:
+0000436c <altera_avalon_jtag_uart_write>:
 /* ----------------------------------------------------------- */
 
 int 
 altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, 
   const char * ptr, int count, int flags)
 {
-    4324:	defff304 	addi	sp,sp,-52
-    4328:	dfc00c15 	stw	ra,48(sp)
-    432c:	df000b15 	stw	fp,44(sp)
-    4330:	df000b04 	addi	fp,sp,44
-    4334:	e13ffc15 	stw	r4,-16(fp)
-    4338:	e17ffd15 	stw	r5,-12(fp)
-    433c:	e1bffe15 	stw	r6,-8(fp)
-    4340:	e1ffff15 	stw	r7,-4(fp)
+    436c:	defff304 	addi	sp,sp,-52
+    4370:	dfc00c15 	stw	ra,48(sp)
+    4374:	df000b15 	stw	fp,44(sp)
+    4378:	df000b04 	addi	fp,sp,44
+    437c:	e13ff815 	stw	r4,-32(fp)
+    4380:	e17ff715 	stw	r5,-36(fp)
+    4384:	e1bff615 	stw	r6,-40(fp)
+    4388:	e1fff515 	stw	r7,-44(fp)
   /* Remove warning at optimisation level 03 by seting out to 0 */
   unsigned int in, out=0;
-    4344:	e03ff515 	stw	zero,-44(fp)
+    438c:	e03fff15 	stw	zero,-4(fp)
   unsigned int n;
   alt_irq_context context;
 
   const char * start = ptr;
-    4348:	e0bffd17 	ldw	r2,-12(fp)
-    434c:	e0bff715 	stw	r2,-36(fp)
+    4390:	e0bff717 	ldw	r2,-36(fp)
+    4394:	e0bffd15 	stw	r2,-12(fp)
   ALT_SEM_PEND (sp->write_lock, 0);
 
   do
   {
     /* Copy as much as we can into the transmit buffer */
     while (count > 0)
-    4350:	00003706 	br	4430 <altera_avalon_jtag_uart_write+0x10c>
+    4398:	00003706 	br	4478 <altera_avalon_jtag_uart_write+0x10c>
     {
       /* We need a stable value of the out pointer to calculate the space available */
       in  = sp->tx_in;
-    4354:	e0bffc17 	ldw	r2,-16(fp)
-    4358:	10800c17 	ldw	r2,48(r2)
-    435c:	e0bff915 	stw	r2,-28(fp)
+    439c:	e0bff817 	ldw	r2,-32(fp)
+    43a0:	10800c17 	ldw	r2,48(r2)
+    43a4:	e0bffc15 	stw	r2,-16(fp)
       out = sp->tx_out;
-    4360:	e0bffc17 	ldw	r2,-16(fp)
-    4364:	10800d17 	ldw	r2,52(r2)
-    4368:	e0bff515 	stw	r2,-44(fp)
+    43a8:	e0bff817 	ldw	r2,-32(fp)
+    43ac:	10800d17 	ldw	r2,52(r2)
+    43b0:	e0bfff15 	stw	r2,-4(fp)
 
       if (in < out)
-    436c:	e0fff917 	ldw	r3,-28(fp)
-    4370:	e0bff517 	ldw	r2,-44(fp)
-    4374:	1880062e 	bgeu	r3,r2,4390 <altera_avalon_jtag_uart_write+0x6c>
+    43b4:	e0fffc17 	ldw	r3,-16(fp)
+    43b8:	e0bfff17 	ldw	r2,-4(fp)
+    43bc:	1880062e 	bgeu	r3,r2,43d8 <altera_avalon_jtag_uart_write+0x6c>
         n = out - 1 - in;
-    4378:	e0fff517 	ldw	r3,-44(fp)
-    437c:	e0bff917 	ldw	r2,-28(fp)
-    4380:	1885c83a 	sub	r2,r3,r2
-    4384:	10bfffc4 	addi	r2,r2,-1
-    4388:	e0bff615 	stw	r2,-40(fp)
-    438c:	00000b06 	br	43bc <altera_avalon_jtag_uart_write+0x98>
+    43c0:	e0ffff17 	ldw	r3,-4(fp)
+    43c4:	e0bffc17 	ldw	r2,-16(fp)
+    43c8:	1885c83a 	sub	r2,r3,r2
+    43cc:	10bfffc4 	addi	r2,r2,-1
+    43d0:	e0bffe15 	stw	r2,-8(fp)
+    43d4:	00000b06 	br	4404 <altera_avalon_jtag_uart_write+0x98>
       else if (out > 0)
-    4390:	e0bff517 	ldw	r2,-44(fp)
-    4394:	10000526 	beq	r2,zero,43ac <altera_avalon_jtag_uart_write+0x88>
+    43d8:	e0bfff17 	ldw	r2,-4(fp)
+    43dc:	10000526 	beq	r2,zero,43f4 <altera_avalon_jtag_uart_write+0x88>
         n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in;
-    4398:	00c20004 	movi	r3,2048
-    439c:	e0bff917 	ldw	r2,-28(fp)
-    43a0:	1885c83a 	sub	r2,r3,r2
-    43a4:	e0bff615 	stw	r2,-40(fp)
-    43a8:	00000406 	br	43bc <altera_avalon_jtag_uart_write+0x98>
+    43e0:	00c20004 	movi	r3,2048
+    43e4:	e0bffc17 	ldw	r2,-16(fp)
+    43e8:	1885c83a 	sub	r2,r3,r2
+    43ec:	e0bffe15 	stw	r2,-8(fp)
+    43f0:	00000406 	br	4404 <altera_avalon_jtag_uart_write+0x98>
       else
         n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in;
-    43ac:	00c1ffc4 	movi	r3,2047
-    43b0:	e0bff917 	ldw	r2,-28(fp)
-    43b4:	1885c83a 	sub	r2,r3,r2
-    43b8:	e0bff615 	stw	r2,-40(fp)
+    43f4:	00c1ffc4 	movi	r3,2047
+    43f8:	e0bffc17 	ldw	r2,-16(fp)
+    43fc:	1885c83a 	sub	r2,r3,r2
+    4400:	e0bffe15 	stw	r2,-8(fp)
 
       if (n == 0)
-    43bc:	e0bff617 	ldw	r2,-40(fp)
-    43c0:	10001e26 	beq	r2,zero,443c <altera_avalon_jtag_uart_write+0x118>
+    4404:	e0bffe17 	ldw	r2,-8(fp)
+    4408:	10001e26 	beq	r2,zero,4484 <altera_avalon_jtag_uart_write+0x118>
         break;
 
       if (n > count)
-    43c4:	e0fffe17 	ldw	r3,-8(fp)
-    43c8:	e0bff617 	ldw	r2,-40(fp)
-    43cc:	1880022e 	bgeu	r3,r2,43d8 <altera_avalon_jtag_uart_write+0xb4>
+    440c:	e0fff617 	ldw	r3,-40(fp)
+    4410:	e0bffe17 	ldw	r2,-8(fp)
+    4414:	1880022e 	bgeu	r3,r2,4420 <altera_avalon_jtag_uart_write+0xb4>
         n = count;
-    43d0:	e0bffe17 	ldw	r2,-8(fp)
-    43d4:	e0bff615 	stw	r2,-40(fp)
+    4418:	e0bff617 	ldw	r2,-40(fp)
+    441c:	e0bffe15 	stw	r2,-8(fp)
 
       memcpy(sp->tx_buf + in, ptr, n);
-    43d8:	e0bffc17 	ldw	r2,-16(fp)
-    43dc:	10c20e04 	addi	r3,r2,2104
-    43e0:	e0bff917 	ldw	r2,-28(fp)
-    43e4:	1885883a 	add	r2,r3,r2
-    43e8:	e1bff617 	ldw	r6,-40(fp)
-    43ec:	e17ffd17 	ldw	r5,-12(fp)
-    43f0:	1009883a 	mov	r4,r2
-    43f4:	00017940 	call	1794 <memcpy>
+    4420:	e0bff817 	ldw	r2,-32(fp)
+    4424:	10c20e04 	addi	r3,r2,2104
+    4428:	e0bffc17 	ldw	r2,-16(fp)
+    442c:	1885883a 	add	r2,r3,r2
+    4430:	e1bffe17 	ldw	r6,-8(fp)
+    4434:	e17ff717 	ldw	r5,-36(fp)
+    4438:	1009883a 	mov	r4,r2
+    443c:	00016d40 	call	16d4 <memcpy>
       ptr   += n;
-    43f8:	e0fffd17 	ldw	r3,-12(fp)
-    43fc:	e0bff617 	ldw	r2,-40(fp)
-    4400:	1885883a 	add	r2,r3,r2
-    4404:	e0bffd15 	stw	r2,-12(fp)
+    4440:	e0fff717 	ldw	r3,-36(fp)
+    4444:	e0bffe17 	ldw	r2,-8(fp)
+    4448:	1885883a 	add	r2,r3,r2
+    444c:	e0bff715 	stw	r2,-36(fp)
       count -= n;
-    4408:	e0fffe17 	ldw	r3,-8(fp)
-    440c:	e0bff617 	ldw	r2,-40(fp)
-    4410:	1885c83a 	sub	r2,r3,r2
-    4414:	e0bffe15 	stw	r2,-8(fp)
+    4450:	e0fff617 	ldw	r3,-40(fp)
+    4454:	e0bffe17 	ldw	r2,-8(fp)
+    4458:	1885c83a 	sub	r2,r3,r2
+    445c:	e0bff615 	stw	r2,-40(fp)
 
       sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
-    4418:	e0fff917 	ldw	r3,-28(fp)
-    441c:	e0bff617 	ldw	r2,-40(fp)
-    4420:	1885883a 	add	r2,r3,r2
-    4424:	10c1ffcc 	andi	r3,r2,2047
-    4428:	e0bffc17 	ldw	r2,-16(fp)
-    442c:	10c00c15 	stw	r3,48(r2)
-  ALT_SEM_PEND (sp->write_lock, 0);
-
-  do
-  {
-    /* Copy as much as we can into the transmit buffer */
+    4460:	e0fffc17 	ldw	r3,-16(fp)
+    4464:	e0bffe17 	ldw	r2,-8(fp)
+    4468:	1885883a 	add	r2,r3,r2
+    446c:	10c1ffcc 	andi	r3,r2,2047
+    4470:	e0bff817 	ldw	r2,-32(fp)
+    4474:	10c00c15 	stw	r3,48(r2)
     while (count > 0)
-    4430:	e0bffe17 	ldw	r2,-8(fp)
-    4434:	00bfc716 	blt	zero,r2,4354 <__alt_data_end+0xfffe4354>
-    4438:	00000106 	br	4440 <altera_avalon_jtag_uart_write+0x11c>
-        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in;
-      else
-        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in;
-
-      if (n == 0)
+    4478:	e0bff617 	ldw	r2,-40(fp)
+    447c:	00bfc716 	blt	zero,r2,439c <altera_avalon_jtag_uart_write+0x30>
+    4480:	00000106 	br	4488 <altera_avalon_jtag_uart_write+0x11c>
         break;
-    443c:	0001883a 	nop
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    4484:	0001883a 	nop
   NIOS2_READ_STATUS (context);
-    4440:	0005303a 	rdctl	r2,status
-    4444:	e0bffb15 	stw	r2,-20(fp)
-
+    4488:	0005303a 	rdctl	r2,status
+    448c:	e0bff915 	stw	r2,-28(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    4448:	e0fffb17 	ldw	r3,-20(fp)
-    444c:	00bfff84 	movi	r2,-2
-    4450:	1884703a 	and	r2,r3,r2
-    4454:	1001703a 	wrctl	status,r2
-  
+    4490:	e0fff917 	ldw	r3,-28(fp)
+    4494:	00bfff84 	movi	r2,-2
+    4498:	1884703a 	and	r2,r3,r2
+    449c:	1001703a 	wrctl	status,r2
   return context;
-    4458:	e0bffb17 	ldw	r2,-20(fp)
+    44a0:	e0bff917 	ldw	r2,-28(fp)
      * to enable interrupts if there is no space left in the FIFO
      *
      * For now kick the interrupt routine every time to make it transmit 
      * the data 
      */
     context = alt_irq_disable_all();
-    445c:	e0bffa15 	stw	r2,-24(fp)
+    44a4:	e0bffb15 	stw	r2,-20(fp)
     sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK;
-    4460:	e0bffc17 	ldw	r2,-16(fp)
-    4464:	10800817 	ldw	r2,32(r2)
-    4468:	10c00094 	ori	r3,r2,2
-    446c:	e0bffc17 	ldw	r2,-16(fp)
-    4470:	10c00815 	stw	r3,32(r2)
+    44a8:	e0bff817 	ldw	r2,-32(fp)
+    44ac:	10800817 	ldw	r2,32(r2)
+    44b0:	10c00094 	ori	r3,r2,2
+    44b4:	e0bff817 	ldw	r2,-32(fp)
+    44b8:	10c00815 	stw	r3,32(r2)
     IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
-    4474:	e0bffc17 	ldw	r2,-16(fp)
-    4478:	10800017 	ldw	r2,0(r2)
-    447c:	10800104 	addi	r2,r2,4
-    4480:	1007883a 	mov	r3,r2
-    4484:	e0bffc17 	ldw	r2,-16(fp)
-    4488:	10800817 	ldw	r2,32(r2)
-    448c:	18800035 	stwio	r2,0(r3)
-    4490:	e0bffa17 	ldw	r2,-24(fp)
-    4494:	e0bff815 	stw	r2,-32(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    44bc:	e0bff817 	ldw	r2,-32(fp)
+    44c0:	10800017 	ldw	r2,0(r2)
+    44c4:	10800104 	addi	r2,r2,4
+    44c8:	1007883a 	mov	r3,r2
+    44cc:	e0bff817 	ldw	r2,-32(fp)
+    44d0:	10800817 	ldw	r2,32(r2)
+    44d4:	18800035 	stwio	r2,0(r3)
+    44d8:	e0bffb17 	ldw	r2,-20(fp)
+    44dc:	e0bffa15 	stw	r2,-24(fp)
   NIOS2_WRITE_STATUS (context);
-    4498:	e0bff817 	ldw	r2,-32(fp)
-    449c:	1001703a 	wrctl	status,r2
+    44e0:	e0bffa17 	ldw	r2,-24(fp)
+    44e4:	1001703a 	wrctl	status,r2
+}
+    44e8:	0001883a 	nop
     /* 
      * If there is any data left then either return now or block until 
      * some has been sent 
      */
     /* consider: test whether there is anything there while doing this and delay for at most 2s. */
     if (count > 0)
-    44a0:	e0bffe17 	ldw	r2,-8(fp)
-    44a4:	0080100e 	bge	zero,r2,44e8 <altera_avalon_jtag_uart_write+0x1c4>
+    44ec:	e0bff617 	ldw	r2,-40(fp)
+    44f0:	0080100e 	bge	zero,r2,4534 <altera_avalon_jtag_uart_write+0x1c8>
     {
       if (flags & O_NONBLOCK)
-    44a8:	e0bfff17 	ldw	r2,-4(fp)
-    44ac:	1090000c 	andi	r2,r2,16384
-    44b0:	1000101e 	bne	r2,zero,44f4 <altera_avalon_jtag_uart_write+0x1d0>
+    44f4:	e0bff517 	ldw	r2,-44(fp)
+    44f8:	1090000c 	andi	r2,r2,16384
+    44fc:	1000101e 	bne	r2,zero,4540 <altera_avalon_jtag_uart_write+0x1d4>
       /*
        * No OS present: Always wait for data to be removed from buffer.  Once
        * the interrupt routine has removed some data then we will be able to
        * insert some more.
        */
       while (out == sp->tx_out && sp->host_inactive < sp->timeout)
-    44b4:	0001883a 	nop
-    44b8:	e0bffc17 	ldw	r2,-16(fp)
-    44bc:	10c00d17 	ldw	r3,52(r2)
-    44c0:	e0bff517 	ldw	r2,-44(fp)
-    44c4:	1880051e 	bne	r3,r2,44dc <altera_avalon_jtag_uart_write+0x1b8>
-    44c8:	e0bffc17 	ldw	r2,-16(fp)
-    44cc:	10c00917 	ldw	r3,36(r2)
-    44d0:	e0bffc17 	ldw	r2,-16(fp)
-    44d4:	10800117 	ldw	r2,4(r2)
-    44d8:	18bff736 	bltu	r3,r2,44b8 <__alt_data_end+0xfffe44b8>
+    4500:	0001883a 	nop
+    4504:	e0bff817 	ldw	r2,-32(fp)
+    4508:	10800d17 	ldw	r2,52(r2)
+    450c:	e0ffff17 	ldw	r3,-4(fp)
+    4510:	1880051e 	bne	r3,r2,4528 <altera_avalon_jtag_uart_write+0x1bc>
+    4514:	e0bff817 	ldw	r2,-32(fp)
+    4518:	10c00917 	ldw	r3,36(r2)
+    451c:	e0bff817 	ldw	r2,-32(fp)
+    4520:	10800117 	ldw	r2,4(r2)
+    4524:	18bff736 	bltu	r3,r2,4504 <altera_avalon_jtag_uart_write+0x198>
         ;
 #endif /* __ucosii__ */
 
       if  (sp->host_inactive)
-    44dc:	e0bffc17 	ldw	r2,-16(fp)
-    44e0:	10800917 	ldw	r2,36(r2)
-    44e4:	1000051e 	bne	r2,zero,44fc <altera_avalon_jtag_uart_write+0x1d8>
+    4528:	e0bff817 	ldw	r2,-32(fp)
+    452c:	10800917 	ldw	r2,36(r2)
+    4530:	1000051e 	bne	r2,zero,4548 <altera_avalon_jtag_uart_write+0x1dc>
          break;
     }
   }
   while (count > 0);
-    44e8:	e0bffe17 	ldw	r2,-8(fp)
-    44ec:	00bfd016 	blt	zero,r2,4430 <__alt_data_end+0xfffe4430>
-    44f0:	00000306 	br	4500 <altera_avalon_jtag_uart_write+0x1dc>
-     */
-    /* consider: test whether there is anything there while doing this and delay for at most 2s. */
-    if (count > 0)
-    {
-      if (flags & O_NONBLOCK)
+    4534:	e0bff617 	ldw	r2,-40(fp)
+    4538:	00bfcf16 	blt	zero,r2,4478 <altera_avalon_jtag_uart_write+0x10c>
+    453c:	00000306 	br	454c <altera_avalon_jtag_uart_write+0x1e0>
         break;
-    44f4:	0001883a 	nop
-    44f8:	00000106 	br	4500 <altera_avalon_jtag_uart_write+0x1dc>
-      while (out == sp->tx_out && sp->host_inactive < sp->timeout)
-        ;
-#endif /* __ucosii__ */
-
-      if  (sp->host_inactive)
+    4540:	0001883a 	nop
+    4544:	00000106 	br	454c <altera_avalon_jtag_uart_write+0x1e0>
          break;
-    44fc:	0001883a 	nop
+    4548:	0001883a 	nop
    * Now that access to the circular buffer is complete, release the write
    * semaphore so that other threads can access the buffer.
    */
   ALT_SEM_POST (sp->write_lock);
 
   if (ptr != start)
-    4500:	e0fffd17 	ldw	r3,-12(fp)
-    4504:	e0bff717 	ldw	r2,-36(fp)
-    4508:	18800426 	beq	r3,r2,451c <altera_avalon_jtag_uart_write+0x1f8>
+    454c:	e0fff717 	ldw	r3,-36(fp)
+    4550:	e0bffd17 	ldw	r2,-12(fp)
+    4554:	18800426 	beq	r3,r2,4568 <altera_avalon_jtag_uart_write+0x1fc>
     return ptr - start;
-    450c:	e0fffd17 	ldw	r3,-12(fp)
-    4510:	e0bff717 	ldw	r2,-36(fp)
-    4514:	1885c83a 	sub	r2,r3,r2
-    4518:	00000606 	br	4534 <altera_avalon_jtag_uart_write+0x210>
+    4558:	e0fff717 	ldw	r3,-36(fp)
+    455c:	e0bffd17 	ldw	r2,-12(fp)
+    4560:	1885c83a 	sub	r2,r3,r2
+    4564:	00000606 	br	4580 <altera_avalon_jtag_uart_write+0x214>
   else if (flags & O_NONBLOCK)
-    451c:	e0bfff17 	ldw	r2,-4(fp)
-    4520:	1090000c 	andi	r2,r2,16384
-    4524:	10000226 	beq	r2,zero,4530 <altera_avalon_jtag_uart_write+0x20c>
+    4568:	e0bff517 	ldw	r2,-44(fp)
+    456c:	1090000c 	andi	r2,r2,16384
+    4570:	10000226 	beq	r2,zero,457c <altera_avalon_jtag_uart_write+0x210>
     return -EWOULDBLOCK;
-    4528:	00bffd44 	movi	r2,-11
-    452c:	00000106 	br	4534 <altera_avalon_jtag_uart_write+0x210>
+    4574:	00bffd44 	movi	r2,-11
+    4578:	00000106 	br	4580 <altera_avalon_jtag_uart_write+0x214>
     sp->tx_out = sp->tx_in = 0;
     return ptr - start + count;
   }
 #endif
   else
     return -EIO; /* Host not connected */
-    4530:	00bffec4 	movi	r2,-5
+    457c:	00bffec4 	movi	r2,-5
 }
-    4534:	e037883a 	mov	sp,fp
-    4538:	dfc00117 	ldw	ra,4(sp)
-    453c:	df000017 	ldw	fp,0(sp)
-    4540:	dec00204 	addi	sp,sp,8
-    4544:	f800283a 	ret
+    4580:	e037883a 	mov	sp,fp
+    4584:	dfc00117 	ldw	ra,4(sp)
+    4588:	df000017 	ldw	fp,0(sp)
+    458c:	dec00204 	addi	sp,sp,8
+    4590:	f800283a 	ret
 
-00004548 <alt_avalon_timer_sc_irq>:
+00004594 <alt_avalon_timer_sc_irq>:
 #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
 static void alt_avalon_timer_sc_irq (void* base)
 #else
 static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
 #endif
 {
-    4548:	defffa04 	addi	sp,sp,-24
-    454c:	dfc00515 	stw	ra,20(sp)
-    4550:	df000415 	stw	fp,16(sp)
-    4554:	df000404 	addi	fp,sp,16
-    4558:	e13fff15 	stw	r4,-4(fp)
+    4594:	defffa04 	addi	sp,sp,-24
+    4598:	dfc00515 	stw	ra,20(sp)
+    459c:	df000415 	stw	fp,16(sp)
+    45a0:	df000404 	addi	fp,sp,16
+    45a4:	e13ffc15 	stw	r4,-16(fp)
   alt_irq_context cpu_sr;
   
   /* clear the interrupt */
   IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
-    455c:	0007883a 	mov	r3,zero
-    4560:	e0bfff17 	ldw	r2,-4(fp)
-    4564:	10c00035 	stwio	r3,0(r2)
+    45a8:	0007883a 	mov	r3,zero
+    45ac:	e0bffc17 	ldw	r2,-16(fp)
+    45b0:	10c00035 	stwio	r3,0(r2)
   /* 
    * Dummy read to ensure IRQ is negated before the ISR returns.
    * The control register is read because reading the status
    * register has side-effects per the register map documentation.
    */
   IORD_ALTERA_AVALON_TIMER_CONTROL (base);
-    4568:	e0bfff17 	ldw	r2,-4(fp)
-    456c:	10800104 	addi	r2,r2,4
-    4570:	10800037 	ldwio	r2,0(r2)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    45b4:	e0bffc17 	ldw	r2,-16(fp)
+    45b8:	10800104 	addi	r2,r2,4
+    45bc:	10800037 	ldwio	r2,0(r2)
   NIOS2_READ_STATUS (context);
-    4574:	0005303a 	rdctl	r2,status
-    4578:	e0bffd15 	stw	r2,-12(fp)
-
+    45c0:	0005303a 	rdctl	r2,status
+    45c4:	e0bffd15 	stw	r2,-12(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    457c:	e0fffd17 	ldw	r3,-12(fp)
-    4580:	00bfff84 	movi	r2,-2
-    4584:	1884703a 	and	r2,r3,r2
-    4588:	1001703a 	wrctl	status,r2
-  
+    45c8:	e0fffd17 	ldw	r3,-12(fp)
+    45cc:	00bfff84 	movi	r2,-2
+    45d0:	1884703a 	and	r2,r3,r2
+    45d4:	1001703a 	wrctl	status,r2
   return context;
-    458c:	e0bffd17 	ldw	r2,-12(fp)
+    45d8:	e0bffd17 	ldw	r2,-12(fp)
 
   /* 
    * Notify the system of a clock tick. disable interrupts 
    * during this time to safely support ISR preemption
    */
   cpu_sr = alt_irq_disable_all();
-    4590:	e0bffc15 	stw	r2,-16(fp)
+    45dc:	e0bfff15 	stw	r2,-4(fp)
   alt_tick ();
-    4594:	00050280 	call	5028 <alt_tick>
-    4598:	e0bffc17 	ldw	r2,-16(fp)
-    459c:	e0bffe15 	stw	r2,-8(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    45e0:	00050780 	call	5078 <alt_tick>
+    45e4:	e0bfff17 	ldw	r2,-4(fp)
+    45e8:	e0bffe15 	stw	r2,-8(fp)
   NIOS2_WRITE_STATUS (context);
-    45a0:	e0bffe17 	ldw	r2,-8(fp)
-    45a4:	1001703a 	wrctl	status,r2
+    45ec:	e0bffe17 	ldw	r2,-8(fp)
+    45f0:	1001703a 	wrctl	status,r2
+}
+    45f4:	0001883a 	nop
   alt_irq_enable_all(cpu_sr);
 }
-    45a8:	0001883a 	nop
-    45ac:	e037883a 	mov	sp,fp
-    45b0:	dfc00117 	ldw	ra,4(sp)
-    45b4:	df000017 	ldw	fp,0(sp)
-    45b8:	dec00204 	addi	sp,sp,8
-    45bc:	f800283a 	ret
+    45f8:	0001883a 	nop
+    45fc:	e037883a 	mov	sp,fp
+    4600:	dfc00117 	ldw	ra,4(sp)
+    4604:	df000017 	ldw	fp,0(sp)
+    4608:	dec00204 	addi	sp,sp,8
+    460c:	f800283a 	ret
 
-000045c0 <alt_avalon_timer_sc_init>:
+00004610 <alt_avalon_timer_sc_init>:
  * auto-generated alt_sys_init() function.
  */
 
 void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, 
                                 alt_u32 irq, alt_u32 freq)
 {
-    45c0:	defff804 	addi	sp,sp,-32
-    45c4:	dfc00715 	stw	ra,28(sp)
-    45c8:	df000615 	stw	fp,24(sp)
-    45cc:	df000604 	addi	fp,sp,24
-    45d0:	e13ffc15 	stw	r4,-16(fp)
-    45d4:	e17ffd15 	stw	r5,-12(fp)
-    45d8:	e1bffe15 	stw	r6,-8(fp)
-    45dc:	e1ffff15 	stw	r7,-4(fp)
-    45e0:	e0bfff17 	ldw	r2,-4(fp)
-    45e4:	e0bffb15 	stw	r2,-20(fp)
+    4610:	defff804 	addi	sp,sp,-32
+    4614:	dfc00715 	stw	ra,28(sp)
+    4618:	df000615 	stw	fp,24(sp)
+    461c:	df000604 	addi	fp,sp,24
+    4620:	e13ffe15 	stw	r4,-8(fp)
+    4624:	e17ffd15 	stw	r5,-12(fp)
+    4628:	e1bffc15 	stw	r6,-16(fp)
+    462c:	e1fffb15 	stw	r7,-20(fp)
+    4630:	e0bffb17 	ldw	r2,-20(fp)
+    4634:	e0bfff15 	stw	r2,-4(fp)
  * in order to initialise the value of the clock frequency.
  */
 
 static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks)
 {
   if (! _alt_tick_rate)
-    45e8:	d0a01617 	ldw	r2,-32680(gp)
-    45ec:	1000021e 	bne	r2,zero,45f8 <alt_avalon_timer_sc_init+0x38>
+    4638:	d0a01617 	ldw	r2,-32680(gp)
+    463c:	1000031e 	bne	r2,zero,464c <alt_avalon_timer_sc_init+0x3c>
   {
     _alt_tick_rate = nticks;
-    45f0:	e0bffb17 	ldw	r2,-20(fp)
-    45f4:	d0a01615 	stw	r2,-32680(gp)
+    4640:	e0bfff17 	ldw	r2,-4(fp)
+    4644:	d0a01615 	stw	r2,-32680(gp)
+    return 0;
+    4648:	00000106 	br	4650 <alt_avalon_timer_sc_init+0x40>
+  }
+  else
+  {
+    return -1;
+    464c:	0001883a 	nop
   
   alt_sysclk_init (freq);
   
   /* set to free running mode */
   
   IOWR_ALTERA_AVALON_TIMER_CONTROL (base, 
-    45f8:	e0bffc17 	ldw	r2,-16(fp)
-    45fc:	10800104 	addi	r2,r2,4
-    4600:	00c001c4 	movi	r3,7
-    4604:	10c00035 	stwio	r3,0(r2)
+    4650:	e0bffe17 	ldw	r2,-8(fp)
+    4654:	10800104 	addi	r2,r2,4
+    4658:	00c001c4 	movi	r3,7
+    465c:	10c00035 	stwio	r3,0(r2)
             ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
             ALTERA_AVALON_TIMER_CONTROL_START_MSK);
 
   /* register the interrupt handler, and enable the interrupt */
 #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
   alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, 
-    4608:	d8000015 	stw	zero,0(sp)
-    460c:	e1fffc17 	ldw	r7,-16(fp)
-    4610:	01800034 	movhi	r6,0
-    4614:	31915204 	addi	r6,r6,17736
-    4618:	e17ffe17 	ldw	r5,-8(fp)
-    461c:	e13ffd17 	ldw	r4,-12(fp)
-    4620:	00049080 	call	4908 <alt_ic_isr_register>
+    4660:	d8000015 	stw	zero,0(sp)
+    4664:	e1fffe17 	ldw	r7,-8(fp)
+    4668:	01800034 	movhi	r6,0
+    466c:	31916504 	addi	r6,r6,17812
+    4670:	e17ffc17 	ldw	r5,-16(fp)
+    4674:	e13ffd17 	ldw	r4,-12(fp)
+    4678:	00049740 	call	4974 <alt_ic_isr_register>
                       base, NULL);
 #else
   alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
 #endif  
 }
-    4624:	0001883a 	nop
-    4628:	e037883a 	mov	sp,fp
-    462c:	dfc00117 	ldw	ra,4(sp)
-    4630:	df000017 	ldw	fp,0(sp)
-    4634:	dec00204 	addi	sp,sp,8
-    4638:	f800283a 	ret
+    467c:	0001883a 	nop
+    4680:	e037883a 	mov	sp,fp
+    4684:	dfc00117 	ldw	ra,4(sp)
+    4688:	df000017 	ldw	fp,0(sp)
+    468c:	dec00204 	addi	sp,sp,8
+    4690:	f800283a 	ret
 
-0000463c <alt_alarm_start>:
+00004694 <alt_alarm_start>:
  */ 
 
 int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks,
                      alt_u32 (*callback) (void* context),
                      void* context)
 {
-    463c:	defff504 	addi	sp,sp,-44
-    4640:	df000a15 	stw	fp,40(sp)
-    4644:	df000a04 	addi	fp,sp,40
-    4648:	e13ffc15 	stw	r4,-16(fp)
-    464c:	e17ffd15 	stw	r5,-12(fp)
-    4650:	e1bffe15 	stw	r6,-8(fp)
-    4654:	e1ffff15 	stw	r7,-4(fp)
+    4694:	defff504 	addi	sp,sp,-44
+    4698:	df000a15 	stw	fp,40(sp)
+    469c:	df000a04 	addi	fp,sp,40
+    46a0:	e13ff915 	stw	r4,-28(fp)
+    46a4:	e17ff815 	stw	r5,-32(fp)
+    46a8:	e1bff715 	stw	r6,-36(fp)
+    46ac:	e1fff615 	stw	r7,-40(fp)
   alt_irq_context irq_context;
   alt_u32 current_nticks = 0;
-    4658:	e03ff615 	stw	zero,-40(fp)
- * Obtain the system clock rate in ticks/s. 
- */
-
-static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void)
-{
+    46b0:	e03fff15 	stw	zero,-4(fp)
   return _alt_tick_rate;
-    465c:	d0a01617 	ldw	r2,-32680(gp)
+    46b4:	d0a01617 	ldw	r2,-32680(gp)
   
   if (alt_ticks_per_second ())
-    4660:	10003c26 	beq	r2,zero,4754 <alt_alarm_start+0x118>
+    46b8:	10003e26 	beq	r2,zero,47b4 <alt_alarm_start+0x120>
   {
     if (alarm)
-    4664:	e0bffc17 	ldw	r2,-16(fp)
-    4668:	10003826 	beq	r2,zero,474c <alt_alarm_start+0x110>
+    46bc:	e0bff917 	ldw	r2,-28(fp)
+    46c0:	10003a26 	beq	r2,zero,47ac <alt_alarm_start+0x118>
     {
       alarm->callback = callback;
-    466c:	e0bffc17 	ldw	r2,-16(fp)
-    4670:	e0fffe17 	ldw	r3,-8(fp)
-    4674:	10c00315 	stw	r3,12(r2)
+    46c4:	e0bff917 	ldw	r2,-28(fp)
+    46c8:	e0fff717 	ldw	r3,-36(fp)
+    46cc:	10c00315 	stw	r3,12(r2)
       alarm->context  = context;
-    4678:	e0bffc17 	ldw	r2,-16(fp)
-    467c:	e0ffff17 	ldw	r3,-4(fp)
-    4680:	10c00515 	stw	r3,20(r2)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    46d0:	e0bff917 	ldw	r2,-28(fp)
+    46d4:	e0fff617 	ldw	r3,-40(fp)
+    46d8:	10c00515 	stw	r3,20(r2)
   NIOS2_READ_STATUS (context);
-    4684:	0005303a 	rdctl	r2,status
-    4688:	e0bff915 	stw	r2,-28(fp)
-
+    46dc:	0005303a 	rdctl	r2,status
+    46e0:	e0bffd15 	stw	r2,-12(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    468c:	e0fff917 	ldw	r3,-28(fp)
-    4690:	00bfff84 	movi	r2,-2
-    4694:	1884703a 	and	r2,r3,r2
-    4698:	1001703a 	wrctl	status,r2
-  
+    46e4:	e0fffd17 	ldw	r3,-12(fp)
+    46e8:	00bfff84 	movi	r2,-2
+    46ec:	1884703a 	and	r2,r3,r2
+    46f0:	1001703a 	wrctl	status,r2
   return context;
-    469c:	e0bff917 	ldw	r2,-28(fp)
+    46f4:	e0bffd17 	ldw	r2,-12(fp)
  
       irq_context = alt_irq_disable_all ();
-    46a0:	e0bff815 	stw	r2,-32(fp)
+    46f8:	e0bffe15 	stw	r2,-8(fp)
  * alt_nticks() returns the elapsed number of system clock ticks since reset.
  */
 
 static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void)
 {
   return _alt_nticks;
-    46a4:	d0a01717 	ldw	r2,-32676(gp)
+    46fc:	d0a01717 	ldw	r2,-32676(gp)
       
       current_nticks = alt_nticks();
-    46a8:	e0bff615 	stw	r2,-40(fp)
+    4700:	e0bfff15 	stw	r2,-4(fp)
       
       alarm->time = nticks + current_nticks + 1; 
-    46ac:	e0fffd17 	ldw	r3,-12(fp)
-    46b0:	e0bff617 	ldw	r2,-40(fp)
-    46b4:	1885883a 	add	r2,r3,r2
-    46b8:	10c00044 	addi	r3,r2,1
-    46bc:	e0bffc17 	ldw	r2,-16(fp)
-    46c0:	10c00215 	stw	r3,8(r2)
+    4704:	e0fff817 	ldw	r3,-32(fp)
+    4708:	e0bfff17 	ldw	r2,-4(fp)
+    470c:	1885883a 	add	r2,r3,r2
+    4710:	10c00044 	addi	r3,r2,1
+    4714:	e0bff917 	ldw	r2,-28(fp)
+    4718:	10c00215 	stw	r3,8(r2)
       /* 
        * If the desired alarm time causes a roll-over, set the rollover
        * flag. This will prevent the subsequent tick event from causing
        * an alarm too early.
        */
       if(alarm->time < current_nticks)
-    46c4:	e0bffc17 	ldw	r2,-16(fp)
-    46c8:	10c00217 	ldw	r3,8(r2)
-    46cc:	e0bff617 	ldw	r2,-40(fp)
-    46d0:	1880042e 	bgeu	r3,r2,46e4 <alt_alarm_start+0xa8>
+    471c:	e0bff917 	ldw	r2,-28(fp)
+    4720:	10c00217 	ldw	r3,8(r2)
+    4724:	e0bfff17 	ldw	r2,-4(fp)
+    4728:	1880042e 	bgeu	r3,r2,473c <alt_alarm_start+0xa8>
       {
         alarm->rollover = 1;
-    46d4:	e0bffc17 	ldw	r2,-16(fp)
-    46d8:	00c00044 	movi	r3,1
-    46dc:	10c00405 	stb	r3,16(r2)
-    46e0:	00000206 	br	46ec <alt_alarm_start+0xb0>
+    472c:	e0bff917 	ldw	r2,-28(fp)
+    4730:	00c00044 	movi	r3,1
+    4734:	10c00405 	stb	r3,16(r2)
+    4738:	00000206 	br	4744 <alt_alarm_start+0xb0>
       }
       else
       {
         alarm->rollover = 0;
-    46e4:	e0bffc17 	ldw	r2,-16(fp)
-    46e8:	10000405 	stb	zero,16(r2)
+    473c:	e0bff917 	ldw	r2,-28(fp)
+    4740:	10000405 	stb	zero,16(r2)
       }
     
       alt_llist_insert (&alt_alarm_list, &alarm->llist);
-    46ec:	e0bffc17 	ldw	r2,-16(fp)
-    46f0:	d0e00c04 	addi	r3,gp,-32720
-    46f4:	e0fffa15 	stw	r3,-24(fp)
-    46f8:	e0bffb15 	stw	r2,-20(fp)
+    4744:	e0bff917 	ldw	r2,-28(fp)
+    4748:	d0e00c04 	addi	r3,gp,-32720
+    474c:	e0fffb15 	stw	r3,-20(fp)
+    4750:	e0bffa15 	stw	r2,-24(fp)
  */
 
 static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, 
                 alt_llist* entry)
 {
   entry->previous = list;
-    46fc:	e0bffb17 	ldw	r2,-20(fp)
-    4700:	e0fffa17 	ldw	r3,-24(fp)
-    4704:	10c00115 	stw	r3,4(r2)
+    4754:	e0bffa17 	ldw	r2,-24(fp)
+    4758:	e0fffb17 	ldw	r3,-20(fp)
+    475c:	10c00115 	stw	r3,4(r2)
   entry->next     = list->next;
-    4708:	e0bffa17 	ldw	r2,-24(fp)
-    470c:	10c00017 	ldw	r3,0(r2)
-    4710:	e0bffb17 	ldw	r2,-20(fp)
-    4714:	10c00015 	stw	r3,0(r2)
+    4760:	e0bffb17 	ldw	r2,-20(fp)
+    4764:	10c00017 	ldw	r3,0(r2)
+    4768:	e0bffa17 	ldw	r2,-24(fp)
+    476c:	10c00015 	stw	r3,0(r2)
 
   list->next->previous = entry;
-    4718:	e0bffa17 	ldw	r2,-24(fp)
-    471c:	10800017 	ldw	r2,0(r2)
-    4720:	e0fffb17 	ldw	r3,-20(fp)
-    4724:	10c00115 	stw	r3,4(r2)
+    4770:	e0bffb17 	ldw	r2,-20(fp)
+    4774:	10800017 	ldw	r2,0(r2)
+    4778:	e0fffa17 	ldw	r3,-24(fp)
+    477c:	10c00115 	stw	r3,4(r2)
   list->next           = entry;
-    4728:	e0bffa17 	ldw	r2,-24(fp)
-    472c:	e0fffb17 	ldw	r3,-20(fp)
-    4730:	10c00015 	stw	r3,0(r2)
-    4734:	e0bff817 	ldw	r2,-32(fp)
-    4738:	e0bff715 	stw	r2,-36(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    4780:	e0bffb17 	ldw	r2,-20(fp)
+    4784:	e0fffa17 	ldw	r3,-24(fp)
+    4788:	10c00015 	stw	r3,0(r2)
+}
+    478c:	0001883a 	nop
+    4790:	e0bffe17 	ldw	r2,-8(fp)
+    4794:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context);
-    473c:	e0bff717 	ldw	r2,-36(fp)
-    4740:	1001703a 	wrctl	status,r2
+    4798:	e0bffc17 	ldw	r2,-16(fp)
+    479c:	1001703a 	wrctl	status,r2
+}
+    47a0:	0001883a 	nop
       alt_irq_enable_all (irq_context);
 
       return 0;
-    4744:	0005883a 	mov	r2,zero
-    4748:	00000306 	br	4758 <alt_alarm_start+0x11c>
+    47a4:	0005883a 	mov	r2,zero
+    47a8:	00000306 	br	47b8 <alt_alarm_start+0x124>
     }
     else
     {
       return -EINVAL;
-    474c:	00bffa84 	movi	r2,-22
-    4750:	00000106 	br	4758 <alt_alarm_start+0x11c>
+    47ac:	00bffa84 	movi	r2,-22
+    47b0:	00000106 	br	47b8 <alt_alarm_start+0x124>
     }
   }
   else
   {
     return -ENOTSUP;
-    4754:	00bfde84 	movi	r2,-134
+    47b4:	00bfde84 	movi	r2,-134
   }
 }
-    4758:	e037883a 	mov	sp,fp
-    475c:	df000017 	ldw	fp,0(sp)
-    4760:	dec00104 	addi	sp,sp,4
-    4764:	f800283a 	ret
+    47b8:	e037883a 	mov	sp,fp
+    47bc:	df000017 	ldw	fp,0(sp)
+    47c0:	dec00104 	addi	sp,sp,4
+    47c4:	f800283a 	ret
 
-00004768 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
+000047c8 <alt_get_errno>:
 {
-    4768:	defffe04 	addi	sp,sp,-8
-    476c:	dfc00115 	stw	ra,4(sp)
-    4770:	df000015 	stw	fp,0(sp)
-    4774:	d839883a 	mov	fp,sp
+    47c8:	defffe04 	addi	sp,sp,-8
+    47cc:	dfc00115 	stw	ra,4(sp)
+    47d0:	df000015 	stw	fp,0(sp)
+    47d4:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    4778:	d0a00917 	ldw	r2,-32732(gp)
-    477c:	10000326 	beq	r2,zero,478c <alt_get_errno+0x24>
-    4780:	d0a00917 	ldw	r2,-32732(gp)
-    4784:	103ee83a 	callr	r2
-    4788:	00000106 	br	4790 <alt_get_errno+0x28>
-    478c:	d0a01104 	addi	r2,gp,-32700
+    47d8:	d0a00917 	ldw	r2,-32732(gp)
+    47dc:	10000326 	beq	r2,zero,47ec <alt_get_errno+0x24>
+    47e0:	d0a00917 	ldw	r2,-32732(gp)
+    47e4:	103ee83a 	callr	r2
+    47e8:	00000106 	br	47f0 <alt_get_errno+0x28>
+    47ec:	d0a01104 	addi	r2,gp,-32700
 }
-    4790:	e037883a 	mov	sp,fp
-    4794:	dfc00117 	ldw	ra,4(sp)
-    4798:	df000017 	ldw	fp,0(sp)
-    479c:	dec00204 	addi	sp,sp,8
-    47a0:	f800283a 	ret
+    47f0:	e037883a 	mov	sp,fp
+    47f4:	dfc00117 	ldw	ra,4(sp)
+    47f8:	df000017 	ldw	fp,0(sp)
+    47fc:	dec00204 	addi	sp,sp,8
+    4800:	f800283a 	ret
 
-000047a4 <alt_dev_llist_insert>:
+00004804 <alt_dev_llist_insert>:
 /*
  *
  */
 
 int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list)
 {
-    47a4:	defffa04 	addi	sp,sp,-24
-    47a8:	dfc00515 	stw	ra,20(sp)
-    47ac:	df000415 	stw	fp,16(sp)
-    47b0:	df000404 	addi	fp,sp,16
-    47b4:	e13ffe15 	stw	r4,-8(fp)
-    47b8:	e17fff15 	stw	r5,-4(fp)
+    4804:	defffa04 	addi	sp,sp,-24
+    4808:	dfc00515 	stw	ra,20(sp)
+    480c:	df000415 	stw	fp,16(sp)
+    4810:	df000404 	addi	fp,sp,16
+    4814:	e13ffd15 	stw	r4,-12(fp)
+    4818:	e17ffc15 	stw	r5,-16(fp)
   /*
    * check that the device exists, and that it has a valid name.
    */
 
   if (!dev || !dev->name)
-    47bc:	e0bffe17 	ldw	r2,-8(fp)
-    47c0:	10000326 	beq	r2,zero,47d0 <alt_dev_llist_insert+0x2c>
-    47c4:	e0bffe17 	ldw	r2,-8(fp)
-    47c8:	10800217 	ldw	r2,8(r2)
-    47cc:	1000061e 	bne	r2,zero,47e8 <alt_dev_llist_insert+0x44>
+    481c:	e0bffd17 	ldw	r2,-12(fp)
+    4820:	10000326 	beq	r2,zero,4830 <alt_dev_llist_insert+0x2c>
+    4824:	e0bffd17 	ldw	r2,-12(fp)
+    4828:	10800217 	ldw	r2,8(r2)
+    482c:	1000061e 	bne	r2,zero,4848 <alt_dev_llist_insert+0x44>
   {
     ALT_ERRNO = EINVAL;
-    47d0:	00047680 	call	4768 <alt_get_errno>
-    47d4:	1007883a 	mov	r3,r2
-    47d8:	00800584 	movi	r2,22
-    47dc:	18800015 	stw	r2,0(r3)
+    4830:	00047c80 	call	47c8 <alt_get_errno>
+    4834:	1007883a 	mov	r3,r2
+    4838:	00800584 	movi	r2,22
+    483c:	18800015 	stw	r2,0(r3)
     return -EINVAL;
-    47e0:	00bffa84 	movi	r2,-22
-    47e4:	00001306 	br	4834 <alt_dev_llist_insert+0x90>
+    4840:	00bffa84 	movi	r2,-22
+    4844:	00001406 	br	4898 <alt_dev_llist_insert+0x94>
   
   /*
    * register the device.
    */
   
   alt_llist_insert(list, &dev->llist);
-    47e8:	e0bffe17 	ldw	r2,-8(fp)
-    47ec:	e0ffff17 	ldw	r3,-4(fp)
-    47f0:	e0fffc15 	stw	r3,-16(fp)
-    47f4:	e0bffd15 	stw	r2,-12(fp)
- */
-
-static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, 
-                alt_llist* entry)
-{
+    4848:	e0bffd17 	ldw	r2,-12(fp)
+    484c:	e0fffc17 	ldw	r3,-16(fp)
+    4850:	e0ffff15 	stw	r3,-4(fp)
+    4854:	e0bffe15 	stw	r2,-8(fp)
   entry->previous = list;
-    47f8:	e0bffd17 	ldw	r2,-12(fp)
-    47fc:	e0fffc17 	ldw	r3,-16(fp)
-    4800:	10c00115 	stw	r3,4(r2)
+    4858:	e0bffe17 	ldw	r2,-8(fp)
+    485c:	e0ffff17 	ldw	r3,-4(fp)
+    4860:	10c00115 	stw	r3,4(r2)
   entry->next     = list->next;
-    4804:	e0bffc17 	ldw	r2,-16(fp)
-    4808:	10c00017 	ldw	r3,0(r2)
-    480c:	e0bffd17 	ldw	r2,-12(fp)
-    4810:	10c00015 	stw	r3,0(r2)
-
+    4864:	e0bfff17 	ldw	r2,-4(fp)
+    4868:	10c00017 	ldw	r3,0(r2)
+    486c:	e0bffe17 	ldw	r2,-8(fp)
+    4870:	10c00015 	stw	r3,0(r2)
   list->next->previous = entry;
-    4814:	e0bffc17 	ldw	r2,-16(fp)
-    4818:	10800017 	ldw	r2,0(r2)
-    481c:	e0fffd17 	ldw	r3,-12(fp)
-    4820:	10c00115 	stw	r3,4(r2)
+    4874:	e0bfff17 	ldw	r2,-4(fp)
+    4878:	10800017 	ldw	r2,0(r2)
+    487c:	e0fffe17 	ldw	r3,-8(fp)
+    4880:	10c00115 	stw	r3,4(r2)
   list->next           = entry;
-    4824:	e0bffc17 	ldw	r2,-16(fp)
-    4828:	e0fffd17 	ldw	r3,-12(fp)
-    482c:	10c00015 	stw	r3,0(r2)
+    4884:	e0bfff17 	ldw	r2,-4(fp)
+    4888:	e0fffe17 	ldw	r3,-8(fp)
+    488c:	10c00015 	stw	r3,0(r2)
+}
+    4890:	0001883a 	nop
 
   return 0;  
-    4830:	0005883a 	mov	r2,zero
+    4894:	0005883a 	mov	r2,zero
 }
-    4834:	e037883a 	mov	sp,fp
-    4838:	dfc00117 	ldw	ra,4(sp)
-    483c:	df000017 	ldw	fp,0(sp)
-    4840:	dec00204 	addi	sp,sp,8
-    4844:	f800283a 	ret
+    4898:	e037883a 	mov	sp,fp
+    489c:	dfc00117 	ldw	ra,4(sp)
+    48a0:	df000017 	ldw	fp,0(sp)
+    48a4:	dec00204 	addi	sp,sp,8
+    48a8:	f800283a 	ret
 
-00004848 <_do_ctors>:
+000048ac <_do_ctors>:
 /*
  * Run the C++ static constructors.
  */
 
 void _do_ctors(void)
 {
-    4848:	defffd04 	addi	sp,sp,-12
-    484c:	dfc00215 	stw	ra,8(sp)
-    4850:	df000115 	stw	fp,4(sp)
-    4854:	df000104 	addi	fp,sp,4
+    48ac:	defffd04 	addi	sp,sp,-12
+    48b0:	dfc00215 	stw	ra,8(sp)
+    48b4:	df000115 	stw	fp,4(sp)
+    48b8:	df000104 	addi	fp,sp,4
   constructor* ctor;
 
   for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
-    4858:	00800034 	movhi	r2,0
-    485c:	1095f704 	addi	r2,r2,22492
-    4860:	e0bfff15 	stw	r2,-4(fp)
-    4864:	00000606 	br	4880 <_do_ctors+0x38>
+    48bc:	00800034 	movhi	r2,0
+    48c0:	1095cc04 	addi	r2,r2,22320
+    48c4:	e0bfff15 	stw	r2,-4(fp)
+    48c8:	00000606 	br	48e4 <_do_ctors+0x38>
         (*ctor) (); 
-    4868:	e0bfff17 	ldw	r2,-4(fp)
-    486c:	10800017 	ldw	r2,0(r2)
-    4870:	103ee83a 	callr	r2
-
-void _do_ctors(void)
-{
-  constructor* ctor;
-
+    48cc:	e0bfff17 	ldw	r2,-4(fp)
+    48d0:	10800017 	ldw	r2,0(r2)
+    48d4:	103ee83a 	callr	r2
   for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
-    4874:	e0bfff17 	ldw	r2,-4(fp)
-    4878:	10bfff04 	addi	r2,r2,-4
-    487c:	e0bfff15 	stw	r2,-4(fp)
-    4880:	e0ffff17 	ldw	r3,-4(fp)
-    4884:	00800034 	movhi	r2,0
-    4888:	1095f804 	addi	r2,r2,22496
-    488c:	18bff62e 	bgeu	r3,r2,4868 <__alt_data_end+0xfffe4868>
-        (*ctor) (); 
+    48d8:	e0bfff17 	ldw	r2,-4(fp)
+    48dc:	10bfff04 	addi	r2,r2,-4
+    48e0:	e0bfff15 	stw	r2,-4(fp)
+    48e4:	e0ffff17 	ldw	r3,-4(fp)
+    48e8:	00800034 	movhi	r2,0
+    48ec:	1095cd04 	addi	r2,r2,22324
+    48f0:	18bff62e 	bgeu	r3,r2,48cc <_do_ctors+0x20>
 }
-    4890:	0001883a 	nop
-    4894:	e037883a 	mov	sp,fp
-    4898:	dfc00117 	ldw	ra,4(sp)
-    489c:	df000017 	ldw	fp,0(sp)
-    48a0:	dec00204 	addi	sp,sp,8
-    48a4:	f800283a 	ret
+    48f4:	0001883a 	nop
+    48f8:	0001883a 	nop
+    48fc:	e037883a 	mov	sp,fp
+    4900:	dfc00117 	ldw	ra,4(sp)
+    4904:	df000017 	ldw	fp,0(sp)
+    4908:	dec00204 	addi	sp,sp,8
+    490c:	f800283a 	ret
 
-000048a8 <_do_dtors>:
+00004910 <_do_dtors>:
 /*
  * Run the C++ static destructors.
  */
 
 void _do_dtors(void)
 {
-    48a8:	defffd04 	addi	sp,sp,-12
-    48ac:	dfc00215 	stw	ra,8(sp)
-    48b0:	df000115 	stw	fp,4(sp)
-    48b4:	df000104 	addi	fp,sp,4
+    4910:	defffd04 	addi	sp,sp,-12
+    4914:	dfc00215 	stw	ra,8(sp)
+    4918:	df000115 	stw	fp,4(sp)
+    491c:	df000104 	addi	fp,sp,4
   destructor* dtor;
 
   for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
-    48b8:	00800034 	movhi	r2,0
-    48bc:	1095f704 	addi	r2,r2,22492
-    48c0:	e0bfff15 	stw	r2,-4(fp)
-    48c4:	00000606 	br	48e0 <_do_dtors+0x38>
+    4920:	00800034 	movhi	r2,0
+    4924:	1095cc04 	addi	r2,r2,22320
+    4928:	e0bfff15 	stw	r2,-4(fp)
+    492c:	00000606 	br	4948 <_do_dtors+0x38>
         (*dtor) (); 
-    48c8:	e0bfff17 	ldw	r2,-4(fp)
-    48cc:	10800017 	ldw	r2,0(r2)
-    48d0:	103ee83a 	callr	r2
-
-void _do_dtors(void)
-{
-  destructor* dtor;
-
+    4930:	e0bfff17 	ldw	r2,-4(fp)
+    4934:	10800017 	ldw	r2,0(r2)
+    4938:	103ee83a 	callr	r2
   for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
-    48d4:	e0bfff17 	ldw	r2,-4(fp)
-    48d8:	10bfff04 	addi	r2,r2,-4
-    48dc:	e0bfff15 	stw	r2,-4(fp)
-    48e0:	e0ffff17 	ldw	r3,-4(fp)
-    48e4:	00800034 	movhi	r2,0
-    48e8:	1095f804 	addi	r2,r2,22496
-    48ec:	18bff62e 	bgeu	r3,r2,48c8 <__alt_data_end+0xfffe48c8>
-        (*dtor) (); 
+    493c:	e0bfff17 	ldw	r2,-4(fp)
+    4940:	10bfff04 	addi	r2,r2,-4
+    4944:	e0bfff15 	stw	r2,-4(fp)
+    4948:	e0ffff17 	ldw	r3,-4(fp)
+    494c:	00800034 	movhi	r2,0
+    4950:	1095cd04 	addi	r2,r2,22324
+    4954:	18bff62e 	bgeu	r3,r2,4930 <_do_dtors+0x20>
 }
-    48f0:	0001883a 	nop
-    48f4:	e037883a 	mov	sp,fp
-    48f8:	dfc00117 	ldw	ra,4(sp)
-    48fc:	df000017 	ldw	fp,0(sp)
-    4900:	dec00204 	addi	sp,sp,8
-    4904:	f800283a 	ret
+    4958:	0001883a 	nop
+    495c:	0001883a 	nop
+    4960:	e037883a 	mov	sp,fp
+    4964:	dfc00117 	ldw	ra,4(sp)
+    4968:	df000017 	ldw	fp,0(sp)
+    496c:	dec00204 	addi	sp,sp,8
+    4970:	f800283a 	ret
 
-00004908 <alt_ic_isr_register>:
+00004974 <alt_ic_isr_register>:
   * @param irq              IRQ number
   * @return                 0 if successful, else error (-1)
   */
 int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
   void *isr_context, void *flags)
 {
-    4908:	defff904 	addi	sp,sp,-28
-    490c:	dfc00615 	stw	ra,24(sp)
-    4910:	df000515 	stw	fp,20(sp)
-    4914:	df000504 	addi	fp,sp,20
-    4918:	e13ffc15 	stw	r4,-16(fp)
-    491c:	e17ffd15 	stw	r5,-12(fp)
-    4920:	e1bffe15 	stw	r6,-8(fp)
-    4924:	e1ffff15 	stw	r7,-4(fp)
+    4974:	defff904 	addi	sp,sp,-28
+    4978:	dfc00615 	stw	ra,24(sp)
+    497c:	df000515 	stw	fp,20(sp)
+    4980:	df000504 	addi	fp,sp,20
+    4984:	e13fff15 	stw	r4,-4(fp)
+    4988:	e17ffe15 	stw	r5,-8(fp)
+    498c:	e1bffd15 	stw	r6,-12(fp)
+    4990:	e1fffc15 	stw	r7,-16(fp)
     return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags);
-    4928:	e0800217 	ldw	r2,8(fp)
-    492c:	d8800015 	stw	r2,0(sp)
-    4930:	e1ffff17 	ldw	r7,-4(fp)
-    4934:	e1bffe17 	ldw	r6,-8(fp)
-    4938:	e17ffd17 	ldw	r5,-12(fp)
-    493c:	e13ffc17 	ldw	r4,-16(fp)
-    4940:	0004ab80 	call	4ab8 <alt_iic_isr_register>
+    4994:	e0800217 	ldw	r2,8(fp)
+    4998:	d8800015 	stw	r2,0(sp)
+    499c:	e1fffc17 	ldw	r7,-16(fp)
+    49a0:	e1bffd17 	ldw	r6,-12(fp)
+    49a4:	e17ffe17 	ldw	r5,-8(fp)
+    49a8:	e13fff17 	ldw	r4,-4(fp)
+    49ac:	0004b240 	call	4b24 <alt_iic_isr_register>
 }  
-    4944:	e037883a 	mov	sp,fp
-    4948:	dfc00117 	ldw	ra,4(sp)
-    494c:	df000017 	ldw	fp,0(sp)
-    4950:	dec00204 	addi	sp,sp,8
-    4954:	f800283a 	ret
+    49b0:	e037883a 	mov	sp,fp
+    49b4:	dfc00117 	ldw	ra,4(sp)
+    49b8:	df000017 	ldw	fp,0(sp)
+    49bc:	dec00204 	addi	sp,sp,8
+    49c0:	f800283a 	ret
 
-00004958 <alt_ic_irq_enable>:
+000049c4 <alt_ic_irq_enable>:
   * @param ic_id            Ignored.
   * @param irq              IRQ number
   * @return                 0 if successful, else error (-1)
   */
 int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq)
 {
-    4958:	defff904 	addi	sp,sp,-28
-    495c:	df000615 	stw	fp,24(sp)
-    4960:	df000604 	addi	fp,sp,24
-    4964:	e13ffe15 	stw	r4,-8(fp)
-    4968:	e17fff15 	stw	r5,-4(fp)
-    496c:	e0bfff17 	ldw	r2,-4(fp)
-    4970:	e0bffa15 	stw	r2,-24(fp)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    49c4:	defff904 	addi	sp,sp,-28
+    49c8:	df000615 	stw	fp,24(sp)
+    49cc:	df000604 	addi	fp,sp,24
+    49d0:	e13ffb15 	stw	r4,-20(fp)
+    49d4:	e17ffa15 	stw	r5,-24(fp)
+    49d8:	e0bffa17 	ldw	r2,-24(fp)
+    49dc:	e0bfff15 	stw	r2,-4(fp)
   NIOS2_READ_STATUS (context);
-    4974:	0005303a 	rdctl	r2,status
-    4978:	e0bffb15 	stw	r2,-20(fp)
-
+    49e0:	0005303a 	rdctl	r2,status
+    49e4:	e0bffe15 	stw	r2,-8(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    497c:	e0fffb17 	ldw	r3,-20(fp)
-    4980:	00bfff84 	movi	r2,-2
-    4984:	1884703a 	and	r2,r3,r2
-    4988:	1001703a 	wrctl	status,r2
-  
+    49e8:	e0fffe17 	ldw	r3,-8(fp)
+    49ec:	00bfff84 	movi	r2,-2
+    49f0:	1884703a 	and	r2,r3,r2
+    49f4:	1001703a 	wrctl	status,r2
   return context;
-    498c:	e0bffb17 	ldw	r2,-20(fp)
+    49f8:	e0bffe17 	ldw	r2,-8(fp)
 static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id)
 {
   alt_irq_context  status;
   extern volatile alt_u32 alt_irq_active;
 
   status = alt_irq_disable_all ();
-    4990:	e0bffc15 	stw	r2,-16(fp)
+    49fc:	e0bffd15 	stw	r2,-12(fp)
 
   alt_irq_active |= (1 << id);
-    4994:	00c00044 	movi	r3,1
-    4998:	e0bffa17 	ldw	r2,-24(fp)
-    499c:	1884983a 	sll	r2,r3,r2
-    49a0:	1007883a 	mov	r3,r2
-    49a4:	d0a01517 	ldw	r2,-32684(gp)
-    49a8:	1884b03a 	or	r2,r3,r2
-    49ac:	d0a01515 	stw	r2,-32684(gp)
+    4a00:	00c00044 	movi	r3,1
+    4a04:	e0bfff17 	ldw	r2,-4(fp)
+    4a08:	1884983a 	sll	r2,r3,r2
+    4a0c:	1007883a 	mov	r3,r2
+    4a10:	d0a01517 	ldw	r2,-32684(gp)
+    4a14:	1884b03a 	or	r2,r3,r2
+    4a18:	d0a01515 	stw	r2,-32684(gp)
   NIOS2_WRITE_IENABLE (alt_irq_active);
-    49b0:	d0a01517 	ldw	r2,-32684(gp)
-    49b4:	100170fa 	wrctl	ienable,r2
-    49b8:	e0bffc17 	ldw	r2,-16(fp)
-    49bc:	e0bffd15 	stw	r2,-12(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    4a1c:	d0a01517 	ldw	r2,-32684(gp)
+    4a20:	100170fa 	wrctl	ienable,r2
+    4a24:	e0bffd17 	ldw	r2,-12(fp)
+    4a28:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context);
-    49c0:	e0bffd17 	ldw	r2,-12(fp)
-    49c4:	1001703a 	wrctl	status,r2
+    4a2c:	e0bffc17 	ldw	r2,-16(fp)
+    4a30:	1001703a 	wrctl	status,r2
+}
+    4a34:	0001883a 	nop
 
   alt_irq_enable_all(status);
 
   return 0;
-    49c8:	0005883a 	mov	r2,zero
+    4a38:	0005883a 	mov	r2,zero
     return alt_irq_enable(irq);
-    49cc:	0001883a 	nop
 }
-    49d0:	e037883a 	mov	sp,fp
-    49d4:	df000017 	ldw	fp,0(sp)
-    49d8:	dec00104 	addi	sp,sp,4
-    49dc:	f800283a 	ret
+    4a3c:	e037883a 	mov	sp,fp
+    4a40:	df000017 	ldw	fp,0(sp)
+    4a44:	dec00104 	addi	sp,sp,4
+    4a48:	f800283a 	ret
 
-000049e0 <alt_ic_irq_disable>:
+00004a4c <alt_ic_irq_disable>:
   * @param ic_id            Ignored.
   * @param irq              IRQ number
   * @return                 0 if successful, else error (-1)
   */
 int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq)
 {
-    49e0:	defff904 	addi	sp,sp,-28
-    49e4:	df000615 	stw	fp,24(sp)
-    49e8:	df000604 	addi	fp,sp,24
-    49ec:	e13ffe15 	stw	r4,-8(fp)
-    49f0:	e17fff15 	stw	r5,-4(fp)
-    49f4:	e0bfff17 	ldw	r2,-4(fp)
-    49f8:	e0bffa15 	stw	r2,-24(fp)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    4a4c:	defff904 	addi	sp,sp,-28
+    4a50:	df000615 	stw	fp,24(sp)
+    4a54:	df000604 	addi	fp,sp,24
+    4a58:	e13ffb15 	stw	r4,-20(fp)
+    4a5c:	e17ffa15 	stw	r5,-24(fp)
+    4a60:	e0bffa17 	ldw	r2,-24(fp)
+    4a64:	e0bfff15 	stw	r2,-4(fp)
   NIOS2_READ_STATUS (context);
-    49fc:	0005303a 	rdctl	r2,status
-    4a00:	e0bffb15 	stw	r2,-20(fp)
-
+    4a68:	0005303a 	rdctl	r2,status
+    4a6c:	e0bffe15 	stw	r2,-8(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    4a04:	e0fffb17 	ldw	r3,-20(fp)
-    4a08:	00bfff84 	movi	r2,-2
-    4a0c:	1884703a 	and	r2,r3,r2
-    4a10:	1001703a 	wrctl	status,r2
-  
+    4a70:	e0fffe17 	ldw	r3,-8(fp)
+    4a74:	00bfff84 	movi	r2,-2
+    4a78:	1884703a 	and	r2,r3,r2
+    4a7c:	1001703a 	wrctl	status,r2
   return context;
-    4a14:	e0bffb17 	ldw	r2,-20(fp)
-static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id)
-{
-  alt_irq_context  status;
-  extern volatile alt_u32 alt_irq_active;
-
+    4a80:	e0bffe17 	ldw	r2,-8(fp)
   status = alt_irq_disable_all ();
-    4a18:	e0bffc15 	stw	r2,-16(fp)
-
+    4a84:	e0bffd15 	stw	r2,-12(fp)
   alt_irq_active &= ~(1 << id);
-    4a1c:	00c00044 	movi	r3,1
-    4a20:	e0bffa17 	ldw	r2,-24(fp)
-    4a24:	1884983a 	sll	r2,r3,r2
-    4a28:	0084303a 	nor	r2,zero,r2
-    4a2c:	1007883a 	mov	r3,r2
-    4a30:	d0a01517 	ldw	r2,-32684(gp)
-    4a34:	1884703a 	and	r2,r3,r2
-    4a38:	d0a01515 	stw	r2,-32684(gp)
+    4a88:	00c00044 	movi	r3,1
+    4a8c:	e0bfff17 	ldw	r2,-4(fp)
+    4a90:	1884983a 	sll	r2,r3,r2
+    4a94:	0084303a 	nor	r2,zero,r2
+    4a98:	1007883a 	mov	r3,r2
+    4a9c:	d0a01517 	ldw	r2,-32684(gp)
+    4aa0:	1884703a 	and	r2,r3,r2
+    4aa4:	d0a01515 	stw	r2,-32684(gp)
   NIOS2_WRITE_IENABLE (alt_irq_active);
-    4a3c:	d0a01517 	ldw	r2,-32684(gp)
-    4a40:	100170fa 	wrctl	ienable,r2
-    4a44:	e0bffc17 	ldw	r2,-16(fp)
-    4a48:	e0bffd15 	stw	r2,-12(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    4aa8:	d0a01517 	ldw	r2,-32684(gp)
+    4aac:	100170fa 	wrctl	ienable,r2
+    4ab0:	e0bffd17 	ldw	r2,-12(fp)
+    4ab4:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context);
-    4a4c:	e0bffd17 	ldw	r2,-12(fp)
-    4a50:	1001703a 	wrctl	status,r2
-
-  alt_irq_enable_all(status);
-
-  return 0;
-    4a54:	0005883a 	mov	r2,zero
-    return alt_irq_disable(irq);
-    4a58:	0001883a 	nop
+    4ab8:	e0bffc17 	ldw	r2,-16(fp)
+    4abc:	1001703a 	wrctl	status,r2
 }
-    4a5c:	e037883a 	mov	sp,fp
-    4a60:	df000017 	ldw	fp,0(sp)
-    4a64:	dec00104 	addi	sp,sp,4
-    4a68:	f800283a 	ret
+    4ac0:	0001883a 	nop
+  return 0;
+    4ac4:	0005883a 	mov	r2,zero
+    return alt_irq_disable(irq);
+}
+    4ac8:	e037883a 	mov	sp,fp
+    4acc:	df000017 	ldw	fp,0(sp)
+    4ad0:	dec00104 	addi	sp,sp,4
+    4ad4:	f800283a 	ret
 
-00004a6c <alt_ic_irq_enabled>:
+00004ad8 <alt_ic_irq_enabled>:
   * @param irq              IRQ number
   * @return                 Zero if corresponding interrupt is disabled and
   *                         non-zero otherwise.
   */
 alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq)
 {
-    4a6c:	defffc04 	addi	sp,sp,-16
-    4a70:	df000315 	stw	fp,12(sp)
-    4a74:	df000304 	addi	fp,sp,12
-    4a78:	e13ffe15 	stw	r4,-8(fp)
-    4a7c:	e17fff15 	stw	r5,-4(fp)
+    4ad8:	defffc04 	addi	sp,sp,-16
+    4adc:	df000315 	stw	fp,12(sp)
+    4ae0:	df000304 	addi	fp,sp,12
+    4ae4:	e13ffe15 	stw	r4,-8(fp)
+    4ae8:	e17ffd15 	stw	r5,-12(fp)
     alt_u32 irq_enabled;
 
     NIOS2_READ_IENABLE(irq_enabled);
-    4a80:	000530fa 	rdctl	r2,ienable
-    4a84:	e0bffd15 	stw	r2,-12(fp)
+    4aec:	000530fa 	rdctl	r2,ienable
+    4af0:	e0bfff15 	stw	r2,-4(fp)
 
     return (irq_enabled & (1 << irq)) ? 1: 0;
-    4a88:	00c00044 	movi	r3,1
-    4a8c:	e0bfff17 	ldw	r2,-4(fp)
-    4a90:	1884983a 	sll	r2,r3,r2
-    4a94:	1007883a 	mov	r3,r2
-    4a98:	e0bffd17 	ldw	r2,-12(fp)
-    4a9c:	1884703a 	and	r2,r3,r2
-    4aa0:	1004c03a 	cmpne	r2,r2,zero
-    4aa4:	10803fcc 	andi	r2,r2,255
+    4af4:	00c00044 	movi	r3,1
+    4af8:	e0bffd17 	ldw	r2,-12(fp)
+    4afc:	1884983a 	sll	r2,r3,r2
+    4b00:	1007883a 	mov	r3,r2
+    4b04:	e0bfff17 	ldw	r2,-4(fp)
+    4b08:	1884703a 	and	r2,r3,r2
+    4b0c:	1004c03a 	cmpne	r2,r2,zero
+    4b10:	10803fcc 	andi	r2,r2,255
 }
-    4aa8:	e037883a 	mov	sp,fp
-    4aac:	df000017 	ldw	fp,0(sp)
-    4ab0:	dec00104 	addi	sp,sp,4
-    4ab4:	f800283a 	ret
+    4b14:	e037883a 	mov	sp,fp
+    4b18:	df000017 	ldw	fp,0(sp)
+    4b1c:	dec00104 	addi	sp,sp,4
+    4b20:	f800283a 	ret
 
-00004ab8 <alt_iic_isr_register>:
+00004b24 <alt_iic_isr_register>:
   * @param flags            
   * @return                 0 if successful, else error (-1)
   */
 int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
   void *isr_context, void *flags)
 {
-    4ab8:	defff504 	addi	sp,sp,-44
-    4abc:	dfc00a15 	stw	ra,40(sp)
-    4ac0:	df000915 	stw	fp,36(sp)
-    4ac4:	df000904 	addi	fp,sp,36
-    4ac8:	e13ffc15 	stw	r4,-16(fp)
-    4acc:	e17ffd15 	stw	r5,-12(fp)
-    4ad0:	e1bffe15 	stw	r6,-8(fp)
-    4ad4:	e1ffff15 	stw	r7,-4(fp)
+    4b24:	defff504 	addi	sp,sp,-44
+    4b28:	dfc00a15 	stw	ra,40(sp)
+    4b2c:	df000915 	stw	fp,36(sp)
+    4b30:	df000904 	addi	fp,sp,36
+    4b34:	e13ffa15 	stw	r4,-24(fp)
+    4b38:	e17ff915 	stw	r5,-28(fp)
+    4b3c:	e1bff815 	stw	r6,-32(fp)
+    4b40:	e1fff715 	stw	r7,-36(fp)
   int rc = -EINVAL;  
-    4ad8:	00bffa84 	movi	r2,-22
-    4adc:	e0bff715 	stw	r2,-36(fp)
+    4b44:	00bffa84 	movi	r2,-22
+    4b48:	e0bfff15 	stw	r2,-4(fp)
   int id = irq;             /* IRQ interpreted as the interrupt ID. */
-    4ae0:	e0bffd17 	ldw	r2,-12(fp)
-    4ae4:	e0bff815 	stw	r2,-32(fp)
+    4b4c:	e0bff917 	ldw	r2,-28(fp)
+    4b50:	e0bffe15 	stw	r2,-8(fp)
   alt_irq_context status;
 
   if (id < ALT_NIRQ)
-    4ae8:	e0bff817 	ldw	r2,-32(fp)
-    4aec:	10800808 	cmpgei	r2,r2,32
-    4af0:	1000271e 	bne	r2,zero,4b90 <alt_iic_isr_register+0xd8>
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    4b54:	e0bffe17 	ldw	r2,-8(fp)
+    4b58:	10800808 	cmpgei	r2,r2,32
+    4b5c:	1000251e 	bne	r2,zero,4bf4 <alt_iic_isr_register+0xd0>
   NIOS2_READ_STATUS (context);
-    4af4:	0005303a 	rdctl	r2,status
-    4af8:	e0bffb15 	stw	r2,-20(fp)
-
+    4b60:	0005303a 	rdctl	r2,status
+    4b64:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    4afc:	e0fffb17 	ldw	r3,-20(fp)
-    4b00:	00bfff84 	movi	r2,-2
-    4b04:	1884703a 	and	r2,r3,r2
-    4b08:	1001703a 	wrctl	status,r2
-  
+    4b68:	e0fffc17 	ldw	r3,-16(fp)
+    4b6c:	00bfff84 	movi	r2,-2
+    4b70:	1884703a 	and	r2,r3,r2
+    4b74:	1001703a 	wrctl	status,r2
   return context;
-    4b0c:	e0bffb17 	ldw	r2,-20(fp)
+    4b78:	e0bffc17 	ldw	r2,-16(fp)
      * interrupts are disabled while the handler tables are updated to ensure
      * that an interrupt doesn't occur while the tables are in an inconsistant
      * state.
      */
 
     status = alt_irq_disable_all();
-    4b10:	e0bffa15 	stw	r2,-24(fp)
+    4b7c:	e0bffd15 	stw	r2,-12(fp)
 
     alt_irq[id].handler = isr;
-    4b14:	00800034 	movhi	r2,0
-    4b18:	109cc704 	addi	r2,r2,29468
-    4b1c:	e0fff817 	ldw	r3,-32(fp)
-    4b20:	180690fa 	slli	r3,r3,3
-    4b24:	10c5883a 	add	r2,r2,r3
-    4b28:	e0fffe17 	ldw	r3,-8(fp)
-    4b2c:	10c00015 	stw	r3,0(r2)
+    4b80:	e0bffe17 	ldw	r2,-8(fp)
+    4b84:	100890fa 	slli	r4,r2,3
+    4b88:	e0fff817 	ldw	r3,-32(fp)
+    4b8c:	00800034 	movhi	r2,0
+    4b90:	2085883a 	add	r2,r4,r2
+    4b94:	10dc9b15 	stw	r3,29292(r2)
     alt_irq[id].context = isr_context;
-    4b30:	00800034 	movhi	r2,0
-    4b34:	109cc704 	addi	r2,r2,29468
-    4b38:	e0fff817 	ldw	r3,-32(fp)
-    4b3c:	180690fa 	slli	r3,r3,3
-    4b40:	10c5883a 	add	r2,r2,r3
-    4b44:	10800104 	addi	r2,r2,4
-    4b48:	e0ffff17 	ldw	r3,-4(fp)
-    4b4c:	10c00015 	stw	r3,0(r2)
+    4b98:	e0bffe17 	ldw	r2,-8(fp)
+    4b9c:	100890fa 	slli	r4,r2,3
+    4ba0:	e0fff717 	ldw	r3,-36(fp)
+    4ba4:	00800034 	movhi	r2,0
+    4ba8:	2085883a 	add	r2,r4,r2
+    4bac:	10dc9c15 	stw	r3,29296(r2)
 
     rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
-    4b50:	e0bffe17 	ldw	r2,-8(fp)
-    4b54:	10000526 	beq	r2,zero,4b6c <alt_iic_isr_register+0xb4>
-    4b58:	e0bff817 	ldw	r2,-32(fp)
-    4b5c:	100b883a 	mov	r5,r2
-    4b60:	e13ffc17 	ldw	r4,-16(fp)
-    4b64:	00049580 	call	4958 <alt_ic_irq_enable>
-    4b68:	00000406 	br	4b7c <alt_iic_isr_register+0xc4>
-    4b6c:	e0bff817 	ldw	r2,-32(fp)
-    4b70:	100b883a 	mov	r5,r2
-    4b74:	e13ffc17 	ldw	r4,-16(fp)
-    4b78:	00049e00 	call	49e0 <alt_ic_irq_disable>
-    4b7c:	e0bff715 	stw	r2,-36(fp)
-    4b80:	e0bffa17 	ldw	r2,-24(fp)
-    4b84:	e0bff915 	stw	r2,-28(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    4bb0:	e0bff817 	ldw	r2,-32(fp)
+    4bb4:	10000526 	beq	r2,zero,4bcc <alt_iic_isr_register+0xa8>
+    4bb8:	e0bffe17 	ldw	r2,-8(fp)
+    4bbc:	100b883a 	mov	r5,r2
+    4bc0:	e13ffa17 	ldw	r4,-24(fp)
+    4bc4:	00049c40 	call	49c4 <alt_ic_irq_enable>
+    4bc8:	00000406 	br	4bdc <alt_iic_isr_register+0xb8>
+    4bcc:	e0bffe17 	ldw	r2,-8(fp)
+    4bd0:	100b883a 	mov	r5,r2
+    4bd4:	e13ffa17 	ldw	r4,-24(fp)
+    4bd8:	0004a4c0 	call	4a4c <alt_ic_irq_disable>
+    4bdc:	e0bfff15 	stw	r2,-4(fp)
+    4be0:	e0bffd17 	ldw	r2,-12(fp)
+    4be4:	e0bffb15 	stw	r2,-20(fp)
   NIOS2_WRITE_STATUS (context);
-    4b88:	e0bff917 	ldw	r2,-28(fp)
-    4b8c:	1001703a 	wrctl	status,r2
+    4be8:	e0bffb17 	ldw	r2,-20(fp)
+    4bec:	1001703a 	wrctl	status,r2
+}
+    4bf0:	0001883a 	nop
 
     alt_irq_enable_all(status);
   }
 
   return rc; 
-    4b90:	e0bff717 	ldw	r2,-36(fp)
+    4bf4:	e0bfff17 	ldw	r2,-4(fp)
 }
-    4b94:	e037883a 	mov	sp,fp
-    4b98:	dfc00117 	ldw	ra,4(sp)
-    4b9c:	df000017 	ldw	fp,0(sp)
-    4ba0:	dec00204 	addi	sp,sp,8
-    4ba4:	f800283a 	ret
+    4bf8:	e037883a 	mov	sp,fp
+    4bfc:	dfc00117 	ldw	ra,4(sp)
+    4c00:	df000017 	ldw	fp,0(sp)
+    4c04:	dec00204 	addi	sp,sp,8
+    4c08:	f800283a 	ret
 
-00004ba8 <alt_open_fd>:
+00004c0c <alt_open_fd>:
  * If the device can not be succesfully opened, then the input file descriptor
  * remains unchanged.
  */
 
 static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode)
 {
-    4ba8:	defff804 	addi	sp,sp,-32
-    4bac:	dfc00715 	stw	ra,28(sp)
-    4bb0:	df000615 	stw	fp,24(sp)
-    4bb4:	dc000515 	stw	r16,20(sp)
-    4bb8:	df000604 	addi	fp,sp,24
-    4bbc:	e13ffb15 	stw	r4,-20(fp)
-    4bc0:	e17ffc15 	stw	r5,-16(fp)
-    4bc4:	e1bffd15 	stw	r6,-12(fp)
-    4bc8:	e1fffe15 	stw	r7,-8(fp)
+    4c0c:	defff904 	addi	sp,sp,-28
+    4c10:	dfc00615 	stw	ra,24(sp)
+    4c14:	df000515 	stw	fp,20(sp)
+    4c18:	df000504 	addi	fp,sp,20
+    4c1c:	e13ffe15 	stw	r4,-8(fp)
+    4c20:	e17ffd15 	stw	r5,-12(fp)
+    4c24:	e1bffc15 	stw	r6,-16(fp)
+    4c28:	e1fffb15 	stw	r7,-20(fp)
   int old;
 
   old = open (name, flags, mode);
-    4bcc:	e1bffe17 	ldw	r6,-8(fp)
-    4bd0:	e17ffd17 	ldw	r5,-12(fp)
-    4bd4:	e13ffc17 	ldw	r4,-16(fp)
-    4bd8:	0004e300 	call	4e30 <open>
-    4bdc:	e0bffa15 	stw	r2,-24(fp)
+    4c2c:	e1bffb17 	ldw	r6,-20(fp)
+    4c30:	e17ffc17 	ldw	r5,-16(fp)
+    4c34:	e13ffd17 	ldw	r4,-12(fp)
+    4c38:	0004e740 	call	4e74 <open>
+    4c3c:	e0bfff15 	stw	r2,-4(fp)
 
   if (old >= 0)
-    4be0:	e0bffa17 	ldw	r2,-24(fp)
-    4be4:	10002216 	blt	r2,zero,4c70 <alt_open_fd+0xc8>
+    4c40:	e0bfff17 	ldw	r2,-4(fp)
+    4c44:	10002016 	blt	r2,zero,4cc8 <alt_open_fd+0xbc>
   {
     fd->dev      = alt_fd_list[old].dev;
-    4be8:	04000034 	movhi	r16,0
-    4bec:	84182c04 	addi	r16,r16,24752
-    4bf0:	e0bffa17 	ldw	r2,-24(fp)
-    4bf4:	01400304 	movi	r5,12
-    4bf8:	1009883a 	mov	r4,r2
-    4bfc:	000311c0 	call	311c <__mulsi3>
-    4c00:	8085883a 	add	r2,r16,r2
-    4c04:	10c00017 	ldw	r3,0(r2)
-    4c08:	e0bffb17 	ldw	r2,-20(fp)
-    4c0c:	10c00015 	stw	r3,0(r2)
+    4c48:	e0ffff17 	ldw	r3,-4(fp)
+    4c4c:	1805883a 	mov	r2,r3
+    4c50:	1085883a 	add	r2,r2,r2
+    4c54:	10c5883a 	add	r2,r2,r3
+    4c58:	100490ba 	slli	r2,r2,2
+    4c5c:	00c00034 	movhi	r3,0
+    4c60:	10c7883a 	add	r3,r2,r3
+    4c64:	18d80017 	ldw	r3,24576(r3)
+    4c68:	e0bffe17 	ldw	r2,-8(fp)
+    4c6c:	10c00015 	stw	r3,0(r2)
     fd->priv     = alt_fd_list[old].priv;
-    4c10:	04000034 	movhi	r16,0
-    4c14:	84182c04 	addi	r16,r16,24752
-    4c18:	e0bffa17 	ldw	r2,-24(fp)
-    4c1c:	01400304 	movi	r5,12
-    4c20:	1009883a 	mov	r4,r2
-    4c24:	000311c0 	call	311c <__mulsi3>
-    4c28:	8085883a 	add	r2,r16,r2
-    4c2c:	10800104 	addi	r2,r2,4
-    4c30:	10c00017 	ldw	r3,0(r2)
-    4c34:	e0bffb17 	ldw	r2,-20(fp)
-    4c38:	10c00115 	stw	r3,4(r2)
+    4c70:	e0ffff17 	ldw	r3,-4(fp)
+    4c74:	1805883a 	mov	r2,r3
+    4c78:	1085883a 	add	r2,r2,r2
+    4c7c:	10c5883a 	add	r2,r2,r3
+    4c80:	100490ba 	slli	r2,r2,2
+    4c84:	00c00034 	movhi	r3,0
+    4c88:	10c7883a 	add	r3,r2,r3
+    4c8c:	18d80117 	ldw	r3,24580(r3)
+    4c90:	e0bffe17 	ldw	r2,-8(fp)
+    4c94:	10c00115 	stw	r3,4(r2)
     fd->fd_flags = alt_fd_list[old].fd_flags;
-    4c3c:	04000034 	movhi	r16,0
-    4c40:	84182c04 	addi	r16,r16,24752
-    4c44:	e0bffa17 	ldw	r2,-24(fp)
-    4c48:	01400304 	movi	r5,12
-    4c4c:	1009883a 	mov	r4,r2
-    4c50:	000311c0 	call	311c <__mulsi3>
-    4c54:	8085883a 	add	r2,r16,r2
-    4c58:	10800204 	addi	r2,r2,8
-    4c5c:	10c00017 	ldw	r3,0(r2)
-    4c60:	e0bffb17 	ldw	r2,-20(fp)
-    4c64:	10c00215 	stw	r3,8(r2)
+    4c98:	e0ffff17 	ldw	r3,-4(fp)
+    4c9c:	1805883a 	mov	r2,r3
+    4ca0:	1085883a 	add	r2,r2,r2
+    4ca4:	10c5883a 	add	r2,r2,r3
+    4ca8:	100490ba 	slli	r2,r2,2
+    4cac:	00c00034 	movhi	r3,0
+    4cb0:	10c7883a 	add	r3,r2,r3
+    4cb4:	18d80217 	ldw	r3,24584(r3)
+    4cb8:	e0bffe17 	ldw	r2,-8(fp)
+    4cbc:	10c00215 	stw	r3,8(r2)
 
     alt_release_fd (old);
-    4c68:	e13ffa17 	ldw	r4,-24(fp)
-    4c6c:	00037a40 	call	37a4 <alt_release_fd>
+    4cc0:	e13fff17 	ldw	r4,-4(fp)
+    4cc4:	00037e80 	call	37e8 <alt_release_fd>
   }
 } 
-    4c70:	0001883a 	nop
-    4c74:	e6ffff04 	addi	sp,fp,-4
-    4c78:	dfc00217 	ldw	ra,8(sp)
-    4c7c:	df000117 	ldw	fp,4(sp)
-    4c80:	dc000017 	ldw	r16,0(sp)
-    4c84:	dec00304 	addi	sp,sp,12
-    4c88:	f800283a 	ret
+    4cc8:	0001883a 	nop
+    4ccc:	e037883a 	mov	sp,fp
+    4cd0:	dfc00117 	ldw	ra,4(sp)
+    4cd4:	df000017 	ldw	fp,0(sp)
+    4cd8:	dec00204 	addi	sp,sp,8
+    4cdc:	f800283a 	ret
 
-00004c8c <alt_io_redirect>:
+00004ce0 <alt_io_redirect>:
  */
  
 void alt_io_redirect(const char* stdout_dev, 
                      const char* stdin_dev, 
                      const char* stderr_dev)
 {
-    4c8c:	defffb04 	addi	sp,sp,-20
-    4c90:	dfc00415 	stw	ra,16(sp)
-    4c94:	df000315 	stw	fp,12(sp)
-    4c98:	df000304 	addi	fp,sp,12
-    4c9c:	e13ffd15 	stw	r4,-12(fp)
-    4ca0:	e17ffe15 	stw	r5,-8(fp)
-    4ca4:	e1bfff15 	stw	r6,-4(fp)
+    4ce0:	defffb04 	addi	sp,sp,-20
+    4ce4:	dfc00415 	stw	ra,16(sp)
+    4ce8:	df000315 	stw	fp,12(sp)
+    4cec:	df000304 	addi	fp,sp,12
+    4cf0:	e13fff15 	stw	r4,-4(fp)
+    4cf4:	e17ffe15 	stw	r5,-8(fp)
+    4cf8:	e1bffd15 	stw	r6,-12(fp)
   /* Redirect the channels */
 
   alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777);
-    4ca8:	01c07fc4 	movi	r7,511
-    4cac:	01800044 	movi	r6,1
-    4cb0:	e17ffd17 	ldw	r5,-12(fp)
-    4cb4:	01000034 	movhi	r4,0
-    4cb8:	21182f04 	addi	r4,r4,24764
-    4cbc:	0004ba80 	call	4ba8 <alt_open_fd>
+    4cfc:	01c07fc4 	movi	r7,511
+    4d00:	01800044 	movi	r6,1
+    4d04:	e17fff17 	ldw	r5,-4(fp)
+    4d08:	01000034 	movhi	r4,0
+    4d0c:	21180304 	addi	r4,r4,24588
+    4d10:	0004c0c0 	call	4c0c <alt_open_fd>
   alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777);
-    4cc0:	01c07fc4 	movi	r7,511
-    4cc4:	000d883a 	mov	r6,zero
-    4cc8:	e17ffe17 	ldw	r5,-8(fp)
-    4ccc:	01000034 	movhi	r4,0
-    4cd0:	21182c04 	addi	r4,r4,24752
-    4cd4:	0004ba80 	call	4ba8 <alt_open_fd>
+    4d14:	01c07fc4 	movi	r7,511
+    4d18:	000d883a 	mov	r6,zero
+    4d1c:	e17ffe17 	ldw	r5,-8(fp)
+    4d20:	01000034 	movhi	r4,0
+    4d24:	21180004 	addi	r4,r4,24576
+    4d28:	0004c0c0 	call	4c0c <alt_open_fd>
   alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777);
-    4cd8:	01c07fc4 	movi	r7,511
-    4cdc:	01800044 	movi	r6,1
-    4ce0:	e17fff17 	ldw	r5,-4(fp)
-    4ce4:	01000034 	movhi	r4,0
-    4ce8:	21183204 	addi	r4,r4,24776
-    4cec:	0004ba80 	call	4ba8 <alt_open_fd>
+    4d2c:	01c07fc4 	movi	r7,511
+    4d30:	01800044 	movi	r6,1
+    4d34:	e17ffd17 	ldw	r5,-12(fp)
+    4d38:	01000034 	movhi	r4,0
+    4d3c:	21180604 	addi	r4,r4,24600
+    4d40:	0004c0c0 	call	4c0c <alt_open_fd>
 }  
-    4cf0:	0001883a 	nop
-    4cf4:	e037883a 	mov	sp,fp
-    4cf8:	dfc00117 	ldw	ra,4(sp)
-    4cfc:	df000017 	ldw	fp,0(sp)
-    4d00:	dec00204 	addi	sp,sp,8
-    4d04:	f800283a 	ret
+    4d44:	0001883a 	nop
+    4d48:	e037883a 	mov	sp,fp
+    4d4c:	dfc00117 	ldw	ra,4(sp)
+    4d50:	df000017 	ldw	fp,0(sp)
+    4d54:	dec00204 	addi	sp,sp,8
+    4d58:	f800283a 	ret
 
-00004d08 <alt_get_errno>:
-#undef errno
-
-extern int errno;
-
-static ALT_INLINE int* alt_get_errno(void)
+00004d5c <alt_get_errno>:
 {
-    4d08:	defffe04 	addi	sp,sp,-8
-    4d0c:	dfc00115 	stw	ra,4(sp)
-    4d10:	df000015 	stw	fp,0(sp)
-    4d14:	d839883a 	mov	fp,sp
+    4d5c:	defffe04 	addi	sp,sp,-8
+    4d60:	dfc00115 	stw	ra,4(sp)
+    4d64:	df000015 	stw	fp,0(sp)
+    4d68:	d839883a 	mov	fp,sp
   return ((alt_errno) ? alt_errno() : &errno);
-    4d18:	d0a00917 	ldw	r2,-32732(gp)
-    4d1c:	10000326 	beq	r2,zero,4d2c <alt_get_errno+0x24>
-    4d20:	d0a00917 	ldw	r2,-32732(gp)
-    4d24:	103ee83a 	callr	r2
-    4d28:	00000106 	br	4d30 <alt_get_errno+0x28>
-    4d2c:	d0a01104 	addi	r2,gp,-32700
+    4d6c:	d0a00917 	ldw	r2,-32732(gp)
+    4d70:	10000326 	beq	r2,zero,4d80 <alt_get_errno+0x24>
+    4d74:	d0a00917 	ldw	r2,-32732(gp)
+    4d78:	103ee83a 	callr	r2
+    4d7c:	00000106 	br	4d84 <alt_get_errno+0x28>
+    4d80:	d0a01104 	addi	r2,gp,-32700
 }
-    4d30:	e037883a 	mov	sp,fp
-    4d34:	dfc00117 	ldw	ra,4(sp)
-    4d38:	df000017 	ldw	fp,0(sp)
-    4d3c:	dec00204 	addi	sp,sp,8
-    4d40:	f800283a 	ret
+    4d84:	e037883a 	mov	sp,fp
+    4d88:	dfc00117 	ldw	ra,4(sp)
+    4d8c:	df000017 	ldw	fp,0(sp)
+    4d90:	dec00204 	addi	sp,sp,8
+    4d94:	f800283a 	ret
 
-00004d44 <alt_file_locked>:
+00004d98 <alt_file_locked>:
  * performed for devices. Filesystems are required to handle the ioctl() call
  * themselves, and report the error from the filesystems open() function. 
  */ 
 
 static int alt_file_locked (alt_fd* fd)
 {
-    4d44:	defffb04 	addi	sp,sp,-20
-    4d48:	dfc00415 	stw	ra,16(sp)
-    4d4c:	df000315 	stw	fp,12(sp)
-    4d50:	dc000215 	stw	r16,8(sp)
-    4d54:	df000304 	addi	fp,sp,12
-    4d58:	e13ffe15 	stw	r4,-8(fp)
+    4d98:	defffd04 	addi	sp,sp,-12
+    4d9c:	df000215 	stw	fp,8(sp)
+    4da0:	df000204 	addi	fp,sp,8
+    4da4:	e13ffe15 	stw	r4,-8(fp)
 
   /*
    * Mark the file descriptor as belonging to a device.
    */
 
   fd->fd_flags |= ALT_FD_DEV;
-    4d5c:	e0bffe17 	ldw	r2,-8(fp)
-    4d60:	10800217 	ldw	r2,8(r2)
-    4d64:	10d00034 	orhi	r3,r2,16384
-    4d68:	e0bffe17 	ldw	r2,-8(fp)
-    4d6c:	10c00215 	stw	r3,8(r2)
+    4da8:	e0bffe17 	ldw	r2,-8(fp)
+    4dac:	10800217 	ldw	r2,8(r2)
+    4db0:	10d00034 	orhi	r3,r2,16384
+    4db4:	e0bffe17 	ldw	r2,-8(fp)
+    4db8:	10c00215 	stw	r3,8(r2)
   /*
    * Loop through all current file descriptors searching for one that's locked
    * for exclusive access. If a match is found, generate an error.
    */
 
   for (i = 0; i <= alt_max_fd; i++)
-    4d70:	e03ffd15 	stw	zero,-12(fp)
-    4d74:	00002306 	br	4e04 <alt_file_locked+0xc0>
+    4dbc:	e03fff15 	stw	zero,-4(fp)
+    4dc0:	00002306 	br	4e50 <alt_file_locked+0xb8>
   {
     if ((alt_fd_list[i].dev == fd->dev) &&
-    4d78:	04000034 	movhi	r16,0
-    4d7c:	84182c04 	addi	r16,r16,24752
-    4d80:	e0bffd17 	ldw	r2,-12(fp)
-    4d84:	01400304 	movi	r5,12
-    4d88:	1009883a 	mov	r4,r2
-    4d8c:	000311c0 	call	311c <__mulsi3>
-    4d90:	8085883a 	add	r2,r16,r2
-    4d94:	10c00017 	ldw	r3,0(r2)
-    4d98:	e0bffe17 	ldw	r2,-8(fp)
-    4d9c:	10800017 	ldw	r2,0(r2)
-    4da0:	1880151e 	bne	r3,r2,4df8 <alt_file_locked+0xb4>
+    4dc4:	e0ffff17 	ldw	r3,-4(fp)
+    4dc8:	1805883a 	mov	r2,r3
+    4dcc:	1085883a 	add	r2,r2,r2
+    4dd0:	10c5883a 	add	r2,r2,r3
+    4dd4:	100490ba 	slli	r2,r2,2
+    4dd8:	00c00034 	movhi	r3,0
+    4ddc:	10c7883a 	add	r3,r2,r3
+    4de0:	18d80017 	ldw	r3,24576(r3)
+    4de4:	e0bffe17 	ldw	r2,-8(fp)
+    4de8:	10800017 	ldw	r2,0(r2)
+    4dec:	1880151e 	bne	r3,r2,4e44 <alt_file_locked+0xac>
         (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
-    4da4:	04000034 	movhi	r16,0
-    4da8:	84182c04 	addi	r16,r16,24752
-    4dac:	e0bffd17 	ldw	r2,-12(fp)
-    4db0:	01400304 	movi	r5,12
-    4db4:	1009883a 	mov	r4,r2
-    4db8:	000311c0 	call	311c <__mulsi3>
-    4dbc:	8085883a 	add	r2,r16,r2
-    4dc0:	10800204 	addi	r2,r2,8
-    4dc4:	10800017 	ldw	r2,0(r2)
-   * for exclusive access. If a match is found, generate an error.
-   */
-
-  for (i = 0; i <= alt_max_fd; i++)
-  {
+    4df0:	e0ffff17 	ldw	r3,-4(fp)
+    4df4:	1805883a 	mov	r2,r3
+    4df8:	1085883a 	add	r2,r2,r2
+    4dfc:	10c5883a 	add	r2,r2,r3
+    4e00:	100490ba 	slli	r2,r2,2
+    4e04:	00c00034 	movhi	r3,0
+    4e08:	10c7883a 	add	r3,r2,r3
+    4e0c:	18980217 	ldw	r2,24584(r3)
     if ((alt_fd_list[i].dev == fd->dev) &&
-    4dc8:	10000b0e 	bge	r2,zero,4df8 <alt_file_locked+0xb4>
-        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+    4e10:	10000c0e 	bge	r2,zero,4e44 <alt_file_locked+0xac>
         (&alt_fd_list[i] != fd))
-    4dcc:	01400304 	movi	r5,12
-    4dd0:	e13ffd17 	ldw	r4,-12(fp)
-    4dd4:	000311c0 	call	311c <__mulsi3>
-    4dd8:	1007883a 	mov	r3,r2
-    4ddc:	00800034 	movhi	r2,0
-    4de0:	10982c04 	addi	r2,r2,24752
-    4de4:	1887883a 	add	r3,r3,r2
-   */
-
-  for (i = 0; i <= alt_max_fd; i++)
-  {
-    if ((alt_fd_list[i].dev == fd->dev) &&
+    4e14:	e0ffff17 	ldw	r3,-4(fp)
+    4e18:	1805883a 	mov	r2,r3
+    4e1c:	1085883a 	add	r2,r2,r2
+    4e20:	10c5883a 	add	r2,r2,r3
+    4e24:	100490ba 	slli	r2,r2,2
+    4e28:	00c00034 	movhi	r3,0
+    4e2c:	18d80004 	addi	r3,r3,24576
+    4e30:	10c5883a 	add	r2,r2,r3
         (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
-    4de8:	e0bffe17 	ldw	r2,-8(fp)
-    4dec:	18800226 	beq	r3,r2,4df8 <alt_file_locked+0xb4>
-        (&alt_fd_list[i] != fd))
+    4e34:	e0fffe17 	ldw	r3,-8(fp)
+    4e38:	18800226 	beq	r3,r2,4e44 <alt_file_locked+0xac>
     {
       return -EACCES;
-    4df0:	00bffcc4 	movi	r2,-13
-    4df4:	00000806 	br	4e18 <alt_file_locked+0xd4>
-  /*
-   * Loop through all current file descriptors searching for one that's locked
-   * for exclusive access. If a match is found, generate an error.
-   */
-
+    4e3c:	00bffcc4 	movi	r2,-13
+    4e40:	00000806 	br	4e64 <alt_file_locked+0xcc>
   for (i = 0; i <= alt_max_fd; i++)
-    4df8:	e0bffd17 	ldw	r2,-12(fp)
-    4dfc:	10800044 	addi	r2,r2,1
-    4e00:	e0bffd15 	stw	r2,-12(fp)
-    4e04:	d0a00817 	ldw	r2,-32736(gp)
-    4e08:	1007883a 	mov	r3,r2
-    4e0c:	e0bffd17 	ldw	r2,-12(fp)
-    4e10:	18bfd92e 	bgeu	r3,r2,4d78 <__alt_data_end+0xfffe4d78>
+    4e44:	e0bfff17 	ldw	r2,-4(fp)
+    4e48:	10800044 	addi	r2,r2,1
+    4e4c:	e0bfff15 	stw	r2,-4(fp)
+    4e50:	d0a00817 	ldw	r2,-32736(gp)
+    4e54:	1007883a 	mov	r3,r2
+    4e58:	e0bfff17 	ldw	r2,-4(fp)
+    4e5c:	18bfd92e 	bgeu	r3,r2,4dc4 <alt_file_locked+0x2c>
     }
   }
   
   /* The device is not locked */
  
   return 0;
-    4e14:	0005883a 	mov	r2,zero
+    4e60:	0005883a 	mov	r2,zero
 }
-    4e18:	e6ffff04 	addi	sp,fp,-4
-    4e1c:	dfc00217 	ldw	ra,8(sp)
-    4e20:	df000117 	ldw	fp,4(sp)
-    4e24:	dc000017 	ldw	r16,0(sp)
-    4e28:	dec00304 	addi	sp,sp,12
-    4e2c:	f800283a 	ret
+    4e64:	e037883a 	mov	sp,fp
+    4e68:	df000017 	ldw	fp,0(sp)
+    4e6c:	dec00104 	addi	sp,sp,4
+    4e70:	f800283a 	ret
 
-00004e30 <open>:
+00004e74 <open>:
  *
  * ALT_OPEN is mapped onto the open() system call in alt_syscall.h
  */
  
 int ALT_OPEN (const char* file, int flags, int mode)
 { 
-    4e30:	defff604 	addi	sp,sp,-40
-    4e34:	dfc00915 	stw	ra,36(sp)
-    4e38:	df000815 	stw	fp,32(sp)
-    4e3c:	df000804 	addi	fp,sp,32
-    4e40:	e13ffd15 	stw	r4,-12(fp)
-    4e44:	e17ffe15 	stw	r5,-8(fp)
-    4e48:	e1bfff15 	stw	r6,-4(fp)
+    4e74:	defff604 	addi	sp,sp,-40
+    4e78:	dfc00915 	stw	ra,36(sp)
+    4e7c:	df000815 	stw	fp,32(sp)
+    4e80:	df000804 	addi	fp,sp,32
+    4e84:	e13ffa15 	stw	r4,-24(fp)
+    4e88:	e17ff915 	stw	r5,-28(fp)
+    4e8c:	e1bff815 	stw	r6,-32(fp)
   alt_dev* dev;
   alt_fd*  fd;
   int index  = -1;
-    4e4c:	00bfffc4 	movi	r2,-1
-    4e50:	e0bff915 	stw	r2,-28(fp)
+    4e90:	00bfffc4 	movi	r2,-1
+    4e94:	e0bffe15 	stw	r2,-8(fp)
   int status = -ENODEV;
-    4e54:	00bffb44 	movi	r2,-19
-    4e58:	e0bffa15 	stw	r2,-24(fp)
+    4e98:	00bffb44 	movi	r2,-19
+    4e9c:	e0bffd15 	stw	r2,-12(fp)
   int isafs = 0;
-    4e5c:	e03ffb15 	stw	zero,-20(fp)
+    4ea0:	e03ffc15 	stw	zero,-16(fp)
   /* 
    * Check the device list, to see if a device with a matching name is 
    * registered.
    */
   
   if (!(dev = alt_find_dev (file, &alt_dev_list)))
-    4e60:	d1600604 	addi	r5,gp,-32744
-    4e64:	e13ffd17 	ldw	r4,-12(fp)
-    4e68:	00051540 	call	5154 <alt_find_dev>
-    4e6c:	e0bff815 	stw	r2,-32(fp)
-    4e70:	e0bff817 	ldw	r2,-32(fp)
-    4e74:	1000051e 	bne	r2,zero,4e8c <open+0x5c>
+    4ea4:	d1600604 	addi	r5,gp,-32744
+    4ea8:	e13ffa17 	ldw	r4,-24(fp)
+    4eac:	00051a40 	call	51a4 <alt_find_dev>
+    4eb0:	e0bfff15 	stw	r2,-4(fp)
+    4eb4:	e0bfff17 	ldw	r2,-4(fp)
+    4eb8:	1000051e 	bne	r2,zero,4ed0 <open+0x5c>
   {
     /* No matching device, so try the filesystem list */
 
     dev   = alt_find_file (file);
-    4e78:	e13ffd17 	ldw	r4,-12(fp)
-    4e7c:	00051e40 	call	51e4 <alt_find_file>
-    4e80:	e0bff815 	stw	r2,-32(fp)
+    4ebc:	e13ffa17 	ldw	r4,-24(fp)
+    4ec0:	00052340 	call	5234 <alt_find_file>
+    4ec4:	e0bfff15 	stw	r2,-4(fp)
     isafs = 1;
-    4e84:	00800044 	movi	r2,1
-    4e88:	e0bffb15 	stw	r2,-20(fp)
+    4ec8:	00800044 	movi	r2,1
+    4ecc:	e0bffc15 	stw	r2,-16(fp)
 
   /* 
    * If a matching device or filesystem is found, allocate a file descriptor. 
    */
 
   if (dev)
-    4e8c:	e0bff817 	ldw	r2,-32(fp)
-    4e90:	10002b26 	beq	r2,zero,4f40 <open+0x110>
+    4ed0:	e0bfff17 	ldw	r2,-4(fp)
+    4ed4:	10002c26 	beq	r2,zero,4f88 <open+0x114>
   {
     if ((index = alt_get_fd (dev)) < 0)
-    4e94:	e13ff817 	ldw	r4,-32(fp)
-    4e98:	00052ec0 	call	52ec <alt_get_fd>
-    4e9c:	e0bff915 	stw	r2,-28(fp)
-    4ea0:	e0bff917 	ldw	r2,-28(fp)
-    4ea4:	1000030e 	bge	r2,zero,4eb4 <open+0x84>
+    4ed8:	e13fff17 	ldw	r4,-4(fp)
+    4edc:	000533c0 	call	533c <alt_get_fd>
+    4ee0:	e0bffe15 	stw	r2,-8(fp)
+    4ee4:	e0bffe17 	ldw	r2,-8(fp)
+    4ee8:	1000030e 	bge	r2,zero,4ef8 <open+0x84>
     {
       status = index;
-    4ea8:	e0bff917 	ldw	r2,-28(fp)
-    4eac:	e0bffa15 	stw	r2,-24(fp)
-    4eb0:	00002506 	br	4f48 <open+0x118>
+    4eec:	e0bffe17 	ldw	r2,-8(fp)
+    4ef0:	e0bffd15 	stw	r2,-12(fp)
+    4ef4:	00002606 	br	4f90 <open+0x11c>
     }
     else
     {
       fd = &alt_fd_list[index];
-    4eb4:	01400304 	movi	r5,12
-    4eb8:	e13ff917 	ldw	r4,-28(fp)
-    4ebc:	000311c0 	call	311c <__mulsi3>
-    4ec0:	1007883a 	mov	r3,r2
-    4ec4:	00800034 	movhi	r2,0
-    4ec8:	10982c04 	addi	r2,r2,24752
-    4ecc:	1885883a 	add	r2,r3,r2
-    4ed0:	e0bffc15 	stw	r2,-16(fp)
+    4ef8:	e0fffe17 	ldw	r3,-8(fp)
+    4efc:	1805883a 	mov	r2,r3
+    4f00:	1085883a 	add	r2,r2,r2
+    4f04:	10c5883a 	add	r2,r2,r3
+    4f08:	100490ba 	slli	r2,r2,2
+    4f0c:	00c00034 	movhi	r3,0
+    4f10:	18d80004 	addi	r3,r3,24576
+    4f14:	10c5883a 	add	r2,r2,r3
+    4f18:	e0bffb15 	stw	r2,-20(fp)
       fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK);
-    4ed4:	e0fffe17 	ldw	r3,-8(fp)
-    4ed8:	00900034 	movhi	r2,16384
-    4edc:	10bfffc4 	addi	r2,r2,-1
-    4ee0:	1886703a 	and	r3,r3,r2
-    4ee4:	e0bffc17 	ldw	r2,-16(fp)
-    4ee8:	10c00215 	stw	r3,8(r2)
+    4f1c:	e0fff917 	ldw	r3,-28(fp)
+    4f20:	00900034 	movhi	r2,16384
+    4f24:	10bfffc4 	addi	r2,r2,-1
+    4f28:	1886703a 	and	r3,r3,r2
+    4f2c:	e0bffb17 	ldw	r2,-20(fp)
+    4f30:	10c00215 	stw	r3,8(r2)
       
       /* If this is a device, ensure it isn't already locked */
 
       if (isafs || ((status = alt_file_locked (fd)) >= 0))
-    4eec:	e0bffb17 	ldw	r2,-20(fp)
-    4ef0:	1000051e 	bne	r2,zero,4f08 <open+0xd8>
-    4ef4:	e13ffc17 	ldw	r4,-16(fp)
-    4ef8:	0004d440 	call	4d44 <alt_file_locked>
-    4efc:	e0bffa15 	stw	r2,-24(fp)
-    4f00:	e0bffa17 	ldw	r2,-24(fp)
-    4f04:	10001016 	blt	r2,zero,4f48 <open+0x118>
+    4f34:	e0bffc17 	ldw	r2,-16(fp)
+    4f38:	1000051e 	bne	r2,zero,4f50 <open+0xdc>
+    4f3c:	e13ffb17 	ldw	r4,-20(fp)
+    4f40:	0004d980 	call	4d98 <alt_file_locked>
+    4f44:	e0bffd15 	stw	r2,-12(fp)
+    4f48:	e0bffd17 	ldw	r2,-12(fp)
+    4f4c:	10001016 	blt	r2,zero,4f90 <open+0x11c>
         /* 
          * If the device or filesystem provides an open() callback function,
          * call it now to perform any device/filesystem specific operations.
          */
     
         status = (dev->open) ? dev->open(fd, file, flags, mode): 0;
-    4f08:	e0bff817 	ldw	r2,-32(fp)
-    4f0c:	10800317 	ldw	r2,12(r2)
-    4f10:	10000826 	beq	r2,zero,4f34 <open+0x104>
-    4f14:	e0bff817 	ldw	r2,-32(fp)
-    4f18:	10800317 	ldw	r2,12(r2)
-    4f1c:	e1ffff17 	ldw	r7,-4(fp)
-    4f20:	e1bffe17 	ldw	r6,-8(fp)
-    4f24:	e17ffd17 	ldw	r5,-12(fp)
-    4f28:	e13ffc17 	ldw	r4,-16(fp)
-    4f2c:	103ee83a 	callr	r2
-    4f30:	00000106 	br	4f38 <open+0x108>
-    4f34:	0005883a 	mov	r2,zero
-    4f38:	e0bffa15 	stw	r2,-24(fp)
-    4f3c:	00000206 	br	4f48 <open+0x118>
+    4f50:	e0bfff17 	ldw	r2,-4(fp)
+    4f54:	10800317 	ldw	r2,12(r2)
+    4f58:	10000826 	beq	r2,zero,4f7c <open+0x108>
+    4f5c:	e0bfff17 	ldw	r2,-4(fp)
+    4f60:	10800317 	ldw	r2,12(r2)
+    4f64:	e1fff817 	ldw	r7,-32(fp)
+    4f68:	e1bff917 	ldw	r6,-28(fp)
+    4f6c:	e17ffa17 	ldw	r5,-24(fp)
+    4f70:	e13ffb17 	ldw	r4,-20(fp)
+    4f74:	103ee83a 	callr	r2
+    4f78:	00000106 	br	4f80 <open+0x10c>
+    4f7c:	0005883a 	mov	r2,zero
+    4f80:	e0bffd15 	stw	r2,-12(fp)
+    4f84:	00000206 	br	4f90 <open+0x11c>
       }
     }
   }
   else
   {
     status = -ENODEV;
-    4f40:	00bffb44 	movi	r2,-19
-    4f44:	e0bffa15 	stw	r2,-24(fp)
+    4f88:	00bffb44 	movi	r2,-19
+    4f8c:	e0bffd15 	stw	r2,-12(fp)
   }
 
   /* Allocation failed, so clean up and return an error */ 
 
   if (status < 0)
-    4f48:	e0bffa17 	ldw	r2,-24(fp)
-    4f4c:	1000090e 	bge	r2,zero,4f74 <open+0x144>
+    4f90:	e0bffd17 	ldw	r2,-12(fp)
+    4f94:	1000090e 	bge	r2,zero,4fbc <open+0x148>
   {
     alt_release_fd (index);  
-    4f50:	e13ff917 	ldw	r4,-28(fp)
-    4f54:	00037a40 	call	37a4 <alt_release_fd>
+    4f98:	e13ffe17 	ldw	r4,-8(fp)
+    4f9c:	00037e80 	call	37e8 <alt_release_fd>
     ALT_ERRNO = -status;
-    4f58:	0004d080 	call	4d08 <alt_get_errno>
-    4f5c:	1007883a 	mov	r3,r2
-    4f60:	e0bffa17 	ldw	r2,-24(fp)
-    4f64:	0085c83a 	sub	r2,zero,r2
-    4f68:	18800015 	stw	r2,0(r3)
+    4fa0:	0004d5c0 	call	4d5c <alt_get_errno>
+    4fa4:	1007883a 	mov	r3,r2
+    4fa8:	e0bffd17 	ldw	r2,-12(fp)
+    4fac:	0085c83a 	sub	r2,zero,r2
+    4fb0:	18800015 	stw	r2,0(r3)
     return -1;
-    4f6c:	00bfffc4 	movi	r2,-1
-    4f70:	00000106 	br	4f78 <open+0x148>
+    4fb4:	00bfffc4 	movi	r2,-1
+    4fb8:	00000106 	br	4fc0 <open+0x14c>
   }
   
   /* return the reference upon success */
 
   return index;
-    4f74:	e0bff917 	ldw	r2,-28(fp)
+    4fbc:	e0bffe17 	ldw	r2,-8(fp)
 }
-    4f78:	e037883a 	mov	sp,fp
-    4f7c:	dfc00117 	ldw	ra,4(sp)
-    4f80:	df000017 	ldw	fp,0(sp)
-    4f84:	dec00204 	addi	sp,sp,8
-    4f88:	f800283a 	ret
+    4fc0:	e037883a 	mov	sp,fp
+    4fc4:	dfc00117 	ldw	ra,4(sp)
+    4fc8:	df000017 	ldw	fp,0(sp)
+    4fcc:	dec00204 	addi	sp,sp,8
+    4fd0:	f800283a 	ret
 
-00004f8c <alt_alarm_stop>:
+00004fd4 <alt_alarm_stop>:
  * alarms. Alternatively an alarm can unregister itself by returning zero when 
  * the alarm executes.
  */
 
 void alt_alarm_stop (alt_alarm* alarm)
 {
-    4f8c:	defffa04 	addi	sp,sp,-24
-    4f90:	df000515 	stw	fp,20(sp)
-    4f94:	df000504 	addi	fp,sp,20
-    4f98:	e13fff15 	stw	r4,-4(fp)
-static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
-       alt_irq_disable_all (void)
-{
-  alt_irq_context context;
-
+    4fd4:	defffa04 	addi	sp,sp,-24
+    4fd8:	df000515 	stw	fp,20(sp)
+    4fdc:	df000504 	addi	fp,sp,20
+    4fe0:	e13ffb15 	stw	r4,-20(fp)
   NIOS2_READ_STATUS (context);
-    4f9c:	0005303a 	rdctl	r2,status
-    4fa0:	e0bffc15 	stw	r2,-16(fp)
-
+    4fe4:	0005303a 	rdctl	r2,status
+    4fe8:	e0bffc15 	stw	r2,-16(fp)
   NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
-    4fa4:	e0fffc17 	ldw	r3,-16(fp)
-    4fa8:	00bfff84 	movi	r2,-2
-    4fac:	1884703a 	and	r2,r3,r2
-    4fb0:	1001703a 	wrctl	status,r2
-  
+    4fec:	e0fffc17 	ldw	r3,-16(fp)
+    4ff0:	00bfff84 	movi	r2,-2
+    4ff4:	1884703a 	and	r2,r3,r2
+    4ff8:	1001703a 	wrctl	status,r2
   return context;
-    4fb4:	e0bffc17 	ldw	r2,-16(fp)
+    4ffc:	e0bffc17 	ldw	r2,-16(fp)
   alt_irq_context irq_context;
 
   irq_context = alt_irq_disable_all();
-    4fb8:	e0bffb15 	stw	r2,-20(fp)
+    5000:	e0bfff15 	stw	r2,-4(fp)
   alt_llist_remove (&alarm->llist);
-    4fbc:	e0bfff17 	ldw	r2,-4(fp)
-    4fc0:	e0bffd15 	stw	r2,-12(fp)
+    5004:	e0bffb17 	ldw	r2,-20(fp)
+    5008:	e0bffd15 	stw	r2,-12(fp)
  * input argument is the element to remove.
  */
      
 static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry)
 {
   entry->next->previous = entry->previous;
-    4fc4:	e0bffd17 	ldw	r2,-12(fp)
-    4fc8:	10800017 	ldw	r2,0(r2)
-    4fcc:	e0fffd17 	ldw	r3,-12(fp)
-    4fd0:	18c00117 	ldw	r3,4(r3)
-    4fd4:	10c00115 	stw	r3,4(r2)
+    500c:	e0bffd17 	ldw	r2,-12(fp)
+    5010:	10800017 	ldw	r2,0(r2)
+    5014:	e0fffd17 	ldw	r3,-12(fp)
+    5018:	18c00117 	ldw	r3,4(r3)
+    501c:	10c00115 	stw	r3,4(r2)
   entry->previous->next = entry->next;
-    4fd8:	e0bffd17 	ldw	r2,-12(fp)
-    4fdc:	10800117 	ldw	r2,4(r2)
-    4fe0:	e0fffd17 	ldw	r3,-12(fp)
-    4fe4:	18c00017 	ldw	r3,0(r3)
-    4fe8:	10c00015 	stw	r3,0(r2)
+    5020:	e0bffd17 	ldw	r2,-12(fp)
+    5024:	10800117 	ldw	r2,4(r2)
+    5028:	e0fffd17 	ldw	r3,-12(fp)
+    502c:	18c00017 	ldw	r3,0(r3)
+    5030:	10c00015 	stw	r3,0(r2)
   /* 
    * Set the entry to point to itself, so that any further calls to
    * alt_llist_remove() are harmless.
    */
 
   entry->previous = entry;
-    4fec:	e0bffd17 	ldw	r2,-12(fp)
-    4ff0:	e0fffd17 	ldw	r3,-12(fp)
-    4ff4:	10c00115 	stw	r3,4(r2)
+    5034:	e0bffd17 	ldw	r2,-12(fp)
+    5038:	e0fffd17 	ldw	r3,-12(fp)
+    503c:	10c00115 	stw	r3,4(r2)
   entry->next     = entry;
-    4ff8:	e0bffd17 	ldw	r2,-12(fp)
-    4ffc:	e0fffd17 	ldw	r3,-12(fp)
-    5000:	10c00015 	stw	r3,0(r2)
-    5004:	e0bffb17 	ldw	r2,-20(fp)
-    5008:	e0bffe15 	stw	r2,-8(fp)
-  status &= ~NIOS2_STATUS_PIE_MSK;
-  status |= (context & NIOS2_STATUS_PIE_MSK);
-  
-  NIOS2_WRITE_STATUS (status);
-#else
+    5040:	e0bffd17 	ldw	r2,-12(fp)
+    5044:	e0fffd17 	ldw	r3,-12(fp)
+    5048:	10c00015 	stw	r3,0(r2)
+} 
+    504c:	0001883a 	nop
+    5050:	e0bfff17 	ldw	r2,-4(fp)
+    5054:	e0bffe15 	stw	r2,-8(fp)
   NIOS2_WRITE_STATUS (context);
-    500c:	e0bffe17 	ldw	r2,-8(fp)
-    5010:	1001703a 	wrctl	status,r2
+    5058:	e0bffe17 	ldw	r2,-8(fp)
+    505c:	1001703a 	wrctl	status,r2
+}
+    5060:	0001883a 	nop
   alt_irq_enable_all (irq_context);
 }
-    5014:	0001883a 	nop
-    5018:	e037883a 	mov	sp,fp
-    501c:	df000017 	ldw	fp,0(sp)
-    5020:	dec00104 	addi	sp,sp,4
-    5024:	f800283a 	ret
+    5064:	0001883a 	nop
+    5068:	e037883a 	mov	sp,fp
+    506c:	df000017 	ldw	fp,0(sp)
+    5070:	dec00104 	addi	sp,sp,4
+    5074:	f800283a 	ret
 
-00005028 <alt_tick>:
+00005078 <alt_tick>:
  * 
  * alt_tick() is expected to run at interrupt level.
  */
 
 void alt_tick (void)
 {
-    5028:	defffb04 	addi	sp,sp,-20
-    502c:	dfc00415 	stw	ra,16(sp)
-    5030:	df000315 	stw	fp,12(sp)
-    5034:	df000304 	addi	fp,sp,12
+    5078:	defffb04 	addi	sp,sp,-20
+    507c:	dfc00415 	stw	ra,16(sp)
+    5080:	df000315 	stw	fp,12(sp)
+    5084:	df000304 	addi	fp,sp,12
   alt_alarm* next;
   alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next;
-    5038:	d0a00c17 	ldw	r2,-32720(gp)
-    503c:	e0bffd15 	stw	r2,-12(fp)
+    5088:	d0a00c17 	ldw	r2,-32720(gp)
+    508c:	e0bfff15 	stw	r2,-4(fp)
 
   alt_u32    next_callback;
 
   /* update the tick counter */
 
   _alt_nticks++;
-    5040:	d0a01717 	ldw	r2,-32676(gp)
-    5044:	10800044 	addi	r2,r2,1
-    5048:	d0a01715 	stw	r2,-32676(gp)
+    5090:	d0a01717 	ldw	r2,-32676(gp)
+    5094:	10800044 	addi	r2,r2,1
+    5098:	d0a01715 	stw	r2,-32676(gp)
 
   /* process the registered callbacks */
 
   while (alarm != (alt_alarm*) &alt_alarm_list)
-    504c:	00002e06 	br	5108 <alt_tick+0xe0>
+    509c:	00002e06 	br	5158 <alt_tick+0xe0>
   {
     next = (alt_alarm*) alarm->llist.next;
-    5050:	e0bffd17 	ldw	r2,-12(fp)
-    5054:	10800017 	ldw	r2,0(r2)
-    5058:	e0bffe15 	stw	r2,-8(fp)
+    50a0:	e0bfff17 	ldw	r2,-4(fp)
+    50a4:	10800017 	ldw	r2,0(r2)
+    50a8:	e0bffe15 	stw	r2,-8(fp)
     /* 
      * Upon the tick-counter rolling over it is safe to clear the 
      * roll-over flag; once the flag is cleared this (or subsequnt)
      * tick events are enabled to generate an alarm event. 
      */
     if ((alarm->rollover) && (_alt_nticks == 0))
-    505c:	e0bffd17 	ldw	r2,-12(fp)
-    5060:	10800403 	ldbu	r2,16(r2)
-    5064:	10803fcc 	andi	r2,r2,255
-    5068:	10000426 	beq	r2,zero,507c <alt_tick+0x54>
-    506c:	d0a01717 	ldw	r2,-32676(gp)
-    5070:	1000021e 	bne	r2,zero,507c <alt_tick+0x54>
+    50ac:	e0bfff17 	ldw	r2,-4(fp)
+    50b0:	10800403 	ldbu	r2,16(r2)
+    50b4:	10803fcc 	andi	r2,r2,255
+    50b8:	10000426 	beq	r2,zero,50cc <alt_tick+0x54>
+    50bc:	d0a01717 	ldw	r2,-32676(gp)
+    50c0:	1000021e 	bne	r2,zero,50cc <alt_tick+0x54>
     {
       alarm->rollover = 0;
-    5074:	e0bffd17 	ldw	r2,-12(fp)
-    5078:	10000405 	stb	zero,16(r2)
+    50c4:	e0bfff17 	ldw	r2,-4(fp)
+    50c8:	10000405 	stb	zero,16(r2)
     }
     
     /* if the alarm period has expired, make the callback */    
     if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0))
-    507c:	e0bffd17 	ldw	r2,-12(fp)
-    5080:	10800217 	ldw	r2,8(r2)
-    5084:	d0e01717 	ldw	r3,-32676(gp)
-    5088:	18801d36 	bltu	r3,r2,5100 <alt_tick+0xd8>
-    508c:	e0bffd17 	ldw	r2,-12(fp)
-    5090:	10800403 	ldbu	r2,16(r2)
-    5094:	10803fcc 	andi	r2,r2,255
-    5098:	1000191e 	bne	r2,zero,5100 <alt_tick+0xd8>
+    50cc:	e0bfff17 	ldw	r2,-4(fp)
+    50d0:	10800217 	ldw	r2,8(r2)
+    50d4:	d0e01717 	ldw	r3,-32676(gp)
+    50d8:	18801d36 	bltu	r3,r2,5150 <alt_tick+0xd8>
+    50dc:	e0bfff17 	ldw	r2,-4(fp)
+    50e0:	10800403 	ldbu	r2,16(r2)
+    50e4:	10803fcc 	andi	r2,r2,255
+    50e8:	1000191e 	bne	r2,zero,5150 <alt_tick+0xd8>
     {
       next_callback = alarm->callback (alarm->context);
-    509c:	e0bffd17 	ldw	r2,-12(fp)
-    50a0:	10800317 	ldw	r2,12(r2)
-    50a4:	e0fffd17 	ldw	r3,-12(fp)
-    50a8:	18c00517 	ldw	r3,20(r3)
-    50ac:	1809883a 	mov	r4,r3
-    50b0:	103ee83a 	callr	r2
-    50b4:	e0bfff15 	stw	r2,-4(fp)
+    50ec:	e0bfff17 	ldw	r2,-4(fp)
+    50f0:	10800317 	ldw	r2,12(r2)
+    50f4:	e0ffff17 	ldw	r3,-4(fp)
+    50f8:	18c00517 	ldw	r3,20(r3)
+    50fc:	1809883a 	mov	r4,r3
+    5100:	103ee83a 	callr	r2
+    5104:	e0bffd15 	stw	r2,-12(fp)
 
       /* deactivate the alarm if the return value is zero */
 
       if (next_callback == 0)
-    50b8:	e0bfff17 	ldw	r2,-4(fp)
-    50bc:	1000031e 	bne	r2,zero,50cc <alt_tick+0xa4>
+    5108:	e0bffd17 	ldw	r2,-12(fp)
+    510c:	1000031e 	bne	r2,zero,511c <alt_tick+0xa4>
       {
         alt_alarm_stop (alarm);
-    50c0:	e13ffd17 	ldw	r4,-12(fp)
-    50c4:	0004f8c0 	call	4f8c <alt_alarm_stop>
-    50c8:	00000d06 	br	5100 <alt_tick+0xd8>
+    5110:	e13fff17 	ldw	r4,-4(fp)
+    5114:	0004fd40 	call	4fd4 <alt_alarm_stop>
+    5118:	00000d06 	br	5150 <alt_tick+0xd8>
       }
       else
       {
         alarm->time += next_callback;
-    50cc:	e0bffd17 	ldw	r2,-12(fp)
-    50d0:	10c00217 	ldw	r3,8(r2)
-    50d4:	e0bfff17 	ldw	r2,-4(fp)
-    50d8:	1887883a 	add	r3,r3,r2
-    50dc:	e0bffd17 	ldw	r2,-12(fp)
-    50e0:	10c00215 	stw	r3,8(r2)
+    511c:	e0bfff17 	ldw	r2,-4(fp)
+    5120:	10c00217 	ldw	r3,8(r2)
+    5124:	e0bffd17 	ldw	r2,-12(fp)
+    5128:	1887883a 	add	r3,r3,r2
+    512c:	e0bfff17 	ldw	r2,-4(fp)
+    5130:	10c00215 	stw	r3,8(r2)
         /* 
          * If the desired alarm time causes a roll-over, set the rollover
          * flag. This will prevent the subsequent tick event from causing
          * an alarm too early.
          */
         if(alarm->time < _alt_nticks)
-    50e4:	e0bffd17 	ldw	r2,-12(fp)
-    50e8:	10c00217 	ldw	r3,8(r2)
-    50ec:	d0a01717 	ldw	r2,-32676(gp)
-    50f0:	1880032e 	bgeu	r3,r2,5100 <alt_tick+0xd8>
+    5134:	e0bfff17 	ldw	r2,-4(fp)
+    5138:	10c00217 	ldw	r3,8(r2)
+    513c:	d0a01717 	ldw	r2,-32676(gp)
+    5140:	1880032e 	bgeu	r3,r2,5150 <alt_tick+0xd8>
         {
           alarm->rollover = 1;
-    50f4:	e0bffd17 	ldw	r2,-12(fp)
-    50f8:	00c00044 	movi	r3,1
-    50fc:	10c00405 	stb	r3,16(r2)
+    5144:	e0bfff17 	ldw	r2,-4(fp)
+    5148:	00c00044 	movi	r3,1
+    514c:	10c00405 	stb	r3,16(r2)
         }
       }
     }
     alarm = next;
-    5100:	e0bffe17 	ldw	r2,-8(fp)
-    5104:	e0bffd15 	stw	r2,-12(fp)
-
-  _alt_nticks++;
-
-  /* process the registered callbacks */
-
+    5150:	e0bffe17 	ldw	r2,-8(fp)
+    5154:	e0bfff15 	stw	r2,-4(fp)
   while (alarm != (alt_alarm*) &alt_alarm_list)
-    5108:	e0fffd17 	ldw	r3,-12(fp)
-    510c:	d0a00c04 	addi	r2,gp,-32720
-    5110:	18bfcf1e 	bne	r3,r2,5050 <__alt_data_end+0xfffe5050>
+    5158:	e0ffff17 	ldw	r3,-4(fp)
+    515c:	d0a00c04 	addi	r2,gp,-32720
+    5160:	18bfcf1e 	bne	r3,r2,50a0 <alt_tick+0x28>
 
   /* 
    * Update the operating system specific timer facilities.
    */
 
   ALT_OS_TIME_TICK();
-    5114:	0001883a 	nop
+    5164:	0001883a 	nop
 }
-    5118:	0001883a 	nop
-    511c:	e037883a 	mov	sp,fp
-    5120:	dfc00117 	ldw	ra,4(sp)
-    5124:	df000017 	ldw	fp,0(sp)
-    5128:	dec00204 	addi	sp,sp,8
-    512c:	f800283a 	ret
+    5168:	0001883a 	nop
+    516c:	e037883a 	mov	sp,fp
+    5170:	dfc00117 	ldw	ra,4(sp)
+    5174:	df000017 	ldw	fp,0(sp)
+    5178:	dec00204 	addi	sp,sp,8
+    517c:	f800283a 	ret
 
-00005130 <altera_nios2_gen2_irq_init>:
+00005180 <altera_nios2_gen2_irq_init>:
 /*
  * To initialize the internal interrupt controller, just clear the IENABLE
  * register so that all possible IRQs are disabled.
  */
 void altera_nios2_gen2_irq_init(void) 
 {
-    5130:	deffff04 	addi	sp,sp,-4
-    5134:	df000015 	stw	fp,0(sp)
-    5138:	d839883a 	mov	fp,sp
+    5180:	deffff04 	addi	sp,sp,-4
+    5184:	df000015 	stw	fp,0(sp)
+    5188:	d839883a 	mov	fp,sp
     NIOS2_WRITE_IENABLE(0);
-    513c:	000170fa 	wrctl	ienable,zero
+    518c:	000170fa 	wrctl	ienable,zero
 }
-    5140:	0001883a 	nop
-    5144:	e037883a 	mov	sp,fp
-    5148:	df000017 	ldw	fp,0(sp)
-    514c:	dec00104 	addi	sp,sp,4
-    5150:	f800283a 	ret
+    5190:	0001883a 	nop
+    5194:	e037883a 	mov	sp,fp
+    5198:	df000017 	ldw	fp,0(sp)
+    519c:	dec00104 	addi	sp,sp,4
+    51a0:	f800283a 	ret
 
-00005154 <alt_find_dev>:
+000051a4 <alt_find_dev>:
  * "name" must be an exact match for the devices registered name for a match to
  * be found.
  */
  
 alt_dev* alt_find_dev(const char* name, alt_llist* llist)
 {
-    5154:	defffa04 	addi	sp,sp,-24
-    5158:	dfc00515 	stw	ra,20(sp)
-    515c:	df000415 	stw	fp,16(sp)
-    5160:	df000404 	addi	fp,sp,16
-    5164:	e13ffe15 	stw	r4,-8(fp)
-    5168:	e17fff15 	stw	r5,-4(fp)
+    51a4:	defffa04 	addi	sp,sp,-24
+    51a8:	dfc00515 	stw	ra,20(sp)
+    51ac:	df000415 	stw	fp,16(sp)
+    51b0:	df000404 	addi	fp,sp,16
+    51b4:	e13ffd15 	stw	r4,-12(fp)
+    51b8:	e17ffc15 	stw	r5,-16(fp)
   alt_dev* next = (alt_dev*) llist->next;
-    516c:	e0bfff17 	ldw	r2,-4(fp)
-    5170:	10800017 	ldw	r2,0(r2)
-    5174:	e0bffc15 	stw	r2,-16(fp)
+    51bc:	e0bffc17 	ldw	r2,-16(fp)
+    51c0:	10800017 	ldw	r2,0(r2)
+    51c4:	e0bfff15 	stw	r2,-4(fp)
   alt_32 len;
 
   len  = strlen(name) + 1;
-    5178:	e13ffe17 	ldw	r4,-8(fp)
-    517c:	000040c0 	call	40c <strlen>
-    5180:	10800044 	addi	r2,r2,1
-    5184:	e0bffd15 	stw	r2,-12(fp)
+    51c8:	e13ffd17 	ldw	r4,-12(fp)
+    51cc:	00003d80 	call	3d8 <strlen>
+    51d0:	10800044 	addi	r2,r2,1
+    51d4:	e0bffe15 	stw	r2,-8(fp)
   /*
    * Check each list entry in turn, until a match is found, or we reach the
    * end of the list (i.e. next winds up pointing back to the list head).
    */ 
 
   while (next != (alt_dev*) llist)
-    5188:	00000d06 	br	51c0 <alt_find_dev+0x6c>
+    51d8:	00000d06 	br	5210 <alt_find_dev+0x6c>
     /* 
      * memcmp() is used here rather than strcmp() in order to reduce the size
      * of the executable.
      */
 
     if (!memcmp (next->name, name, len))
-    518c:	e0bffc17 	ldw	r2,-16(fp)
-    5190:	10800217 	ldw	r2,8(r2)
-    5194:	e0fffd17 	ldw	r3,-12(fp)
-    5198:	180d883a 	mov	r6,r3
-    519c:	e17ffe17 	ldw	r5,-8(fp)
-    51a0:	1009883a 	mov	r4,r2
-    51a4:	00054980 	call	5498 <memcmp>
-    51a8:	1000021e 	bne	r2,zero,51b4 <alt_find_dev+0x60>
+    51dc:	e0bfff17 	ldw	r2,-4(fp)
+    51e0:	10800217 	ldw	r2,8(r2)
+    51e4:	e0fffe17 	ldw	r3,-8(fp)
+    51e8:	180d883a 	mov	r6,r3
+    51ec:	e17ffd17 	ldw	r5,-12(fp)
+    51f0:	1009883a 	mov	r4,r2
+    51f4:	00054d40 	call	54d4 <memcmp>
+    51f8:	1000021e 	bne	r2,zero,5204 <alt_find_dev+0x60>
     {
       /* match found */
 
       return next;
-    51ac:	e0bffc17 	ldw	r2,-16(fp)
-    51b0:	00000706 	br	51d0 <alt_find_dev+0x7c>
+    51fc:	e0bfff17 	ldw	r2,-4(fp)
+    5200:	00000706 	br	5220 <alt_find_dev+0x7c>
     }
     next = (alt_dev*) next->llist.next;
-    51b4:	e0bffc17 	ldw	r2,-16(fp)
-    51b8:	10800017 	ldw	r2,0(r2)
-    51bc:	e0bffc15 	stw	r2,-16(fp)
-  /*
-   * Check each list entry in turn, until a match is found, or we reach the
-   * end of the list (i.e. next winds up pointing back to the list head).
-   */ 
-
+    5204:	e0bfff17 	ldw	r2,-4(fp)
+    5208:	10800017 	ldw	r2,0(r2)
+    520c:	e0bfff15 	stw	r2,-4(fp)
   while (next != (alt_dev*) llist)
-    51c0:	e0fffc17 	ldw	r3,-16(fp)
-    51c4:	e0bfff17 	ldw	r2,-4(fp)
-    51c8:	18bff01e 	bne	r3,r2,518c <__alt_data_end+0xfffe518c>
-    next = (alt_dev*) next->llist.next;
+    5210:	e0ffff17 	ldw	r3,-4(fp)
+    5214:	e0bffc17 	ldw	r2,-16(fp)
+    5218:	18bff01e 	bne	r3,r2,51dc <alt_find_dev+0x38>
   }
   
   /* No match found */
   
   return NULL;
-    51cc:	0005883a 	mov	r2,zero
+    521c:	0005883a 	mov	r2,zero
 }
-    51d0:	e037883a 	mov	sp,fp
-    51d4:	dfc00117 	ldw	ra,4(sp)
-    51d8:	df000017 	ldw	fp,0(sp)
-    51dc:	dec00204 	addi	sp,sp,8
-    51e0:	f800283a 	ret
+    5220:	e037883a 	mov	sp,fp
+    5224:	dfc00117 	ldw	ra,4(sp)
+    5228:	df000017 	ldw	fp,0(sp)
+    522c:	dec00204 	addi	sp,sp,8
+    5230:	f800283a 	ret
 
-000051e4 <alt_find_file>:
+00005234 <alt_find_file>:
  * either '/' or '\0' is the prefix of the filename. For example the filename:
  * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". 
  */
  
 alt_dev* alt_find_file (const char* name)
 {
-    51e4:	defffb04 	addi	sp,sp,-20
-    51e8:	dfc00415 	stw	ra,16(sp)
-    51ec:	df000315 	stw	fp,12(sp)
-    51f0:	df000304 	addi	fp,sp,12
-    51f4:	e13fff15 	stw	r4,-4(fp)
+    5234:	defffb04 	addi	sp,sp,-20
+    5238:	dfc00415 	stw	ra,16(sp)
+    523c:	df000315 	stw	fp,12(sp)
+    5240:	df000304 	addi	fp,sp,12
+    5244:	e13ffd15 	stw	r4,-12(fp)
   alt_dev* next = (alt_dev*) alt_fs_list.next;   
-    51f8:	d0a00417 	ldw	r2,-32752(gp)
-    51fc:	e0bffd15 	stw	r2,-12(fp)
+    5248:	d0a00417 	ldw	r2,-32752(gp)
+    524c:	e0bfff15 	stw	r2,-4(fp)
   /*
    * Check each list entry in turn, until a match is found, or we reach the
    * end of the list (i.e. next winds up pointing back to the list head).
    */ 
  
   while (next != (alt_dev*) &alt_fs_list)
-    5200:	00003106 	br	52c8 <alt_find_file+0xe4>
+    5250:	00003106 	br	5318 <alt_find_file+0xe4>
   {
     len = strlen(next->name);
-    5204:	e0bffd17 	ldw	r2,-12(fp)
-    5208:	10800217 	ldw	r2,8(r2)
-    520c:	1009883a 	mov	r4,r2
-    5210:	000040c0 	call	40c <strlen>
-    5214:	e0bffe15 	stw	r2,-8(fp)
+    5254:	e0bfff17 	ldw	r2,-4(fp)
+    5258:	10800217 	ldw	r2,8(r2)
+    525c:	1009883a 	mov	r4,r2
+    5260:	00003d80 	call	3d8 <strlen>
+    5264:	e0bffe15 	stw	r2,-8(fp)
     
     if (next->name[len-1] == '/')
-    5218:	e0bffd17 	ldw	r2,-12(fp)
-    521c:	10c00217 	ldw	r3,8(r2)
-    5220:	e0bffe17 	ldw	r2,-8(fp)
-    5224:	10bfffc4 	addi	r2,r2,-1
-    5228:	1885883a 	add	r2,r3,r2
-    522c:	10800003 	ldbu	r2,0(r2)
-    5230:	10803fcc 	andi	r2,r2,255
-    5234:	1080201c 	xori	r2,r2,128
-    5238:	10bfe004 	addi	r2,r2,-128
-    523c:	10800bd8 	cmpnei	r2,r2,47
-    5240:	1000031e 	bne	r2,zero,5250 <alt_find_file+0x6c>
+    5268:	e0bfff17 	ldw	r2,-4(fp)
+    526c:	10c00217 	ldw	r3,8(r2)
+    5270:	e0bffe17 	ldw	r2,-8(fp)
+    5274:	10bfffc4 	addi	r2,r2,-1
+    5278:	1885883a 	add	r2,r3,r2
+    527c:	10800003 	ldbu	r2,0(r2)
+    5280:	10803fcc 	andi	r2,r2,255
+    5284:	1080201c 	xori	r2,r2,128
+    5288:	10bfe004 	addi	r2,r2,-128
+    528c:	10800bd8 	cmpnei	r2,r2,47
+    5290:	1000031e 	bne	r2,zero,52a0 <alt_find_file+0x6c>
     {
       len -= 1;
-    5244:	e0bffe17 	ldw	r2,-8(fp)
-    5248:	10bfffc4 	addi	r2,r2,-1
-    524c:	e0bffe15 	stw	r2,-8(fp)
+    5294:	e0bffe17 	ldw	r2,-8(fp)
+    5298:	10bfffc4 	addi	r2,r2,-1
+    529c:	e0bffe15 	stw	r2,-8(fp)
     }
 
     if (((name[len] == '/') || (name[len] == '\0')) && 
-    5250:	e0bffe17 	ldw	r2,-8(fp)
-    5254:	e0ffff17 	ldw	r3,-4(fp)
-    5258:	1885883a 	add	r2,r3,r2
-    525c:	10800003 	ldbu	r2,0(r2)
-    5260:	10803fcc 	andi	r2,r2,255
-    5264:	1080201c 	xori	r2,r2,128
-    5268:	10bfe004 	addi	r2,r2,-128
-    526c:	10800be0 	cmpeqi	r2,r2,47
-    5270:	1000081e 	bne	r2,zero,5294 <alt_find_file+0xb0>
-    5274:	e0bffe17 	ldw	r2,-8(fp)
-    5278:	e0ffff17 	ldw	r3,-4(fp)
-    527c:	1885883a 	add	r2,r3,r2
-    5280:	10800003 	ldbu	r2,0(r2)
-    5284:	10803fcc 	andi	r2,r2,255
-    5288:	1080201c 	xori	r2,r2,128
-    528c:	10bfe004 	addi	r2,r2,-128
-    5290:	10000a1e 	bne	r2,zero,52bc <alt_find_file+0xd8>
+    52a0:	e0bffe17 	ldw	r2,-8(fp)
+    52a4:	e0fffd17 	ldw	r3,-12(fp)
+    52a8:	1885883a 	add	r2,r3,r2
+    52ac:	10800003 	ldbu	r2,0(r2)
+    52b0:	10803fcc 	andi	r2,r2,255
+    52b4:	1080201c 	xori	r2,r2,128
+    52b8:	10bfe004 	addi	r2,r2,-128
+    52bc:	10800be0 	cmpeqi	r2,r2,47
+    52c0:	1000081e 	bne	r2,zero,52e4 <alt_find_file+0xb0>
+    52c4:	e0bffe17 	ldw	r2,-8(fp)
+    52c8:	e0fffd17 	ldw	r3,-12(fp)
+    52cc:	1885883a 	add	r2,r3,r2
+    52d0:	10800003 	ldbu	r2,0(r2)
+    52d4:	10803fcc 	andi	r2,r2,255
+    52d8:	1080201c 	xori	r2,r2,128
+    52dc:	10bfe004 	addi	r2,r2,-128
+    52e0:	10000a1e 	bne	r2,zero,530c <alt_find_file+0xd8>
         !memcmp (next->name, name, len))
-    5294:	e0bffd17 	ldw	r2,-12(fp)
-    5298:	10800217 	ldw	r2,8(r2)
-    529c:	e0fffe17 	ldw	r3,-8(fp)
-    52a0:	180d883a 	mov	r6,r3
-    52a4:	e17fff17 	ldw	r5,-4(fp)
-    52a8:	1009883a 	mov	r4,r2
-    52ac:	00054980 	call	5498 <memcmp>
-    if (next->name[len-1] == '/')
-    {
-      len -= 1;
-    }
-
+    52e4:	e0bfff17 	ldw	r2,-4(fp)
+    52e8:	10800217 	ldw	r2,8(r2)
+    52ec:	e0fffe17 	ldw	r3,-8(fp)
+    52f0:	180d883a 	mov	r6,r3
+    52f4:	e17ffd17 	ldw	r5,-12(fp)
+    52f8:	1009883a 	mov	r4,r2
+    52fc:	00054d40 	call	54d4 <memcmp>
     if (((name[len] == '/') || (name[len] == '\0')) && 
-    52b0:	1000021e 	bne	r2,zero,52bc <alt_find_file+0xd8>
-        !memcmp (next->name, name, len))
+    5300:	1000021e 	bne	r2,zero,530c <alt_find_file+0xd8>
     {
       /* match found */
 
       return next;
-    52b4:	e0bffd17 	ldw	r2,-12(fp)
-    52b8:	00000706 	br	52d8 <alt_find_file+0xf4>
+    5304:	e0bfff17 	ldw	r2,-4(fp)
+    5308:	00000706 	br	5328 <alt_find_file+0xf4>
     }
     next = (alt_dev*) next->llist.next;
-    52bc:	e0bffd17 	ldw	r2,-12(fp)
-    52c0:	10800017 	ldw	r2,0(r2)
-    52c4:	e0bffd15 	stw	r2,-12(fp)
-  /*
-   * Check each list entry in turn, until a match is found, or we reach the
-   * end of the list (i.e. next winds up pointing back to the list head).
-   */ 
- 
+    530c:	e0bfff17 	ldw	r2,-4(fp)
+    5310:	10800017 	ldw	r2,0(r2)
+    5314:	e0bfff15 	stw	r2,-4(fp)
   while (next != (alt_dev*) &alt_fs_list)
-    52c8:	e0fffd17 	ldw	r3,-12(fp)
-    52cc:	d0a00404 	addi	r2,gp,-32752
-    52d0:	18bfcc1e 	bne	r3,r2,5204 <__alt_data_end+0xfffe5204>
-    next = (alt_dev*) next->llist.next;
+    5318:	e0ffff17 	ldw	r3,-4(fp)
+    531c:	d0a00404 	addi	r2,gp,-32752
+    5320:	18bfcc1e 	bne	r3,r2,5254 <alt_find_file+0x20>
   }
   
   /* No match found */
   
   return NULL;     
-    52d4:	0005883a 	mov	r2,zero
+    5324:	0005883a 	mov	r2,zero
 }
-    52d8:	e037883a 	mov	sp,fp
-    52dc:	dfc00117 	ldw	ra,4(sp)
-    52e0:	df000017 	ldw	fp,0(sp)
-    52e4:	dec00204 	addi	sp,sp,8
-    52e8:	f800283a 	ret
+    5328:	e037883a 	mov	sp,fp
+    532c:	dfc00117 	ldw	ra,4(sp)
+    5330:	df000017 	ldw	fp,0(sp)
+    5334:	dec00204 	addi	sp,sp,8
+    5338:	f800283a 	ret
 
-000052ec <alt_get_fd>:
+0000533c <alt_get_fd>:
  * the offset of the file descriptor within the file descriptor array). A
  * negative value indicates failure.
  */
 
 int alt_get_fd (alt_dev* dev)
 {
-    52ec:	defffa04 	addi	sp,sp,-24
-    52f0:	dfc00515 	stw	ra,20(sp)
-    52f4:	df000415 	stw	fp,16(sp)
-    52f8:	dc000315 	stw	r16,12(sp)
-    52fc:	df000404 	addi	fp,sp,16
-    5300:	e13ffe15 	stw	r4,-8(fp)
+    533c:	defffc04 	addi	sp,sp,-16
+    5340:	df000315 	stw	fp,12(sp)
+    5344:	df000304 	addi	fp,sp,12
+    5348:	e13ffd15 	stw	r4,-12(fp)
   alt_32 i;
   int rc = -EMFILE;
-    5304:	00bffa04 	movi	r2,-24
-    5308:	e0bffd15 	stw	r2,-12(fp)
+    534c:	00bffa04 	movi	r2,-24
+    5350:	e0bffe15 	stw	r2,-8(fp)
    * indicates the highest file descriptor ever allocated. This is used to
    * improve efficency when searching the file descriptor list, and 
    * therefore reduce contention on the alt_fd_list_lock semaphore. 
    */
 
   for (i = 0; i < ALT_MAX_FD; i++)
-    530c:	e03ffc15 	stw	zero,-16(fp)
-    5310:	00001d06 	br	5388 <alt_get_fd+0x9c>
+    5354:	e03fff15 	stw	zero,-4(fp)
+    5358:	00001d06 	br	53d0 <alt_get_fd+0x94>
   {
     if (!alt_fd_list[i].dev)
-    5314:	04000034 	movhi	r16,0
-    5318:	84182c04 	addi	r16,r16,24752
-    531c:	e0bffc17 	ldw	r2,-16(fp)
-    5320:	01400304 	movi	r5,12
-    5324:	1009883a 	mov	r4,r2
-    5328:	000311c0 	call	311c <__mulsi3>
-    532c:	8085883a 	add	r2,r16,r2
-    5330:	10800017 	ldw	r2,0(r2)
-    5334:	1000111e 	bne	r2,zero,537c <alt_get_fd+0x90>
+    535c:	e0ffff17 	ldw	r3,-4(fp)
+    5360:	1805883a 	mov	r2,r3
+    5364:	1085883a 	add	r2,r2,r2
+    5368:	10c5883a 	add	r2,r2,r3
+    536c:	100490ba 	slli	r2,r2,2
+    5370:	00c00034 	movhi	r3,0
+    5374:	10c7883a 	add	r3,r2,r3
+    5378:	18980017 	ldw	r2,24576(r3)
+    537c:	1000111e 	bne	r2,zero,53c4 <alt_get_fd+0x88>
     {
       alt_fd_list[i].dev = dev;
-    5338:	04000034 	movhi	r16,0
-    533c:	84182c04 	addi	r16,r16,24752
-    5340:	e0bffc17 	ldw	r2,-16(fp)
-    5344:	01400304 	movi	r5,12
-    5348:	1009883a 	mov	r4,r2
-    534c:	000311c0 	call	311c <__mulsi3>
-    5350:	8085883a 	add	r2,r16,r2
-    5354:	e0fffe17 	ldw	r3,-8(fp)
-    5358:	10c00015 	stw	r3,0(r2)
+    5380:	e0ffff17 	ldw	r3,-4(fp)
+    5384:	1805883a 	mov	r2,r3
+    5388:	1085883a 	add	r2,r2,r2
+    538c:	10c5883a 	add	r2,r2,r3
+    5390:	100490ba 	slli	r2,r2,2
+    5394:	e13ffd17 	ldw	r4,-12(fp)
+    5398:	00c00034 	movhi	r3,0
+    539c:	10c7883a 	add	r3,r2,r3
+    53a0:	19180015 	stw	r4,24576(r3)
       if (i > alt_max_fd)
-    535c:	d0e00817 	ldw	r3,-32736(gp)
-    5360:	e0bffc17 	ldw	r2,-16(fp)
-    5364:	1880020e 	bge	r3,r2,5370 <alt_get_fd+0x84>
+    53a4:	d0e00817 	ldw	r3,-32736(gp)
+    53a8:	e0bfff17 	ldw	r2,-4(fp)
+    53ac:	1880020e 	bge	r3,r2,53b8 <alt_get_fd+0x7c>
       {
         alt_max_fd = i;
-    5368:	e0bffc17 	ldw	r2,-16(fp)
-    536c:	d0a00815 	stw	r2,-32736(gp)
+    53b0:	e0bfff17 	ldw	r2,-4(fp)
+    53b4:	d0a00815 	stw	r2,-32736(gp)
       }
       rc = i;
-    5370:	e0bffc17 	ldw	r2,-16(fp)
-    5374:	e0bffd15 	stw	r2,-12(fp)
+    53b8:	e0bfff17 	ldw	r2,-4(fp)
+    53bc:	e0bffe15 	stw	r2,-8(fp)
       goto alt_get_fd_exit;
-    5378:	00000606 	br	5394 <alt_get_fd+0xa8>
-   * indicates the highest file descriptor ever allocated. This is used to
-   * improve efficency when searching the file descriptor list, and 
-   * therefore reduce contention on the alt_fd_list_lock semaphore. 
-   */
-
+    53c0:	00000706 	br	53e0 <alt_get_fd+0xa4>
   for (i = 0; i < ALT_MAX_FD; i++)
-    537c:	e0bffc17 	ldw	r2,-16(fp)
-    5380:	10800044 	addi	r2,r2,1
-    5384:	e0bffc15 	stw	r2,-16(fp)
-    5388:	e0bffc17 	ldw	r2,-16(fp)
-    538c:	10800810 	cmplti	r2,r2,32
-    5390:	103fe01e 	bne	r2,zero,5314 <__alt_data_end+0xfffe5314>
+    53c4:	e0bfff17 	ldw	r2,-4(fp)
+    53c8:	10800044 	addi	r2,r2,1
+    53cc:	e0bfff15 	stw	r2,-4(fp)
+    53d0:	e0bfff17 	ldw	r2,-4(fp)
+    53d4:	10800810 	cmplti	r2,r2,32
+    53d8:	103fe01e 	bne	r2,zero,535c <alt_get_fd+0x20>
+    }
+  }
+
+ alt_get_fd_exit:
+    53dc:	0001883a 	nop
    * file descriptor pool.
    */
 
   ALT_SEM_POST(alt_fd_list_lock);
 
   return rc;
-    5394:	e0bffd17 	ldw	r2,-12(fp)
+    53e0:	e0bffe17 	ldw	r2,-8(fp)
 }
-    5398:	e6ffff04 	addi	sp,fp,-4
-    539c:	dfc00217 	ldw	ra,8(sp)
-    53a0:	df000117 	ldw	fp,4(sp)
-    53a4:	dc000017 	ldw	r16,0(sp)
-    53a8:	dec00304 	addi	sp,sp,12
-    53ac:	f800283a 	ret
+    53e4:	e037883a 	mov	sp,fp
+    53e8:	df000017 	ldw	fp,0(sp)
+    53ec:	dec00104 	addi	sp,sp,4
+    53f0:	f800283a 	ret
 
-000053b0 <alt_exception_cause_generated_bad_addr>:
+000053f4 <alt_exception_cause_generated_bad_addr>:
  * Return: 1: BADADDR (bad_addr argument to handler) is valid
  *         0: BADADDR is not valid
  */
 int 
 alt_exception_cause_generated_bad_addr(alt_exception_cause cause)
 {
-    53b0:	defffe04 	addi	sp,sp,-8
-    53b4:	df000115 	stw	fp,4(sp)
-    53b8:	df000104 	addi	fp,sp,4
-    53bc:	e13fff15 	stw	r4,-4(fp)
-  switch (cause) {
-    53c0:	e0bfff17 	ldw	r2,-4(fp)
-    53c4:	10bffe84 	addi	r2,r2,-6
-    53c8:	10c00428 	cmpgeui	r3,r2,16
-    53cc:	18001a1e 	bne	r3,zero,5438 <alt_exception_cause_generated_bad_addr+0x88>
-    53d0:	100690ba 	slli	r3,r2,2
-    53d4:	00800034 	movhi	r2,0
-    53d8:	1094fa04 	addi	r2,r2,21480
-    53dc:	1885883a 	add	r2,r3,r2
-    53e0:	10800017 	ldw	r2,0(r2)
-    53e4:	1000683a 	jmp	r2
-    53e8:	00005428 	cmpgeui	zero,zero,336
-    53ec:	00005428 	cmpgeui	zero,zero,336
-    53f0:	00005438 	rdprs	zero,zero,336
-    53f4:	00005438 	rdprs	zero,zero,336
-    53f8:	00005438 	rdprs	zero,zero,336
-    53fc:	00005428 	cmpgeui	zero,zero,336
-    5400:	00005430 	cmpltui	zero,zero,336
-    5404:	00005438 	rdprs	zero,zero,336
-    5408:	00005428 	cmpgeui	zero,zero,336
-    540c:	00005428 	cmpgeui	zero,zero,336
-    5410:	00005438 	rdprs	zero,zero,336
-    5414:	00005428 	cmpgeui	zero,zero,336
-    5418:	00005430 	cmpltui	zero,zero,336
-    541c:	00005438 	rdprs	zero,zero,336
-    5420:	00005438 	rdprs	zero,zero,336
-    5424:	00005428 	cmpgeui	zero,zero,336
+    53f4:	defffe04 	addi	sp,sp,-8
+    53f8:	df000115 	stw	fp,4(sp)
+    53fc:	df000104 	addi	fp,sp,4
+    5400:	e13fff15 	stw	r4,-4(fp)
+    5404:	e0bfff17 	ldw	r2,-4(fp)
+    5408:	10bffe84 	addi	r2,r2,-6
+    540c:	10c00428 	cmpgeui	r3,r2,16
+    5410:	1800191e 	bne	r3,zero,5478 <alt_exception_cause_generated_bad_addr+0x84>
+    5414:	100690ba 	slli	r3,r2,2
+    5418:	00800034 	movhi	r2,0
+    541c:	1885883a 	add	r2,r3,r2
+    5420:	10950a17 	ldw	r2,21544(r2)
+    5424:	1000683a 	jmp	r2
+    5428:	00005468 	cmpgeui	zero,zero,337
+    542c:	00005468 	cmpgeui	zero,zero,337
+    5430:	00005478 	rdprs	zero,zero,337
+    5434:	00005478 	rdprs	zero,zero,337
+    5438:	00005478 	rdprs	zero,zero,337
+    543c:	00005468 	cmpgeui	zero,zero,337
+    5440:	00005470 	cmpltui	zero,zero,337
+    5444:	00005478 	rdprs	zero,zero,337
+    5448:	00005468 	cmpgeui	zero,zero,337
+    544c:	00005468 	cmpgeui	zero,zero,337
+    5450:	00005478 	rdprs	zero,zero,337
+    5454:	00005468 	cmpgeui	zero,zero,337
+    5458:	00005470 	cmpltui	zero,zero,337
+    545c:	00005478 	rdprs	zero,zero,337
+    5460:	00005478 	rdprs	zero,zero,337
+    5464:	00005468 	cmpgeui	zero,zero,337
   case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC:
   case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION:
   case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION:
   case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION:
   case NIOS2_EXCEPTION_ECC_DATA_ERR:
     return 1;
-    5428:	00800044 	movi	r2,1
-    542c:	00000306 	br	543c <alt_exception_cause_generated_bad_addr+0x8c>
+    5468:	00800044 	movi	r2,1
+    546c:	00000306 	br	547c <alt_exception_cause_generated_bad_addr+0x88>
 
   case NIOS2_EXCEPTION_TLB_MISS:
   case NIOS2_EXCEPTION_ECC_TLB_ERR:
     return 0;
-    5430:	0005883a 	mov	r2,zero
-    5434:	00000106 	br	543c <alt_exception_cause_generated_bad_addr+0x8c>
+    5470:	0005883a 	mov	r2,zero
+    5474:	00000106 	br	547c <alt_exception_cause_generated_bad_addr+0x88>
 
   default:
     return 0;
-    5438:	0005883a 	mov	r2,zero
+    5478:	0005883a 	mov	r2,zero
   }
 }
-    543c:	e037883a 	mov	sp,fp
-    5440:	df000017 	ldw	fp,0(sp)
-    5444:	dec00104 	addi	sp,sp,4
-    5448:	f800283a 	ret
+    547c:	e037883a 	mov	sp,fp
+    5480:	df000017 	ldw	fp,0(sp)
+    5484:	dec00104 	addi	sp,sp,4
+    5488:	f800283a 	ret
 
-0000544c <atexit>:
-    544c:	200b883a 	mov	r5,r4
-    5450:	000f883a 	mov	r7,zero
-    5454:	000d883a 	mov	r6,zero
-    5458:	0009883a 	mov	r4,zero
-    545c:	00055141 	jmpi	5514 <__register_exitproc>
+0000548c <atexit>:
+    548c:	200b883a 	mov	r5,r4
+    5490:	000f883a 	mov	r7,zero
+    5494:	000d883a 	mov	r6,zero
+    5498:	0009883a 	mov	r4,zero
+    549c:	000554c1 	jmpi	554c <__register_exitproc>
 
-00005460 <exit>:
-    5460:	defffe04 	addi	sp,sp,-8
-    5464:	000b883a 	mov	r5,zero
-    5468:	dc000015 	stw	r16,0(sp)
-    546c:	dfc00115 	stw	ra,4(sp)
-    5470:	2021883a 	mov	r16,r4
-    5474:	000562c0 	call	562c <__call_exitprocs>
-    5478:	00800034 	movhi	r2,0
-    547c:	109ca404 	addi	r2,r2,29328
-    5480:	11000017 	ldw	r4,0(r2)
-    5484:	20800f17 	ldw	r2,60(r4)
-    5488:	10000126 	beq	r2,zero,5490 <exit+0x30>
-    548c:	103ee83a 	callr	r2
-    5490:	8009883a 	mov	r4,r16
-    5494:	00057ac0 	call	57ac <_exit>
+000054a0 <exit>:
+    54a0:	defffe04 	addi	sp,sp,-8
+    54a4:	000b883a 	mov	r5,zero
+    54a8:	dc000015 	stw	r16,0(sp)
+    54ac:	dfc00115 	stw	ra,4(sp)
+    54b0:	2021883a 	mov	r16,r4
+    54b4:	00055dc0 	call	55dc <__call_exitprocs>
+    54b8:	00800034 	movhi	r2,0
+    54bc:	111c7817 	ldw	r4,29152(r2)
+    54c0:	20800f17 	ldw	r2,60(r4)
+    54c4:	10000126 	beq	r2,zero,54cc <exit+0x2c>
+    54c8:	103ee83a 	callr	r2
+    54cc:	8009883a 	mov	r4,r16
+    54d0:	00056fc0 	call	56fc <_exit>
 
-00005498 <memcmp>:
-    5498:	01c000c4 	movi	r7,3
-    549c:	3980192e 	bgeu	r7,r6,5504 <memcmp+0x6c>
-    54a0:	2144b03a 	or	r2,r4,r5
-    54a4:	11c4703a 	and	r2,r2,r7
-    54a8:	10000f26 	beq	r2,zero,54e8 <memcmp+0x50>
-    54ac:	20800003 	ldbu	r2,0(r4)
-    54b0:	28c00003 	ldbu	r3,0(r5)
-    54b4:	10c0151e 	bne	r2,r3,550c <memcmp+0x74>
-    54b8:	31bfff84 	addi	r6,r6,-2
-    54bc:	01ffffc4 	movi	r7,-1
-    54c0:	00000406 	br	54d4 <memcmp+0x3c>
-    54c4:	20800003 	ldbu	r2,0(r4)
-    54c8:	28c00003 	ldbu	r3,0(r5)
-    54cc:	31bfffc4 	addi	r6,r6,-1
-    54d0:	10c00e1e 	bne	r2,r3,550c <memcmp+0x74>
-    54d4:	21000044 	addi	r4,r4,1
-    54d8:	29400044 	addi	r5,r5,1
-    54dc:	31fff91e 	bne	r6,r7,54c4 <__alt_data_end+0xfffe54c4>
-    54e0:	0005883a 	mov	r2,zero
-    54e4:	f800283a 	ret
+000054d4 <memcmp>:
+    54d4:	30800130 	cmpltui	r2,r6,4
+    54d8:	10000b1e 	bne	r2,zero,5508 <memcmp+0x34>
+    54dc:	2144b03a 	or	r2,r4,r5
+    54e0:	108000cc 	andi	r2,r2,3
+    54e4:	1000171e 	bne	r2,zero,5544 <memcmp+0x70>
     54e8:	20c00017 	ldw	r3,0(r4)
     54ec:	28800017 	ldw	r2,0(r5)
-    54f0:	18bfee1e 	bne	r3,r2,54ac <__alt_data_end+0xfffe54ac>
+    54f0:	1880141e 	bne	r3,r2,5544 <memcmp+0x70>
     54f4:	31bfff04 	addi	r6,r6,-4
-    54f8:	21000104 	addi	r4,r4,4
-    54fc:	29400104 	addi	r5,r5,4
-    5500:	39bff936 	bltu	r7,r6,54e8 <__alt_data_end+0xfffe54e8>
-    5504:	303fe91e 	bne	r6,zero,54ac <__alt_data_end+0xfffe54ac>
-    5508:	003ff506 	br	54e0 <__alt_data_end+0xfffe54e0>
-    550c:	10c5c83a 	sub	r2,r2,r3
-    5510:	f800283a 	ret
+    54f8:	30800128 	cmpgeui	r2,r6,4
+    54fc:	21000104 	addi	r4,r4,4
+    5500:	29400104 	addi	r5,r5,4
+    5504:	103ff81e 	bne	r2,zero,54e8 <memcmp+0x14>
+    5508:	30bfffc4 	addi	r2,r6,-1
+    550c:	30000b26 	beq	r6,zero,553c <memcmp+0x68>
+    5510:	11800044 	addi	r6,r2,1
+    5514:	218d883a 	add	r6,r4,r6
+    5518:	00000106 	br	5520 <memcmp+0x4c>
+    551c:	21800726 	beq	r4,r6,553c <memcmp+0x68>
+    5520:	20800003 	ldbu	r2,0(r4)
+    5524:	28c00003 	ldbu	r3,0(r5)
+    5528:	21000044 	addi	r4,r4,1
+    552c:	29400044 	addi	r5,r5,1
+    5530:	10fffa26 	beq	r2,r3,551c <memcmp+0x48>
+    5534:	10c5c83a 	sub	r2,r2,r3
+    5538:	f800283a 	ret
+    553c:	0005883a 	mov	r2,zero
+    5540:	f800283a 	ret
+    5544:	30bfffc4 	addi	r2,r6,-1
+    5548:	003ff106 	br	5510 <memcmp+0x3c>
 
-00005514 <__register_exitproc>:
-    5514:	defffa04 	addi	sp,sp,-24
-    5518:	dc000315 	stw	r16,12(sp)
-    551c:	04000034 	movhi	r16,0
-    5520:	841ca404 	addi	r16,r16,29328
-    5524:	80c00017 	ldw	r3,0(r16)
-    5528:	dc400415 	stw	r17,16(sp)
-    552c:	dfc00515 	stw	ra,20(sp)
-    5530:	18805217 	ldw	r2,328(r3)
-    5534:	2023883a 	mov	r17,r4
-    5538:	10003726 	beq	r2,zero,5618 <__register_exitproc+0x104>
-    553c:	10c00117 	ldw	r3,4(r2)
-    5540:	010007c4 	movi	r4,31
-    5544:	20c00e16 	blt	r4,r3,5580 <__register_exitproc+0x6c>
-    5548:	1a000044 	addi	r8,r3,1
-    554c:	8800221e 	bne	r17,zero,55d8 <__register_exitproc+0xc4>
-    5550:	18c00084 	addi	r3,r3,2
-    5554:	18c7883a 	add	r3,r3,r3
-    5558:	18c7883a 	add	r3,r3,r3
-    555c:	12000115 	stw	r8,4(r2)
-    5560:	10c7883a 	add	r3,r2,r3
-    5564:	19400015 	stw	r5,0(r3)
-    5568:	0005883a 	mov	r2,zero
-    556c:	dfc00517 	ldw	ra,20(sp)
-    5570:	dc400417 	ldw	r17,16(sp)
-    5574:	dc000317 	ldw	r16,12(sp)
-    5578:	dec00604 	addi	sp,sp,24
-    557c:	f800283a 	ret
-    5580:	00800034 	movhi	r2,0
-    5584:	10800004 	addi	r2,r2,0
-    5588:	10002626 	beq	r2,zero,5624 <__register_exitproc+0x110>
-    558c:	01006404 	movi	r4,400
-    5590:	d9400015 	stw	r5,0(sp)
-    5594:	d9800115 	stw	r6,4(sp)
-    5598:	d9c00215 	stw	r7,8(sp)
-    559c:	00000000 	call	0 <__alt_mem_mem>
-    55a0:	d9400017 	ldw	r5,0(sp)
-    55a4:	d9800117 	ldw	r6,4(sp)
-    55a8:	d9c00217 	ldw	r7,8(sp)
-    55ac:	10001d26 	beq	r2,zero,5624 <__register_exitproc+0x110>
-    55b0:	81000017 	ldw	r4,0(r16)
-    55b4:	10000115 	stw	zero,4(r2)
-    55b8:	02000044 	movi	r8,1
-    55bc:	22405217 	ldw	r9,328(r4)
-    55c0:	0007883a 	mov	r3,zero
-    55c4:	12400015 	stw	r9,0(r2)
-    55c8:	20805215 	stw	r2,328(r4)
-    55cc:	10006215 	stw	zero,392(r2)
-    55d0:	10006315 	stw	zero,396(r2)
-    55d4:	883fde26 	beq	r17,zero,5550 <__alt_data_end+0xfffe5550>
-    55d8:	18c9883a 	add	r4,r3,r3
-    55dc:	2109883a 	add	r4,r4,r4
-    55e0:	1109883a 	add	r4,r2,r4
-    55e4:	21802215 	stw	r6,136(r4)
-    55e8:	01800044 	movi	r6,1
-    55ec:	12406217 	ldw	r9,392(r2)
-    55f0:	30cc983a 	sll	r6,r6,r3
-    55f4:	4992b03a 	or	r9,r9,r6
-    55f8:	12406215 	stw	r9,392(r2)
-    55fc:	21c04215 	stw	r7,264(r4)
-    5600:	01000084 	movi	r4,2
-    5604:	893fd21e 	bne	r17,r4,5550 <__alt_data_end+0xfffe5550>
-    5608:	11006317 	ldw	r4,396(r2)
-    560c:	218cb03a 	or	r6,r4,r6
-    5610:	11806315 	stw	r6,396(r2)
-    5614:	003fce06 	br	5550 <__alt_data_end+0xfffe5550>
-    5618:	18805304 	addi	r2,r3,332
-    561c:	18805215 	stw	r2,328(r3)
-    5620:	003fc606 	br	553c <__alt_data_end+0xfffe553c>
-    5624:	00bfffc4 	movi	r2,-1
-    5628:	003fd006 	br	556c <__alt_data_end+0xfffe556c>
+0000554c <__register_exitproc>:
+    554c:	00800034 	movhi	r2,0
+    5550:	10dc7817 	ldw	r3,29152(r2)
+    5554:	18805217 	ldw	r2,328(r3)
+    5558:	10001726 	beq	r2,zero,55b8 <__register_exitproc+0x6c>
+    555c:	10c00117 	ldw	r3,4(r2)
+    5560:	1a000808 	cmpgei	r8,r3,32
+    5564:	40001b1e 	bne	r8,zero,55d4 <__register_exitproc+0x88>
+    5568:	20000b26 	beq	r4,zero,5598 <__register_exitproc+0x4c>
+    556c:	181090ba 	slli	r8,r3,2
+    5570:	02400044 	movi	r9,1
+    5574:	48d2983a 	sll	r9,r9,r3
+    5578:	1211883a 	add	r8,r2,r8
+    557c:	41802215 	stw	r6,136(r8)
+    5580:	11806217 	ldw	r6,392(r2)
+    5584:	21000098 	cmpnei	r4,r4,2
+    5588:	324cb03a 	or	r6,r6,r9
+    558c:	11806215 	stw	r6,392(r2)
+    5590:	41c04215 	stw	r7,264(r8)
+    5594:	20000b26 	beq	r4,zero,55c4 <__register_exitproc+0x78>
+    5598:	19000084 	addi	r4,r3,2
+    559c:	200890ba 	slli	r4,r4,2
+    55a0:	18c00044 	addi	r3,r3,1
+    55a4:	10c00115 	stw	r3,4(r2)
+    55a8:	1105883a 	add	r2,r2,r4
+    55ac:	11400015 	stw	r5,0(r2)
+    55b0:	0005883a 	mov	r2,zero
+    55b4:	f800283a 	ret
+    55b8:	18805304 	addi	r2,r3,332
+    55bc:	18805215 	stw	r2,328(r3)
+    55c0:	003fe606 	br	555c <__register_exitproc+0x10>
+    55c4:	11006317 	ldw	r4,396(r2)
+    55c8:	2252b03a 	or	r9,r4,r9
+    55cc:	12406315 	stw	r9,396(r2)
+    55d0:	003ff106 	br	5598 <__register_exitproc+0x4c>
+    55d4:	00bfffc4 	movi	r2,-1
+    55d8:	f800283a 	ret
 
-0000562c <__call_exitprocs>:
-    562c:	defff504 	addi	sp,sp,-44
-    5630:	df000915 	stw	fp,36(sp)
-    5634:	dd400615 	stw	r21,24(sp)
-    5638:	dc800315 	stw	r18,12(sp)
-    563c:	dfc00a15 	stw	ra,40(sp)
-    5640:	ddc00815 	stw	r23,32(sp)
-    5644:	dd800715 	stw	r22,28(sp)
-    5648:	dd000515 	stw	r20,20(sp)
-    564c:	dcc00415 	stw	r19,16(sp)
-    5650:	dc400215 	stw	r17,8(sp)
-    5654:	dc000115 	stw	r16,4(sp)
-    5658:	d9000015 	stw	r4,0(sp)
-    565c:	2839883a 	mov	fp,r5
-    5660:	04800044 	movi	r18,1
-    5664:	057fffc4 	movi	r21,-1
-    5668:	00800034 	movhi	r2,0
-    566c:	109ca404 	addi	r2,r2,29328
-    5670:	12000017 	ldw	r8,0(r2)
-    5674:	45005217 	ldw	r20,328(r8)
-    5678:	44c05204 	addi	r19,r8,328
-    567c:	a0001c26 	beq	r20,zero,56f0 <__call_exitprocs+0xc4>
-    5680:	a0800117 	ldw	r2,4(r20)
-    5684:	15ffffc4 	addi	r23,r2,-1
-    5688:	b8000d16 	blt	r23,zero,56c0 <__call_exitprocs+0x94>
-    568c:	14000044 	addi	r16,r2,1
-    5690:	8421883a 	add	r16,r16,r16
-    5694:	8421883a 	add	r16,r16,r16
-    5698:	84402004 	addi	r17,r16,128
-    569c:	a463883a 	add	r17,r20,r17
-    56a0:	a421883a 	add	r16,r20,r16
-    56a4:	e0001e26 	beq	fp,zero,5720 <__call_exitprocs+0xf4>
-    56a8:	80804017 	ldw	r2,256(r16)
-    56ac:	e0801c26 	beq	fp,r2,5720 <__call_exitprocs+0xf4>
-    56b0:	bdffffc4 	addi	r23,r23,-1
-    56b4:	843fff04 	addi	r16,r16,-4
-    56b8:	8c7fff04 	addi	r17,r17,-4
-    56bc:	bd7ff91e 	bne	r23,r21,56a4 <__alt_data_end+0xfffe56a4>
-    56c0:	00800034 	movhi	r2,0
-    56c4:	10800004 	addi	r2,r2,0
-    56c8:	10000926 	beq	r2,zero,56f0 <__call_exitprocs+0xc4>
-    56cc:	a0800117 	ldw	r2,4(r20)
-    56d0:	1000301e 	bne	r2,zero,5794 <__call_exitprocs+0x168>
-    56d4:	a0800017 	ldw	r2,0(r20)
-    56d8:	10003226 	beq	r2,zero,57a4 <__call_exitprocs+0x178>
-    56dc:	a009883a 	mov	r4,r20
-    56e0:	98800015 	stw	r2,0(r19)
-    56e4:	00000000 	call	0 <__alt_mem_mem>
-    56e8:	9d000017 	ldw	r20,0(r19)
-    56ec:	a03fe41e 	bne	r20,zero,5680 <__alt_data_end+0xfffe5680>
-    56f0:	dfc00a17 	ldw	ra,40(sp)
-    56f4:	df000917 	ldw	fp,36(sp)
-    56f8:	ddc00817 	ldw	r23,32(sp)
-    56fc:	dd800717 	ldw	r22,28(sp)
-    5700:	dd400617 	ldw	r21,24(sp)
-    5704:	dd000517 	ldw	r20,20(sp)
-    5708:	dcc00417 	ldw	r19,16(sp)
-    570c:	dc800317 	ldw	r18,12(sp)
-    5710:	dc400217 	ldw	r17,8(sp)
-    5714:	dc000117 	ldw	r16,4(sp)
-    5718:	dec00b04 	addi	sp,sp,44
-    571c:	f800283a 	ret
-    5720:	a0800117 	ldw	r2,4(r20)
-    5724:	80c00017 	ldw	r3,0(r16)
-    5728:	10bfffc4 	addi	r2,r2,-1
-    572c:	15c01426 	beq	r2,r23,5780 <__call_exitprocs+0x154>
-    5730:	80000015 	stw	zero,0(r16)
-    5734:	183fde26 	beq	r3,zero,56b0 <__alt_data_end+0xfffe56b0>
-    5738:	95c8983a 	sll	r4,r18,r23
-    573c:	a0806217 	ldw	r2,392(r20)
-    5740:	a5800117 	ldw	r22,4(r20)
-    5744:	2084703a 	and	r2,r4,r2
-    5748:	10000b26 	beq	r2,zero,5778 <__call_exitprocs+0x14c>
-    574c:	a0806317 	ldw	r2,396(r20)
-    5750:	2088703a 	and	r4,r4,r2
-    5754:	20000c1e 	bne	r4,zero,5788 <__call_exitprocs+0x15c>
-    5758:	89400017 	ldw	r5,0(r17)
-    575c:	d9000017 	ldw	r4,0(sp)
-    5760:	183ee83a 	callr	r3
-    5764:	a0800117 	ldw	r2,4(r20)
-    5768:	15bfbf1e 	bne	r2,r22,5668 <__alt_data_end+0xfffe5668>
-    576c:	98800017 	ldw	r2,0(r19)
-    5770:	153fcf26 	beq	r2,r20,56b0 <__alt_data_end+0xfffe56b0>
-    5774:	003fbc06 	br	5668 <__alt_data_end+0xfffe5668>
-    5778:	183ee83a 	callr	r3
-    577c:	003ff906 	br	5764 <__alt_data_end+0xfffe5764>
-    5780:	a5c00115 	stw	r23,4(r20)
-    5784:	003feb06 	br	5734 <__alt_data_end+0xfffe5734>
-    5788:	89000017 	ldw	r4,0(r17)
-    578c:	183ee83a 	callr	r3
-    5790:	003ff406 	br	5764 <__alt_data_end+0xfffe5764>
-    5794:	a0800017 	ldw	r2,0(r20)
-    5798:	a027883a 	mov	r19,r20
-    579c:	1029883a 	mov	r20,r2
-    57a0:	003fb606 	br	567c <__alt_data_end+0xfffe567c>
-    57a4:	0005883a 	mov	r2,zero
-    57a8:	003ffb06 	br	5798 <__alt_data_end+0xfffe5798>
+000055dc <__call_exitprocs>:
+    55dc:	defff704 	addi	sp,sp,-36
+    55e0:	00800034 	movhi	r2,0
+    55e4:	dcc00315 	stw	r19,12(sp)
+    55e8:	14dc7817 	ldw	r19,29152(r2)
+    55ec:	dc800215 	stw	r18,8(sp)
+    55f0:	dfc00815 	stw	ra,32(sp)
+    55f4:	9c805217 	ldw	r18,328(r19)
+    55f8:	ddc00715 	stw	r23,28(sp)
+    55fc:	dd800615 	stw	r22,24(sp)
+    5600:	dd400515 	stw	r21,20(sp)
+    5604:	dd000415 	stw	r20,16(sp)
+    5608:	dc400115 	stw	r17,4(sp)
+    560c:	dc000015 	stw	r16,0(sp)
+    5610:	90001026 	beq	r18,zero,5654 <__call_exitprocs+0x78>
+    5614:	202b883a 	mov	r21,r4
+    5618:	282d883a 	mov	r22,r5
+    561c:	05000044 	movi	r20,1
+    5620:	94000117 	ldw	r16,4(r18)
+    5624:	847fffc4 	addi	r17,r16,-1
+    5628:	88000a16 	blt	r17,zero,5654 <__call_exitprocs+0x78>
+    562c:	84000044 	addi	r16,r16,1
+    5630:	802090ba 	slli	r16,r16,2
+    5634:	9421883a 	add	r16,r18,r16
+    5638:	b0001126 	beq	r22,zero,5680 <__call_exitprocs+0xa4>
+    563c:	80804017 	ldw	r2,256(r16)
+    5640:	15800f26 	beq	r2,r22,5680 <__call_exitprocs+0xa4>
+    5644:	8c7fffc4 	addi	r17,r17,-1
+    5648:	88bfffd8 	cmpnei	r2,r17,-1
+    564c:	843fff04 	addi	r16,r16,-4
+    5650:	103ff91e 	bne	r2,zero,5638 <__call_exitprocs+0x5c>
+    5654:	dfc00817 	ldw	ra,32(sp)
+    5658:	ddc00717 	ldw	r23,28(sp)
+    565c:	dd800617 	ldw	r22,24(sp)
+    5660:	dd400517 	ldw	r21,20(sp)
+    5664:	dd000417 	ldw	r20,16(sp)
+    5668:	dcc00317 	ldw	r19,12(sp)
+    566c:	dc800217 	ldw	r18,8(sp)
+    5670:	dc400117 	ldw	r17,4(sp)
+    5674:	dc000017 	ldw	r16,0(sp)
+    5678:	dec00904 	addi	sp,sp,36
+    567c:	f800283a 	ret
+    5680:	90800117 	ldw	r2,4(r18)
+    5684:	81800017 	ldw	r6,0(r16)
+    5688:	10bfffc4 	addi	r2,r2,-1
+    568c:	14401726 	beq	r2,r17,56ec <__call_exitprocs+0x110>
+    5690:	80000015 	stw	zero,0(r16)
+    5694:	303feb26 	beq	r6,zero,5644 <__call_exitprocs+0x68>
+    5698:	a446983a 	sll	r3,r20,r17
+    569c:	90806217 	ldw	r2,392(r18)
+    56a0:	95c00117 	ldw	r23,4(r18)
+    56a4:	1884703a 	and	r2,r3,r2
+    56a8:	1000081e 	bne	r2,zero,56cc <__call_exitprocs+0xf0>
+    56ac:	303ee83a 	callr	r6
+    56b0:	90c00117 	ldw	r3,4(r18)
+    56b4:	98805217 	ldw	r2,328(r19)
+    56b8:	1dc0011e 	bne	r3,r23,56c0 <__call_exitprocs+0xe4>
+    56bc:	90bfe126 	beq	r18,r2,5644 <__call_exitprocs+0x68>
+    56c0:	103fe426 	beq	r2,zero,5654 <__call_exitprocs+0x78>
+    56c4:	1025883a 	mov	r18,r2
+    56c8:	003fd506 	br	5620 <__call_exitprocs+0x44>
+    56cc:	90806317 	ldw	r2,396(r18)
+    56d0:	81002017 	ldw	r4,128(r16)
+    56d4:	1886703a 	and	r3,r3,r2
+    56d8:	1800061e 	bne	r3,zero,56f4 <__call_exitprocs+0x118>
+    56dc:	200b883a 	mov	r5,r4
+    56e0:	a809883a 	mov	r4,r21
+    56e4:	303ee83a 	callr	r6
+    56e8:	003ff106 	br	56b0 <__call_exitprocs+0xd4>
+    56ec:	94400115 	stw	r17,4(r18)
+    56f0:	003fe806 	br	5694 <__call_exitprocs+0xb8>
+    56f4:	303ee83a 	callr	r6
+    56f8:	003fed06 	br	56b0 <__call_exitprocs+0xd4>
 
-000057ac <_exit>:
+000056fc <_exit>:
  *
  * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h
  */
 
 void ALT_EXIT (int exit_code)
 {
-    57ac:	defffd04 	addi	sp,sp,-12
-    57b0:	df000215 	stw	fp,8(sp)
-    57b4:	df000204 	addi	fp,sp,8
-    57b8:	e13fff15 	stw	r4,-4(fp)
+    56fc:	defffd04 	addi	sp,sp,-12
+    5700:	df000215 	stw	fp,8(sp)
+    5704:	df000204 	addi	fp,sp,8
+    5708:	e13ffe15 	stw	r4,-8(fp)
   ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n");
   ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code);
   /* Stop all other threads */
 
   ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n");
   ALT_OS_STOP();
-    57bc:	0001883a 	nop
-    57c0:	e0bfff17 	ldw	r2,-4(fp)
-    57c4:	e0bffe15 	stw	r2,-8(fp)
+    570c:	0001883a 	nop
+    5710:	e0bffe17 	ldw	r2,-8(fp)
+    5714:	e0bfff15 	stw	r2,-4(fp)
 /*
  * Routine called on exit.
  */
 static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code)
 {
   register int r2 asm ("r2") = exit_code;
-    57c8:	e0bffe17 	ldw	r2,-8(fp)
+    5718:	e0bfff17 	ldw	r2,-4(fp)
   __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */
 
   __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA );
 
 #else /* !DEBUG_STUB */
   if (r2) {
-    57cc:	10000226 	beq	r2,zero,57d8 <_exit+0x2c>
+    571c:	10000226 	beq	r2,zero,5728 <_exit+0x2c>
     ALT_SIM_FAIL();
-    57d0:	002af070 	cmpltui	zero,zero,43969
-    57d4:	00000106 	br	57dc <_exit+0x30>
+    5720:	002af070 	cmpltui	zero,zero,43969
   } else {
     ALT_SIM_PASS();
-    57d8:	002af0b0 	cmpltui	zero,zero,43970
+  }
+#endif /* DEBUG_STUB */
+}
+    5724:	00000106 	br	572c <_exit+0x30>
+    ALT_SIM_PASS();
+    5728:	002af0b0 	cmpltui	zero,zero,43970
+}
+    572c:	0001883a 	nop
   ALT_SIM_HALT(exit_code);
 
   /* spin forever, since there's no where to go back to */
 
   ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n");
   while (1);
-    57dc:	003fff06 	br	57dc <__alt_data_end+0xfffe57dc>
+    5730:	003fff06 	br	5730 <_exit+0x34>
diff --git a/Top/software/semafor/altera_avalon_sem_regs.h b/Top/software/semafor/altera_avalon_sem_regs.h
index 7ea16aa..0a550fa 100644
--- a/Top/software/semafor/altera_avalon_sem_regs.h
+++ b/Top/software/semafor/altera_avalon_sem_regs.h
@@ -1,42 +1,42 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-*                                                                             *
-******************************************************************************/
-
-#ifndef __ALTERA_AVALON_SEM_REGS_H__
-#define __ALTERA_AVALON_SEM_REGS_H__
-
-#include <io.h>
-
-#define IORD_ALTERA_AVALON_SEM_CTL(base)            IORD(base, 0) 
-#define IOWR_ALTERA_AVALON_SEM_CTL(base, data)      IOWR(base, 0, data)
-
-#define IORD_ALTERA_AVALON_SEM_DIVSET(base)         IORD(base, 1) 
-#define IOWR_ALTERA_AVALON_SEM_DIVSET(base, data)   IOWR(base, 1, data)
-
-#endif /* __ALTERA_AVALON_SEM_REGS_H__ */
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_SEM_REGS_H__
+#define __ALTERA_AVALON_SEM_REGS_H__
+
+#include <io.h>
+
+#define IORD_ALTERA_AVALON_SEM_CTL(base)            IORD(base, 0) 
+#define IOWR_ALTERA_AVALON_SEM_CTL(base, data)      IOWR(base, 0, data)
+
+#define IORD_ALTERA_AVALON_SEM_DIVSET(base)         IORD(base, 1) 
+#define IOWR_ALTERA_AVALON_SEM_DIVSET(base, data)   IOWR(base, 1, data)
+
+#endif /* __ALTERA_AVALON_SEM_REGS_H__ */
diff --git a/Top/software/semafor/create-this-app b/Top/software/semafor/create-this-app
index 8c034cc..5da2e5e 100644
--- a/Top/software/semafor/create-this-app
+++ b/Top/software/semafor/create-this-app
@@ -1,114 +1,114 @@
-#!/bin/bash
-#
-# This script creates the blank_project application in this directory.
-
-
-BSP_DIR=../semafor_bsp
-QUARTUS_PROJECT_DIR=../../
-NIOS2_APP_GEN_ARGS="--elf-name semafor.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
-
-
-# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
-# This variable is required for the command line tools to execute correctly.
-if [ -z "${SOPC_KIT_NIOS2}" ]
-then
-    echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
-    exit 1
-fi
-
-
-# Also make sure that the APP has not been created already.  Check for
-# existence of Makefile in the app directory
-if [ -f ./Makefile ]
-then
-    echo Application has already been created!  Delete Makefile if you want to create a new application makefile
-    exit 1
-fi
-
-
-# We are selecting hal_default bsp because it supports this application.
-# Check to see if the hal_default has already been generated by checking for
-# existence of the public.mk file.  If not, we need to run
-# create-this-bsp file to generate the bsp.
-if [ ! -f ${BSP_DIR}/public.mk ]; then
-    # Since BSP doesn't exist, create the BSP
-    # Pass any command line arguments passed to this script to the BSP.
-    pushd ${BSP_DIR} >> /dev/null
-    ./create-this-bsp "$@" || {
-        echo "create-this-bsp failed"
-        exit 1
-    }
-    popd >> /dev/null
-fi
-
-
-# Don't run make if create-this-app script is called with --no-make arg
-SKIP_MAKE=
-while [ $# -gt 0 ]
-do
-  case "$1" in
-      --no-make)
-          SKIP_MAKE=1
-          ;;
-  esac
-  shift
-done
-
-
-# Now we also need to go copy the sources for this application to the
-# local directory.
-find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
-        echo "failed during copying example source files"
-        exit 1
-}
-
-find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
-        echo "failed copying readme file"
-}
-
-if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
-then
-        cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
-                echo "failed during copying project support files"
-                exit 1
-        }
-fi
-
-chmod -R +w . || {
-        echo "failed during changing file permissions"
-        exit 1
-}
-
-cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
-
-echo "create-this-app: Running \"${cmd}\""
-$cmd || {
-    echo "nios2-app-generate-makefile failed"
-    exit 1
-}
-
-if [ -z "$SKIP_MAKE" ]; then
-        cmd="make"
-
-        echo "create-this-app: Running \"$cmd\""
-        $cmd || {
-        echo "make failed"
-            exit 1
-        }
-
-        echo
-        echo "To download and run the application:"
-        echo "    1. Make sure the board is connected to the system."
-        echo "    2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
-        echo "    3. If you have a stdio device, run 'nios2-terminal' in a different shell."
-        echo "    4. Run 'make download-elf' from the application directory."
-        echo
-        echo "To debug the application:"
-        echo "    Import the project into Nios II Software Build Tools for Eclipse."
-        echo "    Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
-        echo
-        echo -e ""
-fi
-
-
-exit 0
+#!/bin/bash
+#
+# This script creates the blank_project application in this directory.
+
+
+BSP_DIR=../semafor_bsp
+QUARTUS_PROJECT_DIR=../../
+NIOS2_APP_GEN_ARGS="--elf-name semafor.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
+
+
+# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
+# This variable is required for the command line tools to execute correctly.
+if [ -z "${SOPC_KIT_NIOS2}" ]
+then
+    echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
+    exit 1
+fi
+
+
+# Also make sure that the APP has not been created already.  Check for
+# existence of Makefile in the app directory
+if [ -f ./Makefile ]
+then
+    echo Application has already been created!  Delete Makefile if you want to create a new application makefile
+    exit 1
+fi
+
+
+# We are selecting hal_default bsp because it supports this application.
+# Check to see if the hal_default has already been generated by checking for
+# existence of the public.mk file.  If not, we need to run
+# create-this-bsp file to generate the bsp.
+if [ ! -f ${BSP_DIR}/public.mk ]; then
+    # Since BSP doesn't exist, create the BSP
+    # Pass any command line arguments passed to this script to the BSP.
+    pushd ${BSP_DIR} >> /dev/null
+    ./create-this-bsp "$@" || {
+        echo "create-this-bsp failed"
+        exit 1
+    }
+    popd >> /dev/null
+fi
+
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+  case "$1" in
+      --no-make)
+          SKIP_MAKE=1
+          ;;
+  esac
+  shift
+done
+
+
+# Now we also need to go copy the sources for this application to the
+# local directory.
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
+        echo "failed during copying example source files"
+        exit 1
+}
+
+find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
+        echo "failed copying readme file"
+}
+
+if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
+then
+        cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
+                echo "failed during copying project support files"
+                exit 1
+        }
+fi
+
+chmod -R +w . || {
+        echo "failed during changing file permissions"
+        exit 1
+}
+
+cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
+
+echo "create-this-app: Running \"${cmd}\""
+$cmd || {
+    echo "nios2-app-generate-makefile failed"
+    exit 1
+}
+
+if [ -z "$SKIP_MAKE" ]; then
+        cmd="make"
+
+        echo "create-this-app: Running \"$cmd\""
+        $cmd || {
+        echo "make failed"
+            exit 1
+        }
+
+        echo
+        echo "To download and run the application:"
+        echo "    1. Make sure the board is connected to the system."
+        echo "    2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
+        echo "    3. If you have a stdio device, run 'nios2-terminal' in a different shell."
+        echo "    4. Run 'make download-elf' from the application directory."
+        echo
+        echo "To debug the application:"
+        echo "    Import the project into Nios II Software Build Tools for Eclipse."
+        echo "    Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
+        echo
+        echo -e ""
+fi
+
+
+exit 0
diff --git a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
index 5a8a51d..6ad99f3 100644
--- a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
+++ b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
@@ -1,5 +1,5 @@
 @0000 00400034
-@0001 08408C14
+@0001 08408914
 @0002 0800683A
 @0003 00000000
 @0004 00000000
@@ -36,7 +36,7 @@
 @0023 DF401215
 @0024 E8BFFF17
 @0025 E93FFF04
-@0026 00001D00
+@0026 00001C40
 @0027 1000021E
 @0028 EBFFFF04
 @0029 DBC01215
@@ -67,5596 +67,5596 @@
 @0042 DF000504
 @0043 0001883A
 @0044 0005313A
-@0045 E0BFFE15
-@0046 E0BFFE17
-@0047 E0BFFB15
+@0045 E0BFFC15
+@0046 E0BFFC17
+@0047 E0BFFF15
 @0048 E03FFD15
 @0049 00800044
-@004A E0BFFC15
-@004B E0FFFB17
-@004C E0BFFC17
+@004A E0BFFE15
+@004B E0FFFF17
+@004C E0BFFE17
 @004D 1884703A
-@004E 10001426
-@004F 00800034
-@0050 109CC704
-@0051 E0FFFD17
-@0052 180690FA
-@0053 10C5883A
-@0054 10C00017
-@0055 00800034
-@0056 109CC704
-@0057 E13FFD17
-@0058 200890FA
-@0059 1105883A
-@005A 10800104
-@005B 10800017
-@005C 1009883A
-@005D 183EE83A
-@005E 0001883A
-@005F 0005313A
-@0060 E0BFFF15
-@0061 E0BFFF17
-@0062 00000706
-@0063 E0BFFC17
-@0064 1085883A
-@0065 E0BFFC15
-@0066 E0BFFD17
-@0067 10800044
-@0068 E0BFFD15
-@0069 003FE106
-@006A E0BFFB15
-@006B E0BFFB17
-@006C 103FDB1E
-@006D 0001883A
-@006E 0001883A
-@006F E037883A
-@0070 DFC00117
-@0071 DF000017
-@0072 DEC00204
-@0073 F800283A
-@0074 DEFFFB04
-@0075 DFC00415
-@0076 DF000315
-@0077 DF000304
-@0078 E13FFF15
-@0079 00BFFFC4
-@007A E0BFFD15
-@007B E03FFE15
-@007C D0A01817
-@007D 10000726
-@007E D0A01817
-@007F E0FFFD17
-@0080 E1BFFE17
-@0081 E17FFF17
-@0082 1809883A
-@0083 103EE83A
-@0084 00000206
-@0085 003DA03A
-@0086 0005883A
-@0087 E037883A
-@0088 DFC00117
-@0089 DF000017
-@008A DEC00204
-@008B F800283A
-@008C 06C000B4
-@008D DEC00014
-@008E 06800034
-@008F D6BCA414
-@0090 00035A00
-@0091 003FFF06
-@0092 DEFFFA04
-@0093 DFC00515
-@0094 DF000415
-@0095 DF000404
-@0096 008000B4
-@0097 10840004
-@0098 E0BFFE15
-@0099 E03FFC15
-@009A 00002306
-@009B E03FFF15
-@009C 00800104
-@009D E0BFFD15
-@009E 00001406
-@009F E0FFFF17
-@00A0 00800804
-@00A1 1888983A
-@00A2 E0BFFD17
-@00A3 117FFFC4
-@00A4 00800034
-@00A5 1095F804
-@00A6 E0FFFC17
-@00A7 18C7883A
-@00A8 18C7883A
-@00A9 1947883A
-@00AA 18C7883A
-@00AB 18C7883A
-@00AC 10C5883A
-@00AD 10800017
-@00AE 2084B03A
-@00AF E0BFFF15
-@00B0 E0BFFD17
-@00B1 10BFFFC4
-@00B2 E0BFFD15
-@00B3 E0BFFD17
-@00B4 00BFEA16
-@00B5 E0BFFE17
-@00B6 E0FFFF17
-@00B7 10C00015
-@00B8 E0BFFE17
-@00B9 10800104
-@00BA E0BFFE15
-@00BB E0BFFC17
-@00BC 10800044
-@00BD E0BFFC15
-@00BE E0BFFC17
-@00BF 10800110
-@00C0 103FDA1E
-@00C1 00032580
-@00C2 0007883A
-@00C3 008000B4
-@00C4 10841904
-@00C5 10C00035
-@00C6 00C00044
-@00C7 008000B4
-@00C8 10841804
-@00C9 10C00035
-@00CA 01000034
-@00CB 21160804
-@00CC 00003F80
-@00CD 003FFF06
-@00CE DEFFF604
-@00CF DC000715
-@00D0 2021883A
-@00D1 2809883A
-@00D2 DC400815
-@00D3 DFC00915
-@00D4 2823883A
-@00D5 000040C0
-@00D6 10C00044
-@00D7 D8800115
-@00D8 00800034
-@00D9 10960A04
-@00DA D8800215
-@00DB 00800044
-@00DC D8800315
-@00DD 00800084
-@00DE DC400015
-@00DF D8C00615
-@00E0 DEC00415
-@00E1 D8800515
-@00E2 80000226
-@00E3 80800E17
-@00E4 10001426
-@00E5 81400217
-@00E6 2880030B
-@00E7 10C8000C
-@00E8 1800061E
-@00E9 29001917
-@00EA 00F7FFC4
-@00EB 10880014
-@00EC 20C6703A
-@00ED 2880030D
-@00EE 28C01915
-@00EF D9800404
-@00F0 8009883A
-@00F1 00008540
-@00F2 1000091E
-@00F3 00800284
-@00F4 DFC00917
-@00F5 DC400817
-@00F6 DC000717
-@00F7 DEC00A04
-@00F8 F800283A
-@00F9 8009883A
-@00FA 00008040
-@00FB 003FE906
-@00FC 00BFFFC4
-@00FD 003FF606
-@00FE 00800034
-@00FF 109CA504
-@0100 200B883A
-@0101 11000017
-@0102 00003381
-@0103 208000CC
-@0104 10002026
-@0105 20800007
-@0106 10002026
-@0107 2005883A
-@0108 00000206
-@0109 10C00007
-@010A 18001826
-@010B 10800044
-@010C 10C000CC
-@010D 183FFB1E
-@010E 10C00017
-@010F 01FFBFF4
-@0110 39FFBFC4
-@0111 00CA303A
-@0112 01A02074
-@0113 19C7883A
-@0114 31A02004
-@0115 1946703A
-@0116 1986703A
-@0117 1800091E
-@0118 10800104
-@0119 10C00017
-@011A 19CB883A
-@011B 00C6303A
-@011C 28C6703A
-@011D 1986703A
-@011E 183FF926
-@011F 00000106
-@0120 10800044
-@0121 10C00007
-@0122 183FFD1E
-@0123 1105C83A
-@0124 F800283A
-@0125 2005883A
-@0126 003FE706
-@0127 0005883A
-@0128 F800283A
-@0129 0005883A
-@012A F800283A
-@012B 01400034
-@012C 29491704
-@012D 0000DE01
-@012E DEFFF704
-@012F 00C00034
-@0130 DFC00815
-@0131 DDC00715
-@0132 DD800615
-@0133 DD400515
-@0134 DD000415
-@0135 DCC00315
-@0136 DC800215
-@0137 DC400115
-@0138 DC000015
-@0139 18C12B04
-@013A 24000117
-@013B 20C00F15
-@013C 2080BB04
-@013D 00C000C4
-@013E 20C0B915
-@013F 2080BA15
-@0140 2000B815
-@0141 05C00204
-@0142 00800104
-@0143 2025883A
-@0144 B80D883A
-@0145 81001704
-@0146 000B883A
-@0147 80000015
-@0148 80000115
-@0149 80000215
-@014A 8080030D
-@014B 80001915
-@014C 8000038D
-@014D 80000415
-@014E 80000515
-@014F 80000615
-@0150 0001A380
-@0151 05800034
-@0152 94400217
-@0153 05400034
-@0154 05000034
-@0155 04C00034
-@0156 B5884604
-@0157 AD485D04
-@0158 A5087C04
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diff --git a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
index 6bca76e..0a8aff7 100644
--- a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
+++ b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
@@ -3,167 +3,169 @@
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diff --git a/Top/software/semafor/mem_init/niosII_mem.hex b/Top/software/semafor/mem_init/niosII_mem.hex
index e301f0d..a8f8d7a 100644
--- a/Top/software/semafor/mem_init/niosII_mem.hex
+++ b/Top/software/semafor/mem_init/niosII_mem.hex
@@ -1,717 +1,717 @@
 :020000020000FC
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+:2000000000400034084089140800683A0000000000000000000000000000000000000000DD
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diff --git a/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do b/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
index 922670d..b4f3eb3 100644
--- a/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
+++ b/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
@@ -59,6 +59,6 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ps} {662 ps}
+WaveRestoreZoom {565752283 ps} {596447355 ps}
 
 run 800us
\ No newline at end of file
diff --git a/Top/software/semafor/readme.txt b/Top/software/semafor/readme.txt
index 57f6738..6d4e500 100644
--- a/Top/software/semafor/readme.txt
+++ b/Top/software/semafor/readme.txt
@@ -1,11 +1,11 @@
-This template is starting point for creating a project based on your custom C code.
-It will provide you a default project to which you can add your software files. To
-add files to a project, manually copy the file into the application directory (e.g. 
-using Windows Explorer), then right click on your application project and select 
-refresh.
-
-You can also add files to the project using the Nios II Software Build Tools for Eclipse import function. 
-Select File -> Import. 
-Expand General and select File System in the Import Window and click Next.
-Identify the appropriate source and destination directories.
-Check the files you want to add and click Finish.
+This template is starting point for creating a project based on your custom C code.
+It will provide you a default project to which you can add your software files. To
+add files to a project, manually copy the file into the application directory (e.g. 
+using Windows Explorer), then right click on your application project and select 
+refresh.
+
+You can also add files to the project using the Nios II Software Build Tools for Eclipse import function. 
+Select File -> Import. 
+Expand General and select File System in the Import Window and click Next.
+Identify the appropriate source and destination directories.
+Check the files you want to add and click Finish.
diff --git a/Top/software/semafor/sem.c b/Top/software/semafor/sem.c
index 77c8c88..0056410 100644
--- a/Top/software/semafor/sem.c
+++ b/Top/software/semafor/sem.c
@@ -6,10 +6,10 @@
 #define TIME_SETS	4
 #define TIME_STATES	4
 const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
-		{0x00000010, 0x00000010, 0x00000005, 0x00000010},
-		{0x00000010, 0x00000020, 0x00000010, 0x00000010},
-		{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
-		{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
+		{0x0ff00010, 0x0ff00010, 0x0ff00005, 0x00700010},
+		{0x0ff00010, 0x0ff00020, 0x0ff00010, 0x00700010},
+		{0x0ff000f1, 0x0ff000f1, 0x0ff000f1, 0x00700011},
+		{0x0ff000d1, 0x0ff000f1, 0x0ff000f1, 0x00700011}
 };
 
 int main()
@@ -21,19 +21,15 @@ int main()
 	//program divisors
 	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
 	for (i = 0; i < TIME_SETS; i++)	{
-		tmp = 0;
 		for (j = TIME_STATES; j > 0; j--) {
-			tmp = (tmp << 32) | divisors[i][j - 1];
+			*p = divisors[i][j - 1];
+			alt_dcache_flush();
+			p++;
 		}
-		*p = tmp;
-		p++;
 	}
-	//since we use pointers (cached data access) to write divisor RAM, 
-	//and not direct i/o access with IOWR, we need to flush cache
-	alt_dcache_flush();
 	
 	//select timeset and run semafor
-	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00);
+	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x02);
 	IOWR_ALTERA_AVALON_SEM_CTL(SEM_CTL_SLAVE_BASE,0x01);
 
 	printf("Ready\n");
diff --git a/Top/software/semafor/semafor.elf b/Top/software/semafor/semafor.elf
new file mode 100644
index 0000000..2398418
Binary files /dev/null and b/Top/software/semafor/semafor.elf differ
diff --git a/Top/software/semafor/semafor.map b/Top/software/semafor/semafor.map
new file mode 100644
index 0000000..1a37c0b
--- /dev/null
+++ b/Top/software/semafor/semafor.map
@@ -0,0 +1,1648 @@
+Archive member included to satisfy reference by file (symbol)
+
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+                              obj/default/sem.o (puts)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (strlen)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (__sinit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o) (__sfvwrite_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_fwalk)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-impure.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_global_impure_ptr)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_malloc_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memchr)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memcpy)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (memmove)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (memset)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (_realloc_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o) (_sbrk_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (__sread)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_write_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (__swsetup_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_close_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (_fclose_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o) (__sflush_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (_free_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-int_errno.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o) (errno)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_lseek_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o) (__smakebuf_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o) (_read_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o) (_fstat_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o) (_isatty_r)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o) (__divsi3)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o) (__mulsi3)
+../semafor_bsp//libhal_bsp.a(alt_close.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o) (close)
+../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
+                              obj/default/sem.o (alt_dcache_flush)
+../semafor_bsp//libhal_bsp.a(alt_dev.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_fd_list)
+../semafor_bsp//libhal_bsp.a(alt_errno.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_errno)
+../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o) (fstat)
+../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o) (isatty)
+../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o) (lseek)
+../semafor_bsp//libhal_bsp.a(alt_main.o)
+                              ../semafor_bsp//obj/HAL/src/crt0.o (alt_main)
+../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o) (__malloc_lock)
+../semafor_bsp//libhal_bsp.a(alt_read.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o) (read)
+../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_close.o) (alt_release_fd)
+../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o) (sbrk)
+../semafor_bsp//libhal_bsp.a(alt_write.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o) (write)
+../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (alt_irq_init)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read)
+../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write)
+../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init)
+../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start)
+../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert)
+../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (_do_ctors)
+../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (_do_dtors)
+../semafor_bsp//libhal_bsp.a(alt_iic.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register)
+../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic.o) (alt_iic_isr_register)
+../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (alt_io_redirect)
+../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry)
+../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o) (alt_irq)
+../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_iic.o) (alt_irq_active)
+../semafor_bsp//libhal_bsp.a(alt_open.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o) (open)
+../semafor_bsp//libhal_bsp.a(alt_tick.o)
+                              ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate)
+../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_sys_init.o) (altera_nios2_gen2_irq_init)
+../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o) (alt_exception)
+../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_find_dev)
+../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_find_file)
+../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_open.o) (alt_get_fd)
+../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o) (alt_instruction_exception_entry)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (atexit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_main.o) (exit)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+                              ../semafor_bsp//libhal_bsp.a(alt_find_dev.o) (memcmp)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o) (__register_exitproc)
+/opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o) (__call_exitprocs)
+../semafor_bsp//libhal_bsp.a(alt_exit.o)
+                              /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o) (_exit)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+reset            0x0000000000000000 0x0000000000000020
+mem              0x0000000000000020 0x000000000001ffe0
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD ../semafor_bsp//obj/HAL/src/crt0.o
+LOAD obj/default/sem.o
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libstdc++.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libm.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
+START GROUP
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
+LOAD ../semafor_bsp//libhal_bsp.a
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libm.a
+END GROUP
+LOAD /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a
+                0x0000000000000000                __alt_mem_mem = 0x0
+
+.entry          0x0000000000000000        0x0
+ *(.entry)
+ .entry         0x0000000000000000        0x0 ../semafor_bsp//obj/HAL/src/crt0.o
+                0x0000000000000000                __reset
+
+.exceptions     0x0000000000000020      0x204
+                [!provide]                        PROVIDE (__ram_exceptions_start = ABSOLUTE (.))
+                0x0000000000000020                . = ALIGN (0x20)
+ *(.irq)
+ *(.exceptions.entry.label)
+ .exceptions.entry.label
+                0x0000000000000020        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+                0x0000000000000020                alt_irq_entry
+ .exceptions.entry.label
+                0x0000000000000020        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+                0x0000000000000020                alt_exception
+ *(.exceptions.entry.user)
+ *(.exceptions.entry.ecc_fatal)
+ *(.exceptions.entry)
+ .exceptions.entry
+                0x0000000000000020       0x54 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ *(.exceptions.irqtest.user)
+ *(.exceptions.irqtest)
+ .exceptions.irqtest
+                0x0000000000000074       0x10 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ *(.exceptions.irqhandler.user)
+ *(.exceptions.irqhandler)
+ .exceptions.irqhandler
+                0x0000000000000084        0x4 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ *(.exceptions.irqreturn.user)
+ *(.exceptions.irqreturn)
+ .exceptions.irqreturn
+                0x0000000000000088        0x4 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ *(.exceptions.notirq.label)
+ .exceptions.notirq.label
+                0x000000000000008c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ *(.exceptions.notirq.user)
+ *(.exceptions.notirq)
+ .exceptions.notirq
+                0x000000000000008c        0x8 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ *(.exceptions.soft.user)
+ *(.exceptions.soft)
+ *(.exceptions.unknown.user)
+ *(.exceptions.unknown)
+ .exceptions.unknown
+                0x0000000000000094       0x14 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ *(.exceptions.exit.label)
+ .exceptions.exit.label
+                0x00000000000000a8        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .exceptions.exit.label
+                0x00000000000000a8        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ *(.exceptions.exit.user)
+ *(.exceptions.exit)
+ .exceptions.exit
+                0x00000000000000a8       0x54 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ *(.exceptions)
+ .exceptions    0x00000000000000fc       0xc8 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+                0x00000000000000fc                alt_irq_handler
+ .exceptions    0x00000000000001c4       0x60 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                0x00000000000001c4                alt_instruction_exception_entry
+                [!provide]                        PROVIDE (__ram_exceptions_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_exceptions_start = LOADADDR (.exceptions))
+
+.text           0x0000000000000224     0x5530
+                [!provide]                        PROVIDE (stext = ABSOLUTE (.))
+ *(.interp)
+ *(.hash)
+ *(.dynsym)
+ *(.dynstr)
+ *(.gnu.version)
+ *(.gnu.version_d)
+ *(.gnu.version_r)
+ *(.rel.init)
+ *(.rela.init)
+ *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rel.fini)
+ *(.rela.fini)
+ *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rel.ctors)
+ *(.rela.ctors)
+ *(.rel.dtors)
+ *(.rela.dtors)
+ *(.rel.got)
+ *(.rela.got)
+ *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ *(.rel.plt)
+ *(.rela.plt)
+ *(.rel.dyn)
+ *(.init)
+ *(.plt)
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ .text          0x0000000000000224       0x38 ../semafor_bsp//obj/HAL/src/crt0.o
+                0x0000000000000224                _start
+ .text          0x000000000000025c       0xc0 obj/default/sem.o
+                0x000000000000025c                main
+ .text          0x000000000000031c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .text._puts_r  0x000000000000031c       0xcc /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+                0x000000000000031c                _puts_r
+ .text.puts     0x00000000000003e8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+                0x00000000000003e8                puts
+ .text          0x00000000000003f8        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .text.strlen   0x00000000000003f8       0x98 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+                0x00000000000003f8                strlen
+ .text          0x0000000000000490        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .text.__fp_lock
+                0x0000000000000490        0x8 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .text._cleanup_r
+                0x0000000000000498        0xc /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000498                _cleanup_r
+ .text.__fp_unlock
+                0x00000000000004a4        0x8 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .text.__sinit.part.0
+                0x00000000000004ac      0x168 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .text.__sfmoreglue
+                0x0000000000000614       0x78 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000614                __sfmoreglue
+ .text.__sfp    0x000000000000068c      0x154 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x000000000000068c                __sfp
+ .text._cleanup
+                0x00000000000007e0       0x14 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x00000000000007e0                _cleanup
+ .text.__sinit  0x00000000000007f4       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x00000000000007f4                __sinit
+ .text.__sfp_lock_acquire
+                0x0000000000000804        0x4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000804                __sfp_lock_acquire
+ .text.__sfp_lock_release
+                0x0000000000000808        0x4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000808                __sfp_lock_release
+ .text.__sinit_lock_acquire
+                0x000000000000080c        0x4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x000000000000080c                __sinit_lock_acquire
+ .text.__sinit_lock_release
+                0x0000000000000810        0x4 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000810                __sinit_lock_release
+ .text.__fp_lock_all
+                0x0000000000000814       0x14 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000814                __fp_lock_all
+ .text.__fp_unlock_all
+                0x0000000000000828       0x14 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+                0x0000000000000828                __fp_unlock_all
+ .text          0x000000000000083c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .text.__sfvwrite_r
+                0x000000000000083c      0x4c8 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+                0x000000000000083c                __sfvwrite_r
+ .text          0x0000000000000d04        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .text._fwalk   0x0000000000000d04       0x98 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+                0x0000000000000d04                _fwalk
+ .text._fwalk_reent
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+ .text._malloc_r
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+ .text.memchr   0x0000000000001624       0xd0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+                0x0000000000001624                memchr
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+ .text.memcpy   0x00000000000016f4      0x100 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
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+ .text.memset   0x0000000000001920       0xf0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
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+ .text._realloc_r
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+ .text._write_r
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+ .text.__swsetup_r
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+ .text._close_r
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+ .text._fclose_r.part.0
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+ .text._fclose_r
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+                0x0000000000004630                alt_avalon_timer_sc_init
+ .text          0x00000000000046b4      0x134 ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+                0x00000000000046b4                alt_alarm_start
+ .text          0x00000000000047e8       0xe4 ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+                0x0000000000004824                alt_dev_llist_insert
+ .text          0x00000000000048cc       0x64 ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+                0x00000000000048cc                _do_ctors
+ .text          0x0000000000004930       0x64 ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+                0x0000000000004930                _do_dtors
+ .text          0x0000000000004994      0x1b0 ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+                0x0000000000004994                alt_ic_isr_register
+                0x00000000000049e4                alt_ic_irq_enable
+                0x0000000000004a6c                alt_ic_irq_disable
+                0x0000000000004af8                alt_ic_irq_enabled
+ .text          0x0000000000004b44       0xe8 ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+                0x0000000000004b44                alt_iic_isr_register
+ .text          0x0000000000004c2c      0x150 ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+                0x0000000000004d00                alt_io_redirect
+ .text          0x0000000000004d7c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .text          0x0000000000004d7c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .text          0x0000000000004d7c        0x0 ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+ .text          0x0000000000004d7c      0x278 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+                0x0000000000004e94                open
+ .text          0x0000000000004ff4      0x1ac ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+                0x0000000000004ff4                alt_alarm_stop
+                0x0000000000005098                alt_tick
+ .text          0x00000000000051a0       0x24 ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+                0x00000000000051a0                altera_nios2_gen2_irq_init
+ .text          0x00000000000051c4        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .text          0x00000000000051c4       0x90 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+                0x00000000000051c4                alt_find_dev
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+                0x0000000000005254                alt_find_file
+ .text          0x000000000000535c       0xb8 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+                0x000000000000535c                alt_get_fd
+ .text          0x0000000000005414       0x98 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                0x0000000000005414                alt_exception_cause_generated_bad_addr
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+ .text.atexit   0x00000000000054ac       0x14 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+                0x00000000000054ac                atexit
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+ .text.exit     0x00000000000054c0       0x34 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+                0x00000000000054c0                exit
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+ .text.memcmp   0x00000000000054f4       0x78 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+                0x00000000000054f4                memcmp
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+ .text.__register_exitproc
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+                0x000000000000556c                __register_exitproc
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+ .text.__call_exitprocs
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+                0x00000000000055fc                __call_exitprocs
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+                0x000000000000571c                _exit
+ *(.gnu.warning.*)
+ *(.fini)
+                [!provide]                        PROVIDE (__etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (etext = ABSOLUTE (.))
+ *(.eh_frame_hdr)
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+                [!provide]                        PROVIDE (__preinit_array_start = ABSOLUTE (.))
+ *(.preinit_array)
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+                [!provide]                        PROVIDE (__init_array_start = ABSOLUTE (.))
+ *(.init_array)
+                [!provide]                        PROVIDE (__init_array_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__fini_array_start = ABSOLUTE (.))
+ *(.fini_array)
+                [!provide]                        PROVIDE (__fini_array_end = ABSOLUTE (.))
+ *(.eh_frame)
+ *(.gcc_except_table .gcc_except_table.*)
+ *(.dynamic)
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+ *(.ctors)
+ *(SORT_BY_NAME(.ctors.*))
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+                0x0000000000005754                PROVIDE (__DTOR_LIST__ = ABSOLUTE (.))
+ *(.dtors)
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+ *(.jcr)
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+
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+                [!provide]                        PROVIDE (__ram_rodata_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_rodata_start = LOADADDR (.rodata))
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+.rwdata         0x00000000000057cc     0x1a6c
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+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .bss           0x000000000000738c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .bss           0x000000000000738c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .bss           0x000000000000738c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .bss           0x000000000000738c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .bss           0x000000000000738c        0x0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+ .bss           0x000000000000738c        0x0 ../semafor_bsp//libhal_bsp.a(alt_exit.o)
+ *(COMMON)
+                0x000000000000738c                . = ALIGN (0x4)
+                0x000000000000738c                __bss_end = ABSOLUTE (.)
+
+.mem            0x000000000000738c        0x0
+                [!provide]                        PROVIDE (_alt_partition_mem_start = ABSOLUTE (.))
+ *(.mem .mem. mem.*)
+                0x000000000000738c                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_mem_end = ABSOLUTE (.))
+                0x000000000000738c                _end = ABSOLUTE (.)
+                0x000000000000738c                end = ABSOLUTE (.)
+                0x000000000000738c                __alt_stack_base = ABSOLUTE (.)
+                [!provide]                        PROVIDE (_alt_partition_mem_load_addr = LOADADDR (.mem))
+
+.stab
+ *(.stab)
+
+.stabstr
+ *(.stabstr)
+
+.stab.excl
+ *(.stab.excl)
+
+.stab.exclstr
+ *(.stab.exclstr)
+
+.stab.index
+ *(.stab.index)
+
+.stab.indexstr
+ *(.stab.indexstr)
+
+.comment        0x0000000000000000       0x2d
+ *(.comment)
+ .comment       0x0000000000000000       0x2d obj/default/sem.o
+                                         0x2e (size before relaxing)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-impure.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-writer.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-int_errno.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_close.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dcache_flush.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dev.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_errno.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_fstat.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_isatty.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_lseek.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_main.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_malloc_lock.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_read.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_release_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_sbrk.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_write.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_sys_init.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_open.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .comment       0x000000000000002d       0x2e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+ .comment       0x000000000000002d       0x2e ../semafor_bsp//libhal_bsp.a(alt_exit.o)
+
+.debug
+ *(.debug)
+
+.line
+ *(.line)
+
+.debug_srcinfo
+ *(.debug_srcinfo)
+
+.debug_sfnames
+ *(.debug_sfnames)
+
+.debug_aranges  0x0000000000000000      0x9f8
+ *(.debug_aranges)
+ .debug_aranges
+                0x0000000000000000       0x20 ../semafor_bsp//obj/HAL/src/crt0.o
+ .debug_aranges
+                0x0000000000000020       0x20 obj/default/sem.o
+ .debug_aranges
+                0x0000000000000040       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .debug_aranges
+                0x0000000000000068       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .debug_aranges
+                0x0000000000000088       0x68 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .debug_aranges
+                0x00000000000000f0       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .debug_aranges
+                0x0000000000000110       0x28 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .debug_aranges
+                0x0000000000000138       0x18 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-impure.o)
+ .debug_aranges
+                0x0000000000000150       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+ .debug_aranges
+                0x0000000000000170       0x20 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
+ .debug_aranges
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+ .debug_str     0x0000000000001b9d       0x4a ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o)
+                                        0x26a (size before relaxing)
+ .debug_str     0x0000000000001be7       0x48 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+                                        0x2bf (size before relaxing)
+ .debug_str     0x0000000000001c2f       0x4a ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_write.o)
+                                        0x2c0 (size before relaxing)
+ .debug_str     0x0000000000001c79       0x72 ../semafor_bsp//libhal_bsp.a(altera_avalon_timer_sc.o)
+                                        0x20d (size before relaxing)
+ .debug_str     0x0000000000001ceb       0x65 ../semafor_bsp//libhal_bsp.a(alt_alarm_start.o)
+                                        0x27d (size before relaxing)
+ .debug_str     0x0000000000001d50       0x34 ../semafor_bsp//libhal_bsp.a(alt_dev_llist_insert.o)
+                                        0x1cb (size before relaxing)
+ .debug_str     0x0000000000001d84       0x48 ../semafor_bsp//libhal_bsp.a(alt_do_ctors.o)
+                                         0xd8 (size before relaxing)
+ .debug_str     0x0000000000001dcc       0x4c ../semafor_bsp//libhal_bsp.a(alt_do_dtors.o)
+                                         0xd7 (size before relaxing)
+ .debug_str     0x0000000000001e18       0xb2 ../semafor_bsp//libhal_bsp.a(alt_iic.o)
+                                        0x22b (size before relaxing)
+ .debug_str     0x0000000000001eca       0x4c ../semafor_bsp//libhal_bsp.a(alt_iic_isr_register.o)
+                                        0x1e7 (size before relaxing)
+ .debug_str     0x0000000000001f16       0x56 ../semafor_bsp//libhal_bsp.a(alt_io_redirect.o)
+                                        0x367 (size before relaxing)
+ .debug_str     0x0000000000001f6c       0x18 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+                                         0x5f (size before relaxing)
+ .debug_str     0x0000000000001f84       0x3a ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+                                        0x196 (size before relaxing)
+ .debug_str     0x0000000000001fbe       0x29 ../semafor_bsp//libhal_bsp.a(alt_irq_vars.o)
+                                        0x142 (size before relaxing)
+ .debug_str     0x0000000000001fe7       0x29 ../semafor_bsp//libhal_bsp.a(alt_open.o)
+                                        0x24a (size before relaxing)
+ .debug_str     0x0000000000002010       0x4a ../semafor_bsp//libhal_bsp.a(alt_tick.o)
+                                        0x251 (size before relaxing)
+ .debug_str     0x000000000000205a       0x3b ../semafor_bsp//libhal_bsp.a(altera_nios2_gen2_irq.o)
+                                        0x15b (size before relaxing)
+ .debug_str     0x0000000000002095       0x1e ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+                                         0x65 (size before relaxing)
+ .debug_str     0x00000000000020b3       0x24 ../semafor_bsp//libhal_bsp.a(alt_find_dev.o)
+                                        0x1de (size before relaxing)
+ .debug_str     0x00000000000020d7       0x26 ../semafor_bsp//libhal_bsp.a(alt_find_file.o)
+                                        0x1ec (size before relaxing)
+ .debug_str     0x00000000000020fd       0x30 ../semafor_bsp//libhal_bsp.a(alt_get_fd.o)
+                                        0x20e (size before relaxing)
+ .debug_str     0x000000000000212d      0x48b ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+                                        0x5a8 (size before relaxing)
+ .debug_str     0x00000000000025b8       0x83 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+                                        0x219 (size before relaxing)
+ .debug_str     0x000000000000263b       0x4e /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+                                        0x5c0 (size before relaxing)
+ .debug_str     0x0000000000002689       0x46 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+                                        0x1dc (size before relaxing)
+ .debug_str     0x00000000000026cf       0x41 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+                                        0x5f1 (size before relaxing)
+ .debug_str     0x0000000000002710       0x6d /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+                                        0x5ea (size before relaxing)
+ .debug_str     0x000000000000277d       0x2a ../semafor_bsp//libhal_bsp.a(alt_exit.o)
+                                        0x150 (size before relaxing)
+
+.debug_loc      0x0000000000000000     0x5fc0
+ *(.debug_loc)
+ .debug_loc     0x0000000000000000      0x143 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-puts.o)
+ .debug_loc     0x0000000000000143       0x73 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .debug_loc     0x00000000000001b6      0x339 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
+ .debug_loc     0x00000000000004ef      0x748 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fvwrite.o)
+ .debug_loc     0x0000000000000c37      0x1eb /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fwalk.o)
+ .debug_loc     0x0000000000000e22      0xd34 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
+ .debug_loc     0x0000000000001b56      0x240 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memchr.o)
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+ .debug_loc     0x0000000000003f9f      0x2fc /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
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+ .debug_loc     0x0000000000005aac       0xa7 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-mul.o)
+ .debug_loc     0x0000000000005b53       0x32 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .debug_loc     0x0000000000005b85       0x22 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .debug_loc     0x0000000000005ba7      0x158 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .debug_loc     0x0000000000005cff       0xf7 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .debug_loc     0x0000000000005df6      0x1ca /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
+
+.debug_macinfo
+ *(.debug_macinfo)
+
+.debug_weaknames
+ *(.debug_weaknames)
+
+.debug_funcnames
+ *(.debug_funcnames)
+
+.debug_typenames
+ *(.debug_typenames)
+
+.debug_varnames
+ *(.debug_varnames)
+
+.debug_alt_sim_info
+                0x0000000000000000       0x10
+ *(.debug_alt_sim_info)
+ .debug_alt_sim_info
+                0x0000000000000000       0x10 ../semafor_bsp//obj/HAL/src/crt0.o
+                0x0000000000020000                __alt_data_end = 0x20000
+                0x0000000000020000                PROVIDE (__alt_stack_pointer = __alt_data_end)
+                [!provide]                        PROVIDE (__alt_stack_limit = __alt_stack_base)
+                0x000000000000738c                PROVIDE (__alt_heap_start = end)
+                0x0000000000020000                PROVIDE (__alt_heap_limit = 0x20000)
+OUTPUT(semafor.elf elf32-littlenios2)
+LOAD linker stubs
+
+.debug_ranges   0x0000000000000000      0x888
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+ .debug_ranges  0x0000000000000030       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-strlen.o)
+ .debug_ranges  0x0000000000000040      0x148 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-findfp.o)
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+ .debug_ranges  0x00000000000001d8       0x60 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-mallocr.o)
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+ .debug_ranges  0x0000000000000248       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcpy.o)
+ .debug_ranges  0x0000000000000258       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memmove.o)
+ .debug_ranges  0x0000000000000268       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memset.o)
+ .debug_ranges  0x0000000000000278      0x160 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-reallocr.o)
+ .debug_ranges  0x00000000000003d8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-sbrkr.o)
+ .debug_ranges  0x00000000000003e8       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-stdio.o)
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+ .debug_ranges  0x0000000000000428       0x30 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-wsetup.o)
+ .debug_ranges  0x0000000000000458       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(closer.o)
+ .debug_ranges  0x0000000000000468       0x90 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fclose.o)
+ .debug_ranges  0x00000000000004f8       0xc8 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fflush.o)
+ .debug_ranges  0x00000000000005c0       0x18 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-freer.o)
+ .debug_ranges  0x00000000000005d8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-lseekr.o)
+ .debug_ranges  0x00000000000005e8       0xc0 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-makebuf.o)
+ .debug_ranges  0x00000000000006a8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-readr.o)
+ .debug_ranges  0x00000000000006b8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-fstatr.o)
+ .debug_ranges  0x00000000000006c8       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-isattyr.o)
+ .debug_ranges  0x00000000000006d8       0x70 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/mno-hw-mul/libgcc.a(lib2-divmod.o)
+ .debug_ranges  0x0000000000000748       0x30 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_init.o)
+ .debug_ranges  0x0000000000000778       0x18 ../semafor_bsp//libhal_bsp.a(altera_avalon_jtag_uart_read.o)
+ .debug_ranges  0x0000000000000790       0x28 ../semafor_bsp//libhal_bsp.a(alt_irq_entry.o)
+ .debug_ranges  0x00000000000007b8       0x10 ../semafor_bsp//libhal_bsp.a(alt_irq_handler.o)
+ .debug_ranges  0x00000000000007c8       0x30 ../semafor_bsp//libhal_bsp.a(alt_exception_entry.o)
+ .debug_ranges  0x00000000000007f8       0x18 ../semafor_bsp//libhal_bsp.a(alt_instruction_exception_entry.o)
+ .debug_ranges  0x0000000000000810       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-atexit.o)
+ .debug_ranges  0x0000000000000820       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-exit.o)
+ .debug_ranges  0x0000000000000830       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-memcmp.o)
+ .debug_ranges  0x0000000000000840       0x10 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__atexit.o)
+ .debug_ranges  0x0000000000000850       0x38 /opt/soft/intelFPGA_lite/20.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/lib/mno-hw-mul/libc.a(lib_a-__call_atexit.o)
diff --git a/Top/software/semafor/semafor.objdump b/Top/software/semafor/semafor.objdump
new file mode 100644
index 0000000..3d01f80
--- /dev/null
+++ b/Top/software/semafor/semafor.objdump
@@ -0,0 +1,8021 @@
+
+semafor.elf:     file format elf32-littlenios2
+semafor.elf
+architecture: nios2:r1, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x00000224
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12
+         filesz 0x00000000 memsz 0x00000000 flags r-x
+    LOAD off    0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12
+         filesz 0x00007218 memsz 0x0000736c flags rwx
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .entry        00000000  00000000  00000000  00001000  2**5
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .exceptions   00000204  00000020  00000020  00001020  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .text         00005530  00000224  00000224  00001224  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  3 .rodata       00000078  00005754  00005754  00006754  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  4 .rwdata       00001a6c  000057cc  000057cc  000067cc  2**2
+                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
+  5 .bss          00000154  00007238  00007238  00008238  2**2
+                  ALLOC, SMALL_DATA
+  6 .mem          00000000  0000738c  0000738c  00008238  2**0
+                  CONTENTS
+  7 .comment      0000002d  00000000  00000000  00008238  2**0
+                  CONTENTS, READONLY
+  8 .debug_aranges 000009f8  00000000  00000000  00008268  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+  9 .debug_info   00017df0  00000000  00000000  00008c60  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 10 .debug_abbrev 00006a85  00000000  00000000  00020a50  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 11 .debug_line   00009a4f  00000000  00000000  000274d5  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 12 .debug_frame  00001510  00000000  00000000  00030f24  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_str    000027a7  00000000  00000000  00032434  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_loc    00005fc0  00000000  00000000  00034bdb  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_alt_sim_info 00000010  00000000  00000000  0003ab9c  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_ranges 00000888  00000000  00000000  0003abb0  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .thread_model 00000003  00000000  00000000  0003d75a  2**0
+                  CONTENTS, READONLY
+ 18 .cpu          00000003  00000000  00000000  0003d75d  2**0
+                  CONTENTS, READONLY
+ 19 .qsys         00000001  00000000  00000000  0003d760  2**0
+                  CONTENTS, READONLY
+ 20 .simulation_enabled 00000001  00000000  00000000  0003d761  2**0
+                  CONTENTS, READONLY
+ 21 .stderr_dev   00000009  00000000  00000000  0003d762  2**0
+                  CONTENTS, READONLY
+ 22 .stdin_dev    00000009  00000000  00000000  0003d76b  2**0
+                  CONTENTS, READONLY
+ 23 .stdout_dev   00000009  00000000  00000000  0003d774  2**0
+                  CONTENTS, READONLY
+ 24 .sopc_system_name 00000006  00000000  00000000  0003d77d  2**0
+                  CONTENTS, READONLY
+ 25 .quartus_project_dir 00000022  00000000  00000000  0003d783  2**0
+                  CONTENTS, READONLY
+ 26 .jdi          00004392  00000000  00000000  0003d7a5  2**0
+                  CONTENTS, READONLY
+ 27 .sopcinfo     0003cf5c  00000000  00000000  00041b37  2**0
+                  CONTENTS, READONLY
+SYMBOL TABLE:
+00000000 l    d  .entry	00000000 .entry
+00000020 l    d  .exceptions	00000000 .exceptions
+00000224 l    d  .text	00000000 .text
+00005754 l    d  .rodata	00000000 .rodata
+000057cc l    d  .rwdata	00000000 .rwdata
+00007238 l    d  .bss	00000000 .bss
+0000738c l    d  .mem	00000000 .mem
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_loc	00000000 .debug_loc
+00000000 l    d  .debug_alt_sim_info	00000000 .debug_alt_sim_info
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    df *ABS*	00000000 ../semafor_bsp//obj/HAL/src/crt0.o
+00000258 l       .text	00000000 alt_after_alt_main
+00000000 l    df *ABS*	00000000 alt_irq_handler.c
+00000000 l    df *ABS*	00000000 alt_instruction_exception_entry.c
+00000000 l    df *ABS*	00000000 sem.c
+00000000 l    df *ABS*	00000000 puts.c
+00000000 l    df *ABS*	00000000 strlen.c
+00000000 l    df *ABS*	00000000 findfp.c
+00000490 l     F .text	00000008 __fp_lock
+000004a4 l     F .text	00000008 __fp_unlock
+000004ac l     F .text	00000168 __sinit.part.0
+00000000 l    df *ABS*	00000000 fvwrite.c
+00000000 l    df *ABS*	00000000 fwalk.c
+00000000 l    df *ABS*	00000000 impure.c
+000057cc l     O .rwdata	00000424 impure_data
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 memchr.c
+00000000 l    df *ABS*	00000000 memcpy.c
+00000000 l    df *ABS*	00000000 memmove.c
+00000000 l    df *ABS*	00000000 memset.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 sbrkr.c
+00000000 l    df *ABS*	00000000 stdio.c
+00000000 l    df *ABS*	00000000 writer.c
+00000000 l    df *ABS*	00000000 wsetup.c
+00000000 l    df *ABS*	00000000 closer.c
+00000000 l    df *ABS*	00000000 fclose.c
+0000232c l     F .text	000000c0 _fclose_r.part.0
+00000000 l    df *ABS*	00000000 fflush.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 int_errno.c
+00000000 l    df *ABS*	00000000 lseekr.c
+00000000 l    df *ABS*	00000000 makebuf.c
+00000000 l    df *ABS*	00000000 readr.c
+00000000 l    df *ABS*	00000000 fstatr.c
+00000000 l    df *ABS*	00000000 isattyr.c
+00000000 l    df *ABS*	00000000 lib2-divmod.c
+00000000 l    df *ABS*	00000000 lib2-mul.c
+00000000 l    df *ABS*	00000000 alt_close.c
+00003194 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_dcache_flush.c
+00000000 l    df *ABS*	00000000 alt_dev.c
+000032d4 l     F .text	0000002c alt_dev_null_write
+00000000 l    df *ABS*	00000000 alt_errno.c
+00000000 l    df *ABS*	00000000 alt_fstat.c
+00003300 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_isatty.c
+000033f8 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_lseek.c
+000034e4 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_main.c
+00000000 l    df *ABS*	00000000 alt_malloc_lock.c
+00000000 l    df *ABS*	00000000 alt_read.c
+000036c4 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_release_fd.c
+00000000 l    df *ABS*	00000000 alt_sbrk.c
+00007228 l     O .rwdata	00000004 heap_end
+00000000 l    df *ABS*	00000000 alt_write.c
+00003930 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_sys_init.c
+00003a70 l     F .text	00000034 alt_dev_reg
+000061a0 l     O .rwdata	00001060 jtag_uart
+00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_fd.c
+00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_init.c
+00003d64 l     F .text	0000020c altera_avalon_jtag_uart_irq
+00003f70 l     F .text	000000a0 altera_avalon_jtag_uart_timeout
+00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_ioctl.c
+00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_read.c
+00000000 l    df *ABS*	00000000 altera_avalon_jtag_uart_write.c
+00000000 l    df *ABS*	00000000 altera_avalon_timer_sc.c
+000045b4 l     F .text	0000007c alt_avalon_timer_sc_irq
+00000000 l    df *ABS*	00000000 alt_alarm_start.c
+00000000 l    df *ABS*	00000000 alt_dev_llist_insert.c
+000047e8 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_do_ctors.c
+00000000 l    df *ABS*	00000000 alt_do_dtors.c
+00000000 l    df *ABS*	00000000 alt_iic.c
+00000000 l    df *ABS*	00000000 alt_iic_isr_register.c
+00000000 l    df *ABS*	00000000 alt_io_redirect.c
+00004c2c l     F .text	000000d4 alt_open_fd
+00000000 l    df *ABS*	00000000 alt_irq_vars.c
+00000000 l    df *ABS*	00000000 alt_open.c
+00004d7c l     F .text	0000003c alt_get_errno
+00004db8 l     F .text	000000dc alt_file_locked
+00000000 l    df *ABS*	00000000 alt_tick.c
+00000000 l    df *ABS*	00000000 altera_nios2_gen2_irq.c
+00000000 l    df *ABS*	00000000 alt_find_dev.c
+00000000 l    df *ABS*	00000000 alt_find_file.c
+00000000 l    df *ABS*	00000000 alt_get_fd.c
+00000000 l    df *ABS*	00000000 atexit.c
+00000000 l    df *ABS*	00000000 exit.c
+00000000 l    df *ABS*	00000000 memcmp.c
+00000000 l    df *ABS*	00000000 __atexit.c
+00000000 l    df *ABS*	00000000 __call_atexit.c
+00000000 l    df *ABS*	00000000 alt_exit.c
+00007260 g     O .bss	00000004 alt_instruction_exception_handler
+00002f60 g     F .text	00000058 _isatty_r
+00003600 g     F .text	0000007c alt_main
+0000031c g     F .text	000000cc _puts_r
+0000728c g     O .bss	00000100 alt_irq
+00002bf0 g     F .text	00000064 _lseek_r
+0000738c g       *ABS*	00000000 __alt_heap_start
+000020a8 g     F .text	0000005c __sseek
+000007f4 g     F .text	00000010 __sinit
+00000614 g     F .text	00000078 __sfmoreglue
+000036a0 g     F .text	00000024 __malloc_unlock
+00005754 g     O .rodata	00000040 divisors
+000017f4 g     F .text	0000012c memmove
+000007e0 g     F .text	00000014 _cleanup
+000051a0 g     F .text	00000024 altera_nios2_gen2_irq_init
+00000000 g     F .entry	00000000 __reset
+00002f00 g     F .text	00000060 _fstat_r
+00007244 g     O .bss	00000004 errno
+00002020 g     F .text	00000008 __seofread
+0000724c g     O .bss	00000004 alt_argv
+0000f200 g       *ABS*	00000000 _gp
+00006020 g     O .rwdata	00000180 alt_fd_list
+000051c4 g     F .text	00000090 alt_find_dev
+000016f4 g     F .text	00000100 memcpy
+00000498 g     F .text	0000000c _cleanup_r
+00004d00 g     F .text	0000007c alt_io_redirect
+00005754 g       *ABS*	00000000 __DTOR_END__
+000003e8 g     F .text	00000010 puts
+00005414 g     F .text	00000098 alt_exception_cause_generated_bad_addr
+0000416c g     F .text	00000220 altera_avalon_jtag_uart_read
+000030ac g     F .text	00000064 .hidden __udivsi3
+00003434 g     F .text	000000b0 isatty
+00007240 g     O .bss	00000004 __malloc_top_pad
+0000083c g     F .text	000004c8 __sfvwrite_r
+00001f74 g     F .text	00000058 _sbrk_r
+00002e9c g     F .text	00000064 _read_r
+000032ac g     F .text	00000028 alt_dcache_flush
+00007220 g     O .rwdata	00000004 alt_max_fd
+000023ec g     F .text	00000070 _fclose_r
+00002754 g     F .text	00000084 fflush
+0000723c g     O .bss	00000004 __malloc_max_sbrked_mem
+00003520 g     F .text	000000e0 lseek
+00007200 g     O .rwdata	00000004 _global_impure_ptr
+00001a10 g     F .text	00000564 _realloc_r
+0000738c g       *ABS*	00000000 __bss_end
+00004b44 g     F .text	000000e8 alt_iic_isr_register
+00005098 g     F .text	00000108 alt_tick
+00000814 g     F .text	00000014 __fp_lock_all
+00004af8 g     F .text	0000004c alt_ic_irq_enabled
+00000000 g       *ABS*	00000000 __alt_mem_mem
+00004ff4 g     F .text	000000a4 alt_alarm_stop
+00007254 g     O .bss	00000004 alt_irq_active
+000000fc g     F .exceptions	000000c8 alt_irq_handler
+00005ff8 g     O .rwdata	00000028 alt_dev_null
+00007218 g     O .rwdata	00000008 alt_dev_list
+0000396c g     F .text	00000104 write
+0000333c g     F .text	000000bc fstat
+00003110 g     F .text	0000005c .hidden __umodsi3
+0000738c g       *ABS*	00000000 end
+00003ca4 g     F .text	000000c0 altera_avalon_jtag_uart_init
+000001c4 g     F .exceptions	00000060 alt_instruction_exception_entry
+00005754 g       *ABS*	00000000 __CTOR_LIST__
+00020000 g       *ABS*	00000000 __alt_stack_pointer
+00004630 g     F .text	00000084 alt_avalon_timer_sc_init
+0000438c g     F .text	00000228 altera_avalon_jtag_uart_write
+00000804 g     F .text	00000004 __sfp_lock_acquire
+00001624 g     F .text	000000d0 memchr
+000028f4 g     F .text	000002fc _free_r
+000055fc g     F .text	00000120 __call_exitprocs
+00007208 g     O .rwdata	00000004 __malloc_sbrk_base
+00000224 g     F .text	00000038 _start
+00007258 g     O .bss	00000004 _alt_tick_rate
+0000725c g     O .bss	00000004 _alt_nticks
+00003700 g     F .text	00000108 read
+00003ae0 g     F .text	00000060 alt_sys_init
+0000556c g     F .text	00000090 __register_exitproc
+00004010 g     F .text	00000068 altera_avalon_jtag_uart_close
+0000316c g     F .text	00000028 .hidden __mulsi3
+00007264 g     O .bss	00000028 __malloc_current_mallinfo
+00003b40 g     F .text	00000060 altera_avalon_jtag_uart_read_fd
+0000535c g     F .text	000000b8 alt_get_fd
+000022d4 g     F .text	00000058 _close_r
+000054f4 g     F .text	00000078 memcmp
+00003c00 g     F .text	00000050 altera_avalon_jtag_uart_close_fd
+0000738c g       *ABS*	00000000 __alt_stack_base
+00003c50 g     F .text	00000054 altera_avalon_jtag_uart_ioctl_fd
+00002170 g     F .text	00000164 __swsetup_r
+0000068c g     F .text	00000154 __sfp
+00005bf0 g     O .rwdata	00000408 __malloc_av_
+00000810 g     F .text	00000004 __sinit_lock_release
+00001fcc g     F .text	00000054 __sread
+00005254 g     F .text	00000108 alt_find_file
+00004824 g     F .text	000000a8 alt_dev_llist_insert
+0000367c g     F .text	00000024 __malloc_lock
+00003878 g     F .text	000000b8 sbrk
+000026f4 g     F .text	00000060 _fflush_r
+00007238 g       *ABS*	00000000 __bss_start
+00001920 g     F .text	000000f0 memset
+0000025c g     F .text	000000c0 main
+00007250 g     O .bss	00000004 alt_envp
+00007238 g     O .bss	00000004 __malloc_max_total_mem
+00003ba0 g     F .text	00000060 altera_avalon_jtag_uart_write_fd
+00002104 g     F .text	00000008 __sclose
+00020000 g       *ABS*	00000000 __alt_heap_limit
+0000245c g     F .text	00000070 fclose
+00000e44 g     F .text	000007e0 _malloc_r
+00007224 g     O .rwdata	00000004 alt_errno
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+00002fb8 g     F .text	00000080 .hidden __divsi3
+000027d8 g     F .text	0000011c _malloc_trim_r
+00005754 g       *ABS*	00000000 __CTOR_END__
+00005754 g       *ABS*	00000000 __DTOR_LIST__
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+00003808 g     F .text	00000070 alt_release_fd
+000054ac g     F .text	00000014 atexit
+0000210c g     F .text	00000064 _write_r
+00007204 g     O .rwdata	00000004 _impure_ptr
+00007248 g     O .bss	00000004 alt_argc
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+00000020 g       .exceptions	00000000 alt_irq_entry
+00000828 g     F .text	00000014 __fp_unlock_all
+00007210 g     O .rwdata	00000008 alt_fs_list
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+00004994 g     F .text	00000050 alt_ic_isr_register
+00007238 g       *ABS*	00000000 _edata
+0000738c g       *ABS*	00000000 _end
+00004078 g     F .text	000000f4 altera_avalon_jtag_uart_ioctl
+00004a6c g     F .text	0000008c alt_ic_irq_disable
+00002028 g     F .text	00000080 __swrite
+0000720c g     O .rwdata	00000004 __malloc_trim_threshold
+000054c0 g     F .text	00000034 exit
+00000d9c g     F .text	000000a8 _fwalk_reent
+00003038 g     F .text	00000074 .hidden __modsi3
+00020000 g       *ABS*	00000000 __alt_data_end
+00000020 g     F .exceptions	00000000 alt_exception
+00000808 g     F .text	00000004 __sfp_lock_release
+0000571c g     F .text	00000038 _exit
+000046b4 g     F .text	00000134 alt_alarm_start
+00002c54 g     F .text	000001b0 __smakebuf_r
+000003f8 g     F .text	00000098 strlen
+00004e94 g     F .text	00000160 open
+0000722c g     O .rwdata	00000004 alt_priority_mask
+000049e4 g     F .text	00000088 alt_ic_irq_enable
+00007230 g     O .rwdata	00000008 alt_alarm_list
+000048cc g     F .text	00000064 _do_ctors
+000031d0 g     F .text	000000dc close
+0000080c g     F .text	00000004 __sinit_lock_acquire
+
+
+
+Disassembly of section .exceptions:
+
+00000020 <alt_exception>:
+
+#else /* ALT_EXCEPTION_STACK disabled */
+        /* 
+         * Reserve space on normal stack for registers about to be pushed.
+         */
+        addi  sp, sp, -76
+  20:	deffed04 	addi	sp,sp,-76
+         * documentation for details).
+         *
+         * Leave a gap in the stack frame at 4(sp) for the muldiv handler to
+         * store zero into.
+         */
+        stw   ra,  0(sp)
+  24:	dfc00015 	stw	ra,0(sp)
+        stw   r1,   8(sp)
+  28:	d8400215 	stw	at,8(sp)
+        stw   r2,  12(sp)
+  2c:	d8800315 	stw	r2,12(sp)
+        stw   r3,  16(sp)
+  30:	d8c00415 	stw	r3,16(sp)
+        stw   r4,  20(sp)
+  34:	d9000515 	stw	r4,20(sp)
+        stw   r5,  24(sp)
+  38:	d9400615 	stw	r5,24(sp)
+        stw   r6,  28(sp)
+  3c:	d9800715 	stw	r6,28(sp)
+        stw   r7,  32(sp)
+  40:	d9c00815 	stw	r7,32(sp)
+        rdctl r5, estatus   /* Read early to avoid usage stall */
+  44:	000b307a 	rdctl	r5,estatus
+        stw   r8,  36(sp)
+  48:	da000915 	stw	r8,36(sp)
+        stw   r9,  40(sp)
+  4c:	da400a15 	stw	r9,40(sp)
+        stw   r10, 44(sp)
+  50:	da800b15 	stw	r10,44(sp)
+        stw   r11, 48(sp)
+  54:	dac00c15 	stw	r11,48(sp)
+        stw   r12, 52(sp)
+  58:	db000d15 	stw	r12,52(sp)
+        stw   r13, 56(sp)
+  5c:	db400e15 	stw	r13,56(sp)
+        stw   r14, 60(sp)
+  60:	db800f15 	stw	r14,60(sp)
+        stw   r15, 64(sp)
+  64:	dbc01015 	stw	r15,64(sp)
+        /*
+         * ea-4 contains the address of the instruction being executed
+         * when the exception occured. For interrupt exceptions, we will
+         * will be re-issue the isntruction. Store it in 72(sp)
+         */
+        stw   r5,  68(sp)  /* estatus */
+  68:	d9401115 	stw	r5,68(sp)
+        addi  r15, ea, -4  /* instruction that caused exception */
+  6c:	ebffff04 	addi	r15,ea,-4
+        stw   r15,  72(sp)
+  70:	dbc01215 	stw	r15,72(sp)
+#else
+        /*
+         * Test to see if the exception was a software exception or caused 
+         * by an external interrupt, and vector accordingly.
+         */
+        rdctl r4, ipending
+  74:	0009313a 	rdctl	r4,ipending
+        andi  r2, r5, 1
+  78:	2880004c 	andi	r2,r5,1
+        beq   r2, zero, .Lnot_irq
+  7c:	10000326 	beq	r2,zero,8c <alt_exception+0x6c>
+        beq   r4, zero, .Lnot_irq
+  80:	20000226 	beq	r4,zero,8c <alt_exception+0x6c>
+        /*
+         * Now that all necessary registers have been preserved, call 
+         * alt_irq_handler() to process the interrupts.
+         */
+
+        call alt_irq_handler
+  84:	00000fc0 	call	fc <alt_irq_handler>
+
+        .section .exceptions.irqreturn, "xa"
+
+        br    .Lexception_exit
+  88:	00000706 	br	a8 <alt_exception+0x88>
+         * upon completion, so we write ea (address of instruction *after*
+         * the one where the exception occured) into 72(sp). The actual
+         * instruction that caused the exception is written in r2, which these
+         * handlers will utilize.
+         */
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
+  8c:	df401215 	stw	ea,72(sp)
+.Lunknown_16bit:
+        addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
+        stw r4, 72(sp)
+
+#else /* CDX is not Enabled and all instructions are 32bits */
+        ldw r2, -4(ea) /* Instruction value that caused exception */
+  90:	e8bfff17 	ldw	r2,-4(ea)
+         * debugger is present) or go into an infinite loop since the
+         * handling behavior is undefined; in that case we will not return here.
+         */
+
+        /* Load exception-causing address as first argument (r4) */
+        addi   r4, ea, -4
+  94:	e93fff04 	addi	r4,ea,-4
+
+        /* Call the instruction-exception entry */
+        call   alt_instruction_exception_entry
+  98:	00001c40 	call	1c4 <alt_instruction_exception_entry>
+         * instruction
+         *
+         * Return code was 0: Skip. The instruction after the exception is
+         * already stored in 72(sp).
+         */
+        bne   r2, r0, .Lexception_exit
+  9c:	1000021e 	bne	r2,zero,a8 <alt_exception+0x88>
+
+        /*
+         * Otherwise, modify 72(sp) to re-issue the instruction that caused the
+         * exception.
+         */
+        addi  r15, ea, -4  /* instruction that caused exception */
+  a0:	ebffff04 	addi	r15,ea,-4
+        stw   r15,  72(sp)
+  a4:	dbc01215 	stw	r15,72(sp)
+        /* 
+         * Restore the saved registers, so that all general purpose registers 
+         * have been restored to their state at the time the interrupt occured.
+         */
+
+        ldw   r5,  68(sp)
+  a8:	d9401117 	ldw	r5,68(sp)
+        ldw   ea,  72(sp)  /* This becomes the PC once eret is executed */
+  ac:	df401217 	ldw	ea,72(sp)
+        ldw   ra,   0(sp)
+  b0:	dfc00017 	ldw	ra,0(sp)
+
+        wrctl estatus, r5
+  b4:	2801707a 	wrctl	estatus,r5
+
+        ldw   r1,   8(sp)
+  b8:	d8400217 	ldw	at,8(sp)
+        ldw   r2,  12(sp)
+  bc:	d8800317 	ldw	r2,12(sp)
+        ldw   r3,  16(sp)
+  c0:	d8c00417 	ldw	r3,16(sp)
+        ldw   r4,  20(sp)
+  c4:	d9000517 	ldw	r4,20(sp)
+        ldw   r5,  24(sp)
+  c8:	d9400617 	ldw	r5,24(sp)
+        ldw   r6,  28(sp)
+  cc:	d9800717 	ldw	r6,28(sp)
+        ldw   r7,  32(sp)
+  d0:	d9c00817 	ldw	r7,32(sp)
+
+#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
+        ldw   et, %gprel(alt_exception_old_stack_limit)(gp)
+#endif
+
+        ldw   r8,  36(sp)
+  d4:	da000917 	ldw	r8,36(sp)
+        ldw   r9,  40(sp)
+  d8:	da400a17 	ldw	r9,40(sp)
+        ldw   r10, 44(sp)
+  dc:	da800b17 	ldw	r10,44(sp)
+        ldw   r11, 48(sp)
+  e0:	dac00c17 	ldw	r11,48(sp)
+        ldw   r12, 52(sp)
+  e4:	db000d17 	ldw	r12,52(sp)
+        ldw   r13, 56(sp)
+  e8:	db400e17 	ldw	r13,56(sp)
+        ldw   r14, 60(sp)
+  ec:	db800f17 	ldw	r14,60(sp)
+        ldw   r15, 64(sp)
+  f0:	dbc01017 	ldw	r15,64(sp)
+        stw   et, %gprel(alt_stack_limit_value)(gp)
+        stw   zero, %gprel(alt_exception_old_stack_limit)(gp)
+#endif /* ALT_STACK_CHECK */
+        ldw   sp,  76(sp)
+#else /* ALT_EXCEPTION_STACK disabled */
+        addi  sp, sp, 76
+  f4:	dec01304 	addi	sp,sp,76
+
+        /*
+         * Return to the interrupted instruction.
+         */
+
+        eret
+  f8:	ef80083a 	eret
+
+000000fc <alt_irq_handler>:
+ * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined.
+ */
+
+void alt_irq_handler (void) __attribute__ ((section (".exceptions")));
+void alt_irq_handler (void)
+{
+  fc:	defff904 	addi	sp,sp,-28
+ 100:	dfc00615 	stw	ra,24(sp)
+ 104:	df000515 	stw	fp,20(sp)
+ 108:	df000504 	addi	fp,sp,20
+  
+  /*
+   * Notify the operating system that we are at interrupt level.
+   */ 
+  
+  ALT_OS_INT_ENTER();
+ 10c:	0001883a 	nop
+#ifndef NIOS2_EIC_PRESENT
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
+{
+  alt_u32 active;
+
+  NIOS2_READ_IPENDING (active);
+ 110:	0005313a 	rdctl	r2,ipending
+ 114:	e0bffc15 	stw	r2,-16(fp)
+
+  return active;
+ 118:	e0bffc17 	ldw	r2,-16(fp)
+   * Consider the case where the high priority interupt is asserted during
+   * the interrupt entry sequence for a lower priority interrupt to see why
+   * this is the case.
+   */
+
+  active = alt_irq_pending ();
+ 11c:	e0bfff15 	stw	r2,-4(fp)
+
+  do
+  {
+    i = 0;
+ 120:	e03ffd15 	stw	zero,-12(fp)
+    mask = 1;
+ 124:	00800044 	movi	r2,1
+ 128:	e0bffe15 	stw	r2,-8(fp)
+     * called to clear the interrupt condition.
+     */
+
+    do
+    {
+      if (active & mask)
+ 12c:	e0ffff17 	ldw	r3,-4(fp)
+ 130:	e0bffe17 	ldw	r2,-8(fp)
+ 134:	1884703a 	and	r2,r3,r2
+ 138:	10001126 	beq	r2,zero,180 <alt_irq_handler+0x84>
+      { 
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+        alt_irq[i].handler(alt_irq[i].context); 
+ 13c:	e0bffd17 	ldw	r2,-12(fp)
+ 140:	100690fa 	slli	r3,r2,3
+ 144:	00800034 	movhi	r2,0
+ 148:	1885883a 	add	r2,r3,r2
+ 14c:	10dca317 	ldw	r3,29324(r2)
+ 150:	e0bffd17 	ldw	r2,-12(fp)
+ 154:	100890fa 	slli	r4,r2,3
+ 158:	00800034 	movhi	r2,0
+ 15c:	2085883a 	add	r2,r4,r2
+ 160:	109ca417 	ldw	r2,29328(r2)
+ 164:	1009883a 	mov	r4,r2
+ 168:	183ee83a 	callr	r3
+#else
+        alt_irq[i].handler(alt_irq[i].context, i); 
+#endif
+        break;
+ 16c:	0001883a 	nop
+  NIOS2_READ_IPENDING (active);
+ 170:	0005313a 	rdctl	r2,ipending
+ 174:	e0bffb15 	stw	r2,-20(fp)
+  return active;
+ 178:	e0bffb17 	ldw	r2,-20(fp)
+ 17c:	00000706 	br	19c <alt_irq_handler+0xa0>
+      }
+      mask <<= 1;
+ 180:	e0bffe17 	ldw	r2,-8(fp)
+ 184:	1085883a 	add	r2,r2,r2
+ 188:	e0bffe15 	stw	r2,-8(fp)
+      i++;
+ 18c:	e0bffd17 	ldw	r2,-12(fp)
+ 190:	10800044 	addi	r2,r2,1
+ 194:	e0bffd15 	stw	r2,-12(fp)
+      if (active & mask)
+ 198:	003fe406 	br	12c <alt_irq_handler+0x30>
+
+    } while (1);
+
+    active = alt_irq_pending ();
+ 19c:	e0bfff15 	stw	r2,-4(fp)
+    
+  } while (active);
+ 1a0:	e0bfff17 	ldw	r2,-4(fp)
+ 1a4:	103fde1e 	bne	r2,zero,120 <alt_irq_handler+0x24>
+
+  /*
+   * Notify the operating system that interrupt processing is complete.
+   */ 
+
+  ALT_OS_INT_EXIT();
+ 1a8:	0001883a 	nop
+}
+ 1ac:	0001883a 	nop
+ 1b0:	e037883a 	mov	sp,fp
+ 1b4:	dfc00117 	ldw	ra,4(sp)
+ 1b8:	df000017 	ldw	fp,0(sp)
+ 1bc:	dec00204 	addi	sp,sp,8
+ 1c0:	f800283a 	ret
+
+000001c4 <alt_instruction_exception_entry>:
+ * that handler if it has been registered. Absent a handler, it will
+ * break break or hang as discussed below.
+ */
+int 
+alt_instruction_exception_entry (alt_u32 exception_pc)
+{
+ 1c4:	defffb04 	addi	sp,sp,-20
+ 1c8:	dfc00415 	stw	ra,16(sp)
+ 1cc:	df000315 	stw	fp,12(sp)
+ 1d0:	df000304 	addi	fp,sp,12
+ 1d4:	e13ffd15 	stw	r4,-12(fp)
+  cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >>
+              NIOS2_EXCEPTION_REG_CAUSE_OFST );
+
+  NIOS2_READ_BADADDR(badaddr);
+#else
+  cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT;
+ 1d8:	00bfffc4 	movi	r2,-1
+ 1dc:	e0bfff15 	stw	r2,-4(fp)
+  badaddr = 0;
+ 1e0:	e03ffe15 	stw	zero,-8(fp)
+#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
+
+  if(alt_instruction_exception_handler) {
+ 1e4:	d0a01817 	ldw	r2,-32672(gp)
+ 1e8:	10000726 	beq	r2,zero,208 <alt_instruction_exception_entry+0x44>
+     * Call handler. Its return value indicates whether the exception-causing
+     * instruction should be re-issued. The code that called us,
+     * alt_eceptions_entry.S, will look at this value and adjust the ea
+     * register as necessary
+     */
+    return alt_instruction_exception_handler(cause, exception_pc, badaddr);
+ 1ec:	d0a01817 	ldw	r2,-32672(gp)
+ 1f0:	e0ffff17 	ldw	r3,-4(fp)
+ 1f4:	e1bffe17 	ldw	r6,-8(fp)
+ 1f8:	e17ffd17 	ldw	r5,-12(fp)
+ 1fc:	1809883a 	mov	r4,r3
+ 200:	103ee83a 	callr	r2
+ 204:	00000206 	br	210 <alt_instruction_exception_entry+0x4c>
+   *    (a peripheral which negates its interrupt output before its
+   *    interrupt handler has been executed will cause spurious interrupts)
+   */
+  else {
+#ifdef NIOS2_HAS_DEBUG_STUB
+    NIOS2_BREAK();
+ 208:	003da03a 	break	0
+      ;
+#endif /* NIOS2_HAS_DEBUG_STUB */
+  }
+
+  /* We should not get here. Remove compiler warning. */
+  return NIOS2_EXCEPTION_RETURN_REISSUE_INST;
+ 20c:	0005883a 	mov	r2,zero
+}
+ 210:	e037883a 	mov	sp,fp
+ 214:	dfc00117 	ldw	ra,4(sp)
+ 218:	df000017 	ldw	fp,0(sp)
+ 21c:	dec00204 	addi	sp,sp,8
+ 220:	f800283a 	ret
+
+Disassembly of section .text:
+
+00000224 <_start>:
+
+    /*
+     * Now that the caches are initialized, set up the stack pointer and global pointer.
+     * The values provided by the linker are assumed to be correctly aligned.
+     */
+    movhi sp, %hi(__alt_stack_pointer)
+     224:	06c000b4 	movhi	sp,2
+    ori sp, sp, %lo(__alt_stack_pointer)
+     228:	dec00014 	ori	sp,sp,0
+    movhi gp, %hi(_gp)
+     22c:	06800034 	movhi	gp,0
+    ori gp, gp, %lo(_gp)
+     230:	d6bc8014 	ori	gp,gp,61952
+ */
+#ifndef ALT_SIM_OPTIMIZE
+    /* Log that the BSS is about to be cleared. */
+    ALT_LOG_PUTS(alt_log_msg_bss)
+
+    movhi r2, %hi(__bss_start)
+     234:	00800034 	movhi	r2,0
+    ori r2, r2, %lo(__bss_start)
+     238:	109c8e14 	ori	r2,r2,29240
+
+    movhi r3, %hi(__bss_end)
+     23c:	00c00034 	movhi	r3,0
+    ori r3, r3, %lo(__bss_end)
+     240:	18dce314 	ori	r3,r3,29580
+
+    beq r2, r3, 1f
+     244:	10c00326 	beq	r2,r3,254 <_start+0x30>
+
+0:
+    stw zero, (r2)
+     248:	10000015 	stw	zero,0(r2)
+    addi r2, r2, 4
+     24c:	10800104 	addi	r2,r2,4
+    bltu r2, r3, 0b
+     250:	10fffd36 	bltu	r2,r3,248 <_start+0x24>
+
+    /* Log that alt_main is about to be called. */
+    ALT_LOG_PUTS(alt_log_msg_alt_main)
+
+    /* Call the C entry point. It should never return. */
+    call alt_main
+     254:	00036000 	call	3600 <alt_main>
+
+00000258 <alt_after_alt_main>:
+
+    /* Wait in infinite loop in case alt_main does return. */
+alt_after_alt_main:
+    br alt_after_alt_main
+     258:	003fff06 	br	258 <alt_after_alt_main>
+
+0000025c <main>:
+		{0x0ff000f1, 0x0ff000f1, 0x0ff000f1, 0x00700011},
+		{0x0ff000d1, 0x0ff000f1, 0x0ff000f1, 0x00700011}
+};
+
+int main()
+{ 
+     25c:	defffb04 	addi	sp,sp,-20
+     260:	dfc00415 	stw	ra,16(sp)
+     264:	df000315 	stw	fp,12(sp)
+     268:	df000304 	addi	fp,sp,12
+	int i,j;
+	volatile alt_u32 *p;
+	alt_u32 tmp;
+
+	//program divisors
+	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
+     26c:	008000b4 	movhi	r2,2
+     270:	10840004 	addi	r2,r2,4096
+     274:	e0bffd15 	stw	r2,-12(fp)
+	for (i = 0; i < TIME_SETS; i++)	{
+     278:	e03fff15 	stw	zero,-4(fp)
+     27c:	00001a06 	br	2e8 <main+0x8c>
+		for (j = TIME_STATES; j > 0; j--) {
+     280:	00800104 	movi	r2,4
+     284:	e0bffe15 	stw	r2,-8(fp)
+     288:	00001206 	br	2d4 <main+0x78>
+			*p = divisors[i][j - 1];
+     28c:	e0bffe17 	ldw	r2,-8(fp)
+     290:	10bfffc4 	addi	r2,r2,-1
+     294:	e0ffff17 	ldw	r3,-4(fp)
+     298:	180690ba 	slli	r3,r3,2
+     29c:	1885883a 	add	r2,r3,r2
+     2a0:	100690ba 	slli	r3,r2,2
+     2a4:	00800034 	movhi	r2,0
+     2a8:	1885883a 	add	r2,r3,r2
+     2ac:	10d5d517 	ldw	r3,22356(r2)
+     2b0:	e0bffd17 	ldw	r2,-12(fp)
+     2b4:	10c00015 	stw	r3,0(r2)
+			alt_dcache_flush();
+     2b8:	00032ac0 	call	32ac <alt_dcache_flush>
+			p++;
+     2bc:	e0bffd17 	ldw	r2,-12(fp)
+     2c0:	10800104 	addi	r2,r2,4
+     2c4:	e0bffd15 	stw	r2,-12(fp)
+		for (j = TIME_STATES; j > 0; j--) {
+     2c8:	e0bffe17 	ldw	r2,-8(fp)
+     2cc:	10bfffc4 	addi	r2,r2,-1
+     2d0:	e0bffe15 	stw	r2,-8(fp)
+     2d4:	e0bffe17 	ldw	r2,-8(fp)
+     2d8:	00bfec16 	blt	zero,r2,28c <main+0x30>
+	for (i = 0; i < TIME_SETS; i++)	{
+     2dc:	e0bfff17 	ldw	r2,-4(fp)
+     2e0:	10800044 	addi	r2,r2,1
+     2e4:	e0bfff15 	stw	r2,-4(fp)
+     2e8:	e0bfff17 	ldw	r2,-4(fp)
+     2ec:	10800110 	cmplti	r2,r2,4
+     2f0:	103fe31e 	bne	r2,zero,280 <main+0x24>
+		}
+	}
+	
+	//select timeset and run semafor
+	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x02);
+     2f4:	00c00084 	movi	r3,2
+     2f8:	008000b4 	movhi	r2,2
+     2fc:	10c41935 	stwio	r3,4196(r2)
+	IOWR_ALTERA_AVALON_SEM_CTL(SEM_CTL_SLAVE_BASE,0x01);
+     300:	00c00044 	movi	r3,1
+     304:	008000b4 	movhi	r2,2
+     308:	10c41835 	stwio	r3,4192(r2)
+
+	printf("Ready\n");
+     30c:	01000034 	movhi	r4,0
+     310:	2115e504 	addi	r4,r4,22420
+     314:	00003e80 	call	3e8 <puts>
+
+	while (1)
+     318:	003fff06 	br	318 <main+0xbc>
+
+0000031c <_puts_r>:
+     31c:	defff504 	addi	sp,sp,-44
+     320:	dc000815 	stw	r16,32(sp)
+     324:	2021883a 	mov	r16,r4
+     328:	2809883a 	mov	r4,r5
+     32c:	dc400915 	stw	r17,36(sp)
+     330:	dfc00a15 	stw	ra,40(sp)
+     334:	2823883a 	mov	r17,r5
+     338:	00003f80 	call	3f8 <strlen>
+     33c:	11000044 	addi	r4,r2,1
+     340:	d8800515 	stw	r2,20(sp)
+     344:	00800044 	movi	r2,1
+     348:	00c00034 	movhi	r3,0
+     34c:	d8800715 	stw	r2,28(sp)
+     350:	d8800404 	addi	r2,sp,16
+     354:	18d5e704 	addi	r3,r3,22428
+     358:	d8800115 	stw	r2,4(sp)
+     35c:	00800084 	movi	r2,2
+     360:	dc400415 	stw	r17,16(sp)
+     364:	d8c00615 	stw	r3,24(sp)
+     368:	d9000315 	stw	r4,12(sp)
+     36c:	d8800215 	stw	r2,8(sp)
+     370:	81400217 	ldw	r5,8(r16)
+     374:	80000226 	beq	r16,zero,380 <_puts_r+0x64>
+     378:	80800e17 	ldw	r2,56(r16)
+     37c:	10001326 	beq	r2,zero,3cc <_puts_r+0xb0>
+     380:	2880030b 	ldhu	r2,12(r5)
+     384:	10c8000c 	andi	r3,r2,8192
+     388:	1800061e 	bne	r3,zero,3a4 <_puts_r+0x88>
+     38c:	28c01917 	ldw	r3,100(r5)
+     390:	0137ffc4 	movi	r4,-8193
+     394:	10880014 	ori	r2,r2,8192
+     398:	1906703a 	and	r3,r3,r4
+     39c:	2880030d 	sth	r2,12(r5)
+     3a0:	28c01915 	stw	r3,100(r5)
+     3a4:	d9800104 	addi	r6,sp,4
+     3a8:	8009883a 	mov	r4,r16
+     3ac:	000083c0 	call	83c <__sfvwrite_r>
+     3b0:	10000b1e 	bne	r2,zero,3e0 <_puts_r+0xc4>
+     3b4:	00800284 	movi	r2,10
+     3b8:	dfc00a17 	ldw	ra,40(sp)
+     3bc:	dc400917 	ldw	r17,36(sp)
+     3c0:	dc000817 	ldw	r16,32(sp)
+     3c4:	dec00b04 	addi	sp,sp,44
+     3c8:	f800283a 	ret
+     3cc:	8009883a 	mov	r4,r16
+     3d0:	d9400015 	stw	r5,0(sp)
+     3d4:	00007f40 	call	7f4 <__sinit>
+     3d8:	d9400017 	ldw	r5,0(sp)
+     3dc:	003fe806 	br	380 <_puts_r+0x64>
+     3e0:	00bfffc4 	movi	r2,-1
+     3e4:	003ff406 	br	3b8 <_puts_r+0x9c>
+
+000003e8 <puts>:
+     3e8:	00800034 	movhi	r2,0
+     3ec:	200b883a 	mov	r5,r4
+     3f0:	111c8117 	ldw	r4,29188(r2)
+     3f4:	000031c1 	jmpi	31c <_puts_r>
+
+000003f8 <strlen>:
+     3f8:	208000cc 	andi	r2,r4,3
+     3fc:	10000926 	beq	r2,zero,424 <strlen+0x2c>
+     400:	2005883a 	mov	r2,r4
+     404:	00000306 	br	414 <strlen+0x1c>
+     408:	10800044 	addi	r2,r2,1
+     40c:	10c000cc 	andi	r3,r2,3
+     410:	18000526 	beq	r3,zero,428 <strlen+0x30>
+     414:	10c00007 	ldb	r3,0(r2)
+     418:	183ffb1e 	bne	r3,zero,408 <strlen+0x10>
+     41c:	1105c83a 	sub	r2,r2,r4
+     420:	f800283a 	ret
+     424:	2005883a 	mov	r2,r4
+     428:	11400017 	ldw	r5,0(r2)
+     42c:	01ffbff4 	movhi	r7,65279
+     430:	39ffbfc4 	addi	r7,r7,-257
+     434:	29c7883a 	add	r3,r5,r7
+     438:	01a02074 	movhi	r6,32897
+     43c:	014a303a 	nor	r5,zero,r5
+     440:	1946703a 	and	r3,r3,r5
+     444:	31a02004 	addi	r6,r6,-32640
+     448:	1986703a 	and	r3,r3,r6
+     44c:	1800071e 	bne	r3,zero,46c <strlen+0x74>
+     450:	11400117 	ldw	r5,4(r2)
+     454:	10800104 	addi	r2,r2,4
+     458:	29c7883a 	add	r3,r5,r7
+     45c:	014a303a 	nor	r5,zero,r5
+     460:	1946703a 	and	r3,r3,r5
+     464:	1986703a 	and	r3,r3,r6
+     468:	183ff926 	beq	r3,zero,450 <strlen+0x58>
+     46c:	10c00007 	ldb	r3,0(r2)
+     470:	183fea26 	beq	r3,zero,41c <strlen+0x24>
+     474:	10c00047 	ldb	r3,1(r2)
+     478:	10800044 	addi	r2,r2,1
+     47c:	183fe726 	beq	r3,zero,41c <strlen+0x24>
+     480:	10c00047 	ldb	r3,1(r2)
+     484:	10800044 	addi	r2,r2,1
+     488:	183ffa1e 	bne	r3,zero,474 <strlen+0x7c>
+     48c:	003fe306 	br	41c <strlen+0x24>
+
+00000490 <__fp_lock>:
+     490:	0005883a 	mov	r2,zero
+     494:	f800283a 	ret
+
+00000498 <_cleanup_r>:
+     498:	01400034 	movhi	r5,0
+     49c:	2948fb04 	addi	r5,r5,9196
+     4a0:	0000d9c1 	jmpi	d9c <_fwalk_reent>
+
+000004a4 <__fp_unlock>:
+     4a4:	0005883a 	mov	r2,zero
+     4a8:	f800283a 	ret
+
+000004ac <__sinit.part.0>:
+     4ac:	00c00034 	movhi	r3,0
+     4b0:	20800117 	ldw	r2,4(r4)
+     4b4:	18c12604 	addi	r3,r3,1176
+     4b8:	20c00f15 	stw	r3,60(r4)
+     4bc:	2140bb04 	addi	r5,r4,748
+     4c0:	00c000c4 	movi	r3,3
+     4c4:	20c0b915 	stw	r3,740(r4)
+     4c8:	2140ba15 	stw	r5,744(r4)
+     4cc:	2000b815 	stw	zero,736(r4)
+     4d0:	10001705 	stb	zero,92(r2)
+     4d4:	10001745 	stb	zero,93(r2)
+     4d8:	10001785 	stb	zero,94(r2)
+     4dc:	100017c5 	stb	zero,95(r2)
+     4e0:	10001805 	stb	zero,96(r2)
+     4e4:	10001845 	stb	zero,97(r2)
+     4e8:	10001885 	stb	zero,98(r2)
+     4ec:	100018c5 	stb	zero,99(r2)
+     4f0:	00c00104 	movi	r3,4
+     4f4:	10c00315 	stw	r3,12(r2)
+     4f8:	02000034 	movhi	r8,0
+     4fc:	20c00217 	ldw	r3,8(r4)
+     500:	01c00034 	movhi	r7,0
+     504:	01800034 	movhi	r6,0
+     508:	01400034 	movhi	r5,0
+     50c:	4207f304 	addi	r8,r8,8140
+     510:	39c80a04 	addi	r7,r7,8232
+     514:	31882a04 	addi	r6,r6,8360
+     518:	29484104 	addi	r5,r5,8452
+     51c:	02400074 	movhi	r9,1
+     520:	10001915 	stw	zero,100(r2)
+     524:	10000015 	stw	zero,0(r2)
+     528:	10000115 	stw	zero,4(r2)
+     52c:	10000215 	stw	zero,8(r2)
+     530:	10000415 	stw	zero,16(r2)
+     534:	10000515 	stw	zero,20(r2)
+     538:	10000615 	stw	zero,24(r2)
+     53c:	10800715 	stw	r2,28(r2)
+     540:	12000815 	stw	r8,32(r2)
+     544:	11c00915 	stw	r7,36(r2)
+     548:	11800a15 	stw	r6,40(r2)
+     54c:	11400b15 	stw	r5,44(r2)
+     550:	4a400284 	addi	r9,r9,10
+     554:	1a400315 	stw	r9,12(r3)
+     558:	18001915 	stw	zero,100(r3)
+     55c:	18000015 	stw	zero,0(r3)
+     560:	18000115 	stw	zero,4(r3)
+     564:	18000215 	stw	zero,8(r3)
+     568:	18000415 	stw	zero,16(r3)
+     56c:	18001705 	stb	zero,92(r3)
+     570:	18001745 	stb	zero,93(r3)
+     574:	18001785 	stb	zero,94(r3)
+     578:	180017c5 	stb	zero,95(r3)
+     57c:	18001805 	stb	zero,96(r3)
+     580:	18001845 	stb	zero,97(r3)
+     584:	18001885 	stb	zero,98(r3)
+     588:	180018c5 	stb	zero,99(r3)
+     58c:	20800317 	ldw	r2,12(r4)
+     590:	024000b4 	movhi	r9,2
+     594:	18000515 	stw	zero,20(r3)
+     598:	18000615 	stw	zero,24(r3)
+     59c:	18c00715 	stw	r3,28(r3)
+     5a0:	1a000815 	stw	r8,32(r3)
+     5a4:	19c00915 	stw	r7,36(r3)
+     5a8:	19800a15 	stw	r6,40(r3)
+     5ac:	19400b15 	stw	r5,44(r3)
+     5b0:	4a400484 	addi	r9,r9,18
+     5b4:	10001915 	stw	zero,100(r2)
+     5b8:	10000015 	stw	zero,0(r2)
+     5bc:	10000115 	stw	zero,4(r2)
+     5c0:	10000215 	stw	zero,8(r2)
+     5c4:	12400315 	stw	r9,12(r2)
+     5c8:	10000415 	stw	zero,16(r2)
+     5cc:	10000515 	stw	zero,20(r2)
+     5d0:	10000615 	stw	zero,24(r2)
+     5d4:	10001705 	stb	zero,92(r2)
+     5d8:	10001745 	stb	zero,93(r2)
+     5dc:	10001785 	stb	zero,94(r2)
+     5e0:	100017c5 	stb	zero,95(r2)
+     5e4:	10001805 	stb	zero,96(r2)
+     5e8:	10001845 	stb	zero,97(r2)
+     5ec:	10001885 	stb	zero,98(r2)
+     5f0:	100018c5 	stb	zero,99(r2)
+     5f4:	10800715 	stw	r2,28(r2)
+     5f8:	12000815 	stw	r8,32(r2)
+     5fc:	11c00915 	stw	r7,36(r2)
+     600:	11800a15 	stw	r6,40(r2)
+     604:	11400b15 	stw	r5,44(r2)
+     608:	00800044 	movi	r2,1
+     60c:	20800e15 	stw	r2,56(r4)
+     610:	f800283a 	ret
+
+00000614 <__sfmoreglue>:
+     614:	defffc04 	addi	sp,sp,-16
+     618:	dc800215 	stw	r18,8(sp)
+     61c:	2825883a 	mov	r18,r5
+     620:	dc000015 	stw	r16,0(sp)
+     624:	01401a04 	movi	r5,104
+     628:	2021883a 	mov	r16,r4
+     62c:	913fffc4 	addi	r4,r18,-1
+     630:	dfc00315 	stw	ra,12(sp)
+     634:	dc400115 	stw	r17,4(sp)
+     638:	000316c0 	call	316c <__mulsi3>
+     63c:	8009883a 	mov	r4,r16
+     640:	11401d04 	addi	r5,r2,116
+     644:	1023883a 	mov	r17,r2
+     648:	0000e440 	call	e44 <_malloc_r>
+     64c:	1021883a 	mov	r16,r2
+     650:	10000726 	beq	r2,zero,670 <__sfmoreglue+0x5c>
+     654:	11000304 	addi	r4,r2,12
+     658:	10000015 	stw	zero,0(r2)
+     65c:	14800115 	stw	r18,4(r2)
+     660:	11000215 	stw	r4,8(r2)
+     664:	89801a04 	addi	r6,r17,104
+     668:	000b883a 	mov	r5,zero
+     66c:	00019200 	call	1920 <memset>
+     670:	8005883a 	mov	r2,r16
+     674:	dfc00317 	ldw	ra,12(sp)
+     678:	dc800217 	ldw	r18,8(sp)
+     67c:	dc400117 	ldw	r17,4(sp)
+     680:	dc000017 	ldw	r16,0(sp)
+     684:	dec00404 	addi	sp,sp,16
+     688:	f800283a 	ret
+
+0000068c <__sfp>:
+     68c:	defffb04 	addi	sp,sp,-20
+     690:	00800034 	movhi	r2,0
+     694:	dc000015 	stw	r16,0(sp)
+     698:	141c8017 	ldw	r16,29184(r2)
+     69c:	dc400115 	stw	r17,4(sp)
+     6a0:	dfc00415 	stw	ra,16(sp)
+     6a4:	80800e17 	ldw	r2,56(r16)
+     6a8:	dcc00315 	stw	r19,12(sp)
+     6ac:	dc800215 	stw	r18,8(sp)
+     6b0:	2023883a 	mov	r17,r4
+     6b4:	10003126 	beq	r2,zero,77c <__sfp+0xf0>
+     6b8:	8100ba17 	ldw	r4,744(r16)
+     6bc:	8140b917 	ldw	r5,740(r16)
+     6c0:	04c00104 	movi	r19,4
+     6c4:	8400b804 	addi	r16,r16,736
+     6c8:	297fffc4 	addi	r5,r5,-1
+     6cc:	2800050e 	bge	r5,zero,6e4 <__sfp+0x58>
+     6d0:	00002406 	br	764 <__sfp+0xd8>
+     6d4:	297fffc4 	addi	r5,r5,-1
+     6d8:	28bfffd8 	cmpnei	r2,r5,-1
+     6dc:	21001a04 	addi	r4,r4,104
+     6e0:	10002026 	beq	r2,zero,764 <__sfp+0xd8>
+     6e4:	2080030f 	ldh	r2,12(r4)
+     6e8:	103ffa1e 	bne	r2,zero,6d4 <__sfp+0x48>
+     6ec:	00bffff4 	movhi	r2,65535
+     6f0:	10800044 	addi	r2,r2,1
+     6f4:	20001915 	stw	zero,100(r4)
+     6f8:	20000015 	stw	zero,0(r4)
+     6fc:	20000115 	stw	zero,4(r4)
+     700:	20000215 	stw	zero,8(r4)
+     704:	20800315 	stw	r2,12(r4)
+     708:	20000415 	stw	zero,16(r4)
+     70c:	20000515 	stw	zero,20(r4)
+     710:	20000615 	stw	zero,24(r4)
+     714:	20001705 	stb	zero,92(r4)
+     718:	20001745 	stb	zero,93(r4)
+     71c:	20001785 	stb	zero,94(r4)
+     720:	200017c5 	stb	zero,95(r4)
+     724:	20001805 	stb	zero,96(r4)
+     728:	20001845 	stb	zero,97(r4)
+     72c:	20001885 	stb	zero,98(r4)
+     730:	200018c5 	stb	zero,99(r4)
+     734:	20000c15 	stw	zero,48(r4)
+     738:	20000d15 	stw	zero,52(r4)
+     73c:	20001115 	stw	zero,68(r4)
+     740:	20001215 	stw	zero,72(r4)
+     744:	2005883a 	mov	r2,r4
+     748:	dfc00417 	ldw	ra,16(sp)
+     74c:	dcc00317 	ldw	r19,12(sp)
+     750:	dc800217 	ldw	r18,8(sp)
+     754:	dc400117 	ldw	r17,4(sp)
+     758:	dc000017 	ldw	r16,0(sp)
+     75c:	dec00504 	addi	sp,sp,20
+     760:	f800283a 	ret
+     764:	80800017 	ldw	r2,0(r16)
+     768:	10000726 	beq	r2,zero,788 <__sfp+0xfc>
+     76c:	11000217 	ldw	r4,8(r2)
+     770:	11400117 	ldw	r5,4(r2)
+     774:	1021883a 	mov	r16,r2
+     778:	003fd306 	br	6c8 <__sfp+0x3c>
+     77c:	8009883a 	mov	r4,r16
+     780:	00004ac0 	call	4ac <__sinit.part.0>
+     784:	003fcc06 	br	6b8 <__sfp+0x2c>
+     788:	01406b04 	movi	r5,428
+     78c:	8809883a 	mov	r4,r17
+     790:	0000e440 	call	e44 <_malloc_r>
+     794:	1025883a 	mov	r18,r2
+     798:	10000c26 	beq	r2,zero,7cc <__sfp+0x140>
+     79c:	11000304 	addi	r4,r2,12
+     7a0:	11000215 	stw	r4,8(r2)
+     7a4:	000b883a 	mov	r5,zero
+     7a8:	10000015 	stw	zero,0(r2)
+     7ac:	14c00115 	stw	r19,4(r2)
+     7b0:	01806804 	movi	r6,416
+     7b4:	00019200 	call	1920 <memset>
+     7b8:	1009883a 	mov	r4,r2
+     7bc:	84800015 	stw	r18,0(r16)
+     7c0:	014000c4 	movi	r5,3
+     7c4:	9021883a 	mov	r16,r18
+     7c8:	003fc606 	br	6e4 <__sfp+0x58>
+     7cc:	80000015 	stw	zero,0(r16)
+     7d0:	00800304 	movi	r2,12
+     7d4:	88800015 	stw	r2,0(r17)
+     7d8:	0009883a 	mov	r4,zero
+     7dc:	003fd906 	br	744 <__sfp+0xb8>
+
+000007e0 <_cleanup>:
+     7e0:	00800034 	movhi	r2,0
+     7e4:	111c8017 	ldw	r4,29184(r2)
+     7e8:	01400034 	movhi	r5,0
+     7ec:	2948fb04 	addi	r5,r5,9196
+     7f0:	0000d9c1 	jmpi	d9c <_fwalk_reent>
+
+000007f4 <__sinit>:
+     7f4:	20800e17 	ldw	r2,56(r4)
+     7f8:	10000126 	beq	r2,zero,800 <__sinit+0xc>
+     7fc:	f800283a 	ret
+     800:	00004ac1 	jmpi	4ac <__sinit.part.0>
+
+00000804 <__sfp_lock_acquire>:
+     804:	f800283a 	ret
+
+00000808 <__sfp_lock_release>:
+     808:	f800283a 	ret
+
+0000080c <__sinit_lock_acquire>:
+     80c:	f800283a 	ret
+
+00000810 <__sinit_lock_release>:
+     810:	f800283a 	ret
+
+00000814 <__fp_lock_all>:
+     814:	00800034 	movhi	r2,0
+     818:	111c8117 	ldw	r4,29188(r2)
+     81c:	01400034 	movhi	r5,0
+     820:	29412404 	addi	r5,r5,1168
+     824:	0000d041 	jmpi	d04 <_fwalk>
+
+00000828 <__fp_unlock_all>:
+     828:	00800034 	movhi	r2,0
+     82c:	111c8117 	ldw	r4,29188(r2)
+     830:	01400034 	movhi	r5,0
+     834:	29412904 	addi	r5,r5,1188
+     838:	0000d041 	jmpi	d04 <_fwalk>
+
+0000083c <__sfvwrite_r>:
+     83c:	30800217 	ldw	r2,8(r6)
+     840:	1000a326 	beq	r2,zero,ad0 <__sfvwrite_r+0x294>
+     844:	29c0030b 	ldhu	r7,12(r5)
+     848:	defff404 	addi	sp,sp,-48
+     84c:	ddc00915 	stw	r23,36(sp)
+     850:	dd400715 	stw	r21,28(sp)
+     854:	dc000215 	stw	r16,8(sp)
+     858:	dfc00b15 	stw	ra,44(sp)
+     85c:	df000a15 	stw	fp,40(sp)
+     860:	dd800815 	stw	r22,32(sp)
+     864:	dd000615 	stw	r20,24(sp)
+     868:	dcc00515 	stw	r19,20(sp)
+     86c:	dc800415 	stw	r18,16(sp)
+     870:	dc400315 	stw	r17,12(sp)
+     874:	3880020c 	andi	r2,r7,8
+     878:	302f883a 	mov	r23,r6
+     87c:	202b883a 	mov	r21,r4
+     880:	2821883a 	mov	r16,r5
+     884:	10002226 	beq	r2,zero,910 <__sfvwrite_r+0xd4>
+     888:	28800417 	ldw	r2,16(r5)
+     88c:	10002026 	beq	r2,zero,910 <__sfvwrite_r+0xd4>
+     890:	3880008c 	andi	r2,r7,2
+     894:	bc400017 	ldw	r17,0(r23)
+     898:	10002526 	beq	r2,zero,930 <__sfvwrite_r+0xf4>
+     89c:	80800917 	ldw	r2,36(r16)
+     8a0:	81400717 	ldw	r5,28(r16)
+     8a4:	05200034 	movhi	r20,32768
+     8a8:	0027883a 	mov	r19,zero
+     8ac:	0025883a 	mov	r18,zero
+     8b0:	a53f0004 	addi	r20,r20,-1024
+     8b4:	980d883a 	mov	r6,r19
+     8b8:	a809883a 	mov	r4,r21
+     8bc:	90001026 	beq	r18,zero,900 <__sfvwrite_r+0xc4>
+     8c0:	900f883a 	mov	r7,r18
+     8c4:	a480012e 	bgeu	r20,r18,8cc <__sfvwrite_r+0x90>
+     8c8:	a00f883a 	mov	r7,r20
+     8cc:	103ee83a 	callr	r2
+     8d0:	00807a0e 	bge	zero,r2,abc <__sfvwrite_r+0x280>
+     8d4:	b9000217 	ldw	r4,8(r23)
+     8d8:	98a7883a 	add	r19,r19,r2
+     8dc:	90a5c83a 	sub	r18,r18,r2
+     8e0:	2085c83a 	sub	r2,r4,r2
+     8e4:	b8800215 	stw	r2,8(r23)
+     8e8:	10006326 	beq	r2,zero,a78 <__sfvwrite_r+0x23c>
+     8ec:	80800917 	ldw	r2,36(r16)
+     8f0:	81400717 	ldw	r5,28(r16)
+     8f4:	980d883a 	mov	r6,r19
+     8f8:	a809883a 	mov	r4,r21
+     8fc:	903ff01e 	bne	r18,zero,8c0 <__sfvwrite_r+0x84>
+     900:	8cc00017 	ldw	r19,0(r17)
+     904:	8c800117 	ldw	r18,4(r17)
+     908:	8c400204 	addi	r17,r17,8
+     90c:	003fe906 	br	8b4 <__sfvwrite_r+0x78>
+     910:	800b883a 	mov	r5,r16
+     914:	a809883a 	mov	r4,r21
+     918:	00021700 	call	2170 <__swsetup_r>
+     91c:	1000f71e 	bne	r2,zero,cfc <__sfvwrite_r+0x4c0>
+     920:	81c0030b 	ldhu	r7,12(r16)
+     924:	bc400017 	ldw	r17,0(r23)
+     928:	3880008c 	andi	r2,r7,2
+     92c:	103fdb1e 	bne	r2,zero,89c <__sfvwrite_r+0x60>
+     930:	3880004c 	andi	r2,r7,1
+     934:	84800217 	ldw	r18,8(r16)
+     938:	82000017 	ldw	r8,0(r16)
+     93c:	1000661e 	bne	r2,zero,ad8 <__sfvwrite_r+0x29c>
+     940:	00a00034 	movhi	r2,32768
+     944:	10bfff84 	addi	r2,r2,-2
+     948:	00e00034 	movhi	r3,32768
+     94c:	d8800015 	stw	r2,0(sp)
+     950:	18bfffc4 	addi	r2,r3,-1
+     954:	0039883a 	mov	fp,zero
+     958:	0027883a 	mov	r19,zero
+     95c:	d8800115 	stw	r2,4(sp)
+     960:	98004126 	beq	r19,zero,a68 <__sfvwrite_r+0x22c>
+     964:	3880800c 	andi	r2,r7,512
+     968:	10009726 	beq	r2,zero,bc8 <__sfvwrite_r+0x38c>
+     96c:	902d883a 	mov	r22,r18
+     970:	9c80be36 	bltu	r19,r18,c6c <__sfvwrite_r+0x430>
+     974:	3881200c 	andi	r2,r7,1152
+     978:	10002626 	beq	r2,zero,a14 <__sfvwrite_r+0x1d8>
+     97c:	81800517 	ldw	r6,20(r16)
+     980:	81400417 	ldw	r5,16(r16)
+     984:	98800044 	addi	r2,r19,1
+     988:	3189883a 	add	r4,r6,r6
+     98c:	2189883a 	add	r4,r4,r6
+     990:	2028d7fa 	srli	r20,r4,31
+     994:	4165c83a 	sub	r18,r8,r5
+     998:	1485883a 	add	r2,r2,r18
+     99c:	a109883a 	add	r4,r20,r4
+     9a0:	2029d07a 	srai	r20,r4,1
+     9a4:	a00d883a 	mov	r6,r20
+     9a8:	a080022e 	bgeu	r20,r2,9b4 <__sfvwrite_r+0x178>
+     9ac:	1029883a 	mov	r20,r2
+     9b0:	100d883a 	mov	r6,r2
+     9b4:	39c1000c 	andi	r7,r7,1024
+     9b8:	3800c026 	beq	r7,zero,cbc <__sfvwrite_r+0x480>
+     9bc:	a809883a 	mov	r4,r21
+     9c0:	300b883a 	mov	r5,r6
+     9c4:	0000e440 	call	e44 <_malloc_r>
+     9c8:	1009883a 	mov	r4,r2
+     9cc:	1000c726 	beq	r2,zero,cec <__sfvwrite_r+0x4b0>
+     9d0:	81400417 	ldw	r5,16(r16)
+     9d4:	900d883a 	mov	r6,r18
+     9d8:	00016f40 	call	16f4 <memcpy>
+     9dc:	1009883a 	mov	r4,r2
+     9e0:	8080030b 	ldhu	r2,12(r16)
+     9e4:	00fedfc4 	movi	r3,-1153
+     9e8:	10c4703a 	and	r2,r2,r3
+     9ec:	10802014 	ori	r2,r2,128
+     9f0:	8080030d 	sth	r2,12(r16)
+     9f4:	2491883a 	add	r8,r4,r18
+     9f8:	a485c83a 	sub	r2,r20,r18
+     9fc:	81000415 	stw	r4,16(r16)
+     a00:	82000015 	stw	r8,0(r16)
+     a04:	85000515 	stw	r20,20(r16)
+     a08:	9825883a 	mov	r18,r19
+     a0c:	80800215 	stw	r2,8(r16)
+     a10:	982d883a 	mov	r22,r19
+     a14:	4009883a 	mov	r4,r8
+     a18:	b00d883a 	mov	r6,r22
+     a1c:	e00b883a 	mov	r5,fp
+     a20:	00017f40 	call	17f4 <memmove>
+     a24:	81000217 	ldw	r4,8(r16)
+     a28:	80800017 	ldw	r2,0(r16)
+     a2c:	9829883a 	mov	r20,r19
+     a30:	24a5c83a 	sub	r18,r4,r18
+     a34:	1585883a 	add	r2,r2,r22
+     a38:	84800215 	stw	r18,8(r16)
+     a3c:	80800015 	stw	r2,0(r16)
+     a40:	0027883a 	mov	r19,zero
+     a44:	b8800217 	ldw	r2,8(r23)
+     a48:	e539883a 	add	fp,fp,r20
+     a4c:	1529c83a 	sub	r20,r2,r20
+     a50:	bd000215 	stw	r20,8(r23)
+     a54:	a0000826 	beq	r20,zero,a78 <__sfvwrite_r+0x23c>
+     a58:	81c0030b 	ldhu	r7,12(r16)
+     a5c:	84800217 	ldw	r18,8(r16)
+     a60:	82000017 	ldw	r8,0(r16)
+     a64:	983fbf1e 	bne	r19,zero,964 <__sfvwrite_r+0x128>
+     a68:	8f000017 	ldw	fp,0(r17)
+     a6c:	8cc00117 	ldw	r19,4(r17)
+     a70:	8c400204 	addi	r17,r17,8
+     a74:	003fba06 	br	960 <__sfvwrite_r+0x124>
+     a78:	0005883a 	mov	r2,zero
+     a7c:	dfc00b17 	ldw	ra,44(sp)
+     a80:	df000a17 	ldw	fp,40(sp)
+     a84:	ddc00917 	ldw	r23,36(sp)
+     a88:	dd800817 	ldw	r22,32(sp)
+     a8c:	dd400717 	ldw	r21,28(sp)
+     a90:	dd000617 	ldw	r20,24(sp)
+     a94:	dcc00517 	ldw	r19,20(sp)
+     a98:	dc800417 	ldw	r18,16(sp)
+     a9c:	dc400317 	ldw	r17,12(sp)
+     aa0:	dc000217 	ldw	r16,8(sp)
+     aa4:	dec00c04 	addi	sp,sp,48
+     aa8:	f800283a 	ret
+     aac:	800b883a 	mov	r5,r16
+     ab0:	a809883a 	mov	r4,r21
+     ab4:	00026f40 	call	26f4 <_fflush_r>
+     ab8:	10002026 	beq	r2,zero,b3c <__sfvwrite_r+0x300>
+     abc:	8080030b 	ldhu	r2,12(r16)
+     ac0:	10801014 	ori	r2,r2,64
+     ac4:	8080030d 	sth	r2,12(r16)
+     ac8:	00bfffc4 	movi	r2,-1
+     acc:	003feb06 	br	a7c <__sfvwrite_r+0x240>
+     ad0:	0005883a 	mov	r2,zero
+     ad4:	f800283a 	ret
+     ad8:	002d883a 	mov	r22,zero
+     adc:	0027883a 	mov	r19,zero
+     ae0:	0005883a 	mov	r2,zero
+     ae4:	0039883a 	mov	fp,zero
+     ae8:	b0001d26 	beq	r22,zero,b60 <__sfvwrite_r+0x324>
+     aec:	10002026 	beq	r2,zero,b70 <__sfvwrite_r+0x334>
+     af0:	9829883a 	mov	r20,r19
+     af4:	b500012e 	bgeu	r22,r20,afc <__sfvwrite_r+0x2c0>
+     af8:	b029883a 	mov	r20,r22
+     afc:	80800417 	ldw	r2,16(r16)
+     b00:	81c00517 	ldw	r7,20(r16)
+     b04:	1200022e 	bgeu	r2,r8,b10 <__sfvwrite_r+0x2d4>
+     b08:	3ca5883a 	add	r18,r7,r18
+     b0c:	95002216 	blt	r18,r20,b98 <__sfvwrite_r+0x35c>
+     b10:	a1c05916 	blt	r20,r7,c78 <__sfvwrite_r+0x43c>
+     b14:	80800917 	ldw	r2,36(r16)
+     b18:	81400717 	ldw	r5,28(r16)
+     b1c:	e00d883a 	mov	r6,fp
+     b20:	a809883a 	mov	r4,r21
+     b24:	103ee83a 	callr	r2
+     b28:	1025883a 	mov	r18,r2
+     b2c:	00bfe30e 	bge	zero,r2,abc <__sfvwrite_r+0x280>
+     b30:	9ca7c83a 	sub	r19,r19,r18
+     b34:	983fdd26 	beq	r19,zero,aac <__sfvwrite_r+0x270>
+     b38:	00800044 	movi	r2,1
+     b3c:	b9800217 	ldw	r6,8(r23)
+     b40:	e4b9883a 	add	fp,fp,r18
+     b44:	b4adc83a 	sub	r22,r22,r18
+     b48:	34a5c83a 	sub	r18,r6,r18
+     b4c:	bc800215 	stw	r18,8(r23)
+     b50:	903fc926 	beq	r18,zero,a78 <__sfvwrite_r+0x23c>
+     b54:	84800217 	ldw	r18,8(r16)
+     b58:	82000017 	ldw	r8,0(r16)
+     b5c:	b03fe31e 	bne	r22,zero,aec <__sfvwrite_r+0x2b0>
+     b60:	8d800117 	ldw	r22,4(r17)
+     b64:	8f000017 	ldw	fp,0(r17)
+     b68:	8c400204 	addi	r17,r17,8
+     b6c:	b03ffc26 	beq	r22,zero,b60 <__sfvwrite_r+0x324>
+     b70:	b00d883a 	mov	r6,r22
+     b74:	01400284 	movi	r5,10
+     b78:	e009883a 	mov	r4,fp
+     b7c:	da000015 	stw	r8,0(sp)
+     b80:	00016240 	call	1624 <memchr>
+     b84:	da000017 	ldw	r8,0(sp)
+     b88:	10004926 	beq	r2,zero,cb0 <__sfvwrite_r+0x474>
+     b8c:	10800044 	addi	r2,r2,1
+     b90:	1727c83a 	sub	r19,r2,fp
+     b94:	003fd606 	br	af0 <__sfvwrite_r+0x2b4>
+     b98:	e00b883a 	mov	r5,fp
+     b9c:	4009883a 	mov	r4,r8
+     ba0:	900d883a 	mov	r6,r18
+     ba4:	00017f40 	call	17f4 <memmove>
+     ba8:	80800017 	ldw	r2,0(r16)
+     bac:	800b883a 	mov	r5,r16
+     bb0:	a809883a 	mov	r4,r21
+     bb4:	1485883a 	add	r2,r2,r18
+     bb8:	80800015 	stw	r2,0(r16)
+     bbc:	00026f40 	call	26f4 <_fflush_r>
+     bc0:	103fdb26 	beq	r2,zero,b30 <__sfvwrite_r+0x2f4>
+     bc4:	003fbd06 	br	abc <__sfvwrite_r+0x280>
+     bc8:	80800417 	ldw	r2,16(r16)
+     bcc:	12001436 	bltu	r2,r8,c20 <__sfvwrite_r+0x3e4>
+     bd0:	85000517 	ldw	r20,20(r16)
+     bd4:	9d001236 	bltu	r19,r20,c20 <__sfvwrite_r+0x3e4>
+     bd8:	d8800017 	ldw	r2,0(sp)
+     bdc:	14c0322e 	bgeu	r2,r19,ca8 <__sfvwrite_r+0x46c>
+     be0:	d9000117 	ldw	r4,4(sp)
+     be4:	a00b883a 	mov	r5,r20
+     be8:	0002fb80 	call	2fb8 <__divsi3>
+     bec:	a00b883a 	mov	r5,r20
+     bf0:	1009883a 	mov	r4,r2
+     bf4:	000316c0 	call	316c <__mulsi3>
+     bf8:	82000917 	ldw	r8,36(r16)
+     bfc:	81400717 	ldw	r5,28(r16)
+     c00:	100f883a 	mov	r7,r2
+     c04:	e00d883a 	mov	r6,fp
+     c08:	a809883a 	mov	r4,r21
+     c0c:	403ee83a 	callr	r8
+     c10:	1029883a 	mov	r20,r2
+     c14:	00bfa90e 	bge	zero,r2,abc <__sfvwrite_r+0x280>
+     c18:	9d27c83a 	sub	r19,r19,r20
+     c1c:	003f8906 	br	a44 <__sfvwrite_r+0x208>
+     c20:	9029883a 	mov	r20,r18
+     c24:	9c80012e 	bgeu	r19,r18,c2c <__sfvwrite_r+0x3f0>
+     c28:	9829883a 	mov	r20,r19
+     c2c:	4009883a 	mov	r4,r8
+     c30:	a00d883a 	mov	r6,r20
+     c34:	e00b883a 	mov	r5,fp
+     c38:	00017f40 	call	17f4 <memmove>
+     c3c:	80800217 	ldw	r2,8(r16)
+     c40:	81000017 	ldw	r4,0(r16)
+     c44:	1505c83a 	sub	r2,r2,r20
+     c48:	2509883a 	add	r4,r4,r20
+     c4c:	80800215 	stw	r2,8(r16)
+     c50:	81000015 	stw	r4,0(r16)
+     c54:	103ff01e 	bne	r2,zero,c18 <__sfvwrite_r+0x3dc>
+     c58:	800b883a 	mov	r5,r16
+     c5c:	a809883a 	mov	r4,r21
+     c60:	00026f40 	call	26f4 <_fflush_r>
+     c64:	103fec26 	beq	r2,zero,c18 <__sfvwrite_r+0x3dc>
+     c68:	003f9406 	br	abc <__sfvwrite_r+0x280>
+     c6c:	9825883a 	mov	r18,r19
+     c70:	982d883a 	mov	r22,r19
+     c74:	003f6706 	br	a14 <__sfvwrite_r+0x1d8>
+     c78:	4009883a 	mov	r4,r8
+     c7c:	a00d883a 	mov	r6,r20
+     c80:	e00b883a 	mov	r5,fp
+     c84:	00017f40 	call	17f4 <memmove>
+     c88:	81000217 	ldw	r4,8(r16)
+     c8c:	80800017 	ldw	r2,0(r16)
+     c90:	a025883a 	mov	r18,r20
+     c94:	2509c83a 	sub	r4,r4,r20
+     c98:	1505883a 	add	r2,r2,r20
+     c9c:	81000215 	stw	r4,8(r16)
+     ca0:	80800015 	stw	r2,0(r16)
+     ca4:	003fa206 	br	b30 <__sfvwrite_r+0x2f4>
+     ca8:	9809883a 	mov	r4,r19
+     cac:	003fcd06 	br	be4 <__sfvwrite_r+0x3a8>
+     cb0:	b5000044 	addi	r20,r22,1
+     cb4:	a027883a 	mov	r19,r20
+     cb8:	003f8e06 	br	af4 <__sfvwrite_r+0x2b8>
+     cbc:	a809883a 	mov	r4,r21
+     cc0:	0001a100 	call	1a10 <_realloc_r>
+     cc4:	1009883a 	mov	r4,r2
+     cc8:	103f4a1e 	bne	r2,zero,9f4 <__sfvwrite_r+0x1b8>
+     ccc:	81400417 	ldw	r5,16(r16)
+     cd0:	a809883a 	mov	r4,r21
+     cd4:	00028f40 	call	28f4 <_free_r>
+     cd8:	8080030b 	ldhu	r2,12(r16)
+     cdc:	00c00304 	movi	r3,12
+     ce0:	a8c00015 	stw	r3,0(r21)
+     ce4:	10bfdfcc 	andi	r2,r2,65407
+     ce8:	003f7506 	br	ac0 <__sfvwrite_r+0x284>
+     cec:	00c00304 	movi	r3,12
+     cf0:	8080030b 	ldhu	r2,12(r16)
+     cf4:	a8c00015 	stw	r3,0(r21)
+     cf8:	003f7106 	br	ac0 <__sfvwrite_r+0x284>
+     cfc:	00bfffc4 	movi	r2,-1
+     d00:	003f5e06 	br	a7c <__sfvwrite_r+0x240>
+
+00000d04 <_fwalk>:
+     d04:	defffa04 	addi	sp,sp,-24
+     d08:	dd000415 	stw	r20,16(sp)
+     d0c:	dcc00315 	stw	r19,12(sp)
+     d10:	dc800215 	stw	r18,8(sp)
+     d14:	dfc00515 	stw	ra,20(sp)
+     d18:	dc400115 	stw	r17,4(sp)
+     d1c:	dc000015 	stw	r16,0(sp)
+     d20:	2827883a 	mov	r19,r5
+     d24:	2480b804 	addi	r18,r4,736
+     d28:	0029883a 	mov	r20,zero
+     d2c:	94400117 	ldw	r17,4(r18)
+     d30:	94000217 	ldw	r16,8(r18)
+     d34:	8c7fffc4 	addi	r17,r17,-1
+     d38:	88000d16 	blt	r17,zero,d70 <_fwalk+0x6c>
+     d3c:	8080030b 	ldhu	r2,12(r16)
+     d40:	8c7fffc4 	addi	r17,r17,-1
+     d44:	108000b0 	cmpltui	r2,r2,2
+     d48:	1000061e 	bne	r2,zero,d64 <_fwalk+0x60>
+     d4c:	8080038f 	ldh	r2,14(r16)
+     d50:	8009883a 	mov	r4,r16
+     d54:	10bfffe0 	cmpeqi	r2,r2,-1
+     d58:	1000021e 	bne	r2,zero,d64 <_fwalk+0x60>
+     d5c:	983ee83a 	callr	r19
+     d60:	a0a8b03a 	or	r20,r20,r2
+     d64:	88bfffd8 	cmpnei	r2,r17,-1
+     d68:	84001a04 	addi	r16,r16,104
+     d6c:	103ff31e 	bne	r2,zero,d3c <_fwalk+0x38>
+     d70:	94800017 	ldw	r18,0(r18)
+     d74:	903fed1e 	bne	r18,zero,d2c <_fwalk+0x28>
+     d78:	a005883a 	mov	r2,r20
+     d7c:	dfc00517 	ldw	ra,20(sp)
+     d80:	dd000417 	ldw	r20,16(sp)
+     d84:	dcc00317 	ldw	r19,12(sp)
+     d88:	dc800217 	ldw	r18,8(sp)
+     d8c:	dc400117 	ldw	r17,4(sp)
+     d90:	dc000017 	ldw	r16,0(sp)
+     d94:	dec00604 	addi	sp,sp,24
+     d98:	f800283a 	ret
+
+00000d9c <_fwalk_reent>:
+     d9c:	defff904 	addi	sp,sp,-28
+     da0:	dd400515 	stw	r21,20(sp)
+     da4:	dd000415 	stw	r20,16(sp)
+     da8:	dcc00315 	stw	r19,12(sp)
+     dac:	dc800215 	stw	r18,8(sp)
+     db0:	dfc00615 	stw	ra,24(sp)
+     db4:	dc400115 	stw	r17,4(sp)
+     db8:	dc000015 	stw	r16,0(sp)
+     dbc:	202b883a 	mov	r21,r4
+     dc0:	2827883a 	mov	r19,r5
+     dc4:	2480b804 	addi	r18,r4,736
+     dc8:	0029883a 	mov	r20,zero
+     dcc:	94400117 	ldw	r17,4(r18)
+     dd0:	94000217 	ldw	r16,8(r18)
+     dd4:	8c7fffc4 	addi	r17,r17,-1
+     dd8:	88000e16 	blt	r17,zero,e14 <_fwalk_reent+0x78>
+     ddc:	8080030b 	ldhu	r2,12(r16)
+     de0:	8c7fffc4 	addi	r17,r17,-1
+     de4:	108000b0 	cmpltui	r2,r2,2
+     de8:	1000071e 	bne	r2,zero,e08 <_fwalk_reent+0x6c>
+     dec:	8080038f 	ldh	r2,14(r16)
+     df0:	800b883a 	mov	r5,r16
+     df4:	a809883a 	mov	r4,r21
+     df8:	10bfffe0 	cmpeqi	r2,r2,-1
+     dfc:	1000021e 	bne	r2,zero,e08 <_fwalk_reent+0x6c>
+     e00:	983ee83a 	callr	r19
+     e04:	a0a8b03a 	or	r20,r20,r2
+     e08:	88bfffd8 	cmpnei	r2,r17,-1
+     e0c:	84001a04 	addi	r16,r16,104
+     e10:	103ff21e 	bne	r2,zero,ddc <_fwalk_reent+0x40>
+     e14:	94800017 	ldw	r18,0(r18)
+     e18:	903fec1e 	bne	r18,zero,dcc <_fwalk_reent+0x30>
+     e1c:	a005883a 	mov	r2,r20
+     e20:	dfc00617 	ldw	ra,24(sp)
+     e24:	dd400517 	ldw	r21,20(sp)
+     e28:	dd000417 	ldw	r20,16(sp)
+     e2c:	dcc00317 	ldw	r19,12(sp)
+     e30:	dc800217 	ldw	r18,8(sp)
+     e34:	dc400117 	ldw	r17,4(sp)
+     e38:	dc000017 	ldw	r16,0(sp)
+     e3c:	dec00704 	addi	sp,sp,28
+     e40:	f800283a 	ret
+
+00000e44 <_malloc_r>:
+     e44:	defff604 	addi	sp,sp,-40
+     e48:	dc400115 	stw	r17,4(sp)
+     e4c:	2c4002c4 	addi	r17,r5,11
+     e50:	dc800215 	stw	r18,8(sp)
+     e54:	dfc00915 	stw	ra,36(sp)
+     e58:	df000815 	stw	fp,32(sp)
+     e5c:	ddc00715 	stw	r23,28(sp)
+     e60:	dd800615 	stw	r22,24(sp)
+     e64:	dd400515 	stw	r21,20(sp)
+     e68:	dd000415 	stw	r20,16(sp)
+     e6c:	dcc00315 	stw	r19,12(sp)
+     e70:	dc000015 	stw	r16,0(sp)
+     e74:	888005e8 	cmpgeui	r2,r17,23
+     e78:	2025883a 	mov	r18,r4
+     e7c:	10001b1e 	bne	r2,zero,eec <_malloc_r+0xa8>
+     e80:	29400468 	cmpgeui	r5,r5,17
+     e84:	2800821e 	bne	r5,zero,1090 <_malloc_r+0x24c>
+     e88:	000367c0 	call	367c <__malloc_lock>
+     e8c:	04400404 	movi	r17,16
+     e90:	00800604 	movi	r2,24
+     e94:	01c00084 	movi	r7,2
+     e98:	04c00034 	movhi	r19,0
+     e9c:	9cd6fc04 	addi	r19,r19,23536
+     ea0:	9885883a 	add	r2,r19,r2
+     ea4:	14000117 	ldw	r16,4(r2)
+     ea8:	10fffe04 	addi	r3,r2,-8
+     eac:	80c08b26 	beq	r16,r3,10dc <_malloc_r+0x298>
+     eb0:	80800117 	ldw	r2,4(r16)
+     eb4:	81000317 	ldw	r4,12(r16)
+     eb8:	00ffff04 	movi	r3,-4
+     ebc:	10c4703a 	and	r2,r2,r3
+     ec0:	81400217 	ldw	r5,8(r16)
+     ec4:	8085883a 	add	r2,r16,r2
+     ec8:	10c00117 	ldw	r3,4(r2)
+     ecc:	29000315 	stw	r4,12(r5)
+     ed0:	21400215 	stw	r5,8(r4)
+     ed4:	18c00054 	ori	r3,r3,1
+     ed8:	10c00115 	stw	r3,4(r2)
+     edc:	9009883a 	mov	r4,r18
+     ee0:	00036a00 	call	36a0 <__malloc_unlock>
+     ee4:	80800204 	addi	r2,r16,8
+     ee8:	00006c06 	br	109c <_malloc_r+0x258>
+     eec:	00bffe04 	movi	r2,-8
+     ef0:	88a2703a 	and	r17,r17,r2
+     ef4:	88006616 	blt	r17,zero,1090 <_malloc_r+0x24c>
+     ef8:	89406536 	bltu	r17,r5,1090 <_malloc_r+0x24c>
+     efc:	000367c0 	call	367c <__malloc_lock>
+     f00:	88807e28 	cmpgeui	r2,r17,504
+     f04:	10012226 	beq	r2,zero,1390 <_malloc_r+0x54c>
+     f08:	8804d27a 	srli	r2,r17,9
+     f0c:	10006f26 	beq	r2,zero,10cc <_malloc_r+0x288>
+     f10:	10c00168 	cmpgeui	r3,r2,5
+     f14:	1800fe1e 	bne	r3,zero,1310 <_malloc_r+0x4cc>
+     f18:	8804d1ba 	srli	r2,r17,6
+     f1c:	11c00e44 	addi	r7,r2,57
+     f20:	380890fa 	slli	r4,r7,3
+     f24:	12000e04 	addi	r8,r2,56
+     f28:	04c00034 	movhi	r19,0
+     f2c:	9cd6fc04 	addi	r19,r19,23536
+     f30:	9909883a 	add	r4,r19,r4
+     f34:	24000117 	ldw	r16,4(r4)
+     f38:	213ffe04 	addi	r4,r4,-8
+     f3c:	24000b26 	beq	r4,r16,f6c <_malloc_r+0x128>
+     f40:	01bfff04 	movi	r6,-4
+     f44:	00000306 	br	f54 <_malloc_r+0x110>
+     f48:	1800d60e 	bge	r3,zero,12a4 <_malloc_r+0x460>
+     f4c:	84000317 	ldw	r16,12(r16)
+     f50:	24000626 	beq	r4,r16,f6c <_malloc_r+0x128>
+     f54:	80800117 	ldw	r2,4(r16)
+     f58:	1184703a 	and	r2,r2,r6
+     f5c:	1447c83a 	sub	r3,r2,r17
+     f60:	19400408 	cmpgei	r5,r3,16
+     f64:	283ff826 	beq	r5,zero,f48 <_malloc_r+0x104>
+     f68:	400f883a 	mov	r7,r8
+     f6c:	9c000417 	ldw	r16,16(r19)
+     f70:	02400034 	movhi	r9,0
+     f74:	4a56fe04 	addi	r9,r9,23544
+     f78:	82405f26 	beq	r16,r9,10f8 <_malloc_r+0x2b4>
+     f7c:	80c00117 	ldw	r3,4(r16)
+     f80:	00bfff04 	movi	r2,-4
+     f84:	1884703a 	and	r2,r3,r2
+     f88:	1447c83a 	sub	r3,r2,r17
+     f8c:	19000410 	cmplti	r4,r3,16
+     f90:	20010a26 	beq	r4,zero,13bc <_malloc_r+0x578>
+     f94:	9a400515 	stw	r9,20(r19)
+     f98:	9a400415 	stw	r9,16(r19)
+     f9c:	1800ff0e 	bge	r3,zero,139c <_malloc_r+0x558>
+     fa0:	10c08028 	cmpgeui	r3,r2,512
+     fa4:	1800c11e 	bne	r3,zero,12ac <_malloc_r+0x468>
+     fa8:	1006d0fa 	srli	r3,r2,3
+     fac:	1008d17a 	srli	r4,r2,5
+     fb0:	00800044 	movi	r2,1
+     fb4:	18c00044 	addi	r3,r3,1
+     fb8:	180690fa 	slli	r3,r3,3
+     fbc:	99400117 	ldw	r5,4(r19)
+     fc0:	1104983a 	sll	r2,r2,r4
+     fc4:	98c7883a 	add	r3,r19,r3
+     fc8:	19000017 	ldw	r4,0(r3)
+     fcc:	1144b03a 	or	r2,r2,r5
+     fd0:	197ffe04 	addi	r5,r3,-8
+     fd4:	81400315 	stw	r5,12(r16)
+     fd8:	81000215 	stw	r4,8(r16)
+     fdc:	98800115 	stw	r2,4(r19)
+     fe0:	1c000015 	stw	r16,0(r3)
+     fe4:	24000315 	stw	r16,12(r4)
+     fe8:	3807d0ba 	srai	r3,r7,2
+     fec:	01000044 	movi	r4,1
+     ff0:	20c8983a 	sll	r4,r4,r3
+     ff4:	11004536 	bltu	r2,r4,110c <_malloc_r+0x2c8>
+     ff8:	2086703a 	and	r3,r4,r2
+     ffc:	18000a1e 	bne	r3,zero,1028 <_malloc_r+0x1e4>
+    1000:	00ffff04 	movi	r3,-4
+    1004:	2109883a 	add	r4,r4,r4
+    1008:	38ce703a 	and	r7,r7,r3
+    100c:	2086703a 	and	r3,r4,r2
+    1010:	39c00104 	addi	r7,r7,4
+    1014:	1800041e 	bne	r3,zero,1028 <_malloc_r+0x1e4>
+    1018:	2109883a 	add	r4,r4,r4
+    101c:	2086703a 	and	r3,r4,r2
+    1020:	39c00104 	addi	r7,r7,4
+    1024:	183ffc26 	beq	r3,zero,1018 <_malloc_r+0x1d4>
+    1028:	02bfff04 	movi	r10,-4
+    102c:	381690fa 	slli	r11,r7,3
+    1030:	3819883a 	mov	r12,r7
+    1034:	9ad7883a 	add	r11,r19,r11
+    1038:	5811883a 	mov	r8,r11
+    103c:	40800317 	ldw	r2,12(r8)
+    1040:	4080bc26 	beq	r8,r2,1334 <_malloc_r+0x4f0>
+    1044:	10c00117 	ldw	r3,4(r2)
+    1048:	1021883a 	mov	r16,r2
+    104c:	10800317 	ldw	r2,12(r2)
+    1050:	1a86703a 	and	r3,r3,r10
+    1054:	1c4bc83a 	sub	r5,r3,r17
+    1058:	29800410 	cmplti	r6,r5,16
+    105c:	3000ba26 	beq	r6,zero,1348 <_malloc_r+0x504>
+    1060:	283ff716 	blt	r5,zero,1040 <_malloc_r+0x1fc>
+    1064:	80c7883a 	add	r3,r16,r3
+    1068:	19400117 	ldw	r5,4(r3)
+    106c:	81800217 	ldw	r6,8(r16)
+    1070:	9009883a 	mov	r4,r18
+    1074:	29400054 	ori	r5,r5,1
+    1078:	19400115 	stw	r5,4(r3)
+    107c:	30800315 	stw	r2,12(r6)
+    1080:	11800215 	stw	r6,8(r2)
+    1084:	00036a00 	call	36a0 <__malloc_unlock>
+    1088:	80800204 	addi	r2,r16,8
+    108c:	00000306 	br	109c <_malloc_r+0x258>
+    1090:	00800304 	movi	r2,12
+    1094:	90800015 	stw	r2,0(r18)
+    1098:	0005883a 	mov	r2,zero
+    109c:	dfc00917 	ldw	ra,36(sp)
+    10a0:	df000817 	ldw	fp,32(sp)
+    10a4:	ddc00717 	ldw	r23,28(sp)
+    10a8:	dd800617 	ldw	r22,24(sp)
+    10ac:	dd400517 	ldw	r21,20(sp)
+    10b0:	dd000417 	ldw	r20,16(sp)
+    10b4:	dcc00317 	ldw	r19,12(sp)
+    10b8:	dc800217 	ldw	r18,8(sp)
+    10bc:	dc400117 	ldw	r17,4(sp)
+    10c0:	dc000017 	ldw	r16,0(sp)
+    10c4:	dec00a04 	addi	sp,sp,40
+    10c8:	f800283a 	ret
+    10cc:	01008004 	movi	r4,512
+    10d0:	01c01004 	movi	r7,64
+    10d4:	02000fc4 	movi	r8,63
+    10d8:	003f9306 	br	f28 <_malloc_r+0xe4>
+    10dc:	14000317 	ldw	r16,12(r2)
+    10e0:	39c00084 	addi	r7,r7,2
+    10e4:	143f721e 	bne	r2,r16,eb0 <_malloc_r+0x6c>
+    10e8:	9c000417 	ldw	r16,16(r19)
+    10ec:	02400034 	movhi	r9,0
+    10f0:	4a56fe04 	addi	r9,r9,23544
+    10f4:	827fa11e 	bne	r16,r9,f7c <_malloc_r+0x138>
+    10f8:	3807d0ba 	srai	r3,r7,2
+    10fc:	01000044 	movi	r4,1
+    1100:	98800117 	ldw	r2,4(r19)
+    1104:	20c8983a 	sll	r4,r4,r3
+    1108:	113fbb2e 	bgeu	r2,r4,ff8 <_malloc_r+0x1b4>
+    110c:	9c000217 	ldw	r16,8(r19)
+    1110:	00bfff04 	movi	r2,-4
+    1114:	85400117 	ldw	r21,4(r16)
+    1118:	a8ac703a 	and	r22,r21,r2
+    111c:	b4400336 	bltu	r22,r17,112c <_malloc_r+0x2e8>
+    1120:	b445c83a 	sub	r2,r22,r17
+    1124:	10c00408 	cmpgei	r3,r2,16
+    1128:	1800541e 	bne	r3,zero,127c <_malloc_r+0x438>
+    112c:	00800034 	movhi	r2,0
+    1130:	109c8217 	ldw	r2,29192(r2)
+    1134:	00c00034 	movhi	r3,0
+    1138:	1d5c9017 	ldw	r21,29248(r3)
+    113c:	10bfffd8 	cmpnei	r2,r2,-1
+    1140:	85b9883a 	add	fp,r16,r22
+    1144:	8d6b883a 	add	r21,r17,r21
+    1148:	1000d626 	beq	r2,zero,14a4 <_malloc_r+0x660>
+    114c:	ad4403c4 	addi	r21,r21,4111
+    1150:	00bc0004 	movi	r2,-4096
+    1154:	a8aa703a 	and	r21,r21,r2
+    1158:	a80b883a 	mov	r5,r21
+    115c:	9009883a 	mov	r4,r18
+    1160:	0001f740 	call	1f74 <_sbrk_r>
+    1164:	102f883a 	mov	r23,r2
+    1168:	10bfffd8 	cmpnei	r2,r2,-1
+    116c:	1000a826 	beq	r2,zero,1410 <_malloc_r+0x5cc>
+    1170:	bf00a636 	bltu	r23,fp,140c <_malloc_r+0x5c8>
+    1174:	00800034 	movhi	r2,0
+    1178:	151c9917 	ldw	r20,29284(r2)
+    117c:	ad29883a 	add	r20,r21,r20
+    1180:	151c9915 	stw	r20,29284(r2)
+    1184:	a007883a 	mov	r3,r20
+    1188:	e5c0ec26 	beq	fp,r23,153c <_malloc_r+0x6f8>
+    118c:	00800034 	movhi	r2,0
+    1190:	109c8217 	ldw	r2,29192(r2)
+    1194:	10bfffd8 	cmpnei	r2,r2,-1
+    1198:	1000ef26 	beq	r2,zero,1558 <_malloc_r+0x714>
+    119c:	bf39c83a 	sub	fp,r23,fp
+    11a0:	e0c7883a 	add	r3,fp,r3
+    11a4:	00800034 	movhi	r2,0
+    11a8:	10dc9915 	stw	r3,29284(r2)
+    11ac:	bf0001cc 	andi	fp,r23,7
+    11b0:	e000c526 	beq	fp,zero,14c8 <_malloc_r+0x684>
+    11b4:	bf2fc83a 	sub	r23,r23,fp
+    11b8:	bdc00204 	addi	r23,r23,8
+    11bc:	05040204 	movi	r20,4104
+    11c0:	a729c83a 	sub	r20,r20,fp
+    11c4:	bd6b883a 	add	r21,r23,r21
+    11c8:	a569c83a 	sub	r20,r20,r21
+    11cc:	a503ffcc 	andi	r20,r20,4095
+    11d0:	a00b883a 	mov	r5,r20
+    11d4:	9009883a 	mov	r4,r18
+    11d8:	0001f740 	call	1f74 <_sbrk_r>
+    11dc:	10ffffe0 	cmpeqi	r3,r2,-1
+    11e0:	1800f31e 	bne	r3,zero,15b0 <_malloc_r+0x76c>
+    11e4:	15c5c83a 	sub	r2,r2,r23
+    11e8:	152b883a 	add	r21,r2,r20
+    11ec:	00800034 	movhi	r2,0
+    11f0:	115c9917 	ldw	r5,29284(r2)
+    11f4:	9dc00215 	stw	r23,8(r19)
+    11f8:	ad400054 	ori	r21,r21,1
+    11fc:	a169883a 	add	r20,r20,r5
+    1200:	151c9915 	stw	r20,29284(r2)
+    1204:	bd400115 	stw	r21,4(r23)
+    1208:	84c0d626 	beq	r16,r19,1564 <_malloc_r+0x720>
+    120c:	b0800428 	cmpgeui	r2,r22,16
+    1210:	1000d626 	beq	r2,zero,156c <_malloc_r+0x728>
+    1214:	80c00117 	ldw	r3,4(r16)
+    1218:	013ffe04 	movi	r4,-8
+    121c:	b0bffd04 	addi	r2,r22,-12
+    1220:	1104703a 	and	r2,r2,r4
+    1224:	18c0004c 	andi	r3,r3,1
+    1228:	1886b03a 	or	r3,r3,r2
+    122c:	80c00115 	stw	r3,4(r16)
+    1230:	01000144 	movi	r4,5
+    1234:	8087883a 	add	r3,r16,r2
+    1238:	19000115 	stw	r4,4(r3)
+    123c:	19000215 	stw	r4,8(r3)
+    1240:	10800428 	cmpgeui	r2,r2,16
+    1244:	1000df1e 	bne	r2,zero,15c4 <_malloc_r+0x780>
+    1248:	bd400117 	ldw	r21,4(r23)
+    124c:	b821883a 	mov	r16,r23
+    1250:	00800034 	movhi	r2,0
+    1254:	109c8f17 	ldw	r2,29244(r2)
+    1258:	1500022e 	bgeu	r2,r20,1264 <_malloc_r+0x420>
+    125c:	00800034 	movhi	r2,0
+    1260:	151c8f15 	stw	r20,29244(r2)
+    1264:	00800034 	movhi	r2,0
+    1268:	109c8e17 	ldw	r2,29240(r2)
+    126c:	15006a2e 	bgeu	r2,r20,1418 <_malloc_r+0x5d4>
+    1270:	00800034 	movhi	r2,0
+    1274:	151c8e15 	stw	r20,29240(r2)
+    1278:	00006706 	br	1418 <_malloc_r+0x5d4>
+    127c:	88c00054 	ori	r3,r17,1
+    1280:	80c00115 	stw	r3,4(r16)
+    1284:	8463883a 	add	r17,r16,r17
+    1288:	10800054 	ori	r2,r2,1
+    128c:	9c400215 	stw	r17,8(r19)
+    1290:	88800115 	stw	r2,4(r17)
+    1294:	9009883a 	mov	r4,r18
+    1298:	00036a00 	call	36a0 <__malloc_unlock>
+    129c:	80800204 	addi	r2,r16,8
+    12a0:	003f7e06 	br	109c <_malloc_r+0x258>
+    12a4:	81000317 	ldw	r4,12(r16)
+    12a8:	003f0506 	br	ec0 <_malloc_r+0x7c>
+    12ac:	1006d27a 	srli	r3,r2,9
+    12b0:	19000168 	cmpgeui	r4,r3,5
+    12b4:	20005026 	beq	r4,zero,13f8 <_malloc_r+0x5b4>
+    12b8:	19000568 	cmpgeui	r4,r3,21
+    12bc:	20008c1e 	bne	r4,zero,14f0 <_malloc_r+0x6ac>
+    12c0:	19401704 	addi	r5,r3,92
+    12c4:	280a90fa 	slli	r5,r5,3
+    12c8:	190016c4 	addi	r4,r3,91
+    12cc:	994b883a 	add	r5,r19,r5
+    12d0:	28c00017 	ldw	r3,0(r5)
+    12d4:	297ffe04 	addi	r5,r5,-8
+    12d8:	28c07426 	beq	r5,r3,14ac <_malloc_r+0x668>
+    12dc:	01bfff04 	movi	r6,-4
+    12e0:	19000117 	ldw	r4,4(r3)
+    12e4:	2188703a 	and	r4,r4,r6
+    12e8:	1100022e 	bgeu	r2,r4,12f4 <_malloc_r+0x4b0>
+    12ec:	18c00217 	ldw	r3,8(r3)
+    12f0:	28fffb1e 	bne	r5,r3,12e0 <_malloc_r+0x49c>
+    12f4:	19400317 	ldw	r5,12(r3)
+    12f8:	98800117 	ldw	r2,4(r19)
+    12fc:	81400315 	stw	r5,12(r16)
+    1300:	80c00215 	stw	r3,8(r16)
+    1304:	2c000215 	stw	r16,8(r5)
+    1308:	1c000315 	stw	r16,12(r3)
+    130c:	003f3606 	br	fe8 <_malloc_r+0x1a4>
+    1310:	10c00568 	cmpgeui	r3,r2,21
+    1314:	18004a26 	beq	r3,zero,1440 <_malloc_r+0x5fc>
+    1318:	10c01568 	cmpgeui	r3,r2,85
+    131c:	18007b1e 	bne	r3,zero,150c <_malloc_r+0x6c8>
+    1320:	8804d33a 	srli	r2,r17,12
+    1324:	11c01bc4 	addi	r7,r2,111
+    1328:	380890fa 	slli	r4,r7,3
+    132c:	12001b84 	addi	r8,r2,110
+    1330:	003efd06 	br	f28 <_malloc_r+0xe4>
+    1334:	63000044 	addi	r12,r12,1
+    1338:	608000cc 	andi	r2,r12,3
+    133c:	42000204 	addi	r8,r8,8
+    1340:	103f3e1e 	bne	r2,zero,103c <_malloc_r+0x1f8>
+    1344:	00004506 	br	145c <_malloc_r+0x618>
+    1348:	81000217 	ldw	r4,8(r16)
+    134c:	89800054 	ori	r6,r17,1
+    1350:	81800115 	stw	r6,4(r16)
+    1354:	20800315 	stw	r2,12(r4)
+    1358:	11000215 	stw	r4,8(r2)
+    135c:	8463883a 	add	r17,r16,r17
+    1360:	9c400515 	stw	r17,20(r19)
+    1364:	9c400415 	stw	r17,16(r19)
+    1368:	28800054 	ori	r2,r5,1
+    136c:	88800115 	stw	r2,4(r17)
+    1370:	8a400315 	stw	r9,12(r17)
+    1374:	8a400215 	stw	r9,8(r17)
+    1378:	80c7883a 	add	r3,r16,r3
+    137c:	19400015 	stw	r5,0(r3)
+    1380:	9009883a 	mov	r4,r18
+    1384:	00036a00 	call	36a0 <__malloc_unlock>
+    1388:	80800204 	addi	r2,r16,8
+    138c:	003f4306 	br	109c <_malloc_r+0x258>
+    1390:	880ed0fa 	srli	r7,r17,3
+    1394:	88800204 	addi	r2,r17,8
+    1398:	003ebf06 	br	e98 <_malloc_r+0x54>
+    139c:	8085883a 	add	r2,r16,r2
+    13a0:	10c00117 	ldw	r3,4(r2)
+    13a4:	9009883a 	mov	r4,r18
+    13a8:	18c00054 	ori	r3,r3,1
+    13ac:	10c00115 	stw	r3,4(r2)
+    13b0:	00036a00 	call	36a0 <__malloc_unlock>
+    13b4:	80800204 	addi	r2,r16,8
+    13b8:	003f3806 	br	109c <_malloc_r+0x258>
+    13bc:	89000054 	ori	r4,r17,1
+    13c0:	81000115 	stw	r4,4(r16)
+    13c4:	8463883a 	add	r17,r16,r17
+    13c8:	9c400515 	stw	r17,20(r19)
+    13cc:	9c400415 	stw	r17,16(r19)
+    13d0:	19000054 	ori	r4,r3,1
+    13d4:	89000115 	stw	r4,4(r17)
+    13d8:	8085883a 	add	r2,r16,r2
+    13dc:	8a400315 	stw	r9,12(r17)
+    13e0:	8a400215 	stw	r9,8(r17)
+    13e4:	10c00015 	stw	r3,0(r2)
+    13e8:	9009883a 	mov	r4,r18
+    13ec:	00036a00 	call	36a0 <__malloc_unlock>
+    13f0:	80800204 	addi	r2,r16,8
+    13f4:	003f2906 	br	109c <_malloc_r+0x258>
+    13f8:	1006d1ba 	srli	r3,r2,6
+    13fc:	19400e44 	addi	r5,r3,57
+    1400:	280a90fa 	slli	r5,r5,3
+    1404:	19000e04 	addi	r4,r3,56
+    1408:	003fb006 	br	12cc <_malloc_r+0x488>
+    140c:	84c04626 	beq	r16,r19,1528 <_malloc_r+0x6e4>
+    1410:	9c000217 	ldw	r16,8(r19)
+    1414:	85400117 	ldw	r21,4(r16)
+    1418:	00bfff04 	movi	r2,-4
+    141c:	a8aa703a 	and	r21,r21,r2
+    1420:	ac45c83a 	sub	r2,r21,r17
+    1424:	ac400236 	bltu	r21,r17,1430 <_malloc_r+0x5ec>
+    1428:	10c00408 	cmpgei	r3,r2,16
+    142c:	183f931e 	bne	r3,zero,127c <_malloc_r+0x438>
+    1430:	9009883a 	mov	r4,r18
+    1434:	00036a00 	call	36a0 <__malloc_unlock>
+    1438:	0005883a 	mov	r2,zero
+    143c:	003f1706 	br	109c <_malloc_r+0x258>
+    1440:	11c01704 	addi	r7,r2,92
+    1444:	380890fa 	slli	r4,r7,3
+    1448:	120016c4 	addi	r8,r2,91
+    144c:	003eb606 	br	f28 <_malloc_r+0xe4>
+    1450:	58800217 	ldw	r2,8(r11)
+    1454:	39ffffc4 	addi	r7,r7,-1
+    1458:	12c0701e 	bne	r2,r11,161c <_malloc_r+0x7d8>
+    145c:	388000cc 	andi	r2,r7,3
+    1460:	5afffe04 	addi	r11,r11,-8
+    1464:	103ffa1e 	bne	r2,zero,1450 <_malloc_r+0x60c>
+    1468:	98c00117 	ldw	r3,4(r19)
+    146c:	0104303a 	nor	r2,zero,r4
+    1470:	10c4703a 	and	r2,r2,r3
+    1474:	98800115 	stw	r2,4(r19)
+    1478:	2109883a 	add	r4,r4,r4
+    147c:	113f2336 	bltu	r2,r4,110c <_malloc_r+0x2c8>
+    1480:	203f2226 	beq	r4,zero,110c <_malloc_r+0x2c8>
+    1484:	2086703a 	and	r3,r4,r2
+    1488:	1800041e 	bne	r3,zero,149c <_malloc_r+0x658>
+    148c:	2109883a 	add	r4,r4,r4
+    1490:	2086703a 	and	r3,r4,r2
+    1494:	63000104 	addi	r12,r12,4
+    1498:	183ffc26 	beq	r3,zero,148c <_malloc_r+0x648>
+    149c:	600f883a 	mov	r7,r12
+    14a0:	003ee206 	br	102c <_malloc_r+0x1e8>
+    14a4:	ad400404 	addi	r21,r21,16
+    14a8:	003f2b06 	br	1158 <_malloc_r+0x314>
+    14ac:	2009d0ba 	srai	r4,r4,2
+    14b0:	00800044 	movi	r2,1
+    14b4:	99800117 	ldw	r6,4(r19)
+    14b8:	1104983a 	sll	r2,r2,r4
+    14bc:	1184b03a 	or	r2,r2,r6
+    14c0:	98800115 	stw	r2,4(r19)
+    14c4:	003f8d06 	br	12fc <_malloc_r+0x4b8>
+    14c8:	bd69883a 	add	r20,r23,r21
+    14cc:	0529c83a 	sub	r20,zero,r20
+    14d0:	a503ffcc 	andi	r20,r20,4095
+    14d4:	a00b883a 	mov	r5,r20
+    14d8:	9009883a 	mov	r4,r18
+    14dc:	0001f740 	call	1f74 <_sbrk_r>
+    14e0:	10ffffe0 	cmpeqi	r3,r2,-1
+    14e4:	183f3f26 	beq	r3,zero,11e4 <_malloc_r+0x3a0>
+    14e8:	0029883a 	mov	r20,zero
+    14ec:	003f3f06 	br	11ec <_malloc_r+0x3a8>
+    14f0:	19001568 	cmpgeui	r4,r3,85
+    14f4:	2000201e 	bne	r4,zero,1578 <_malloc_r+0x734>
+    14f8:	1006d33a 	srli	r3,r2,12
+    14fc:	19401bc4 	addi	r5,r3,111
+    1500:	280a90fa 	slli	r5,r5,3
+    1504:	19001b84 	addi	r4,r3,110
+    1508:	003f7006 	br	12cc <_malloc_r+0x488>
+    150c:	10c05568 	cmpgeui	r3,r2,341
+    1510:	1800201e 	bne	r3,zero,1594 <_malloc_r+0x750>
+    1514:	8804d3fa 	srli	r2,r17,15
+    1518:	11c01e04 	addi	r7,r2,120
+    151c:	380890fa 	slli	r4,r7,3
+    1520:	12001dc4 	addi	r8,r2,119
+    1524:	003e8006 	br	f28 <_malloc_r+0xe4>
+    1528:	00800034 	movhi	r2,0
+    152c:	10dc9917 	ldw	r3,29284(r2)
+    1530:	a8c7883a 	add	r3,r21,r3
+    1534:	10dc9915 	stw	r3,29284(r2)
+    1538:	003f1406 	br	118c <_malloc_r+0x348>
+    153c:	e083ffcc 	andi	r2,fp,4095
+    1540:	103f121e 	bne	r2,zero,118c <_malloc_r+0x348>
+    1544:	9c000217 	ldw	r16,8(r19)
+    1548:	b56b883a 	add	r21,r22,r21
+    154c:	ad400054 	ori	r21,r21,1
+    1550:	85400115 	stw	r21,4(r16)
+    1554:	003f3e06 	br	1250 <_malloc_r+0x40c>
+    1558:	00800034 	movhi	r2,0
+    155c:	15dc8215 	stw	r23,29192(r2)
+    1560:	003f1206 	br	11ac <_malloc_r+0x368>
+    1564:	b821883a 	mov	r16,r23
+    1568:	003f3906 	br	1250 <_malloc_r+0x40c>
+    156c:	00800044 	movi	r2,1
+    1570:	b8800115 	stw	r2,4(r23)
+    1574:	003fae06 	br	1430 <_malloc_r+0x5ec>
+    1578:	19005568 	cmpgeui	r4,r3,341
+    157c:	2000191e 	bne	r4,zero,15e4 <_malloc_r+0x7a0>
+    1580:	1006d3fa 	srli	r3,r2,15
+    1584:	19401e04 	addi	r5,r3,120
+    1588:	280a90fa 	slli	r5,r5,3
+    158c:	19001dc4 	addi	r4,r3,119
+    1590:	003f4e06 	br	12cc <_malloc_r+0x488>
+    1594:	10815568 	cmpgeui	r2,r2,1365
+    1598:	1000191e 	bne	r2,zero,1600 <_malloc_r+0x7bc>
+    159c:	8804d4ba 	srli	r2,r17,18
+    15a0:	11c01f44 	addi	r7,r2,125
+    15a4:	380890fa 	slli	r4,r7,3
+    15a8:	12001f04 	addi	r8,r2,124
+    15ac:	003e5e06 	br	f28 <_malloc_r+0xe4>
+    15b0:	e73ffe04 	addi	fp,fp,-8
+    15b4:	af2b883a 	add	r21,r21,fp
+    15b8:	adebc83a 	sub	r21,r21,r23
+    15bc:	0029883a 	mov	r20,zero
+    15c0:	003f0a06 	br	11ec <_malloc_r+0x3a8>
+    15c4:	81400204 	addi	r5,r16,8
+    15c8:	9009883a 	mov	r4,r18
+    15cc:	00028f40 	call	28f4 <_free_r>
+    15d0:	9c000217 	ldw	r16,8(r19)
+    15d4:	00800034 	movhi	r2,0
+    15d8:	151c9917 	ldw	r20,29284(r2)
+    15dc:	85400117 	ldw	r21,4(r16)
+    15e0:	003f1b06 	br	1250 <_malloc_r+0x40c>
+    15e4:	18c15568 	cmpgeui	r3,r3,1365
+    15e8:	1800091e 	bne	r3,zero,1610 <_malloc_r+0x7cc>
+    15ec:	1006d4ba 	srli	r3,r2,18
+    15f0:	19401f44 	addi	r5,r3,125
+    15f4:	280a90fa 	slli	r5,r5,3
+    15f8:	19001f04 	addi	r4,r3,124
+    15fc:	003f3306 	br	12cc <_malloc_r+0x488>
+    1600:	0100fe04 	movi	r4,1016
+    1604:	01c01fc4 	movi	r7,127
+    1608:	02001f84 	movi	r8,126
+    160c:	003e4606 	br	f28 <_malloc_r+0xe4>
+    1610:	0140fe04 	movi	r5,1016
+    1614:	01001f84 	movi	r4,126
+    1618:	003f2c06 	br	12cc <_malloc_r+0x488>
+    161c:	98800117 	ldw	r2,4(r19)
+    1620:	003f9506 	br	1478 <_malloc_r+0x634>
+
+00001624 <memchr>:
+    1624:	208000cc 	andi	r2,r4,3
+    1628:	280f883a 	mov	r7,r5
+    162c:	10000e26 	beq	r2,zero,1668 <memchr+0x44>
+    1630:	30bfffc4 	addi	r2,r6,-1
+    1634:	30001726 	beq	r6,zero,1694 <memchr+0x70>
+    1638:	29803fcc 	andi	r6,r5,255
+    163c:	00000606 	br	1658 <memchr+0x34>
+    1640:	21000044 	addi	r4,r4,1
+    1644:	20c000cc 	andi	r3,r4,3
+    1648:	18000826 	beq	r3,zero,166c <memchr+0x48>
+    164c:	10bfffc4 	addi	r2,r2,-1
+    1650:	10ffffe0 	cmpeqi	r3,r2,-1
+    1654:	18000f1e 	bne	r3,zero,1694 <memchr+0x70>
+    1658:	20c00003 	ldbu	r3,0(r4)
+    165c:	19bff81e 	bne	r3,r6,1640 <memchr+0x1c>
+    1660:	2005883a 	mov	r2,r4
+    1664:	f800283a 	ret
+    1668:	3005883a 	mov	r2,r6
+    166c:	10c00128 	cmpgeui	r3,r2,4
+    1670:	18000a1e 	bne	r3,zero,169c <memchr+0x78>
+    1674:	10001e26 	beq	r2,zero,16f0 <memchr+0xcc>
+    1678:	2087883a 	add	r3,r4,r2
+    167c:	39803fcc 	andi	r6,r7,255
+    1680:	2005883a 	mov	r2,r4
+    1684:	11000003 	ldbu	r4,0(r2)
+    1688:	21bff626 	beq	r4,r6,1664 <memchr+0x40>
+    168c:	10800044 	addi	r2,r2,1
+    1690:	18bffc1e 	bne	r3,r2,1684 <memchr+0x60>
+    1694:	0005883a 	mov	r2,zero
+    1698:	f800283a 	ret
+    169c:	29403fcc 	andi	r5,r5,255
+    16a0:	280c923a 	slli	r6,r5,8
+    16a4:	027fbff4 	movhi	r9,65279
+    16a8:	02202074 	movhi	r8,32897
+    16ac:	314ab03a 	or	r5,r6,r5
+    16b0:	280c943a 	slli	r6,r5,16
+    16b4:	4a7fbfc4 	addi	r9,r9,-257
+    16b8:	42202004 	addi	r8,r8,-32640
+    16bc:	314cb03a 	or	r6,r6,r5
+    16c0:	20c00017 	ldw	r3,0(r4)
+    16c4:	30c6f03a 	xor	r3,r6,r3
+    16c8:	1a4b883a 	add	r5,r3,r9
+    16cc:	00c6303a 	nor	r3,zero,r3
+    16d0:	28c6703a 	and	r3,r5,r3
+    16d4:	1a06703a 	and	r3,r3,r8
+    16d8:	183fe71e 	bne	r3,zero,1678 <memchr+0x54>
+    16dc:	10bfff04 	addi	r2,r2,-4
+    16e0:	10c00128 	cmpgeui	r3,r2,4
+    16e4:	21000104 	addi	r4,r4,4
+    16e8:	183ff51e 	bne	r3,zero,16c0 <memchr+0x9c>
+    16ec:	003fe106 	br	1674 <memchr+0x50>
+    16f0:	f800283a 	ret
+
+000016f4 <memcpy>:
+    16f4:	30c00430 	cmpltui	r3,r6,16
+    16f8:	2005883a 	mov	r2,r4
+    16fc:	18002d1e 	bne	r3,zero,17b4 <memcpy+0xc0>
+    1700:	2906b03a 	or	r3,r5,r4
+    1704:	18c000cc 	andi	r3,r3,3
+    1708:	1800351e 	bne	r3,zero,17e0 <memcpy+0xec>
+    170c:	32fffc04 	addi	r11,r6,-16
+    1710:	5816d13a 	srli	r11,r11,4
+    1714:	280f883a 	mov	r7,r5
+    1718:	2007883a 	mov	r3,r4
+    171c:	5ac00044 	addi	r11,r11,1
+    1720:	5816913a 	slli	r11,r11,4
+    1724:	22d5883a 	add	r10,r4,r11
+    1728:	39000117 	ldw	r4,4(r7)
+    172c:	3a400017 	ldw	r9,0(r7)
+    1730:	3a000217 	ldw	r8,8(r7)
+    1734:	19000115 	stw	r4,4(r3)
+    1738:	39000317 	ldw	r4,12(r7)
+    173c:	1a400015 	stw	r9,0(r3)
+    1740:	1a000215 	stw	r8,8(r3)
+    1744:	19000315 	stw	r4,12(r3)
+    1748:	18c00404 	addi	r3,r3,16
+    174c:	39c00404 	addi	r7,r7,16
+    1750:	50fff51e 	bne	r10,r3,1728 <memcpy+0x34>
+    1754:	3100030c 	andi	r4,r6,12
+    1758:	2acb883a 	add	r5,r5,r11
+    175c:	320003cc 	andi	r8,r6,15
+    1760:	20002226 	beq	r4,zero,17ec <memcpy+0xf8>
+    1764:	280f883a 	mov	r7,r5
+    1768:	1813883a 	mov	r9,r3
+    176c:	39c00104 	addi	r7,r7,4
+    1770:	3abfff17 	ldw	r10,-4(r7)
+    1774:	41c9c83a 	sub	r4,r8,r7
+    1778:	2909883a 	add	r4,r5,r4
+    177c:	4a800015 	stw	r10,0(r9)
+    1780:	21000128 	cmpgeui	r4,r4,4
+    1784:	4a400104 	addi	r9,r9,4
+    1788:	203ff81e 	bne	r4,zero,176c <memcpy+0x78>
+    178c:	413fff04 	addi	r4,r8,-4
+    1790:	2008d0ba 	srli	r4,r4,2
+    1794:	318000cc 	andi	r6,r6,3
+    1798:	31ffffc4 	addi	r7,r6,-1
+    179c:	21000044 	addi	r4,r4,1
+    17a0:	200890ba 	slli	r4,r4,2
+    17a4:	1907883a 	add	r3,r3,r4
+    17a8:	290b883a 	add	r5,r5,r4
+    17ac:	3000041e 	bne	r6,zero,17c0 <memcpy+0xcc>
+    17b0:	f800283a 	ret
+    17b4:	2007883a 	mov	r3,r4
+    17b8:	31ffffc4 	addi	r7,r6,-1
+    17bc:	303ffc26 	beq	r6,zero,17b0 <memcpy+0xbc>
+    17c0:	39c00044 	addi	r7,r7,1
+    17c4:	19cf883a 	add	r7,r3,r7
+    17c8:	29800003 	ldbu	r6,0(r5)
+    17cc:	18c00044 	addi	r3,r3,1
+    17d0:	29400044 	addi	r5,r5,1
+    17d4:	19bfffc5 	stb	r6,-1(r3)
+    17d8:	38fffb1e 	bne	r7,r3,17c8 <memcpy+0xd4>
+    17dc:	f800283a 	ret
+    17e0:	31ffffc4 	addi	r7,r6,-1
+    17e4:	2007883a 	mov	r3,r4
+    17e8:	003ff506 	br	17c0 <memcpy+0xcc>
+    17ec:	400d883a 	mov	r6,r8
+    17f0:	003ff106 	br	17b8 <memcpy+0xc4>
+
+000017f4 <memmove>:
+    17f4:	2005883a 	mov	r2,r4
+    17f8:	29000a2e 	bgeu	r5,r4,1824 <memmove+0x30>
+    17fc:	2989883a 	add	r4,r5,r6
+    1800:	1100082e 	bgeu	r2,r4,1824 <memmove+0x30>
+    1804:	1187883a 	add	r3,r2,r6
+    1808:	30003e26 	beq	r6,zero,1904 <memmove+0x110>
+    180c:	217fffc3 	ldbu	r5,-1(r4)
+    1810:	18ffffc4 	addi	r3,r3,-1
+    1814:	213fffc4 	addi	r4,r4,-1
+    1818:	19400005 	stb	r5,0(r3)
+    181c:	10fffb1e 	bne	r2,r3,180c <memmove+0x18>
+    1820:	f800283a 	ret
+    1824:	30c00430 	cmpltui	r3,r6,16
+    1828:	18000b26 	beq	r3,zero,1858 <memmove+0x64>
+    182c:	1007883a 	mov	r3,r2
+    1830:	31ffffc4 	addi	r7,r6,-1
+    1834:	30003726 	beq	r6,zero,1914 <memmove+0x120>
+    1838:	39c00044 	addi	r7,r7,1
+    183c:	29cf883a 	add	r7,r5,r7
+    1840:	29800003 	ldbu	r6,0(r5)
+    1844:	29400044 	addi	r5,r5,1
+    1848:	18c00044 	addi	r3,r3,1
+    184c:	19bfffc5 	stb	r6,-1(r3)
+    1850:	29fffb1e 	bne	r5,r7,1840 <memmove+0x4c>
+    1854:	f800283a 	ret
+    1858:	2886b03a 	or	r3,r5,r2
+    185c:	18c000cc 	andi	r3,r3,3
+    1860:	1800291e 	bne	r3,zero,1908 <memmove+0x114>
+    1864:	327ffc04 	addi	r9,r6,-16
+    1868:	4812d13a 	srli	r9,r9,4
+    186c:	280f883a 	mov	r7,r5
+    1870:	1007883a 	mov	r3,r2
+    1874:	4a400044 	addi	r9,r9,1
+    1878:	4812913a 	slli	r9,r9,4
+    187c:	1251883a 	add	r8,r2,r9
+    1880:	39000017 	ldw	r4,0(r7)
+    1884:	39c00404 	addi	r7,r7,16
+    1888:	18c00404 	addi	r3,r3,16
+    188c:	193ffc15 	stw	r4,-16(r3)
+    1890:	393ffd17 	ldw	r4,-12(r7)
+    1894:	193ffd15 	stw	r4,-12(r3)
+    1898:	393ffe17 	ldw	r4,-8(r7)
+    189c:	193ffe15 	stw	r4,-8(r3)
+    18a0:	393fff17 	ldw	r4,-4(r7)
+    18a4:	193fff15 	stw	r4,-4(r3)
+    18a8:	40fff51e 	bne	r8,r3,1880 <memmove+0x8c>
+    18ac:	3100030c 	andi	r4,r6,12
+    18b0:	2a4b883a 	add	r5,r5,r9
+    18b4:	320003cc 	andi	r8,r6,15
+    18b8:	20001726 	beq	r4,zero,1918 <memmove+0x124>
+    18bc:	2813883a 	mov	r9,r5
+    18c0:	180f883a 	mov	r7,r3
+    18c4:	4a800017 	ldw	r10,0(r9)
+    18c8:	39c00104 	addi	r7,r7,4
+    18cc:	41c9c83a 	sub	r4,r8,r7
+    18d0:	1909883a 	add	r4,r3,r4
+    18d4:	21000128 	cmpgeui	r4,r4,4
+    18d8:	3abfff15 	stw	r10,-4(r7)
+    18dc:	4a400104 	addi	r9,r9,4
+    18e0:	203ff81e 	bne	r4,zero,18c4 <memmove+0xd0>
+    18e4:	413fff04 	addi	r4,r8,-4
+    18e8:	2008d0ba 	srli	r4,r4,2
+    18ec:	318000cc 	andi	r6,r6,3
+    18f0:	21000044 	addi	r4,r4,1
+    18f4:	200890ba 	slli	r4,r4,2
+    18f8:	1907883a 	add	r3,r3,r4
+    18fc:	290b883a 	add	r5,r5,r4
+    1900:	003fcb06 	br	1830 <memmove+0x3c>
+    1904:	f800283a 	ret
+    1908:	31ffffc4 	addi	r7,r6,-1
+    190c:	1007883a 	mov	r3,r2
+    1910:	003fc906 	br	1838 <memmove+0x44>
+    1914:	f800283a 	ret
+    1918:	400d883a 	mov	r6,r8
+    191c:	003fc406 	br	1830 <memmove+0x3c>
+
+00001920 <memset>:
+    1920:	20c000cc 	andi	r3,r4,3
+    1924:	2005883a 	mov	r2,r4
+    1928:	18003626 	beq	r3,zero,1a04 <memset+0xe4>
+    192c:	31ffffc4 	addi	r7,r6,-1
+    1930:	30003326 	beq	r6,zero,1a00 <memset+0xe0>
+    1934:	2811883a 	mov	r8,r5
+    1938:	2007883a 	mov	r3,r4
+    193c:	00000306 	br	194c <memset+0x2c>
+    1940:	39ffffc4 	addi	r7,r7,-1
+    1944:	39bfffe0 	cmpeqi	r6,r7,-1
+    1948:	30002d1e 	bne	r6,zero,1a00 <memset+0xe0>
+    194c:	18c00044 	addi	r3,r3,1
+    1950:	198000cc 	andi	r6,r3,3
+    1954:	1a3fffc5 	stb	r8,-1(r3)
+    1958:	303ff91e 	bne	r6,zero,1940 <memset+0x20>
+    195c:	39000130 	cmpltui	r4,r7,4
+    1960:	2000221e 	bne	r4,zero,19ec <memset+0xcc>
+    1964:	29003fcc 	andi	r4,r5,255
+    1968:	200c923a 	slli	r6,r4,8
+    196c:	3a000430 	cmpltui	r8,r7,16
+    1970:	3108b03a 	or	r4,r6,r4
+    1974:	200c943a 	slli	r6,r4,16
+    1978:	310cb03a 	or	r6,r6,r4
+    197c:	40000e1e 	bne	r8,zero,19b8 <memset+0x98>
+    1980:	393ffc04 	addi	r4,r7,-16
+    1984:	2008d13a 	srli	r4,r4,4
+    1988:	21000044 	addi	r4,r4,1
+    198c:	2008913a 	slli	r4,r4,4
+    1990:	1909883a 	add	r4,r3,r4
+    1994:	19800015 	stw	r6,0(r3)
+    1998:	19800115 	stw	r6,4(r3)
+    199c:	19800215 	stw	r6,8(r3)
+    19a0:	19800315 	stw	r6,12(r3)
+    19a4:	18c00404 	addi	r3,r3,16
+    19a8:	20fffa1e 	bne	r4,r3,1994 <memset+0x74>
+    19ac:	3900030c 	andi	r4,r7,12
+    19b0:	39c003cc 	andi	r7,r7,15
+    19b4:	20000d26 	beq	r4,zero,19ec <memset+0xcc>
+    19b8:	1811883a 	mov	r8,r3
+    19bc:	42000104 	addi	r8,r8,4
+    19c0:	3a09c83a 	sub	r4,r7,r8
+    19c4:	1909883a 	add	r4,r3,r4
+    19c8:	21000128 	cmpgeui	r4,r4,4
+    19cc:	41bfff15 	stw	r6,-4(r8)
+    19d0:	203ffa1e 	bne	r4,zero,19bc <memset+0x9c>
+    19d4:	393fff04 	addi	r4,r7,-4
+    19d8:	2008d0ba 	srli	r4,r4,2
+    19dc:	39c000cc 	andi	r7,r7,3
+    19e0:	21000044 	addi	r4,r4,1
+    19e4:	200890ba 	slli	r4,r4,2
+    19e8:	1907883a 	add	r3,r3,r4
+    19ec:	38000426 	beq	r7,zero,1a00 <memset+0xe0>
+    19f0:	19cf883a 	add	r7,r3,r7
+    19f4:	18c00044 	addi	r3,r3,1
+    19f8:	197fffc5 	stb	r5,-1(r3)
+    19fc:	38fffd1e 	bne	r7,r3,19f4 <memset+0xd4>
+    1a00:	f800283a 	ret
+    1a04:	2007883a 	mov	r3,r4
+    1a08:	300f883a 	mov	r7,r6
+    1a0c:	003fd306 	br	195c <memset+0x3c>
+
+00001a10 <_realloc_r>:
+    1a10:	defff504 	addi	sp,sp,-44
+    1a14:	dc800315 	stw	r18,12(sp)
+    1a18:	dfc00a15 	stw	ra,40(sp)
+    1a1c:	df000915 	stw	fp,36(sp)
+    1a20:	ddc00815 	stw	r23,32(sp)
+    1a24:	dd800715 	stw	r22,28(sp)
+    1a28:	dd400615 	stw	r21,24(sp)
+    1a2c:	dd000515 	stw	r20,20(sp)
+    1a30:	dcc00415 	stw	r19,16(sp)
+    1a34:	dc400215 	stw	r17,8(sp)
+    1a38:	dc000115 	stw	r16,4(sp)
+    1a3c:	3025883a 	mov	r18,r6
+    1a40:	28008b26 	beq	r5,zero,1c70 <_realloc_r+0x260>
+    1a44:	2821883a 	mov	r16,r5
+    1a48:	2027883a 	mov	r19,r4
+    1a4c:	944002c4 	addi	r17,r18,11
+    1a50:	000367c0 	call	367c <__malloc_lock>
+    1a54:	888005f0 	cmpltui	r2,r17,23
+    1a58:	1000521e 	bne	r2,zero,1ba4 <_realloc_r+0x194>
+    1a5c:	017ffe04 	movi	r5,-8
+    1a60:	8962703a 	and	r17,r17,r5
+    1a64:	8807883a 	mov	r3,r17
+    1a68:	88005116 	blt	r17,zero,1bb0 <_realloc_r+0x1a0>
+    1a6c:	8c805036 	bltu	r17,r18,1bb0 <_realloc_r+0x1a0>
+    1a70:	80bfff17 	ldw	r2,-4(r16)
+    1a74:	017fff04 	movi	r5,-4
+    1a78:	857ffe04 	addi	r21,r16,-8
+    1a7c:	1168703a 	and	r20,r2,r5
+    1a80:	ad2d883a 	add	r22,r21,r20
+    1a84:	a0c0390e 	bge	r20,r3,1b6c <_realloc_r+0x15c>
+    1a88:	07000034 	movhi	fp,0
+    1a8c:	e716fc04 	addi	fp,fp,23536
+    1a90:	e2000217 	ldw	r8,8(fp)
+    1a94:	b1000117 	ldw	r4,4(r22)
+    1a98:	45808e26 	beq	r8,r22,1cd4 <_realloc_r+0x2c4>
+    1a9c:	01bfff84 	movi	r6,-2
+    1aa0:	218c703a 	and	r6,r4,r6
+    1aa4:	b18d883a 	add	r6,r22,r6
+    1aa8:	31800117 	ldw	r6,4(r6)
+    1aac:	3180004c 	andi	r6,r6,1
+    1ab0:	30004f1e 	bne	r6,zero,1bf0 <_realloc_r+0x1e0>
+    1ab4:	2148703a 	and	r4,r4,r5
+    1ab8:	a10b883a 	add	r5,r20,r4
+    1abc:	28c0bf0e 	bge	r5,r3,1dbc <_realloc_r+0x3ac>
+    1ac0:	1080004c 	andi	r2,r2,1
+    1ac4:	10004c1e 	bne	r2,zero,1bf8 <_realloc_r+0x1e8>
+    1ac8:	81fffe17 	ldw	r7,-8(r16)
+    1acc:	00bfff04 	movi	r2,-4
+    1ad0:	a9cfc83a 	sub	r7,r21,r7
+    1ad4:	39400117 	ldw	r5,4(r7)
+    1ad8:	288a703a 	and	r5,r5,r2
+    1adc:	b0000426 	beq	r22,zero,1af0 <_realloc_r+0xe0>
+    1ae0:	a16f883a 	add	r23,r20,r5
+    1ae4:	b92f883a 	add	r23,r23,r4
+    1ae8:	4580bf26 	beq	r8,r22,1de8 <_realloc_r+0x3d8>
+    1aec:	b8c0930e 	bge	r23,r3,1d3c <_realloc_r+0x32c>
+    1af0:	38004126 	beq	r7,zero,1bf8 <_realloc_r+0x1e8>
+    1af4:	a16f883a 	add	r23,r20,r5
+    1af8:	b8c03f16 	blt	r23,r3,1bf8 <_realloc_r+0x1e8>
+    1afc:	38800317 	ldw	r2,12(r7)
+    1b00:	38c00217 	ldw	r3,8(r7)
+    1b04:	a1bfff04 	addi	r6,r20,-4
+    1b08:	31400968 	cmpgeui	r5,r6,37
+    1b0c:	18800315 	stw	r2,12(r3)
+    1b10:	10c00215 	stw	r3,8(r2)
+    1b14:	39000204 	addi	r4,r7,8
+    1b18:	3ded883a 	add	r22,r7,r23
+    1b1c:	2800941e 	bne	r5,zero,1d70 <_realloc_r+0x360>
+    1b20:	30800530 	cmpltui	r2,r6,20
+    1b24:	80c00017 	ldw	r3,0(r16)
+    1b28:	1000df1e 	bne	r2,zero,1ea8 <_realloc_r+0x498>
+    1b2c:	38c00215 	stw	r3,8(r7)
+    1b30:	80c00117 	ldw	r3,4(r16)
+    1b34:	30800728 	cmpgeui	r2,r6,28
+    1b38:	38c00315 	stw	r3,12(r7)
+    1b3c:	1000dc1e 	bne	r2,zero,1eb0 <_realloc_r+0x4a0>
+    1b40:	80c00217 	ldw	r3,8(r16)
+    1b44:	38800404 	addi	r2,r7,16
+    1b48:	84000204 	addi	r16,r16,8
+    1b4c:	10c00015 	stw	r3,0(r2)
+    1b50:	80c00117 	ldw	r3,4(r16)
+    1b54:	b829883a 	mov	r20,r23
+    1b58:	382b883a 	mov	r21,r7
+    1b5c:	10c00115 	stw	r3,4(r2)
+    1b60:	80c00217 	ldw	r3,8(r16)
+    1b64:	2021883a 	mov	r16,r4
+    1b68:	10c00215 	stw	r3,8(r2)
+    1b6c:	a9800117 	ldw	r6,4(r21)
+    1b70:	a445c83a 	sub	r2,r20,r17
+    1b74:	10c00430 	cmpltui	r3,r2,16
+    1b78:	3180004c 	andi	r6,r6,1
+    1b7c:	18004926 	beq	r3,zero,1ca4 <_realloc_r+0x294>
+    1b80:	a18cb03a 	or	r6,r20,r6
+    1b84:	a9800115 	stw	r6,4(r21)
+    1b88:	b0800117 	ldw	r2,4(r22)
+    1b8c:	10800054 	ori	r2,r2,1
+    1b90:	b0800115 	stw	r2,4(r22)
+    1b94:	9809883a 	mov	r4,r19
+    1b98:	00036a00 	call	36a0 <__malloc_unlock>
+    1b9c:	8025883a 	mov	r18,r16
+    1ba0:	00000606 	br	1bbc <_realloc_r+0x1ac>
+    1ba4:	04400404 	movi	r17,16
+    1ba8:	00c00404 	movi	r3,16
+    1bac:	8cbfb02e 	bgeu	r17,r18,1a70 <_realloc_r+0x60>
+    1bb0:	00800304 	movi	r2,12
+    1bb4:	98800015 	stw	r2,0(r19)
+    1bb8:	0025883a 	mov	r18,zero
+    1bbc:	9005883a 	mov	r2,r18
+    1bc0:	dfc00a17 	ldw	ra,40(sp)
+    1bc4:	df000917 	ldw	fp,36(sp)
+    1bc8:	ddc00817 	ldw	r23,32(sp)
+    1bcc:	dd800717 	ldw	r22,28(sp)
+    1bd0:	dd400617 	ldw	r21,24(sp)
+    1bd4:	dd000517 	ldw	r20,20(sp)
+    1bd8:	dcc00417 	ldw	r19,16(sp)
+    1bdc:	dc800317 	ldw	r18,12(sp)
+    1be0:	dc400217 	ldw	r17,8(sp)
+    1be4:	dc000117 	ldw	r16,4(sp)
+    1be8:	dec00b04 	addi	sp,sp,44
+    1bec:	f800283a 	ret
+    1bf0:	1080004c 	andi	r2,r2,1
+    1bf4:	10006c26 	beq	r2,zero,1da8 <_realloc_r+0x398>
+    1bf8:	900b883a 	mov	r5,r18
+    1bfc:	9809883a 	mov	r4,r19
+    1c00:	0000e440 	call	e44 <_malloc_r>
+    1c04:	1025883a 	mov	r18,r2
+    1c08:	10001626 	beq	r2,zero,1c64 <_realloc_r+0x254>
+    1c0c:	80bfff17 	ldw	r2,-4(r16)
+    1c10:	013fff84 	movi	r4,-2
+    1c14:	90fffe04 	addi	r3,r18,-8
+    1c18:	1104703a 	and	r2,r2,r4
+    1c1c:	a885883a 	add	r2,r21,r2
+    1c20:	10c05b26 	beq	r2,r3,1d90 <_realloc_r+0x380>
+    1c24:	a1bfff04 	addi	r6,r20,-4
+    1c28:	30800968 	cmpgeui	r2,r6,37
+    1c2c:	10006a1e 	bne	r2,zero,1dd8 <_realloc_r+0x3c8>
+    1c30:	30800530 	cmpltui	r2,r6,20
+    1c34:	81000017 	ldw	r4,0(r16)
+    1c38:	10003726 	beq	r2,zero,1d18 <_realloc_r+0x308>
+    1c3c:	9005883a 	mov	r2,r18
+    1c40:	8007883a 	mov	r3,r16
+    1c44:	11000015 	stw	r4,0(r2)
+    1c48:	19000117 	ldw	r4,4(r3)
+    1c4c:	11000115 	stw	r4,4(r2)
+    1c50:	18c00217 	ldw	r3,8(r3)
+    1c54:	10c00215 	stw	r3,8(r2)
+    1c58:	800b883a 	mov	r5,r16
+    1c5c:	9809883a 	mov	r4,r19
+    1c60:	00028f40 	call	28f4 <_free_r>
+    1c64:	9809883a 	mov	r4,r19
+    1c68:	00036a00 	call	36a0 <__malloc_unlock>
+    1c6c:	003fd306 	br	1bbc <_realloc_r+0x1ac>
+    1c70:	300b883a 	mov	r5,r6
+    1c74:	dfc00a17 	ldw	ra,40(sp)
+    1c78:	df000917 	ldw	fp,36(sp)
+    1c7c:	ddc00817 	ldw	r23,32(sp)
+    1c80:	dd800717 	ldw	r22,28(sp)
+    1c84:	dd400617 	ldw	r21,24(sp)
+    1c88:	dd000517 	ldw	r20,20(sp)
+    1c8c:	dcc00417 	ldw	r19,16(sp)
+    1c90:	dc800317 	ldw	r18,12(sp)
+    1c94:	dc400217 	ldw	r17,8(sp)
+    1c98:	dc000117 	ldw	r16,4(sp)
+    1c9c:	dec00b04 	addi	sp,sp,44
+    1ca0:	0000e441 	jmpi	e44 <_malloc_r>
+    1ca4:	344cb03a 	or	r6,r6,r17
+    1ca8:	a9800115 	stw	r6,4(r21)
+    1cac:	ac4b883a 	add	r5,r21,r17
+    1cb0:	10800054 	ori	r2,r2,1
+    1cb4:	28800115 	stw	r2,4(r5)
+    1cb8:	b0800117 	ldw	r2,4(r22)
+    1cbc:	29400204 	addi	r5,r5,8
+    1cc0:	9809883a 	mov	r4,r19
+    1cc4:	10800054 	ori	r2,r2,1
+    1cc8:	b0800115 	stw	r2,4(r22)
+    1ccc:	00028f40 	call	28f4 <_free_r>
+    1cd0:	003fb006 	br	1b94 <_realloc_r+0x184>
+    1cd4:	2148703a 	and	r4,r4,r5
+    1cd8:	a10b883a 	add	r5,r20,r4
+    1cdc:	89800404 	addi	r6,r17,16
+    1ce0:	29bf7716 	blt	r5,r6,1ac0 <_realloc_r+0xb0>
+    1ce4:	ac6b883a 	add	r21,r21,r17
+    1ce8:	2c45c83a 	sub	r2,r5,r17
+    1cec:	e5400215 	stw	r21,8(fp)
+    1cf0:	10800054 	ori	r2,r2,1
+    1cf4:	a8800115 	stw	r2,4(r21)
+    1cf8:	80bfff17 	ldw	r2,-4(r16)
+    1cfc:	9809883a 	mov	r4,r19
+    1d00:	8025883a 	mov	r18,r16
+    1d04:	1080004c 	andi	r2,r2,1
+    1d08:	1462b03a 	or	r17,r2,r17
+    1d0c:	847fff15 	stw	r17,-4(r16)
+    1d10:	00036a00 	call	36a0 <__malloc_unlock>
+    1d14:	003fa906 	br	1bbc <_realloc_r+0x1ac>
+    1d18:	91000015 	stw	r4,0(r18)
+    1d1c:	80c00117 	ldw	r3,4(r16)
+    1d20:	30800728 	cmpgeui	r2,r6,28
+    1d24:	90c00115 	stw	r3,4(r18)
+    1d28:	1000551e 	bne	r2,zero,1e80 <_realloc_r+0x470>
+    1d2c:	81000217 	ldw	r4,8(r16)
+    1d30:	80c00204 	addi	r3,r16,8
+    1d34:	90800204 	addi	r2,r18,8
+    1d38:	003fc206 	br	1c44 <_realloc_r+0x234>
+    1d3c:	b0800317 	ldw	r2,12(r22)
+    1d40:	b0c00217 	ldw	r3,8(r22)
+    1d44:	a1bfff04 	addi	r6,r20,-4
+    1d48:	31400968 	cmpgeui	r5,r6,37
+    1d4c:	18800315 	stw	r2,12(r3)
+    1d50:	10c00215 	stw	r3,8(r2)
+    1d54:	38c00217 	ldw	r3,8(r7)
+    1d58:	38800317 	ldw	r2,12(r7)
+    1d5c:	39000204 	addi	r4,r7,8
+    1d60:	3ded883a 	add	r22,r7,r23
+    1d64:	18800315 	stw	r2,12(r3)
+    1d68:	10c00215 	stw	r3,8(r2)
+    1d6c:	283f6c26 	beq	r5,zero,1b20 <_realloc_r+0x110>
+    1d70:	800b883a 	mov	r5,r16
+    1d74:	d9c00015 	stw	r7,0(sp)
+    1d78:	00017f40 	call	17f4 <memmove>
+    1d7c:	d9c00017 	ldw	r7,0(sp)
+    1d80:	1021883a 	mov	r16,r2
+    1d84:	b829883a 	mov	r20,r23
+    1d88:	382b883a 	mov	r21,r7
+    1d8c:	003f7706 	br	1b6c <_realloc_r+0x15c>
+    1d90:	90bfff17 	ldw	r2,-4(r18)
+    1d94:	00ffff04 	movi	r3,-4
+    1d98:	10c4703a 	and	r2,r2,r3
+    1d9c:	a0a9883a 	add	r20,r20,r2
+    1da0:	ad2d883a 	add	r22,r21,r20
+    1da4:	003f7106 	br	1b6c <_realloc_r+0x15c>
+    1da8:	81fffe17 	ldw	r7,-8(r16)
+    1dac:	a9cfc83a 	sub	r7,r21,r7
+    1db0:	38800117 	ldw	r2,4(r7)
+    1db4:	114a703a 	and	r5,r2,r5
+    1db8:	003f4d06 	br	1af0 <_realloc_r+0xe0>
+    1dbc:	b0800317 	ldw	r2,12(r22)
+    1dc0:	b0c00217 	ldw	r3,8(r22)
+    1dc4:	2829883a 	mov	r20,r5
+    1dc8:	a96d883a 	add	r22,r21,r5
+    1dcc:	18800315 	stw	r2,12(r3)
+    1dd0:	10c00215 	stw	r3,8(r2)
+    1dd4:	003f6506 	br	1b6c <_realloc_r+0x15c>
+    1dd8:	800b883a 	mov	r5,r16
+    1ddc:	9009883a 	mov	r4,r18
+    1de0:	00017f40 	call	17f4 <memmove>
+    1de4:	003f9c06 	br	1c58 <_realloc_r+0x248>
+    1de8:	88800404 	addi	r2,r17,16
+    1dec:	b8bf4016 	blt	r23,r2,1af0 <_realloc_r+0xe0>
+    1df0:	38800317 	ldw	r2,12(r7)
+    1df4:	38c00217 	ldw	r3,8(r7)
+    1df8:	a1bfff04 	addi	r6,r20,-4
+    1dfc:	31000968 	cmpgeui	r4,r6,37
+    1e00:	18800315 	stw	r2,12(r3)
+    1e04:	10c00215 	stw	r3,8(r2)
+    1e08:	3c800204 	addi	r18,r7,8
+    1e0c:	20003b1e 	bne	r4,zero,1efc <_realloc_r+0x4ec>
+    1e10:	30800530 	cmpltui	r2,r6,20
+    1e14:	80c00017 	ldw	r3,0(r16)
+    1e18:	1000361e 	bne	r2,zero,1ef4 <_realloc_r+0x4e4>
+    1e1c:	38c00215 	stw	r3,8(r7)
+    1e20:	80c00117 	ldw	r3,4(r16)
+    1e24:	30800728 	cmpgeui	r2,r6,28
+    1e28:	38c00315 	stw	r3,12(r7)
+    1e2c:	1000401e 	bne	r2,zero,1f30 <_realloc_r+0x520>
+    1e30:	80c00217 	ldw	r3,8(r16)
+    1e34:	38800404 	addi	r2,r7,16
+    1e38:	84000204 	addi	r16,r16,8
+    1e3c:	10c00015 	stw	r3,0(r2)
+    1e40:	80c00117 	ldw	r3,4(r16)
+    1e44:	10c00115 	stw	r3,4(r2)
+    1e48:	80c00217 	ldw	r3,8(r16)
+    1e4c:	10c00215 	stw	r3,8(r2)
+    1e50:	3c47883a 	add	r3,r7,r17
+    1e54:	bc45c83a 	sub	r2,r23,r17
+    1e58:	e0c00215 	stw	r3,8(fp)
+    1e5c:	10800054 	ori	r2,r2,1
+    1e60:	18800115 	stw	r2,4(r3)
+    1e64:	38800117 	ldw	r2,4(r7)
+    1e68:	9809883a 	mov	r4,r19
+    1e6c:	1080004c 	andi	r2,r2,1
+    1e70:	1462b03a 	or	r17,r2,r17
+    1e74:	3c400115 	stw	r17,4(r7)
+    1e78:	00036a00 	call	36a0 <__malloc_unlock>
+    1e7c:	003f4f06 	br	1bbc <_realloc_r+0x1ac>
+    1e80:	80800217 	ldw	r2,8(r16)
+    1e84:	31800920 	cmpeqi	r6,r6,36
+    1e88:	90800215 	stw	r2,8(r18)
+    1e8c:	80800317 	ldw	r2,12(r16)
+    1e90:	90800315 	stw	r2,12(r18)
+    1e94:	81000417 	ldw	r4,16(r16)
+    1e98:	30000f1e 	bne	r6,zero,1ed8 <_realloc_r+0x4c8>
+    1e9c:	80c00404 	addi	r3,r16,16
+    1ea0:	90800404 	addi	r2,r18,16
+    1ea4:	003f6706 	br	1c44 <_realloc_r+0x234>
+    1ea8:	2005883a 	mov	r2,r4
+    1eac:	003f2706 	br	1b4c <_realloc_r+0x13c>
+    1eb0:	80800217 	ldw	r2,8(r16)
+    1eb4:	31800920 	cmpeqi	r6,r6,36
+    1eb8:	38800415 	stw	r2,16(r7)
+    1ebc:	80800317 	ldw	r2,12(r16)
+    1ec0:	38800515 	stw	r2,20(r7)
+    1ec4:	80c00417 	ldw	r3,16(r16)
+    1ec8:	3000121e 	bne	r6,zero,1f14 <_realloc_r+0x504>
+    1ecc:	38800604 	addi	r2,r7,24
+    1ed0:	84000404 	addi	r16,r16,16
+    1ed4:	003f1d06 	br	1b4c <_realloc_r+0x13c>
+    1ed8:	91000415 	stw	r4,16(r18)
+    1edc:	81000517 	ldw	r4,20(r16)
+    1ee0:	80c00604 	addi	r3,r16,24
+    1ee4:	90800604 	addi	r2,r18,24
+    1ee8:	91000515 	stw	r4,20(r18)
+    1eec:	81000617 	ldw	r4,24(r16)
+    1ef0:	003f5406 	br	1c44 <_realloc_r+0x234>
+    1ef4:	9005883a 	mov	r2,r18
+    1ef8:	003fd006 	br	1e3c <_realloc_r+0x42c>
+    1efc:	800b883a 	mov	r5,r16
+    1f00:	9009883a 	mov	r4,r18
+    1f04:	d9c00015 	stw	r7,0(sp)
+    1f08:	00017f40 	call	17f4 <memmove>
+    1f0c:	d9c00017 	ldw	r7,0(sp)
+    1f10:	003fcf06 	br	1e50 <_realloc_r+0x440>
+    1f14:	84000604 	addi	r16,r16,24
+    1f18:	38c00615 	stw	r3,24(r7)
+    1f1c:	80ffff17 	ldw	r3,-4(r16)
+    1f20:	38800804 	addi	r2,r7,32
+    1f24:	38c00715 	stw	r3,28(r7)
+    1f28:	80c00017 	ldw	r3,0(r16)
+    1f2c:	003f0706 	br	1b4c <_realloc_r+0x13c>
+    1f30:	80800217 	ldw	r2,8(r16)
+    1f34:	31800920 	cmpeqi	r6,r6,36
+    1f38:	38800415 	stw	r2,16(r7)
+    1f3c:	80800317 	ldw	r2,12(r16)
+    1f40:	38800515 	stw	r2,20(r7)
+    1f44:	80c00417 	ldw	r3,16(r16)
+    1f48:	3000031e 	bne	r6,zero,1f58 <_realloc_r+0x548>
+    1f4c:	38800604 	addi	r2,r7,24
+    1f50:	84000404 	addi	r16,r16,16
+    1f54:	003fb906 	br	1e3c <_realloc_r+0x42c>
+    1f58:	84000604 	addi	r16,r16,24
+    1f5c:	38c00615 	stw	r3,24(r7)
+    1f60:	80ffff17 	ldw	r3,-4(r16)
+    1f64:	38800804 	addi	r2,r7,32
+    1f68:	38c00715 	stw	r3,28(r7)
+    1f6c:	80c00017 	ldw	r3,0(r16)
+    1f70:	003fb206 	br	1e3c <_realloc_r+0x42c>
+
+00001f74 <_sbrk_r>:
+    1f74:	defffe04 	addi	sp,sp,-8
+    1f78:	dc000015 	stw	r16,0(sp)
+    1f7c:	00800034 	movhi	r2,0
+    1f80:	2021883a 	mov	r16,r4
+    1f84:	2809883a 	mov	r4,r5
+    1f88:	dfc00115 	stw	ra,4(sp)
+    1f8c:	101c9115 	stw	zero,29252(r2)
+    1f90:	00038780 	call	3878 <sbrk>
+    1f94:	10ffffd8 	cmpnei	r3,r2,-1
+    1f98:	18000426 	beq	r3,zero,1fac <_sbrk_r+0x38>
+    1f9c:	dfc00117 	ldw	ra,4(sp)
+    1fa0:	dc000017 	ldw	r16,0(sp)
+    1fa4:	dec00204 	addi	sp,sp,8
+    1fa8:	f800283a 	ret
+    1fac:	00c00034 	movhi	r3,0
+    1fb0:	18dc9117 	ldw	r3,29252(r3)
+    1fb4:	183ff926 	beq	r3,zero,1f9c <_sbrk_r+0x28>
+    1fb8:	80c00015 	stw	r3,0(r16)
+    1fbc:	dfc00117 	ldw	ra,4(sp)
+    1fc0:	dc000017 	ldw	r16,0(sp)
+    1fc4:	dec00204 	addi	sp,sp,8
+    1fc8:	f800283a 	ret
+
+00001fcc <__sread>:
+    1fcc:	defffe04 	addi	sp,sp,-8
+    1fd0:	dc000015 	stw	r16,0(sp)
+    1fd4:	2821883a 	mov	r16,r5
+    1fd8:	2940038f 	ldh	r5,14(r5)
+    1fdc:	dfc00115 	stw	ra,4(sp)
+    1fe0:	0002e9c0 	call	2e9c <_read_r>
+    1fe4:	10000716 	blt	r2,zero,2004 <__sread+0x38>
+    1fe8:	80c01417 	ldw	r3,80(r16)
+    1fec:	1887883a 	add	r3,r3,r2
+    1ff0:	80c01415 	stw	r3,80(r16)
+    1ff4:	dfc00117 	ldw	ra,4(sp)
+    1ff8:	dc000017 	ldw	r16,0(sp)
+    1ffc:	dec00204 	addi	sp,sp,8
+    2000:	f800283a 	ret
+    2004:	80c0030b 	ldhu	r3,12(r16)
+    2008:	18fbffcc 	andi	r3,r3,61439
+    200c:	80c0030d 	sth	r3,12(r16)
+    2010:	dfc00117 	ldw	ra,4(sp)
+    2014:	dc000017 	ldw	r16,0(sp)
+    2018:	dec00204 	addi	sp,sp,8
+    201c:	f800283a 	ret
+
+00002020 <__seofread>:
+    2020:	0005883a 	mov	r2,zero
+    2024:	f800283a 	ret
+
+00002028 <__swrite>:
+    2028:	2880030b 	ldhu	r2,12(r5)
+    202c:	defffb04 	addi	sp,sp,-20
+    2030:	dcc00315 	stw	r19,12(sp)
+    2034:	dc800215 	stw	r18,8(sp)
+    2038:	dc400115 	stw	r17,4(sp)
+    203c:	dc000015 	stw	r16,0(sp)
+    2040:	dfc00415 	stw	ra,16(sp)
+    2044:	10c0400c 	andi	r3,r2,256
+    2048:	2821883a 	mov	r16,r5
+    204c:	2023883a 	mov	r17,r4
+    2050:	2940038f 	ldh	r5,14(r5)
+    2054:	3025883a 	mov	r18,r6
+    2058:	3827883a 	mov	r19,r7
+    205c:	18000c1e 	bne	r3,zero,2090 <__swrite+0x68>
+    2060:	10bbffcc 	andi	r2,r2,61439
+    2064:	980f883a 	mov	r7,r19
+    2068:	900d883a 	mov	r6,r18
+    206c:	8809883a 	mov	r4,r17
+    2070:	8080030d 	sth	r2,12(r16)
+    2074:	dfc00417 	ldw	ra,16(sp)
+    2078:	dcc00317 	ldw	r19,12(sp)
+    207c:	dc800217 	ldw	r18,8(sp)
+    2080:	dc400117 	ldw	r17,4(sp)
+    2084:	dc000017 	ldw	r16,0(sp)
+    2088:	dec00504 	addi	sp,sp,20
+    208c:	000210c1 	jmpi	210c <_write_r>
+    2090:	01c00084 	movi	r7,2
+    2094:	000d883a 	mov	r6,zero
+    2098:	0002bf00 	call	2bf0 <_lseek_r>
+    209c:	8080030b 	ldhu	r2,12(r16)
+    20a0:	8140038f 	ldh	r5,14(r16)
+    20a4:	003fee06 	br	2060 <__swrite+0x38>
+
+000020a8 <__sseek>:
+    20a8:	defffe04 	addi	sp,sp,-8
+    20ac:	dc000015 	stw	r16,0(sp)
+    20b0:	2821883a 	mov	r16,r5
+    20b4:	2940038f 	ldh	r5,14(r5)
+    20b8:	dfc00115 	stw	ra,4(sp)
+    20bc:	0002bf00 	call	2bf0 <_lseek_r>
+    20c0:	10ffffd8 	cmpnei	r3,r2,-1
+    20c4:	18000826 	beq	r3,zero,20e8 <__sseek+0x40>
+    20c8:	80c0030b 	ldhu	r3,12(r16)
+    20cc:	80801415 	stw	r2,80(r16)
+    20d0:	18c40014 	ori	r3,r3,4096
+    20d4:	80c0030d 	sth	r3,12(r16)
+    20d8:	dfc00117 	ldw	ra,4(sp)
+    20dc:	dc000017 	ldw	r16,0(sp)
+    20e0:	dec00204 	addi	sp,sp,8
+    20e4:	f800283a 	ret
+    20e8:	80c0030b 	ldhu	r3,12(r16)
+    20ec:	18fbffcc 	andi	r3,r3,61439
+    20f0:	80c0030d 	sth	r3,12(r16)
+    20f4:	dfc00117 	ldw	ra,4(sp)
+    20f8:	dc000017 	ldw	r16,0(sp)
+    20fc:	dec00204 	addi	sp,sp,8
+    2100:	f800283a 	ret
+
+00002104 <__sclose>:
+    2104:	2940038f 	ldh	r5,14(r5)
+    2108:	00022d41 	jmpi	22d4 <_close_r>
+
+0000210c <_write_r>:
+    210c:	2807883a 	mov	r3,r5
+    2110:	defffe04 	addi	sp,sp,-8
+    2114:	dc000015 	stw	r16,0(sp)
+    2118:	300b883a 	mov	r5,r6
+    211c:	00800034 	movhi	r2,0
+    2120:	380d883a 	mov	r6,r7
+    2124:	2021883a 	mov	r16,r4
+    2128:	1809883a 	mov	r4,r3
+    212c:	dfc00115 	stw	ra,4(sp)
+    2130:	101c9115 	stw	zero,29252(r2)
+    2134:	000396c0 	call	396c <write>
+    2138:	10ffffd8 	cmpnei	r3,r2,-1
+    213c:	18000426 	beq	r3,zero,2150 <_write_r+0x44>
+    2140:	dfc00117 	ldw	ra,4(sp)
+    2144:	dc000017 	ldw	r16,0(sp)
+    2148:	dec00204 	addi	sp,sp,8
+    214c:	f800283a 	ret
+    2150:	00c00034 	movhi	r3,0
+    2154:	18dc9117 	ldw	r3,29252(r3)
+    2158:	183ff926 	beq	r3,zero,2140 <_write_r+0x34>
+    215c:	80c00015 	stw	r3,0(r16)
+    2160:	dfc00117 	ldw	ra,4(sp)
+    2164:	dc000017 	ldw	r16,0(sp)
+    2168:	dec00204 	addi	sp,sp,8
+    216c:	f800283a 	ret
+
+00002170 <__swsetup_r>:
+    2170:	00800034 	movhi	r2,0
+    2174:	109c8117 	ldw	r2,29188(r2)
+    2178:	defffd04 	addi	sp,sp,-12
+    217c:	dc400115 	stw	r17,4(sp)
+    2180:	dc000015 	stw	r16,0(sp)
+    2184:	dfc00215 	stw	ra,8(sp)
+    2188:	2023883a 	mov	r17,r4
+    218c:	2821883a 	mov	r16,r5
+    2190:	10000226 	beq	r2,zero,219c <__swsetup_r+0x2c>
+    2194:	10c00e17 	ldw	r3,56(r2)
+    2198:	18001f26 	beq	r3,zero,2218 <__swsetup_r+0xa8>
+    219c:	8180030b 	ldhu	r6,12(r16)
+    21a0:	30c0020c 	andi	r3,r6,8
+    21a4:	3005883a 	mov	r2,r6
+    21a8:	18002126 	beq	r3,zero,2230 <__swsetup_r+0xc0>
+    21ac:	80c00417 	ldw	r3,16(r16)
+    21b0:	18002826 	beq	r3,zero,2254 <__swsetup_r+0xe4>
+    21b4:	1100004c 	andi	r4,r2,1
+    21b8:	20000b1e 	bne	r4,zero,21e8 <__swsetup_r+0x78>
+    21bc:	1100008c 	andi	r4,r2,2
+    21c0:	20002e1e 	bne	r4,zero,227c <__swsetup_r+0x10c>
+    21c4:	81000517 	ldw	r4,20(r16)
+    21c8:	81000215 	stw	r4,8(r16)
+    21cc:	18000b26 	beq	r3,zero,21fc <__swsetup_r+0x8c>
+    21d0:	0005883a 	mov	r2,zero
+    21d4:	dfc00217 	ldw	ra,8(sp)
+    21d8:	dc400117 	ldw	r17,4(sp)
+    21dc:	dc000017 	ldw	r16,0(sp)
+    21e0:	dec00304 	addi	sp,sp,12
+    21e4:	f800283a 	ret
+    21e8:	81000517 	ldw	r4,20(r16)
+    21ec:	80000215 	stw	zero,8(r16)
+    21f0:	0109c83a 	sub	r4,zero,r4
+    21f4:	81000615 	stw	r4,24(r16)
+    21f8:	183ff51e 	bne	r3,zero,21d0 <__swsetup_r+0x60>
+    21fc:	10c0200c 	andi	r3,r2,128
+    2200:	0005883a 	mov	r2,zero
+    2204:	183ff326 	beq	r3,zero,21d4 <__swsetup_r+0x64>
+    2208:	31801014 	ori	r6,r6,64
+    220c:	8180030d 	sth	r6,12(r16)
+    2210:	00bfffc4 	movi	r2,-1
+    2214:	003fef06 	br	21d4 <__swsetup_r+0x64>
+    2218:	1009883a 	mov	r4,r2
+    221c:	00007f40 	call	7f4 <__sinit>
+    2220:	8180030b 	ldhu	r6,12(r16)
+    2224:	30c0020c 	andi	r3,r6,8
+    2228:	3005883a 	mov	r2,r6
+    222c:	183fdf1e 	bne	r3,zero,21ac <__swsetup_r+0x3c>
+    2230:	3080040c 	andi	r2,r6,16
+    2234:	10002126 	beq	r2,zero,22bc <__swsetup_r+0x14c>
+    2238:	3080010c 	andi	r2,r6,4
+    223c:	1000111e 	bne	r2,zero,2284 <__swsetup_r+0x114>
+    2240:	80c00417 	ldw	r3,16(r16)
+    2244:	30800214 	ori	r2,r6,8
+    2248:	8080030d 	sth	r2,12(r16)
+    224c:	100d883a 	mov	r6,r2
+    2250:	183fd81e 	bne	r3,zero,21b4 <__swsetup_r+0x44>
+    2254:	1100a00c 	andi	r4,r2,640
+    2258:	21008020 	cmpeqi	r4,r4,512
+    225c:	203fd51e 	bne	r4,zero,21b4 <__swsetup_r+0x44>
+    2260:	800b883a 	mov	r5,r16
+    2264:	8809883a 	mov	r4,r17
+    2268:	0002c540 	call	2c54 <__smakebuf_r>
+    226c:	8180030b 	ldhu	r6,12(r16)
+    2270:	80c00417 	ldw	r3,16(r16)
+    2274:	3005883a 	mov	r2,r6
+    2278:	003fce06 	br	21b4 <__swsetup_r+0x44>
+    227c:	0009883a 	mov	r4,zero
+    2280:	003fd106 	br	21c8 <__swsetup_r+0x58>
+    2284:	81400c17 	ldw	r5,48(r16)
+    2288:	28000626 	beq	r5,zero,22a4 <__swsetup_r+0x134>
+    228c:	80801004 	addi	r2,r16,64
+    2290:	28800326 	beq	r5,r2,22a0 <__swsetup_r+0x130>
+    2294:	8809883a 	mov	r4,r17
+    2298:	00028f40 	call	28f4 <_free_r>
+    229c:	8180030b 	ldhu	r6,12(r16)
+    22a0:	80000c15 	stw	zero,48(r16)
+    22a4:	80c00417 	ldw	r3,16(r16)
+    22a8:	00bff6c4 	movi	r2,-37
+    22ac:	118c703a 	and	r6,r2,r6
+    22b0:	80000115 	stw	zero,4(r16)
+    22b4:	80c00015 	stw	r3,0(r16)
+    22b8:	003fe206 	br	2244 <__swsetup_r+0xd4>
+    22bc:	00800244 	movi	r2,9
+    22c0:	88800015 	stw	r2,0(r17)
+    22c4:	31801014 	ori	r6,r6,64
+    22c8:	8180030d 	sth	r6,12(r16)
+    22cc:	00bfffc4 	movi	r2,-1
+    22d0:	003fc006 	br	21d4 <__swsetup_r+0x64>
+
+000022d4 <_close_r>:
+    22d4:	defffe04 	addi	sp,sp,-8
+    22d8:	dc000015 	stw	r16,0(sp)
+    22dc:	00800034 	movhi	r2,0
+    22e0:	2021883a 	mov	r16,r4
+    22e4:	2809883a 	mov	r4,r5
+    22e8:	dfc00115 	stw	ra,4(sp)
+    22ec:	101c9115 	stw	zero,29252(r2)
+    22f0:	00031d00 	call	31d0 <close>
+    22f4:	10ffffd8 	cmpnei	r3,r2,-1
+    22f8:	18000426 	beq	r3,zero,230c <_close_r+0x38>
+    22fc:	dfc00117 	ldw	ra,4(sp)
+    2300:	dc000017 	ldw	r16,0(sp)
+    2304:	dec00204 	addi	sp,sp,8
+    2308:	f800283a 	ret
+    230c:	00c00034 	movhi	r3,0
+    2310:	18dc9117 	ldw	r3,29252(r3)
+    2314:	183ff926 	beq	r3,zero,22fc <_close_r+0x28>
+    2318:	80c00015 	stw	r3,0(r16)
+    231c:	dfc00117 	ldw	ra,4(sp)
+    2320:	dc000017 	ldw	r16,0(sp)
+    2324:	dec00204 	addi	sp,sp,8
+    2328:	f800283a 	ret
+
+0000232c <_fclose_r.part.0>:
+    232c:	defffc04 	addi	sp,sp,-16
+    2330:	dc800215 	stw	r18,8(sp)
+    2334:	dc400115 	stw	r17,4(sp)
+    2338:	dc000015 	stw	r16,0(sp)
+    233c:	dfc00315 	stw	ra,12(sp)
+    2340:	2821883a 	mov	r16,r5
+    2344:	2023883a 	mov	r17,r4
+    2348:	00024cc0 	call	24cc <__sflush_r>
+    234c:	80c00b17 	ldw	r3,44(r16)
+    2350:	1025883a 	mov	r18,r2
+    2354:	18000426 	beq	r3,zero,2368 <_fclose_r.part.0+0x3c>
+    2358:	81400717 	ldw	r5,28(r16)
+    235c:	8809883a 	mov	r4,r17
+    2360:	183ee83a 	callr	r3
+    2364:	10001916 	blt	r2,zero,23cc <_fclose_r.part.0+0xa0>
+    2368:	8080030b 	ldhu	r2,12(r16)
+    236c:	1080200c 	andi	r2,r2,128
+    2370:	10001a1e 	bne	r2,zero,23dc <_fclose_r.part.0+0xb0>
+    2374:	81400c17 	ldw	r5,48(r16)
+    2378:	28000526 	beq	r5,zero,2390 <_fclose_r.part.0+0x64>
+    237c:	80801004 	addi	r2,r16,64
+    2380:	28800226 	beq	r5,r2,238c <_fclose_r.part.0+0x60>
+    2384:	8809883a 	mov	r4,r17
+    2388:	00028f40 	call	28f4 <_free_r>
+    238c:	80000c15 	stw	zero,48(r16)
+    2390:	81401117 	ldw	r5,68(r16)
+    2394:	28000326 	beq	r5,zero,23a4 <_fclose_r.part.0+0x78>
+    2398:	8809883a 	mov	r4,r17
+    239c:	00028f40 	call	28f4 <_free_r>
+    23a0:	80001115 	stw	zero,68(r16)
+    23a4:	00008040 	call	804 <__sfp_lock_acquire>
+    23a8:	8000030d 	sth	zero,12(r16)
+    23ac:	00008080 	call	808 <__sfp_lock_release>
+    23b0:	9005883a 	mov	r2,r18
+    23b4:	dfc00317 	ldw	ra,12(sp)
+    23b8:	dc800217 	ldw	r18,8(sp)
+    23bc:	dc400117 	ldw	r17,4(sp)
+    23c0:	dc000017 	ldw	r16,0(sp)
+    23c4:	dec00404 	addi	sp,sp,16
+    23c8:	f800283a 	ret
+    23cc:	8080030b 	ldhu	r2,12(r16)
+    23d0:	04bfffc4 	movi	r18,-1
+    23d4:	1080200c 	andi	r2,r2,128
+    23d8:	103fe626 	beq	r2,zero,2374 <_fclose_r.part.0+0x48>
+    23dc:	81400417 	ldw	r5,16(r16)
+    23e0:	8809883a 	mov	r4,r17
+    23e4:	00028f40 	call	28f4 <_free_r>
+    23e8:	003fe206 	br	2374 <_fclose_r.part.0+0x48>
+
+000023ec <_fclose_r>:
+    23ec:	28001926 	beq	r5,zero,2454 <_fclose_r+0x68>
+    23f0:	defffd04 	addi	sp,sp,-12
+    23f4:	dc000115 	stw	r16,4(sp)
+    23f8:	dfc00215 	stw	ra,8(sp)
+    23fc:	2021883a 	mov	r16,r4
+    2400:	20000226 	beq	r4,zero,240c <_fclose_r+0x20>
+    2404:	20800e17 	ldw	r2,56(r4)
+    2408:	10000c26 	beq	r2,zero,243c <_fclose_r+0x50>
+    240c:	2880030f 	ldh	r2,12(r5)
+    2410:	1000051e 	bne	r2,zero,2428 <_fclose_r+0x3c>
+    2414:	0005883a 	mov	r2,zero
+    2418:	dfc00217 	ldw	ra,8(sp)
+    241c:	dc000117 	ldw	r16,4(sp)
+    2420:	dec00304 	addi	sp,sp,12
+    2424:	f800283a 	ret
+    2428:	8009883a 	mov	r4,r16
+    242c:	dfc00217 	ldw	ra,8(sp)
+    2430:	dc000117 	ldw	r16,4(sp)
+    2434:	dec00304 	addi	sp,sp,12
+    2438:	000232c1 	jmpi	232c <_fclose_r.part.0>
+    243c:	d9400015 	stw	r5,0(sp)
+    2440:	00007f40 	call	7f4 <__sinit>
+    2444:	d9400017 	ldw	r5,0(sp)
+    2448:	2880030f 	ldh	r2,12(r5)
+    244c:	103ff126 	beq	r2,zero,2414 <_fclose_r+0x28>
+    2450:	003ff506 	br	2428 <_fclose_r+0x3c>
+    2454:	0005883a 	mov	r2,zero
+    2458:	f800283a 	ret
+
+0000245c <fclose>:
+    245c:	20000826 	beq	r4,zero,2480 <fclose+0x24>
+    2460:	00800034 	movhi	r2,0
+    2464:	200b883a 	mov	r5,r4
+    2468:	111c8117 	ldw	r4,29188(r2)
+    246c:	20000226 	beq	r4,zero,2478 <fclose+0x1c>
+    2470:	20800e17 	ldw	r2,56(r4)
+    2474:	10000526 	beq	r2,zero,248c <fclose+0x30>
+    2478:	2880030f 	ldh	r2,12(r5)
+    247c:	1000021e 	bne	r2,zero,2488 <fclose+0x2c>
+    2480:	0005883a 	mov	r2,zero
+    2484:	f800283a 	ret
+    2488:	000232c1 	jmpi	232c <_fclose_r.part.0>
+    248c:	defffd04 	addi	sp,sp,-12
+    2490:	d9400115 	stw	r5,4(sp)
+    2494:	d9000015 	stw	r4,0(sp)
+    2498:	dfc00215 	stw	ra,8(sp)
+    249c:	00007f40 	call	7f4 <__sinit>
+    24a0:	d9400117 	ldw	r5,4(sp)
+    24a4:	d9000017 	ldw	r4,0(sp)
+    24a8:	2880030f 	ldh	r2,12(r5)
+    24ac:	10000326 	beq	r2,zero,24bc <fclose+0x60>
+    24b0:	dfc00217 	ldw	ra,8(sp)
+    24b4:	dec00304 	addi	sp,sp,12
+    24b8:	000232c1 	jmpi	232c <_fclose_r.part.0>
+    24bc:	0005883a 	mov	r2,zero
+    24c0:	dfc00217 	ldw	ra,8(sp)
+    24c4:	dec00304 	addi	sp,sp,12
+    24c8:	f800283a 	ret
+
+000024cc <__sflush_r>:
+    24cc:	2880030b 	ldhu	r2,12(r5)
+    24d0:	defffb04 	addi	sp,sp,-20
+    24d4:	dcc00315 	stw	r19,12(sp)
+    24d8:	dc000015 	stw	r16,0(sp)
+    24dc:	dfc00415 	stw	ra,16(sp)
+    24e0:	dc800215 	stw	r18,8(sp)
+    24e4:	dc400115 	stw	r17,4(sp)
+    24e8:	10c0020c 	andi	r3,r2,8
+    24ec:	2821883a 	mov	r16,r5
+    24f0:	2027883a 	mov	r19,r4
+    24f4:	18003f1e 	bne	r3,zero,25f4 <__sflush_r+0x128>
+    24f8:	28c00117 	ldw	r3,4(r5)
+    24fc:	10820014 	ori	r2,r2,2048
+    2500:	2880030d 	sth	r2,12(r5)
+    2504:	00c0550e 	bge	zero,r3,265c <__sflush_r+0x190>
+    2508:	82000a17 	ldw	r8,40(r16)
+    250c:	40003126 	beq	r8,zero,25d4 <__sflush_r+0x108>
+    2510:	9c400017 	ldw	r17,0(r19)
+    2514:	1104000c 	andi	r4,r2,4096
+    2518:	98000015 	stw	zero,0(r19)
+    251c:	81400717 	ldw	r5,28(r16)
+    2520:	1007883a 	mov	r3,r2
+    2524:	2000521e 	bne	r4,zero,2670 <__sflush_r+0x1a4>
+    2528:	01c00044 	movi	r7,1
+    252c:	000d883a 	mov	r6,zero
+    2530:	9809883a 	mov	r4,r19
+    2534:	403ee83a 	callr	r8
+    2538:	10ffffd8 	cmpnei	r3,r2,-1
+    253c:	18005826 	beq	r3,zero,26a0 <__sflush_r+0x1d4>
+    2540:	80c0030b 	ldhu	r3,12(r16)
+    2544:	82000a17 	ldw	r8,40(r16)
+    2548:	81400717 	ldw	r5,28(r16)
+    254c:	18c0010c 	andi	r3,r3,4
+    2550:	18000626 	beq	r3,zero,256c <__sflush_r+0xa0>
+    2554:	81000117 	ldw	r4,4(r16)
+    2558:	80c00c17 	ldw	r3,48(r16)
+    255c:	1105c83a 	sub	r2,r2,r4
+    2560:	18000226 	beq	r3,zero,256c <__sflush_r+0xa0>
+    2564:	80c00f17 	ldw	r3,60(r16)
+    2568:	10c5c83a 	sub	r2,r2,r3
+    256c:	100d883a 	mov	r6,r2
+    2570:	000f883a 	mov	r7,zero
+    2574:	9809883a 	mov	r4,r19
+    2578:	403ee83a 	callr	r8
+    257c:	10ffffd8 	cmpnei	r3,r2,-1
+    2580:	18003d1e 	bne	r3,zero,2678 <__sflush_r+0x1ac>
+    2584:	99000017 	ldw	r4,0(r19)
+    2588:	80c0030b 	ldhu	r3,12(r16)
+    258c:	20004e26 	beq	r4,zero,26c8 <__sflush_r+0x1fc>
+    2590:	21400760 	cmpeqi	r5,r4,29
+    2594:	2800021e 	bne	r5,zero,25a0 <__sflush_r+0xd4>
+    2598:	210005a0 	cmpeqi	r4,r4,22
+    259c:	20002c26 	beq	r4,zero,2650 <__sflush_r+0x184>
+    25a0:	80800417 	ldw	r2,16(r16)
+    25a4:	18fdffcc 	andi	r3,r3,63487
+    25a8:	80c0030d 	sth	r3,12(r16)
+    25ac:	80000115 	stw	zero,4(r16)
+    25b0:	80800015 	stw	r2,0(r16)
+    25b4:	81400c17 	ldw	r5,48(r16)
+    25b8:	9c400015 	stw	r17,0(r19)
+    25bc:	28000526 	beq	r5,zero,25d4 <__sflush_r+0x108>
+    25c0:	80801004 	addi	r2,r16,64
+    25c4:	28800226 	beq	r5,r2,25d0 <__sflush_r+0x104>
+    25c8:	9809883a 	mov	r4,r19
+    25cc:	00028f40 	call	28f4 <_free_r>
+    25d0:	80000c15 	stw	zero,48(r16)
+    25d4:	0005883a 	mov	r2,zero
+    25d8:	dfc00417 	ldw	ra,16(sp)
+    25dc:	dcc00317 	ldw	r19,12(sp)
+    25e0:	dc800217 	ldw	r18,8(sp)
+    25e4:	dc400117 	ldw	r17,4(sp)
+    25e8:	dc000017 	ldw	r16,0(sp)
+    25ec:	dec00504 	addi	sp,sp,20
+    25f0:	f800283a 	ret
+    25f4:	2c800417 	ldw	r18,16(r5)
+    25f8:	903ff626 	beq	r18,zero,25d4 <__sflush_r+0x108>
+    25fc:	2c400017 	ldw	r17,0(r5)
+    2600:	108000cc 	andi	r2,r2,3
+    2604:	2c800015 	stw	r18,0(r5)
+    2608:	8ca3c83a 	sub	r17,r17,r18
+    260c:	1000161e 	bne	r2,zero,2668 <__sflush_r+0x19c>
+    2610:	28800517 	ldw	r2,20(r5)
+    2614:	80800215 	stw	r2,8(r16)
+    2618:	04400316 	blt	zero,r17,2628 <__sflush_r+0x15c>
+    261c:	003fed06 	br	25d4 <__sflush_r+0x108>
+    2620:	90a5883a 	add	r18,r18,r2
+    2624:	047feb0e 	bge	zero,r17,25d4 <__sflush_r+0x108>
+    2628:	80800917 	ldw	r2,36(r16)
+    262c:	81400717 	ldw	r5,28(r16)
+    2630:	880f883a 	mov	r7,r17
+    2634:	900d883a 	mov	r6,r18
+    2638:	9809883a 	mov	r4,r19
+    263c:	103ee83a 	callr	r2
+    2640:	88a3c83a 	sub	r17,r17,r2
+    2644:	00bff616 	blt	zero,r2,2620 <__sflush_r+0x154>
+    2648:	80c0030b 	ldhu	r3,12(r16)
+    264c:	00bfffc4 	movi	r2,-1
+    2650:	18c01014 	ori	r3,r3,64
+    2654:	80c0030d 	sth	r3,12(r16)
+    2658:	003fdf06 	br	25d8 <__sflush_r+0x10c>
+    265c:	28c00f17 	ldw	r3,60(r5)
+    2660:	00ffa916 	blt	zero,r3,2508 <__sflush_r+0x3c>
+    2664:	003fdb06 	br	25d4 <__sflush_r+0x108>
+    2668:	0005883a 	mov	r2,zero
+    266c:	003fe906 	br	2614 <__sflush_r+0x148>
+    2670:	80801417 	ldw	r2,80(r16)
+    2674:	003fb506 	br	254c <__sflush_r+0x80>
+    2678:	80c0030b 	ldhu	r3,12(r16)
+    267c:	81000417 	ldw	r4,16(r16)
+    2680:	80000115 	stw	zero,4(r16)
+    2684:	197dffcc 	andi	r5,r3,63487
+    2688:	8140030d 	sth	r5,12(r16)
+    268c:	81000015 	stw	r4,0(r16)
+    2690:	18c4000c 	andi	r3,r3,4096
+    2694:	183fc726 	beq	r3,zero,25b4 <__sflush_r+0xe8>
+    2698:	80801415 	stw	r2,80(r16)
+    269c:	003fc506 	br	25b4 <__sflush_r+0xe8>
+    26a0:	98c00017 	ldw	r3,0(r19)
+    26a4:	183fa626 	beq	r3,zero,2540 <__sflush_r+0x74>
+    26a8:	19000760 	cmpeqi	r4,r3,29
+    26ac:	20000e1e 	bne	r4,zero,26e8 <__sflush_r+0x21c>
+    26b0:	18c00598 	cmpnei	r3,r3,22
+    26b4:	18000c26 	beq	r3,zero,26e8 <__sflush_r+0x21c>
+    26b8:	80c0030b 	ldhu	r3,12(r16)
+    26bc:	18c01014 	ori	r3,r3,64
+    26c0:	80c0030d 	sth	r3,12(r16)
+    26c4:	003fc406 	br	25d8 <__sflush_r+0x10c>
+    26c8:	81000417 	ldw	r4,16(r16)
+    26cc:	197dffcc 	andi	r5,r3,63487
+    26d0:	8140030d 	sth	r5,12(r16)
+    26d4:	80000115 	stw	zero,4(r16)
+    26d8:	81000015 	stw	r4,0(r16)
+    26dc:	18c4000c 	andi	r3,r3,4096
+    26e0:	183fb426 	beq	r3,zero,25b4 <__sflush_r+0xe8>
+    26e4:	003fec06 	br	2698 <__sflush_r+0x1cc>
+    26e8:	9c400015 	stw	r17,0(r19)
+    26ec:	0005883a 	mov	r2,zero
+    26f0:	003fb906 	br	25d8 <__sflush_r+0x10c>
+
+000026f4 <_fflush_r>:
+    26f4:	defffd04 	addi	sp,sp,-12
+    26f8:	dc000115 	stw	r16,4(sp)
+    26fc:	dfc00215 	stw	ra,8(sp)
+    2700:	2021883a 	mov	r16,r4
+    2704:	20000226 	beq	r4,zero,2710 <_fflush_r+0x1c>
+    2708:	20800e17 	ldw	r2,56(r4)
+    270c:	10000726 	beq	r2,zero,272c <_fflush_r+0x38>
+    2710:	2880030f 	ldh	r2,12(r5)
+    2714:	10000a1e 	bne	r2,zero,2740 <_fflush_r+0x4c>
+    2718:	0005883a 	mov	r2,zero
+    271c:	dfc00217 	ldw	ra,8(sp)
+    2720:	dc000117 	ldw	r16,4(sp)
+    2724:	dec00304 	addi	sp,sp,12
+    2728:	f800283a 	ret
+    272c:	d9400015 	stw	r5,0(sp)
+    2730:	00007f40 	call	7f4 <__sinit>
+    2734:	d9400017 	ldw	r5,0(sp)
+    2738:	2880030f 	ldh	r2,12(r5)
+    273c:	103ff626 	beq	r2,zero,2718 <_fflush_r+0x24>
+    2740:	8009883a 	mov	r4,r16
+    2744:	dfc00217 	ldw	ra,8(sp)
+    2748:	dc000117 	ldw	r16,4(sp)
+    274c:	dec00304 	addi	sp,sp,12
+    2750:	00024cc1 	jmpi	24cc <__sflush_r>
+
+00002754 <fflush>:
+    2754:	20001726 	beq	r4,zero,27b4 <fflush+0x60>
+    2758:	00800034 	movhi	r2,0
+    275c:	200b883a 	mov	r5,r4
+    2760:	111c8117 	ldw	r4,29188(r2)
+    2764:	20000226 	beq	r4,zero,2770 <fflush+0x1c>
+    2768:	20800e17 	ldw	r2,56(r4)
+    276c:	10000526 	beq	r2,zero,2784 <fflush+0x30>
+    2770:	2880030f 	ldh	r2,12(r5)
+    2774:	1000021e 	bne	r2,zero,2780 <fflush+0x2c>
+    2778:	0005883a 	mov	r2,zero
+    277c:	f800283a 	ret
+    2780:	00024cc1 	jmpi	24cc <__sflush_r>
+    2784:	defffd04 	addi	sp,sp,-12
+    2788:	d9400115 	stw	r5,4(sp)
+    278c:	d9000015 	stw	r4,0(sp)
+    2790:	dfc00215 	stw	ra,8(sp)
+    2794:	00007f40 	call	7f4 <__sinit>
+    2798:	d9400117 	ldw	r5,4(sp)
+    279c:	d9000017 	ldw	r4,0(sp)
+    27a0:	2880030f 	ldh	r2,12(r5)
+    27a4:	10000826 	beq	r2,zero,27c8 <fflush+0x74>
+    27a8:	dfc00217 	ldw	ra,8(sp)
+    27ac:	dec00304 	addi	sp,sp,12
+    27b0:	00024cc1 	jmpi	24cc <__sflush_r>
+    27b4:	00800034 	movhi	r2,0
+    27b8:	111c8017 	ldw	r4,29184(r2)
+    27bc:	01400034 	movhi	r5,0
+    27c0:	2949bd04 	addi	r5,r5,9972
+    27c4:	0000d9c1 	jmpi	d9c <_fwalk_reent>
+    27c8:	0005883a 	mov	r2,zero
+    27cc:	dfc00217 	ldw	ra,8(sp)
+    27d0:	dec00304 	addi	sp,sp,12
+    27d4:	f800283a 	ret
+
+000027d8 <_malloc_trim_r>:
+    27d8:	defffb04 	addi	sp,sp,-20
+    27dc:	dcc00315 	stw	r19,12(sp)
+    27e0:	04c00034 	movhi	r19,0
+    27e4:	dc800215 	stw	r18,8(sp)
+    27e8:	dc400115 	stw	r17,4(sp)
+    27ec:	dc000015 	stw	r16,0(sp)
+    27f0:	dfc00415 	stw	ra,16(sp)
+    27f4:	2821883a 	mov	r16,r5
+    27f8:	9cd6fc04 	addi	r19,r19,23536
+    27fc:	2025883a 	mov	r18,r4
+    2800:	000367c0 	call	367c <__malloc_lock>
+    2804:	98800217 	ldw	r2,8(r19)
+    2808:	14400117 	ldw	r17,4(r2)
+    280c:	00bfff04 	movi	r2,-4
+    2810:	88a2703a 	and	r17,r17,r2
+    2814:	8c21c83a 	sub	r16,r17,r16
+    2818:	8403fbc4 	addi	r16,r16,4079
+    281c:	8020d33a 	srli	r16,r16,12
+    2820:	843fffc4 	addi	r16,r16,-1
+    2824:	8020933a 	slli	r16,r16,12
+    2828:	80840008 	cmpgei	r2,r16,4096
+    282c:	10000626 	beq	r2,zero,2848 <_malloc_trim_r+0x70>
+    2830:	000b883a 	mov	r5,zero
+    2834:	9009883a 	mov	r4,r18
+    2838:	0001f740 	call	1f74 <_sbrk_r>
+    283c:	98c00217 	ldw	r3,8(r19)
+    2840:	1c47883a 	add	r3,r3,r17
+    2844:	10c00a26 	beq	r2,r3,2870 <_malloc_trim_r+0x98>
+    2848:	9009883a 	mov	r4,r18
+    284c:	00036a00 	call	36a0 <__malloc_unlock>
+    2850:	0005883a 	mov	r2,zero
+    2854:	dfc00417 	ldw	ra,16(sp)
+    2858:	dcc00317 	ldw	r19,12(sp)
+    285c:	dc800217 	ldw	r18,8(sp)
+    2860:	dc400117 	ldw	r17,4(sp)
+    2864:	dc000017 	ldw	r16,0(sp)
+    2868:	dec00504 	addi	sp,sp,20
+    286c:	f800283a 	ret
+    2870:	040bc83a 	sub	r5,zero,r16
+    2874:	9009883a 	mov	r4,r18
+    2878:	0001f740 	call	1f74 <_sbrk_r>
+    287c:	10bfffd8 	cmpnei	r2,r2,-1
+    2880:	10000d26 	beq	r2,zero,28b8 <_malloc_trim_r+0xe0>
+    2884:	00800034 	movhi	r2,0
+    2888:	109c9917 	ldw	r2,29284(r2)
+    288c:	98c00217 	ldw	r3,8(r19)
+    2890:	8c23c83a 	sub	r17,r17,r16
+    2894:	8c400054 	ori	r17,r17,1
+    2898:	1421c83a 	sub	r16,r2,r16
+    289c:	1c400115 	stw	r17,4(r3)
+    28a0:	00800034 	movhi	r2,0
+    28a4:	9009883a 	mov	r4,r18
+    28a8:	141c9915 	stw	r16,29284(r2)
+    28ac:	00036a00 	call	36a0 <__malloc_unlock>
+    28b0:	00800044 	movi	r2,1
+    28b4:	003fe706 	br	2854 <_malloc_trim_r+0x7c>
+    28b8:	000b883a 	mov	r5,zero
+    28bc:	9009883a 	mov	r4,r18
+    28c0:	0001f740 	call	1f74 <_sbrk_r>
+    28c4:	99000217 	ldw	r4,8(r19)
+    28c8:	1107c83a 	sub	r3,r2,r4
+    28cc:	19400410 	cmplti	r5,r3,16
+    28d0:	283fdd1e 	bne	r5,zero,2848 <_malloc_trim_r+0x70>
+    28d4:	01400034 	movhi	r5,0
+    28d8:	295c8217 	ldw	r5,29192(r5)
+    28dc:	18c00054 	ori	r3,r3,1
+    28e0:	20c00115 	stw	r3,4(r4)
+    28e4:	1145c83a 	sub	r2,r2,r5
+    28e8:	01400034 	movhi	r5,0
+    28ec:	289c9915 	stw	r2,29284(r5)
+    28f0:	003fd506 	br	2848 <_malloc_trim_r+0x70>
+
+000028f4 <_free_r>:
+    28f4:	28004f26 	beq	r5,zero,2a34 <_free_r+0x140>
+    28f8:	defffd04 	addi	sp,sp,-12
+    28fc:	dc400115 	stw	r17,4(sp)
+    2900:	dc000015 	stw	r16,0(sp)
+    2904:	2023883a 	mov	r17,r4
+    2908:	2821883a 	mov	r16,r5
+    290c:	dfc00215 	stw	ra,8(sp)
+    2910:	000367c0 	call	367c <__malloc_lock>
+    2914:	81ffff17 	ldw	r7,-4(r16)
+    2918:	00bfff84 	movi	r2,-2
+    291c:	80fffe04 	addi	r3,r16,-8
+    2920:	3884703a 	and	r2,r7,r2
+    2924:	01000034 	movhi	r4,0
+    2928:	188d883a 	add	r6,r3,r2
+    292c:	2116fc04 	addi	r4,r4,23536
+    2930:	31400117 	ldw	r5,4(r6)
+    2934:	22000217 	ldw	r8,8(r4)
+    2938:	027fff04 	movi	r9,-4
+    293c:	2a4a703a 	and	r5,r5,r9
+    2940:	41806426 	beq	r8,r6,2ad4 <_free_r+0x1e0>
+    2944:	31400115 	stw	r5,4(r6)
+    2948:	39c0004c 	andi	r7,r7,1
+    294c:	3151883a 	add	r8,r6,r5
+    2950:	3800281e 	bne	r7,zero,29f4 <_free_r+0x100>
+    2954:	82bffe17 	ldw	r10,-8(r16)
+    2958:	42000117 	ldw	r8,4(r8)
+    295c:	01c00034 	movhi	r7,0
+    2960:	1a87c83a 	sub	r3,r3,r10
+    2964:	1a400217 	ldw	r9,8(r3)
+    2968:	39d6fe04 	addi	r7,r7,23544
+    296c:	1285883a 	add	r2,r2,r10
+    2970:	4200004c 	andi	r8,r8,1
+    2974:	49c04c26 	beq	r9,r7,2aa8 <_free_r+0x1b4>
+    2978:	1a800317 	ldw	r10,12(r3)
+    297c:	4a800315 	stw	r10,12(r9)
+    2980:	52400215 	stw	r9,8(r10)
+    2984:	40007126 	beq	r8,zero,2b4c <_free_r+0x258>
+    2988:	11400054 	ori	r5,r2,1
+    298c:	19400115 	stw	r5,4(r3)
+    2990:	30800015 	stw	r2,0(r6)
+    2994:	11408028 	cmpgeui	r5,r2,512
+    2998:	28002c1e 	bne	r5,zero,2a4c <_free_r+0x158>
+    299c:	100ad0fa 	srli	r5,r2,3
+    29a0:	100cd17a 	srli	r6,r2,5
+    29a4:	00800044 	movi	r2,1
+    29a8:	29400044 	addi	r5,r5,1
+    29ac:	280a90fa 	slli	r5,r5,3
+    29b0:	21c00117 	ldw	r7,4(r4)
+    29b4:	1184983a 	sll	r2,r2,r6
+    29b8:	214b883a 	add	r5,r4,r5
+    29bc:	29800017 	ldw	r6,0(r5)
+    29c0:	11c4b03a 	or	r2,r2,r7
+    29c4:	29fffe04 	addi	r7,r5,-8
+    29c8:	19c00315 	stw	r7,12(r3)
+    29cc:	19800215 	stw	r6,8(r3)
+    29d0:	20800115 	stw	r2,4(r4)
+    29d4:	28c00015 	stw	r3,0(r5)
+    29d8:	30c00315 	stw	r3,12(r6)
+    29dc:	8809883a 	mov	r4,r17
+    29e0:	dfc00217 	ldw	ra,8(sp)
+    29e4:	dc400117 	ldw	r17,4(sp)
+    29e8:	dc000017 	ldw	r16,0(sp)
+    29ec:	dec00304 	addi	sp,sp,12
+    29f0:	00036a01 	jmpi	36a0 <__malloc_unlock>
+    29f4:	41c00117 	ldw	r7,4(r8)
+    29f8:	39c0004c 	andi	r7,r7,1
+    29fc:	38000e1e 	bne	r7,zero,2a38 <_free_r+0x144>
+    2a00:	01c00034 	movhi	r7,0
+    2a04:	1145883a 	add	r2,r2,r5
+    2a08:	39d6fe04 	addi	r7,r7,23544
+    2a0c:	31400217 	ldw	r5,8(r6)
+    2a10:	12400054 	ori	r9,r2,1
+    2a14:	1891883a 	add	r8,r3,r2
+    2a18:	29c05226 	beq	r5,r7,2b64 <_free_r+0x270>
+    2a1c:	31800317 	ldw	r6,12(r6)
+    2a20:	29800315 	stw	r6,12(r5)
+    2a24:	31400215 	stw	r5,8(r6)
+    2a28:	1a400115 	stw	r9,4(r3)
+    2a2c:	40800015 	stw	r2,0(r8)
+    2a30:	003fd806 	br	2994 <_free_r+0xa0>
+    2a34:	f800283a 	ret
+    2a38:	11400054 	ori	r5,r2,1
+    2a3c:	817fff15 	stw	r5,-4(r16)
+    2a40:	30800015 	stw	r2,0(r6)
+    2a44:	11408028 	cmpgeui	r5,r2,512
+    2a48:	283fd426 	beq	r5,zero,299c <_free_r+0xa8>
+    2a4c:	100ad27a 	srli	r5,r2,9
+    2a50:	29800168 	cmpgeui	r6,r5,5
+    2a54:	3000341e 	bne	r6,zero,2b28 <_free_r+0x234>
+    2a58:	100ad1ba 	srli	r5,r2,6
+    2a5c:	29800e44 	addi	r6,r5,57
+    2a60:	300c90fa 	slli	r6,r6,3
+    2a64:	29c00e04 	addi	r7,r5,56
+    2a68:	218d883a 	add	r6,r4,r6
+    2a6c:	31400017 	ldw	r5,0(r6)
+    2a70:	31bffe04 	addi	r6,r6,-8
+    2a74:	31404226 	beq	r6,r5,2b80 <_free_r+0x28c>
+    2a78:	01ffff04 	movi	r7,-4
+    2a7c:	29000117 	ldw	r4,4(r5)
+    2a80:	21c8703a 	and	r4,r4,r7
+    2a84:	1100022e 	bgeu	r2,r4,2a90 <_free_r+0x19c>
+    2a88:	29400217 	ldw	r5,8(r5)
+    2a8c:	317ffb1e 	bne	r6,r5,2a7c <_free_r+0x188>
+    2a90:	29800317 	ldw	r6,12(r5)
+    2a94:	19800315 	stw	r6,12(r3)
+    2a98:	19400215 	stw	r5,8(r3)
+    2a9c:	30c00215 	stw	r3,8(r6)
+    2aa0:	28c00315 	stw	r3,12(r5)
+    2aa4:	003fcd06 	br	29dc <_free_r+0xe8>
+    2aa8:	40004d1e 	bne	r8,zero,2be0 <_free_r+0x2ec>
+    2aac:	31000317 	ldw	r4,12(r6)
+    2ab0:	31800217 	ldw	r6,8(r6)
+    2ab4:	2885883a 	add	r2,r5,r2
+    2ab8:	11400054 	ori	r5,r2,1
+    2abc:	31000315 	stw	r4,12(r6)
+    2ac0:	21800215 	stw	r6,8(r4)
+    2ac4:	19400115 	stw	r5,4(r3)
+    2ac8:	1887883a 	add	r3,r3,r2
+    2acc:	18800015 	stw	r2,0(r3)
+    2ad0:	003fc206 	br	29dc <_free_r+0xe8>
+    2ad4:	39c0004c 	andi	r7,r7,1
+    2ad8:	1145883a 	add	r2,r2,r5
+    2adc:	3800071e 	bne	r7,zero,2afc <_free_r+0x208>
+    2ae0:	81fffe17 	ldw	r7,-8(r16)
+    2ae4:	19c7c83a 	sub	r3,r3,r7
+    2ae8:	19400317 	ldw	r5,12(r3)
+    2aec:	19800217 	ldw	r6,8(r3)
+    2af0:	11c5883a 	add	r2,r2,r7
+    2af4:	31400315 	stw	r5,12(r6)
+    2af8:	29800215 	stw	r6,8(r5)
+    2afc:	01400034 	movhi	r5,0
+    2b00:	11800054 	ori	r6,r2,1
+    2b04:	295c8317 	ldw	r5,29196(r5)
+    2b08:	19800115 	stw	r6,4(r3)
+    2b0c:	20c00215 	stw	r3,8(r4)
+    2b10:	117fb236 	bltu	r2,r5,29dc <_free_r+0xe8>
+    2b14:	00800034 	movhi	r2,0
+    2b18:	115c9017 	ldw	r5,29248(r2)
+    2b1c:	8809883a 	mov	r4,r17
+    2b20:	00027d80 	call	27d8 <_malloc_trim_r>
+    2b24:	003fad06 	br	29dc <_free_r+0xe8>
+    2b28:	29800568 	cmpgeui	r6,r5,21
+    2b2c:	30000926 	beq	r6,zero,2b54 <_free_r+0x260>
+    2b30:	29801568 	cmpgeui	r6,r5,85
+    2b34:	3000191e 	bne	r6,zero,2b9c <_free_r+0x2a8>
+    2b38:	100ad33a 	srli	r5,r2,12
+    2b3c:	29801bc4 	addi	r6,r5,111
+    2b40:	300c90fa 	slli	r6,r6,3
+    2b44:	29c01b84 	addi	r7,r5,110
+    2b48:	003fc706 	br	2a68 <_free_r+0x174>
+    2b4c:	1145883a 	add	r2,r2,r5
+    2b50:	003fae06 	br	2a0c <_free_r+0x118>
+    2b54:	29801704 	addi	r6,r5,92
+    2b58:	300c90fa 	slli	r6,r6,3
+    2b5c:	29c016c4 	addi	r7,r5,91
+    2b60:	003fc106 	br	2a68 <_free_r+0x174>
+    2b64:	20c00515 	stw	r3,20(r4)
+    2b68:	20c00415 	stw	r3,16(r4)
+    2b6c:	19c00315 	stw	r7,12(r3)
+    2b70:	19c00215 	stw	r7,8(r3)
+    2b74:	1a400115 	stw	r9,4(r3)
+    2b78:	40800015 	stw	r2,0(r8)
+    2b7c:	003f9706 	br	29dc <_free_r+0xe8>
+    2b80:	380fd0ba 	srai	r7,r7,2
+    2b84:	00800044 	movi	r2,1
+    2b88:	22000117 	ldw	r8,4(r4)
+    2b8c:	11ce983a 	sll	r7,r2,r7
+    2b90:	3a0eb03a 	or	r7,r7,r8
+    2b94:	21c00115 	stw	r7,4(r4)
+    2b98:	003fbe06 	br	2a94 <_free_r+0x1a0>
+    2b9c:	29805568 	cmpgeui	r6,r5,341
+    2ba0:	3000051e 	bne	r6,zero,2bb8 <_free_r+0x2c4>
+    2ba4:	100ad3fa 	srli	r5,r2,15
+    2ba8:	29801e04 	addi	r6,r5,120
+    2bac:	300c90fa 	slli	r6,r6,3
+    2bb0:	29c01dc4 	addi	r7,r5,119
+    2bb4:	003fac06 	br	2a68 <_free_r+0x174>
+    2bb8:	29415568 	cmpgeui	r5,r5,1365
+    2bbc:	2800051e 	bne	r5,zero,2bd4 <_free_r+0x2e0>
+    2bc0:	100ad4ba 	srli	r5,r2,18
+    2bc4:	29801f44 	addi	r6,r5,125
+    2bc8:	300c90fa 	slli	r6,r6,3
+    2bcc:	29c01f04 	addi	r7,r5,124
+    2bd0:	003fa506 	br	2a68 <_free_r+0x174>
+    2bd4:	0180fe04 	movi	r6,1016
+    2bd8:	01c01f84 	movi	r7,126
+    2bdc:	003fa206 	br	2a68 <_free_r+0x174>
+    2be0:	11000054 	ori	r4,r2,1
+    2be4:	19000115 	stw	r4,4(r3)
+    2be8:	30800015 	stw	r2,0(r6)
+    2bec:	003f7b06 	br	29dc <_free_r+0xe8>
+
+00002bf0 <_lseek_r>:
+    2bf0:	2807883a 	mov	r3,r5
+    2bf4:	defffe04 	addi	sp,sp,-8
+    2bf8:	dc000015 	stw	r16,0(sp)
+    2bfc:	300b883a 	mov	r5,r6
+    2c00:	00800034 	movhi	r2,0
+    2c04:	380d883a 	mov	r6,r7
+    2c08:	2021883a 	mov	r16,r4
+    2c0c:	1809883a 	mov	r4,r3
+    2c10:	dfc00115 	stw	ra,4(sp)
+    2c14:	101c9115 	stw	zero,29252(r2)
+    2c18:	00035200 	call	3520 <lseek>
+    2c1c:	10ffffd8 	cmpnei	r3,r2,-1
+    2c20:	18000426 	beq	r3,zero,2c34 <_lseek_r+0x44>
+    2c24:	dfc00117 	ldw	ra,4(sp)
+    2c28:	dc000017 	ldw	r16,0(sp)
+    2c2c:	dec00204 	addi	sp,sp,8
+    2c30:	f800283a 	ret
+    2c34:	00c00034 	movhi	r3,0
+    2c38:	18dc9117 	ldw	r3,29252(r3)
+    2c3c:	183ff926 	beq	r3,zero,2c24 <_lseek_r+0x34>
+    2c40:	80c00015 	stw	r3,0(r16)
+    2c44:	dfc00117 	ldw	ra,4(sp)
+    2c48:	dc000017 	ldw	r16,0(sp)
+    2c4c:	dec00204 	addi	sp,sp,8
+    2c50:	f800283a 	ret
+
+00002c54 <__smakebuf_r>:
+    2c54:	2880030b 	ldhu	r2,12(r5)
+    2c58:	deffe804 	addi	sp,sp,-96
+    2c5c:	dc001215 	stw	r16,72(sp)
+    2c60:	dfc01715 	stw	ra,92(sp)
+    2c64:	dd001615 	stw	r20,88(sp)
+    2c68:	dcc01515 	stw	r19,84(sp)
+    2c6c:	dc801415 	stw	r18,80(sp)
+    2c70:	dc401315 	stw	r17,76(sp)
+    2c74:	10c0008c 	andi	r3,r2,2
+    2c78:	2821883a 	mov	r16,r5
+    2c7c:	18000d26 	beq	r3,zero,2cb4 <__smakebuf_r+0x60>
+    2c80:	288010c4 	addi	r2,r5,67
+    2c84:	28800015 	stw	r2,0(r5)
+    2c88:	28800415 	stw	r2,16(r5)
+    2c8c:	00800044 	movi	r2,1
+    2c90:	28800515 	stw	r2,20(r5)
+    2c94:	dfc01717 	ldw	ra,92(sp)
+    2c98:	dd001617 	ldw	r20,88(sp)
+    2c9c:	dcc01517 	ldw	r19,84(sp)
+    2ca0:	dc801417 	ldw	r18,80(sp)
+    2ca4:	dc401317 	ldw	r17,76(sp)
+    2ca8:	dc001217 	ldw	r16,72(sp)
+    2cac:	dec01804 	addi	sp,sp,96
+    2cb0:	f800283a 	ret
+    2cb4:	2940038f 	ldh	r5,14(r5)
+    2cb8:	2023883a 	mov	r17,r4
+    2cbc:	28002816 	blt	r5,zero,2d60 <__smakebuf_r+0x10c>
+    2cc0:	d80d883a 	mov	r6,sp
+    2cc4:	0002f000 	call	2f00 <_fstat_r>
+    2cc8:	10002416 	blt	r2,zero,2d5c <__smakebuf_r+0x108>
+    2ccc:	d8800117 	ldw	r2,4(sp)
+    2cd0:	10bc000c 	andi	r2,r2,61440
+    2cd4:	10880018 	cmpnei	r2,r2,8192
+    2cd8:	1000461e 	bne	r2,zero,2df4 <__smakebuf_r+0x1a0>
+    2cdc:	8140038f 	ldh	r5,14(r16)
+    2ce0:	8809883a 	mov	r4,r17
+    2ce4:	0002f600 	call	2f60 <_isatty_r>
+    2ce8:	10003e26 	beq	r2,zero,2de4 <__smakebuf_r+0x190>
+    2cec:	8080030b 	ldhu	r2,12(r16)
+    2cf0:	80c010c4 	addi	r3,r16,67
+    2cf4:	80c00015 	stw	r3,0(r16)
+    2cf8:	10800054 	ori	r2,r2,1
+    2cfc:	8080030d 	sth	r2,12(r16)
+    2d00:	00800044 	movi	r2,1
+    2d04:	80c00415 	stw	r3,16(r16)
+    2d08:	80800515 	stw	r2,20(r16)
+    2d0c:	04c00044 	movi	r19,1
+    2d10:	05010004 	movi	r20,1024
+    2d14:	04820004 	movi	r18,2048
+    2d18:	a00b883a 	mov	r5,r20
+    2d1c:	8809883a 	mov	r4,r17
+    2d20:	0000e440 	call	e44 <_malloc_r>
+    2d24:	10001726 	beq	r2,zero,2d84 <__smakebuf_r+0x130>
+    2d28:	80c0030b 	ldhu	r3,12(r16)
+    2d2c:	01000034 	movhi	r4,0
+    2d30:	21012604 	addi	r4,r4,1176
+    2d34:	89000f15 	stw	r4,60(r17)
+    2d38:	18c02014 	ori	r3,r3,128
+    2d3c:	80c0030d 	sth	r3,12(r16)
+    2d40:	80800015 	stw	r2,0(r16)
+    2d44:	80800415 	stw	r2,16(r16)
+    2d48:	85000515 	stw	r20,20(r16)
+    2d4c:	98001d1e 	bne	r19,zero,2dc4 <__smakebuf_r+0x170>
+    2d50:	90c6b03a 	or	r3,r18,r3
+    2d54:	80c0030d 	sth	r3,12(r16)
+    2d58:	003fce06 	br	2c94 <__smakebuf_r+0x40>
+    2d5c:	8080030b 	ldhu	r2,12(r16)
+    2d60:	1080200c 	andi	r2,r2,128
+    2d64:	0027883a 	mov	r19,zero
+    2d68:	10001326 	beq	r2,zero,2db8 <__smakebuf_r+0x164>
+    2d6c:	05001004 	movi	r20,64
+    2d70:	a00b883a 	mov	r5,r20
+    2d74:	8809883a 	mov	r4,r17
+    2d78:	0025883a 	mov	r18,zero
+    2d7c:	0000e440 	call	e44 <_malloc_r>
+    2d80:	103fe91e 	bne	r2,zero,2d28 <__smakebuf_r+0xd4>
+    2d84:	8080030b 	ldhu	r2,12(r16)
+    2d88:	10c0800c 	andi	r3,r2,512
+    2d8c:	183fc11e 	bne	r3,zero,2c94 <__smakebuf_r+0x40>
+    2d90:	00ffff04 	movi	r3,-4
+    2d94:	10c4703a 	and	r2,r2,r3
+    2d98:	10800094 	ori	r2,r2,2
+    2d9c:	80c010c4 	addi	r3,r16,67
+    2da0:	8080030d 	sth	r2,12(r16)
+    2da4:	00800044 	movi	r2,1
+    2da8:	80c00015 	stw	r3,0(r16)
+    2dac:	80c00415 	stw	r3,16(r16)
+    2db0:	80800515 	stw	r2,20(r16)
+    2db4:	003fb706 	br	2c94 <__smakebuf_r+0x40>
+    2db8:	05010004 	movi	r20,1024
+    2dbc:	0025883a 	mov	r18,zero
+    2dc0:	003fd506 	br	2d18 <__smakebuf_r+0xc4>
+    2dc4:	8140038f 	ldh	r5,14(r16)
+    2dc8:	8809883a 	mov	r4,r17
+    2dcc:	0002f600 	call	2f60 <_isatty_r>
+    2dd0:	80c0030b 	ldhu	r3,12(r16)
+    2dd4:	103fde26 	beq	r2,zero,2d50 <__smakebuf_r+0xfc>
+    2dd8:	18ffff0c 	andi	r3,r3,65532
+    2ddc:	18c00054 	ori	r3,r3,1
+    2de0:	003fdb06 	br	2d50 <__smakebuf_r+0xfc>
+    2de4:	04c00044 	movi	r19,1
+    2de8:	05010004 	movi	r20,1024
+    2dec:	04820004 	movi	r18,2048
+    2df0:	003fc906 	br	2d18 <__smakebuf_r+0xc4>
+    2df4:	0027883a 	mov	r19,zero
+    2df8:	05010004 	movi	r20,1024
+    2dfc:	04820004 	movi	r18,2048
+    2e00:	003fc506 	br	2d18 <__smakebuf_r+0xc4>
+
+00002e04 <__swhatbuf_r>:
+    2e04:	deffea04 	addi	sp,sp,-88
+    2e08:	dc001215 	stw	r16,72(sp)
+    2e0c:	2821883a 	mov	r16,r5
+    2e10:	2940038f 	ldh	r5,14(r5)
+    2e14:	dc801415 	stw	r18,80(sp)
+    2e18:	dc401315 	stw	r17,76(sp)
+    2e1c:	dfc01515 	stw	ra,84(sp)
+    2e20:	3023883a 	mov	r17,r6
+    2e24:	3825883a 	mov	r18,r7
+    2e28:	28001016 	blt	r5,zero,2e6c <__swhatbuf_r+0x68>
+    2e2c:	d80d883a 	mov	r6,sp
+    2e30:	0002f000 	call	2f00 <_fstat_r>
+    2e34:	10000d16 	blt	r2,zero,2e6c <__swhatbuf_r+0x68>
+    2e38:	d8c00117 	ldw	r3,4(sp)
+    2e3c:	00820004 	movi	r2,2048
+    2e40:	18fc000c 	andi	r3,r3,61440
+    2e44:	18c80020 	cmpeqi	r3,r3,8192
+    2e48:	90c00015 	stw	r3,0(r18)
+    2e4c:	00c10004 	movi	r3,1024
+    2e50:	88c00015 	stw	r3,0(r17)
+    2e54:	dfc01517 	ldw	ra,84(sp)
+    2e58:	dc801417 	ldw	r18,80(sp)
+    2e5c:	dc401317 	ldw	r17,76(sp)
+    2e60:	dc001217 	ldw	r16,72(sp)
+    2e64:	dec01604 	addi	sp,sp,88
+    2e68:	f800283a 	ret
+    2e6c:	8080030b 	ldhu	r2,12(r16)
+    2e70:	90000015 	stw	zero,0(r18)
+    2e74:	1080200c 	andi	r2,r2,128
+    2e78:	10000426 	beq	r2,zero,2e8c <__swhatbuf_r+0x88>
+    2e7c:	00801004 	movi	r2,64
+    2e80:	88800015 	stw	r2,0(r17)
+    2e84:	0005883a 	mov	r2,zero
+    2e88:	003ff206 	br	2e54 <__swhatbuf_r+0x50>
+    2e8c:	00810004 	movi	r2,1024
+    2e90:	88800015 	stw	r2,0(r17)
+    2e94:	0005883a 	mov	r2,zero
+    2e98:	003fee06 	br	2e54 <__swhatbuf_r+0x50>
+
+00002e9c <_read_r>:
+    2e9c:	2807883a 	mov	r3,r5
+    2ea0:	defffe04 	addi	sp,sp,-8
+    2ea4:	dc000015 	stw	r16,0(sp)
+    2ea8:	300b883a 	mov	r5,r6
+    2eac:	00800034 	movhi	r2,0
+    2eb0:	380d883a 	mov	r6,r7
+    2eb4:	2021883a 	mov	r16,r4
+    2eb8:	1809883a 	mov	r4,r3
+    2ebc:	dfc00115 	stw	ra,4(sp)
+    2ec0:	101c9115 	stw	zero,29252(r2)
+    2ec4:	00037000 	call	3700 <read>
+    2ec8:	10ffffd8 	cmpnei	r3,r2,-1
+    2ecc:	18000426 	beq	r3,zero,2ee0 <_read_r+0x44>
+    2ed0:	dfc00117 	ldw	ra,4(sp)
+    2ed4:	dc000017 	ldw	r16,0(sp)
+    2ed8:	dec00204 	addi	sp,sp,8
+    2edc:	f800283a 	ret
+    2ee0:	00c00034 	movhi	r3,0
+    2ee4:	18dc9117 	ldw	r3,29252(r3)
+    2ee8:	183ff926 	beq	r3,zero,2ed0 <_read_r+0x34>
+    2eec:	80c00015 	stw	r3,0(r16)
+    2ef0:	dfc00117 	ldw	ra,4(sp)
+    2ef4:	dc000017 	ldw	r16,0(sp)
+    2ef8:	dec00204 	addi	sp,sp,8
+    2efc:	f800283a 	ret
+
+00002f00 <_fstat_r>:
+    2f00:	2807883a 	mov	r3,r5
+    2f04:	defffe04 	addi	sp,sp,-8
+    2f08:	dc000015 	stw	r16,0(sp)
+    2f0c:	00800034 	movhi	r2,0
+    2f10:	300b883a 	mov	r5,r6
+    2f14:	2021883a 	mov	r16,r4
+    2f18:	1809883a 	mov	r4,r3
+    2f1c:	dfc00115 	stw	ra,4(sp)
+    2f20:	101c9115 	stw	zero,29252(r2)
+    2f24:	000333c0 	call	333c <fstat>
+    2f28:	10ffffd8 	cmpnei	r3,r2,-1
+    2f2c:	18000426 	beq	r3,zero,2f40 <_fstat_r+0x40>
+    2f30:	dfc00117 	ldw	ra,4(sp)
+    2f34:	dc000017 	ldw	r16,0(sp)
+    2f38:	dec00204 	addi	sp,sp,8
+    2f3c:	f800283a 	ret
+    2f40:	00c00034 	movhi	r3,0
+    2f44:	18dc9117 	ldw	r3,29252(r3)
+    2f48:	183ff926 	beq	r3,zero,2f30 <_fstat_r+0x30>
+    2f4c:	80c00015 	stw	r3,0(r16)
+    2f50:	dfc00117 	ldw	ra,4(sp)
+    2f54:	dc000017 	ldw	r16,0(sp)
+    2f58:	dec00204 	addi	sp,sp,8
+    2f5c:	f800283a 	ret
+
+00002f60 <_isatty_r>:
+    2f60:	defffe04 	addi	sp,sp,-8
+    2f64:	dc000015 	stw	r16,0(sp)
+    2f68:	00800034 	movhi	r2,0
+    2f6c:	2021883a 	mov	r16,r4
+    2f70:	2809883a 	mov	r4,r5
+    2f74:	dfc00115 	stw	ra,4(sp)
+    2f78:	101c9115 	stw	zero,29252(r2)
+    2f7c:	00034340 	call	3434 <isatty>
+    2f80:	10ffffd8 	cmpnei	r3,r2,-1
+    2f84:	18000426 	beq	r3,zero,2f98 <_isatty_r+0x38>
+    2f88:	dfc00117 	ldw	ra,4(sp)
+    2f8c:	dc000017 	ldw	r16,0(sp)
+    2f90:	dec00204 	addi	sp,sp,8
+    2f94:	f800283a 	ret
+    2f98:	00c00034 	movhi	r3,0
+    2f9c:	18dc9117 	ldw	r3,29252(r3)
+    2fa0:	183ff926 	beq	r3,zero,2f88 <_isatty_r+0x28>
+    2fa4:	80c00015 	stw	r3,0(r16)
+    2fa8:	dfc00117 	ldw	ra,4(sp)
+    2fac:	dc000017 	ldw	r16,0(sp)
+    2fb0:	dec00204 	addi	sp,sp,8
+    2fb4:	f800283a 	ret
+
+00002fb8 <__divsi3>:
+    2fb8:	20001a16 	blt	r4,zero,3024 <__divsi3+0x6c>
+    2fbc:	000f883a 	mov	r7,zero
+    2fc0:	2800020e 	bge	r5,zero,2fcc <__divsi3+0x14>
+    2fc4:	014bc83a 	sub	r5,zero,r5
+    2fc8:	39c0005c 	xori	r7,r7,1
+    2fcc:	200d883a 	mov	r6,r4
+    2fd0:	00c00044 	movi	r3,1
+    2fd4:	2900092e 	bgeu	r5,r4,2ffc <__divsi3+0x44>
+    2fd8:	00800804 	movi	r2,32
+    2fdc:	00c00044 	movi	r3,1
+    2fe0:	00000106 	br	2fe8 <__divsi3+0x30>
+    2fe4:	10001226 	beq	r2,zero,3030 <__divsi3+0x78>
+    2fe8:	294b883a 	add	r5,r5,r5
+    2fec:	10bfffc4 	addi	r2,r2,-1
+    2ff0:	18c7883a 	add	r3,r3,r3
+    2ff4:	293ffb36 	bltu	r5,r4,2fe4 <__divsi3+0x2c>
+    2ff8:	18000d26 	beq	r3,zero,3030 <__divsi3+0x78>
+    2ffc:	0005883a 	mov	r2,zero
+    3000:	31400236 	bltu	r6,r5,300c <__divsi3+0x54>
+    3004:	314dc83a 	sub	r6,r6,r5
+    3008:	10c4b03a 	or	r2,r2,r3
+    300c:	1806d07a 	srli	r3,r3,1
+    3010:	280ad07a 	srli	r5,r5,1
+    3014:	183ffa1e 	bne	r3,zero,3000 <__divsi3+0x48>
+    3018:	38000126 	beq	r7,zero,3020 <__divsi3+0x68>
+    301c:	0085c83a 	sub	r2,zero,r2
+    3020:	f800283a 	ret
+    3024:	0109c83a 	sub	r4,zero,r4
+    3028:	01c00044 	movi	r7,1
+    302c:	003fe406 	br	2fc0 <__divsi3+0x8>
+    3030:	0005883a 	mov	r2,zero
+    3034:	003ff806 	br	3018 <__divsi3+0x60>
+
+00003038 <__modsi3>:
+    3038:	20001916 	blt	r4,zero,30a0 <__modsi3+0x68>
+    303c:	000f883a 	mov	r7,zero
+    3040:	2005883a 	mov	r2,r4
+    3044:	2800010e 	bge	r5,zero,304c <__modsi3+0x14>
+    3048:	014bc83a 	sub	r5,zero,r5
+    304c:	00c00044 	movi	r3,1
+    3050:	2900092e 	bgeu	r5,r4,3078 <__modsi3+0x40>
+    3054:	01800804 	movi	r6,32
+    3058:	00c00044 	movi	r3,1
+    305c:	00000106 	br	3064 <__modsi3+0x2c>
+    3060:	30000d26 	beq	r6,zero,3098 <__modsi3+0x60>
+    3064:	294b883a 	add	r5,r5,r5
+    3068:	31bfffc4 	addi	r6,r6,-1
+    306c:	18c7883a 	add	r3,r3,r3
+    3070:	293ffb36 	bltu	r5,r4,3060 <__modsi3+0x28>
+    3074:	18000826 	beq	r3,zero,3098 <__modsi3+0x60>
+    3078:	1806d07a 	srli	r3,r3,1
+    307c:	11400136 	bltu	r2,r5,3084 <__modsi3+0x4c>
+    3080:	1145c83a 	sub	r2,r2,r5
+    3084:	280ad07a 	srli	r5,r5,1
+    3088:	183ffb1e 	bne	r3,zero,3078 <__modsi3+0x40>
+    308c:	38000126 	beq	r7,zero,3094 <__modsi3+0x5c>
+    3090:	0085c83a 	sub	r2,zero,r2
+    3094:	f800283a 	ret
+    3098:	2005883a 	mov	r2,r4
+    309c:	003ffb06 	br	308c <__modsi3+0x54>
+    30a0:	0109c83a 	sub	r4,zero,r4
+    30a4:	01c00044 	movi	r7,1
+    30a8:	003fe506 	br	3040 <__modsi3+0x8>
+
+000030ac <__udivsi3>:
+    30ac:	200d883a 	mov	r6,r4
+    30b0:	2900152e 	bgeu	r5,r4,3108 <__udivsi3+0x5c>
+    30b4:	28001416 	blt	r5,zero,3108 <__udivsi3+0x5c>
+    30b8:	00800804 	movi	r2,32
+    30bc:	00c00044 	movi	r3,1
+    30c0:	00000206 	br	30cc <__udivsi3+0x20>
+    30c4:	10000e26 	beq	r2,zero,3100 <__udivsi3+0x54>
+    30c8:	28000516 	blt	r5,zero,30e0 <__udivsi3+0x34>
+    30cc:	294b883a 	add	r5,r5,r5
+    30d0:	10bfffc4 	addi	r2,r2,-1
+    30d4:	18c7883a 	add	r3,r3,r3
+    30d8:	293ffa36 	bltu	r5,r4,30c4 <__udivsi3+0x18>
+    30dc:	18000826 	beq	r3,zero,3100 <__udivsi3+0x54>
+    30e0:	0005883a 	mov	r2,zero
+    30e4:	31400236 	bltu	r6,r5,30f0 <__udivsi3+0x44>
+    30e8:	314dc83a 	sub	r6,r6,r5
+    30ec:	10c4b03a 	or	r2,r2,r3
+    30f0:	1806d07a 	srli	r3,r3,1
+    30f4:	280ad07a 	srli	r5,r5,1
+    30f8:	183ffa1e 	bne	r3,zero,30e4 <__udivsi3+0x38>
+    30fc:	f800283a 	ret
+    3100:	0005883a 	mov	r2,zero
+    3104:	f800283a 	ret
+    3108:	00c00044 	movi	r3,1
+    310c:	003ff406 	br	30e0 <__udivsi3+0x34>
+
+00003110 <__umodsi3>:
+    3110:	2005883a 	mov	r2,r4
+    3114:	2900132e 	bgeu	r5,r4,3164 <__umodsi3+0x54>
+    3118:	28001216 	blt	r5,zero,3164 <__umodsi3+0x54>
+    311c:	01800804 	movi	r6,32
+    3120:	00c00044 	movi	r3,1
+    3124:	00000206 	br	3130 <__umodsi3+0x20>
+    3128:	30000c26 	beq	r6,zero,315c <__umodsi3+0x4c>
+    312c:	28000516 	blt	r5,zero,3144 <__umodsi3+0x34>
+    3130:	294b883a 	add	r5,r5,r5
+    3134:	31bfffc4 	addi	r6,r6,-1
+    3138:	18c7883a 	add	r3,r3,r3
+    313c:	293ffa36 	bltu	r5,r4,3128 <__umodsi3+0x18>
+    3140:	18000626 	beq	r3,zero,315c <__umodsi3+0x4c>
+    3144:	1806d07a 	srli	r3,r3,1
+    3148:	11400136 	bltu	r2,r5,3150 <__umodsi3+0x40>
+    314c:	1145c83a 	sub	r2,r2,r5
+    3150:	280ad07a 	srli	r5,r5,1
+    3154:	183ffb1e 	bne	r3,zero,3144 <__umodsi3+0x34>
+    3158:	f800283a 	ret
+    315c:	2005883a 	mov	r2,r4
+    3160:	f800283a 	ret
+    3164:	00c00044 	movi	r3,1
+    3168:	003ff606 	br	3144 <__umodsi3+0x34>
+
+0000316c <__mulsi3>:
+    316c:	0005883a 	mov	r2,zero
+    3170:	20000726 	beq	r4,zero,3190 <__mulsi3+0x24>
+    3174:	20c0004c 	andi	r3,r4,1
+    3178:	2008d07a 	srli	r4,r4,1
+    317c:	18000126 	beq	r3,zero,3184 <__mulsi3+0x18>
+    3180:	1145883a 	add	r2,r2,r5
+    3184:	294b883a 	add	r5,r5,r5
+    3188:	203ffa1e 	bne	r4,zero,3174 <__mulsi3+0x8>
+    318c:	f800283a 	ret
+    3190:	f800283a 	ret
+
+00003194 <alt_get_errno>:
+#undef errno
+
+extern int errno;
+
+static ALT_INLINE int* alt_get_errno(void)
+{
+    3194:	defffe04 	addi	sp,sp,-8
+    3198:	dfc00115 	stw	ra,4(sp)
+    319c:	df000015 	stw	fp,0(sp)
+    31a0:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    31a4:	d0a00917 	ldw	r2,-32732(gp)
+    31a8:	10000326 	beq	r2,zero,31b8 <alt_get_errno+0x24>
+    31ac:	d0a00917 	ldw	r2,-32732(gp)
+    31b0:	103ee83a 	callr	r2
+    31b4:	00000106 	br	31bc <alt_get_errno+0x28>
+    31b8:	d0a01104 	addi	r2,gp,-32700
+}
+    31bc:	e037883a 	mov	sp,fp
+    31c0:	dfc00117 	ldw	ra,4(sp)
+    31c4:	df000017 	ldw	fp,0(sp)
+    31c8:	dec00204 	addi	sp,sp,8
+    31cc:	f800283a 	ret
+
+000031d0 <close>:
+ *
+ * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h
+ */
+ 
+int ALT_CLOSE (int fildes)
+{
+    31d0:	defffb04 	addi	sp,sp,-20
+    31d4:	dfc00415 	stw	ra,16(sp)
+    31d8:	df000315 	stw	fp,12(sp)
+    31dc:	df000304 	addi	fp,sp,12
+    31e0:	e13ffd15 	stw	r4,-12(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (fildes < 0) ? NULL : &alt_fd_list[fildes];
+    31e4:	e0bffd17 	ldw	r2,-12(fp)
+    31e8:	10000916 	blt	r2,zero,3210 <close+0x40>
+    31ec:	e0fffd17 	ldw	r3,-12(fp)
+    31f0:	1805883a 	mov	r2,r3
+    31f4:	1085883a 	add	r2,r2,r2
+    31f8:	10c5883a 	add	r2,r2,r3
+    31fc:	100490ba 	slli	r2,r2,2
+    3200:	00c00034 	movhi	r3,0
+    3204:	18d80804 	addi	r3,r3,24608
+    3208:	10c5883a 	add	r2,r2,r3
+    320c:	00000106 	br	3214 <close+0x44>
+    3210:	0005883a 	mov	r2,zero
+    3214:	e0bfff15 	stw	r2,-4(fp)
+
+  if (fd)
+    3218:	e0bfff17 	ldw	r2,-4(fp)
+    321c:	10001926 	beq	r2,zero,3284 <close+0xb4>
+    /*
+     * If the associated file system/device has a close function, call it so 
+     * that any necessary cleanup code can run.
+     */
+
+    rval = (fd->dev->close) ? fd->dev->close(fd) : 0;
+    3220:	e0bfff17 	ldw	r2,-4(fp)
+    3224:	10800017 	ldw	r2,0(r2)
+    3228:	10800417 	ldw	r2,16(r2)
+    322c:	10000626 	beq	r2,zero,3248 <close+0x78>
+    3230:	e0bfff17 	ldw	r2,-4(fp)
+    3234:	10800017 	ldw	r2,0(r2)
+    3238:	10800417 	ldw	r2,16(r2)
+    323c:	e13fff17 	ldw	r4,-4(fp)
+    3240:	103ee83a 	callr	r2
+    3244:	00000106 	br	324c <close+0x7c>
+    3248:	0005883a 	mov	r2,zero
+    324c:	e0bffe15 	stw	r2,-8(fp)
+
+    /* Free the file descriptor structure and return. */
+
+    alt_release_fd (fildes);
+    3250:	e13ffd17 	ldw	r4,-12(fp)
+    3254:	00038080 	call	3808 <alt_release_fd>
+    if (rval < 0)
+    3258:	e0bffe17 	ldw	r2,-8(fp)
+    325c:	1000070e 	bge	r2,zero,327c <close+0xac>
+    {
+      ALT_ERRNO = -rval;
+    3260:	00031940 	call	3194 <alt_get_errno>
+    3264:	1007883a 	mov	r3,r2
+    3268:	e0bffe17 	ldw	r2,-8(fp)
+    326c:	0085c83a 	sub	r2,zero,r2
+    3270:	18800015 	stw	r2,0(r3)
+      return -1;
+    3274:	00bfffc4 	movi	r2,-1
+    3278:	00000706 	br	3298 <close+0xc8>
+    }
+    return 0;
+    327c:	0005883a 	mov	r2,zero
+    3280:	00000506 	br	3298 <close+0xc8>
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    3284:	00031940 	call	3194 <alt_get_errno>
+    3288:	1007883a 	mov	r3,r2
+    328c:	00801444 	movi	r2,81
+    3290:	18800015 	stw	r2,0(r3)
+    return -1;
+    3294:	00bfffc4 	movi	r2,-1
+  }
+}
+    3298:	e037883a 	mov	sp,fp
+    329c:	dfc00117 	ldw	ra,4(sp)
+    32a0:	df000017 	ldw	fp,0(sp)
+    32a4:	dec00204 	addi	sp,sp,8
+    32a8:	f800283a 	ret
+
+000032ac <alt_dcache_flush>:
+ *
+ * Any dirty lines in the data cache are written back to memory.
+ */
+
+void alt_dcache_flush (void* start, alt_u32 len)
+{
+    32ac:	defffd04 	addi	sp,sp,-12
+    32b0:	df000215 	stw	fp,8(sp)
+    32b4:	df000204 	addi	fp,sp,8
+    32b8:	e13fff15 	stw	r4,-4(fp)
+    32bc:	e17ffe15 	stw	r5,-8(fp)
+  {
+    ALT_FLUSH_DATA(i);
+  }
+
+#endif /* NIOS2_DCACHE_SIZE > 0 */
+}
+    32c0:	0001883a 	nop
+    32c4:	e037883a 	mov	sp,fp
+    32c8:	df000017 	ldw	fp,0(sp)
+    32cc:	dec00104 	addi	sp,sp,4
+    32d0:	f800283a 	ret
+
+000032d4 <alt_dev_null_write>:
+ * by the alt_dev_null device. It simple discards all data passed to it, and
+ * indicates that the data has been successfully transmitted.
+ */
+
+static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len)
+{
+    32d4:	defffc04 	addi	sp,sp,-16
+    32d8:	df000315 	stw	fp,12(sp)
+    32dc:	df000304 	addi	fp,sp,12
+    32e0:	e13fff15 	stw	r4,-4(fp)
+    32e4:	e17ffe15 	stw	r5,-8(fp)
+    32e8:	e1bffd15 	stw	r6,-12(fp)
+  return len;
+    32ec:	e0bffd17 	ldw	r2,-12(fp)
+}
+    32f0:	e037883a 	mov	sp,fp
+    32f4:	df000017 	ldw	fp,0(sp)
+    32f8:	dec00104 	addi	sp,sp,4
+    32fc:	f800283a 	ret
+
+00003300 <alt_get_errno>:
+{
+    3300:	defffe04 	addi	sp,sp,-8
+    3304:	dfc00115 	stw	ra,4(sp)
+    3308:	df000015 	stw	fp,0(sp)
+    330c:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    3310:	d0a00917 	ldw	r2,-32732(gp)
+    3314:	10000326 	beq	r2,zero,3324 <alt_get_errno+0x24>
+    3318:	d0a00917 	ldw	r2,-32732(gp)
+    331c:	103ee83a 	callr	r2
+    3320:	00000106 	br	3328 <alt_get_errno+0x28>
+    3324:	d0a01104 	addi	r2,gp,-32700
+}
+    3328:	e037883a 	mov	sp,fp
+    332c:	dfc00117 	ldw	ra,4(sp)
+    3330:	df000017 	ldw	fp,0(sp)
+    3334:	dec00204 	addi	sp,sp,8
+    3338:	f800283a 	ret
+
+0000333c <fstat>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_FSTAT (int file, struct stat *st)
+{
+    333c:	defffb04 	addi	sp,sp,-20
+    3340:	dfc00415 	stw	ra,16(sp)
+    3344:	df000315 	stw	fp,12(sp)
+    3348:	df000304 	addi	fp,sp,12
+    334c:	e13ffe15 	stw	r4,-8(fp)
+    3350:	e17ffd15 	stw	r5,-12(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+    3354:	e0bffe17 	ldw	r2,-8(fp)
+    3358:	10000916 	blt	r2,zero,3380 <fstat+0x44>
+    335c:	e0fffe17 	ldw	r3,-8(fp)
+    3360:	1805883a 	mov	r2,r3
+    3364:	1085883a 	add	r2,r2,r2
+    3368:	10c5883a 	add	r2,r2,r3
+    336c:	100490ba 	slli	r2,r2,2
+    3370:	00c00034 	movhi	r3,0
+    3374:	18d80804 	addi	r3,r3,24608
+    3378:	10c5883a 	add	r2,r2,r3
+    337c:	00000106 	br	3384 <fstat+0x48>
+    3380:	0005883a 	mov	r2,zero
+    3384:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+    3388:	e0bfff17 	ldw	r2,-4(fp)
+    338c:	10001026 	beq	r2,zero,33d0 <fstat+0x94>
+  {
+    /* Call the drivers fstat() function to fill out the "st" structure. */
+
+    if (fd->dev->fstat)
+    3390:	e0bfff17 	ldw	r2,-4(fp)
+    3394:	10800017 	ldw	r2,0(r2)
+    3398:	10800817 	ldw	r2,32(r2)
+    339c:	10000726 	beq	r2,zero,33bc <fstat+0x80>
+    {
+      return fd->dev->fstat(fd, st);
+    33a0:	e0bfff17 	ldw	r2,-4(fp)
+    33a4:	10800017 	ldw	r2,0(r2)
+    33a8:	10800817 	ldw	r2,32(r2)
+    33ac:	e17ffd17 	ldw	r5,-12(fp)
+    33b0:	e13fff17 	ldw	r4,-4(fp)
+    33b4:	103ee83a 	callr	r2
+    33b8:	00000a06 	br	33e4 <fstat+0xa8>
+     * device.
+     */
+ 
+    else
+    {
+      st->st_mode = _IFCHR;
+    33bc:	e0bffd17 	ldw	r2,-12(fp)
+    33c0:	00c80004 	movi	r3,8192
+    33c4:	10c00115 	stw	r3,4(r2)
+      return 0;
+    33c8:	0005883a 	mov	r2,zero
+    33cc:	00000506 	br	33e4 <fstat+0xa8>
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    33d0:	00033000 	call	3300 <alt_get_errno>
+    33d4:	1007883a 	mov	r3,r2
+    33d8:	00801444 	movi	r2,81
+    33dc:	18800015 	stw	r2,0(r3)
+    return -1;
+    33e0:	00bfffc4 	movi	r2,-1
+  }
+}
+    33e4:	e037883a 	mov	sp,fp
+    33e8:	dfc00117 	ldw	ra,4(sp)
+    33ec:	df000017 	ldw	fp,0(sp)
+    33f0:	dec00204 	addi	sp,sp,8
+    33f4:	f800283a 	ret
+
+000033f8 <alt_get_errno>:
+{
+    33f8:	defffe04 	addi	sp,sp,-8
+    33fc:	dfc00115 	stw	ra,4(sp)
+    3400:	df000015 	stw	fp,0(sp)
+    3404:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    3408:	d0a00917 	ldw	r2,-32732(gp)
+    340c:	10000326 	beq	r2,zero,341c <alt_get_errno+0x24>
+    3410:	d0a00917 	ldw	r2,-32732(gp)
+    3414:	103ee83a 	callr	r2
+    3418:	00000106 	br	3420 <alt_get_errno+0x28>
+    341c:	d0a01104 	addi	r2,gp,-32700
+}
+    3420:	e037883a 	mov	sp,fp
+    3424:	dfc00117 	ldw	ra,4(sp)
+    3428:	df000017 	ldw	fp,0(sp)
+    342c:	dec00204 	addi	sp,sp,8
+    3430:	f800283a 	ret
+
+00003434 <isatty>:
+ *
+ * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h
+ */
+ 
+int ALT_ISATTY (int file)
+{
+    3434:	deffea04 	addi	sp,sp,-88
+    3438:	dfc01515 	stw	ra,84(sp)
+    343c:	df001415 	stw	fp,80(sp)
+    3440:	df001404 	addi	fp,sp,80
+    3444:	e13fec15 	stw	r4,-80(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+    3448:	e0bfec17 	ldw	r2,-80(fp)
+    344c:	10000916 	blt	r2,zero,3474 <isatty+0x40>
+    3450:	e0ffec17 	ldw	r3,-80(fp)
+    3454:	1805883a 	mov	r2,r3
+    3458:	1085883a 	add	r2,r2,r2
+    345c:	10c5883a 	add	r2,r2,r3
+    3460:	100490ba 	slli	r2,r2,2
+    3464:	00c00034 	movhi	r3,0
+    3468:	18d80804 	addi	r3,r3,24608
+    346c:	10c5883a 	add	r2,r2,r3
+    3470:	00000106 	br	3478 <isatty+0x44>
+    3474:	0005883a 	mov	r2,zero
+    3478:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+    347c:	e0bfff17 	ldw	r2,-4(fp)
+    3480:	10000e26 	beq	r2,zero,34bc <isatty+0x88>
+    /*
+     * If a device driver does not provide an fstat() function, then it is 
+     * treated as a terminal device by default.
+     */
+
+    if (!fd->dev->fstat)
+    3484:	e0bfff17 	ldw	r2,-4(fp)
+    3488:	10800017 	ldw	r2,0(r2)
+    348c:	10800817 	ldw	r2,32(r2)
+    3490:	1000021e 	bne	r2,zero,349c <isatty+0x68>
+    {
+      return 1;
+    3494:	00800044 	movi	r2,1
+    3498:	00000d06 	br	34d0 <isatty+0x9c>
+     * this is called so that the device can identify itself.
+     */ 
+
+    else
+    {
+      fstat (file, &stat);
+    349c:	e0bfed04 	addi	r2,fp,-76
+    34a0:	100b883a 	mov	r5,r2
+    34a4:	e13fec17 	ldw	r4,-80(fp)
+    34a8:	000333c0 	call	333c <fstat>
+      return (stat.st_mode == _IFCHR) ? 1 : 0;
+    34ac:	e0bfee17 	ldw	r2,-72(fp)
+    34b0:	10880020 	cmpeqi	r2,r2,8192
+    34b4:	10803fcc 	andi	r2,r2,255
+    34b8:	00000506 	br	34d0 <isatty+0x9c>
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    34bc:	00033f80 	call	33f8 <alt_get_errno>
+    34c0:	1007883a 	mov	r3,r2
+    34c4:	00801444 	movi	r2,81
+    34c8:	18800015 	stw	r2,0(r3)
+    return 0;
+    34cc:	0005883a 	mov	r2,zero
+  }
+}
+    34d0:	e037883a 	mov	sp,fp
+    34d4:	dfc00117 	ldw	ra,4(sp)
+    34d8:	df000017 	ldw	fp,0(sp)
+    34dc:	dec00204 	addi	sp,sp,8
+    34e0:	f800283a 	ret
+
+000034e4 <alt_get_errno>:
+{
+    34e4:	defffe04 	addi	sp,sp,-8
+    34e8:	dfc00115 	stw	ra,4(sp)
+    34ec:	df000015 	stw	fp,0(sp)
+    34f0:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    34f4:	d0a00917 	ldw	r2,-32732(gp)
+    34f8:	10000326 	beq	r2,zero,3508 <alt_get_errno+0x24>
+    34fc:	d0a00917 	ldw	r2,-32732(gp)
+    3500:	103ee83a 	callr	r2
+    3504:	00000106 	br	350c <alt_get_errno+0x28>
+    3508:	d0a01104 	addi	r2,gp,-32700
+}
+    350c:	e037883a 	mov	sp,fp
+    3510:	dfc00117 	ldw	ra,4(sp)
+    3514:	df000017 	ldw	fp,0(sp)
+    3518:	dec00204 	addi	sp,sp,8
+    351c:	f800283a 	ret
+
+00003520 <lseek>:
+ * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h
+ *
+ */
+
+off_t ALT_LSEEK (int file, off_t ptr, int dir)
+{
+    3520:	defff904 	addi	sp,sp,-28
+    3524:	dfc00615 	stw	ra,24(sp)
+    3528:	df000515 	stw	fp,20(sp)
+    352c:	df000504 	addi	fp,sp,20
+    3530:	e13ffd15 	stw	r4,-12(fp)
+    3534:	e17ffc15 	stw	r5,-16(fp)
+    3538:	e1bffb15 	stw	r6,-20(fp)
+  alt_fd* fd;
+  off_t   rc = 0; 
+    353c:	e03fff15 	stw	zero,-4(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+    3540:	e0bffd17 	ldw	r2,-12(fp)
+    3544:	10000916 	blt	r2,zero,356c <lseek+0x4c>
+    3548:	e0fffd17 	ldw	r3,-12(fp)
+    354c:	1805883a 	mov	r2,r3
+    3550:	1085883a 	add	r2,r2,r2
+    3554:	10c5883a 	add	r2,r2,r3
+    3558:	100490ba 	slli	r2,r2,2
+    355c:	00c00034 	movhi	r3,0
+    3560:	18d80804 	addi	r3,r3,24608
+    3564:	10c5883a 	add	r2,r2,r3
+    3568:	00000106 	br	3570 <lseek+0x50>
+    356c:	0005883a 	mov	r2,zero
+    3570:	e0bffe15 	stw	r2,-8(fp)
+  
+  if (fd) 
+    3574:	e0bffe17 	ldw	r2,-8(fp)
+    3578:	10001026 	beq	r2,zero,35bc <lseek+0x9c>
+    /*
+     * If the device driver provides an implementation of the lseek() function,
+     * then call that to process the request.
+     */
+ 
+    if (fd->dev->lseek)
+    357c:	e0bffe17 	ldw	r2,-8(fp)
+    3580:	10800017 	ldw	r2,0(r2)
+    3584:	10800717 	ldw	r2,28(r2)
+    3588:	10000926 	beq	r2,zero,35b0 <lseek+0x90>
+    {
+      rc = fd->dev->lseek(fd, ptr, dir);
+    358c:	e0bffe17 	ldw	r2,-8(fp)
+    3590:	10800017 	ldw	r2,0(r2)
+    3594:	10800717 	ldw	r2,28(r2)
+    3598:	e1bffb17 	ldw	r6,-20(fp)
+    359c:	e17ffc17 	ldw	r5,-16(fp)
+    35a0:	e13ffe17 	ldw	r4,-8(fp)
+    35a4:	103ee83a 	callr	r2
+    35a8:	e0bfff15 	stw	r2,-4(fp)
+    35ac:	00000506 	br	35c4 <lseek+0xa4>
+     * Otherwise return an error.
+     */
+
+    else
+    {
+      rc = -ENOTSUP;
+    35b0:	00bfde84 	movi	r2,-134
+    35b4:	e0bfff15 	stw	r2,-4(fp)
+    35b8:	00000206 	br	35c4 <lseek+0xa4>
+    }
+  }
+  else  
+  {
+    rc = -EBADFD;
+    35bc:	00bfebc4 	movi	r2,-81
+    35c0:	e0bfff15 	stw	r2,-4(fp)
+  }
+
+  if (rc < 0)
+    35c4:	e0bfff17 	ldw	r2,-4(fp)
+    35c8:	1000070e 	bge	r2,zero,35e8 <lseek+0xc8>
+  {
+    ALT_ERRNO = -rc;
+    35cc:	00034e40 	call	34e4 <alt_get_errno>
+    35d0:	1007883a 	mov	r3,r2
+    35d4:	e0bfff17 	ldw	r2,-4(fp)
+    35d8:	0085c83a 	sub	r2,zero,r2
+    35dc:	18800015 	stw	r2,0(r3)
+    rc = -1;
+    35e0:	00bfffc4 	movi	r2,-1
+    35e4:	e0bfff15 	stw	r2,-4(fp)
+  }
+
+  return rc;
+    35e8:	e0bfff17 	ldw	r2,-4(fp)
+}
+    35ec:	e037883a 	mov	sp,fp
+    35f0:	dfc00117 	ldw	ra,4(sp)
+    35f4:	df000017 	ldw	fp,0(sp)
+    35f8:	dec00204 	addi	sp,sp,8
+    35fc:	f800283a 	ret
+
+00003600 <alt_main>:
+ * devices/filesystems/components in the system; and call the entry point for
+ * the users application, i.e. main().
+ */
+
+void alt_main (void)
+{
+    3600:	defffd04 	addi	sp,sp,-12
+    3604:	dfc00215 	stw	ra,8(sp)
+    3608:	df000115 	stw	fp,4(sp)
+    360c:	df000104 	addi	fp,sp,4
+#endif
+
+  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
+  /* Initialize the interrupt controller. */
+  alt_irq_init (NULL);
+    3610:	0009883a 	mov	r4,zero
+    3614:	0003aa40 	call	3aa4 <alt_irq_init>
+
+  /* Initialize the operating system */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n");
+  ALT_OS_INIT();
+    3618:	0001883a 	nop
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
+  ALT_SEM_CREATE (&alt_fd_list_lock, 1);
+
+  /* Initialize the device drivers/software components. */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
+  alt_sys_init();
+    361c:	0003ae00 	call	3ae0 <alt_sys_init>
+   * devices be present (not equal to /dev/null) and if direct drivers
+   * aren't being used.
+   */
+
+    ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n");
+    alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR);
+    3620:	01800034 	movhi	r6,0
+    3624:	3195eb04 	addi	r6,r6,22444
+    3628:	01400034 	movhi	r5,0
+    362c:	2955eb04 	addi	r5,r5,22444
+    3630:	01000034 	movhi	r4,0
+    3634:	2115eb04 	addi	r4,r4,22444
+    3638:	0004d000 	call	4d00 <alt_io_redirect>
+  /* 
+   * Call the C++ constructors 
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n");
+  _do_ctors ();
+    363c:	00048cc0 	call	48cc <_do_ctors>
+   * redefined as _exit()). This is in the interest of reducing code footprint,
+   * in that the atexit() overhead is removed when it's not needed.
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n");
+  atexit (_do_dtors);
+    3640:	01000034 	movhi	r4,0
+    3644:	21124c04 	addi	r4,r4,18736
+    3648:	00054ac0 	call	54ac <atexit>
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");
+
+#ifdef ALT_NO_EXIT
+  main (alt_argc, alt_argv, alt_envp);
+#else
+  result = main (alt_argc, alt_argv, alt_envp);
+    364c:	d0a01217 	ldw	r2,-32696(gp)
+    3650:	d0e01317 	ldw	r3,-32692(gp)
+    3654:	d1201417 	ldw	r4,-32688(gp)
+    3658:	200d883a 	mov	r6,r4
+    365c:	180b883a 	mov	r5,r3
+    3660:	1009883a 	mov	r4,r2
+    3664:	000025c0 	call	25c <main>
+    3668:	e0bfff15 	stw	r2,-4(fp)
+  close(STDOUT_FILENO);
+    366c:	01000044 	movi	r4,1
+    3670:	00031d00 	call	31d0 <close>
+  exit (result);
+    3674:	e13fff17 	ldw	r4,-4(fp)
+    3678:	00054c00 	call	54c0 <exit>
+
+0000367c <__malloc_lock>:
+ * configuration is single threaded, so there is nothing to do here. Note that 
+ * this requires that malloc is never called by an interrupt service routine.
+ */
+
+void __malloc_lock ( struct _reent *_r )
+{
+    367c:	defffe04 	addi	sp,sp,-8
+    3680:	df000115 	stw	fp,4(sp)
+    3684:	df000104 	addi	fp,sp,4
+    3688:	e13fff15 	stw	r4,-4(fp)
+}
+    368c:	0001883a 	nop
+    3690:	e037883a 	mov	sp,fp
+    3694:	df000017 	ldw	fp,0(sp)
+    3698:	dec00104 	addi	sp,sp,4
+    369c:	f800283a 	ret
+
+000036a0 <__malloc_unlock>:
+/*
+ *
+ */
+
+void __malloc_unlock ( struct _reent *_r )
+{
+    36a0:	defffe04 	addi	sp,sp,-8
+    36a4:	df000115 	stw	fp,4(sp)
+    36a8:	df000104 	addi	fp,sp,4
+    36ac:	e13fff15 	stw	r4,-4(fp)
+}
+    36b0:	0001883a 	nop
+    36b4:	e037883a 	mov	sp,fp
+    36b8:	df000017 	ldw	fp,0(sp)
+    36bc:	dec00104 	addi	sp,sp,4
+    36c0:	f800283a 	ret
+
+000036c4 <alt_get_errno>:
+{
+    36c4:	defffe04 	addi	sp,sp,-8
+    36c8:	dfc00115 	stw	ra,4(sp)
+    36cc:	df000015 	stw	fp,0(sp)
+    36d0:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    36d4:	d0a00917 	ldw	r2,-32732(gp)
+    36d8:	10000326 	beq	r2,zero,36e8 <alt_get_errno+0x24>
+    36dc:	d0a00917 	ldw	r2,-32732(gp)
+    36e0:	103ee83a 	callr	r2
+    36e4:	00000106 	br	36ec <alt_get_errno+0x28>
+    36e8:	d0a01104 	addi	r2,gp,-32700
+}
+    36ec:	e037883a 	mov	sp,fp
+    36f0:	dfc00117 	ldw	ra,4(sp)
+    36f4:	df000017 	ldw	fp,0(sp)
+    36f8:	dec00204 	addi	sp,sp,8
+    36fc:	f800283a 	ret
+
+00003700 <read>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_READ (int file, void *ptr, size_t len)
+{
+    3700:	defff904 	addi	sp,sp,-28
+    3704:	dfc00615 	stw	ra,24(sp)
+    3708:	df000515 	stw	fp,20(sp)
+    370c:	df000504 	addi	fp,sp,20
+    3710:	e13ffd15 	stw	r4,-12(fp)
+    3714:	e17ffc15 	stw	r5,-16(fp)
+    3718:	e1bffb15 	stw	r6,-20(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+    371c:	e0bffd17 	ldw	r2,-12(fp)
+    3720:	10000916 	blt	r2,zero,3748 <read+0x48>
+    3724:	e0fffd17 	ldw	r3,-12(fp)
+    3728:	1805883a 	mov	r2,r3
+    372c:	1085883a 	add	r2,r2,r2
+    3730:	10c5883a 	add	r2,r2,r3
+    3734:	100490ba 	slli	r2,r2,2
+    3738:	00c00034 	movhi	r3,0
+    373c:	18d80804 	addi	r3,r3,24608
+    3740:	10c5883a 	add	r2,r2,r3
+    3744:	00000106 	br	374c <read+0x4c>
+    3748:	0005883a 	mov	r2,zero
+    374c:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+    3750:	e0bfff17 	ldw	r2,-4(fp)
+    3754:	10002226 	beq	r2,zero,37e0 <read+0xe0>
+     * If the file has not been opened with read access, or if the driver does
+     * not provide an implementation of read(), generate an error. Otherwise
+     * call the drivers read() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
+    3758:	e0bfff17 	ldw	r2,-4(fp)
+    375c:	10800217 	ldw	r2,8(r2)
+    3760:	108000cc 	andi	r2,r2,3
+    3764:	10800060 	cmpeqi	r2,r2,1
+    3768:	1000181e 	bne	r2,zero,37cc <read+0xcc>
+        (fd->dev->read))
+    376c:	e0bfff17 	ldw	r2,-4(fp)
+    3770:	10800017 	ldw	r2,0(r2)
+    3774:	10800517 	ldw	r2,20(r2)
+    if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
+    3778:	10001426 	beq	r2,zero,37cc <read+0xcc>
+      {
+        if ((rval = fd->dev->read(fd, ptr, len)) < 0)
+    377c:	e0bfff17 	ldw	r2,-4(fp)
+    3780:	10800017 	ldw	r2,0(r2)
+    3784:	10800517 	ldw	r2,20(r2)
+    3788:	e0fffb17 	ldw	r3,-20(fp)
+    378c:	180d883a 	mov	r6,r3
+    3790:	e17ffc17 	ldw	r5,-16(fp)
+    3794:	e13fff17 	ldw	r4,-4(fp)
+    3798:	103ee83a 	callr	r2
+    379c:	e0bffe15 	stw	r2,-8(fp)
+    37a0:	e0bffe17 	ldw	r2,-8(fp)
+    37a4:	1000070e 	bge	r2,zero,37c4 <read+0xc4>
+        {
+          ALT_ERRNO = -rval;
+    37a8:	00036c40 	call	36c4 <alt_get_errno>
+    37ac:	1007883a 	mov	r3,r2
+    37b0:	e0bffe17 	ldw	r2,-8(fp)
+    37b4:	0085c83a 	sub	r2,zero,r2
+    37b8:	18800015 	stw	r2,0(r3)
+          return -1;
+    37bc:	00bfffc4 	movi	r2,-1
+    37c0:	00000c06 	br	37f4 <read+0xf4>
+        }
+        return rval;
+    37c4:	e0bffe17 	ldw	r2,-8(fp)
+    37c8:	00000a06 	br	37f4 <read+0xf4>
+      }
+      else
+      {
+        ALT_ERRNO = EACCES;
+    37cc:	00036c40 	call	36c4 <alt_get_errno>
+    37d0:	1007883a 	mov	r3,r2
+    37d4:	00800344 	movi	r2,13
+    37d8:	18800015 	stw	r2,0(r3)
+    37dc:	00000406 	br	37f0 <read+0xf0>
+      }
+    }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    37e0:	00036c40 	call	36c4 <alt_get_errno>
+    37e4:	1007883a 	mov	r3,r2
+    37e8:	00801444 	movi	r2,81
+    37ec:	18800015 	stw	r2,0(r3)
+  }
+  return -1;
+    37f0:	00bfffc4 	movi	r2,-1
+}
+    37f4:	e037883a 	mov	sp,fp
+    37f8:	dfc00117 	ldw	ra,4(sp)
+    37fc:	df000017 	ldw	fp,0(sp)
+    3800:	dec00204 	addi	sp,sp,8
+    3804:	f800283a 	ret
+
+00003808 <alt_release_fd>:
+ * File descriptors correcponding to standard in, standard out and standard 
+ * error cannont be released backed to the pool. They are always reserved.
+ */
+
+void alt_release_fd (int fd)
+{
+    3808:	defffe04 	addi	sp,sp,-8
+    380c:	df000115 	stw	fp,4(sp)
+    3810:	df000104 	addi	fp,sp,4
+    3814:	e13fff15 	stw	r4,-4(fp)
+  if (fd > 2)
+    3818:	e0bfff17 	ldw	r2,-4(fp)
+    381c:	108000d0 	cmplti	r2,r2,3
+    3820:	1000101e 	bne	r2,zero,3864 <alt_release_fd+0x5c>
+  {
+    alt_fd_list[fd].fd_flags = 0;
+    3824:	e0ffff17 	ldw	r3,-4(fp)
+    3828:	1805883a 	mov	r2,r3
+    382c:	1085883a 	add	r2,r2,r2
+    3830:	10c5883a 	add	r2,r2,r3
+    3834:	100490ba 	slli	r2,r2,2
+    3838:	00c00034 	movhi	r3,0
+    383c:	10c7883a 	add	r3,r2,r3
+    3840:	18180a15 	stw	zero,24616(r3)
+    alt_fd_list[fd].dev      = 0;
+    3844:	e0ffff17 	ldw	r3,-4(fp)
+    3848:	1805883a 	mov	r2,r3
+    384c:	1085883a 	add	r2,r2,r2
+    3850:	10c5883a 	add	r2,r2,r3
+    3854:	100490ba 	slli	r2,r2,2
+    3858:	00c00034 	movhi	r3,0
+    385c:	10c7883a 	add	r3,r2,r3
+    3860:	18180815 	stw	zero,24608(r3)
+  }
+}
+    3864:	0001883a 	nop
+    3868:	e037883a 	mov	sp,fp
+    386c:	df000017 	ldw	fp,0(sp)
+    3870:	dec00104 	addi	sp,sp,4
+    3874:	f800283a 	ret
+
+00003878 <sbrk>:
+#endif
+ 
+caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function ));
+
+caddr_t ALT_SBRK (int incr)
+{ 
+    3878:	defff904 	addi	sp,sp,-28
+    387c:	df000615 	stw	fp,24(sp)
+    3880:	df000604 	addi	fp,sp,24
+    3884:	e13ffa15 	stw	r4,-24(fp)
+  NIOS2_READ_STATUS (context);
+    3888:	0005303a 	rdctl	r2,status
+    388c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    3890:	e0fffd17 	ldw	r3,-12(fp)
+    3894:	00bfff84 	movi	r2,-2
+    3898:	1884703a 	and	r2,r3,r2
+    389c:	1001703a 	wrctl	status,r2
+  return context;
+    38a0:	e0bffd17 	ldw	r2,-12(fp)
+  alt_irq_context context;
+  char *prev_heap_end; 
+
+  context = alt_irq_disable_all();
+    38a4:	e0bfff15 	stw	r2,-4(fp)
+
+  /* Always return data aligned on a word boundary */
+  heap_end = (char *)(((unsigned int)heap_end + 3) & ~3);
+    38a8:	d0a00a17 	ldw	r2,-32728(gp)
+    38ac:	10c000c4 	addi	r3,r2,3
+    38b0:	00bfff04 	movi	r2,-4
+    38b4:	1884703a 	and	r2,r3,r2
+    38b8:	d0a00a15 	stw	r2,-32728(gp)
+  if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) {
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+  }
+#else
+  if ((heap_end + incr) > __alt_heap_limit) {
+    38bc:	d0e00a17 	ldw	r3,-32728(gp)
+    38c0:	e0bffa17 	ldw	r2,-24(fp)
+    38c4:	1887883a 	add	r3,r3,r2
+    38c8:	008000b4 	movhi	r2,2
+    38cc:	10800004 	addi	r2,r2,0
+    38d0:	10c0072e 	bgeu	r2,r3,38f0 <sbrk+0x78>
+    38d4:	e0bfff17 	ldw	r2,-4(fp)
+    38d8:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+    38dc:	e0bffc17 	ldw	r2,-16(fp)
+    38e0:	1001703a 	wrctl	status,r2
+}
+    38e4:	0001883a 	nop
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+    38e8:	00bfffc4 	movi	r2,-1
+    38ec:	00000c06 	br	3920 <sbrk+0xa8>
+  }
+#endif
+
+  prev_heap_end = heap_end; 
+    38f0:	d0a00a17 	ldw	r2,-32728(gp)
+    38f4:	e0bffe15 	stw	r2,-8(fp)
+  heap_end += incr; 
+    38f8:	d0e00a17 	ldw	r3,-32728(gp)
+    38fc:	e0bffa17 	ldw	r2,-24(fp)
+    3900:	1885883a 	add	r2,r3,r2
+    3904:	d0a00a15 	stw	r2,-32728(gp)
+    3908:	e0bfff17 	ldw	r2,-4(fp)
+    390c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+    3910:	e0bffb17 	ldw	r2,-20(fp)
+    3914:	1001703a 	wrctl	status,r2
+}
+    3918:	0001883a 	nop
+
+#endif
+
+  alt_irq_enable_all(context);
+
+  return (caddr_t) prev_heap_end; 
+    391c:	e0bffe17 	ldw	r2,-8(fp)
+} 
+    3920:	e037883a 	mov	sp,fp
+    3924:	df000017 	ldw	fp,0(sp)
+    3928:	dec00104 	addi	sp,sp,4
+    392c:	f800283a 	ret
+
+00003930 <alt_get_errno>:
+{
+    3930:	defffe04 	addi	sp,sp,-8
+    3934:	dfc00115 	stw	ra,4(sp)
+    3938:	df000015 	stw	fp,0(sp)
+    393c:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    3940:	d0a00917 	ldw	r2,-32732(gp)
+    3944:	10000326 	beq	r2,zero,3954 <alt_get_errno+0x24>
+    3948:	d0a00917 	ldw	r2,-32732(gp)
+    394c:	103ee83a 	callr	r2
+    3950:	00000106 	br	3958 <alt_get_errno+0x28>
+    3954:	d0a01104 	addi	r2,gp,-32700
+}
+    3958:	e037883a 	mov	sp,fp
+    395c:	dfc00117 	ldw	ra,4(sp)
+    3960:	df000017 	ldw	fp,0(sp)
+    3964:	dec00204 	addi	sp,sp,8
+    3968:	f800283a 	ret
+
+0000396c <write>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_WRITE (int file, const void *ptr, size_t len)
+{
+    396c:	defff904 	addi	sp,sp,-28
+    3970:	dfc00615 	stw	ra,24(sp)
+    3974:	df000515 	stw	fp,20(sp)
+    3978:	df000504 	addi	fp,sp,20
+    397c:	e13ffd15 	stw	r4,-12(fp)
+    3980:	e17ffc15 	stw	r5,-16(fp)
+    3984:	e1bffb15 	stw	r6,-20(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+    3988:	e0bffd17 	ldw	r2,-12(fp)
+    398c:	10000916 	blt	r2,zero,39b4 <write+0x48>
+    3990:	e0fffd17 	ldw	r3,-12(fp)
+    3994:	1805883a 	mov	r2,r3
+    3998:	1085883a 	add	r2,r2,r2
+    399c:	10c5883a 	add	r2,r2,r3
+    39a0:	100490ba 	slli	r2,r2,2
+    39a4:	00c00034 	movhi	r3,0
+    39a8:	18d80804 	addi	r3,r3,24608
+    39ac:	10c5883a 	add	r2,r2,r3
+    39b0:	00000106 	br	39b8 <write+0x4c>
+    39b4:	0005883a 	mov	r2,zero
+    39b8:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+    39bc:	e0bfff17 	ldw	r2,-4(fp)
+    39c0:	10002126 	beq	r2,zero,3a48 <write+0xdc>
+     * If the file has not been opened with write access, or if the driver does
+     * not provide an implementation of write(), generate an error. Otherwise
+     * call the drivers write() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write)
+    39c4:	e0bfff17 	ldw	r2,-4(fp)
+    39c8:	10800217 	ldw	r2,8(r2)
+    39cc:	108000cc 	andi	r2,r2,3
+    39d0:	10001826 	beq	r2,zero,3a34 <write+0xc8>
+    39d4:	e0bfff17 	ldw	r2,-4(fp)
+    39d8:	10800017 	ldw	r2,0(r2)
+    39dc:	10800617 	ldw	r2,24(r2)
+    39e0:	10001426 	beq	r2,zero,3a34 <write+0xc8>
+    {
+      
+      /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
+      ALT_LOG_WRITE_FUNCTION(ptr,len);
+
+      if ((rval = fd->dev->write(fd, ptr, len)) < 0)
+    39e4:	e0bfff17 	ldw	r2,-4(fp)
+    39e8:	10800017 	ldw	r2,0(r2)
+    39ec:	10800617 	ldw	r2,24(r2)
+    39f0:	e0fffb17 	ldw	r3,-20(fp)
+    39f4:	180d883a 	mov	r6,r3
+    39f8:	e17ffc17 	ldw	r5,-16(fp)
+    39fc:	e13fff17 	ldw	r4,-4(fp)
+    3a00:	103ee83a 	callr	r2
+    3a04:	e0bffe15 	stw	r2,-8(fp)
+    3a08:	e0bffe17 	ldw	r2,-8(fp)
+    3a0c:	1000070e 	bge	r2,zero,3a2c <write+0xc0>
+      {
+        ALT_ERRNO = -rval;
+    3a10:	00039300 	call	3930 <alt_get_errno>
+    3a14:	1007883a 	mov	r3,r2
+    3a18:	e0bffe17 	ldw	r2,-8(fp)
+    3a1c:	0085c83a 	sub	r2,zero,r2
+    3a20:	18800015 	stw	r2,0(r3)
+        return -1;
+    3a24:	00bfffc4 	movi	r2,-1
+    3a28:	00000c06 	br	3a5c <write+0xf0>
+      }
+      return rval;
+    3a2c:	e0bffe17 	ldw	r2,-8(fp)
+    3a30:	00000a06 	br	3a5c <write+0xf0>
+    }
+    else
+    {
+      ALT_ERRNO = EACCES;
+    3a34:	00039300 	call	3930 <alt_get_errno>
+    3a38:	1007883a 	mov	r3,r2
+    3a3c:	00800344 	movi	r2,13
+    3a40:	18800015 	stw	r2,0(r3)
+    3a44:	00000406 	br	3a58 <write+0xec>
+    }
+  }
+  else  
+  {
+    ALT_ERRNO = EBADFD;
+    3a48:	00039300 	call	3930 <alt_get_errno>
+    3a4c:	1007883a 	mov	r3,r2
+    3a50:	00801444 	movi	r2,81
+    3a54:	18800015 	stw	r2,0(r3)
+  }
+  return -1;
+    3a58:	00bfffc4 	movi	r2,-1
+}
+    3a5c:	e037883a 	mov	sp,fp
+    3a60:	dfc00117 	ldw	ra,4(sp)
+    3a64:	df000017 	ldw	fp,0(sp)
+    3a68:	dec00204 	addi	sp,sp,8
+    3a6c:	f800283a 	ret
+
+00003a70 <alt_dev_reg>:
+ */
+
+extern int alt_fs_reg  (alt_dev* dev); 
+
+static ALT_INLINE int alt_dev_reg (alt_dev* dev)
+{
+    3a70:	defffd04 	addi	sp,sp,-12
+    3a74:	dfc00215 	stw	ra,8(sp)
+    3a78:	df000115 	stw	fp,4(sp)
+    3a7c:	df000104 	addi	fp,sp,4
+    3a80:	e13fff15 	stw	r4,-4(fp)
+  extern alt_llist alt_dev_list;
+
+  return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list);
+    3a84:	d1600604 	addi	r5,gp,-32744
+    3a88:	e13fff17 	ldw	r4,-4(fp)
+    3a8c:	00048240 	call	4824 <alt_dev_llist_insert>
+}
+    3a90:	e037883a 	mov	sp,fp
+    3a94:	dfc00117 	ldw	ra,4(sp)
+    3a98:	df000017 	ldw	fp,0(sp)
+    3a9c:	dec00204 	addi	sp,sp,8
+    3aa0:	f800283a 	ret
+
+00003aa4 <alt_irq_init>:
+ * The "base" parameter is ignored and only
+ * present for backwards-compatibility.
+ */
+
+void alt_irq_init ( const void* base )
+{
+    3aa4:	defffd04 	addi	sp,sp,-12
+    3aa8:	dfc00215 	stw	ra,8(sp)
+    3aac:	df000115 	stw	fp,4(sp)
+    3ab0:	df000104 	addi	fp,sp,4
+    3ab4:	e13fff15 	stw	r4,-4(fp)
+    ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu);
+    3ab8:	00051a00 	call	51a0 <altera_nios2_gen2_irq_init>
+    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
+    3abc:	00800044 	movi	r2,1
+    3ac0:	1001703a 	wrctl	status,r2
+}
+    3ac4:	0001883a 	nop
+    alt_irq_cpu_enable_interrupts();
+}
+    3ac8:	0001883a 	nop
+    3acc:	e037883a 	mov	sp,fp
+    3ad0:	dfc00117 	ldw	ra,4(sp)
+    3ad4:	df000017 	ldw	fp,0(sp)
+    3ad8:	dec00204 	addi	sp,sp,8
+    3adc:	f800283a 	ret
+
+00003ae0 <alt_sys_init>:
+ * Initialize the non-interrupt controller devices.
+ * Called after alt_irq_init().
+ */
+
+void alt_sys_init( void )
+{
+    3ae0:	defffe04 	addi	sp,sp,-8
+    3ae4:	dfc00115 	stw	ra,4(sp)
+    3ae8:	df000015 	stw	fp,0(sp)
+    3aec:	d839883a 	mov	fp,sp
+    ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
+    3af0:	01c0fa04 	movi	r7,1000
+    3af4:	000d883a 	mov	r6,zero
+    3af8:	000b883a 	mov	r5,zero
+    3afc:	010000b4 	movhi	r4,2
+    3b00:	21041004 	addi	r4,r4,4160
+    3b04:	00046300 	call	4630 <alt_avalon_timer_sc_init>
+    ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
+    3b08:	01800044 	movi	r6,1
+    3b0c:	000b883a 	mov	r5,zero
+    3b10:	01000034 	movhi	r4,0
+    3b14:	21187204 	addi	r4,r4,25032
+    3b18:	0003ca40 	call	3ca4 <altera_avalon_jtag_uart_init>
+    3b1c:	01000034 	movhi	r4,0
+    3b20:	21186804 	addi	r4,r4,24992
+    3b24:	0003a700 	call	3a70 <alt_dev_reg>
+}
+    3b28:	0001883a 	nop
+    3b2c:	e037883a 	mov	sp,fp
+    3b30:	dfc00117 	ldw	ra,4(sp)
+    3b34:	df000017 	ldw	fp,0(sp)
+    3b38:	dec00204 	addi	sp,sp,8
+    3b3c:	f800283a 	ret
+
+00003b40 <altera_avalon_jtag_uart_read_fd>:
+ *
+ */
+
+int 
+altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space)
+{
+    3b40:	defffa04 	addi	sp,sp,-24
+    3b44:	dfc00515 	stw	ra,20(sp)
+    3b48:	df000415 	stw	fp,16(sp)
+    3b4c:	df000404 	addi	fp,sp,16
+    3b50:	e13ffe15 	stw	r4,-8(fp)
+    3b54:	e17ffd15 	stw	r5,-12(fp)
+    3b58:	e1bffc15 	stw	r6,-16(fp)
+    altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
+    3b5c:	e0bffe17 	ldw	r2,-8(fp)
+    3b60:	10800017 	ldw	r2,0(r2)
+    3b64:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_jtag_uart_read(&dev->state, buffer, space,
+    3b68:	e0bfff17 	ldw	r2,-4(fp)
+    3b6c:	10c00a04 	addi	r3,r2,40
+    3b70:	e0bffe17 	ldw	r2,-8(fp)
+    3b74:	10800217 	ldw	r2,8(r2)
+    3b78:	100f883a 	mov	r7,r2
+    3b7c:	e1bffc17 	ldw	r6,-16(fp)
+    3b80:	e17ffd17 	ldw	r5,-12(fp)
+    3b84:	1809883a 	mov	r4,r3
+    3b88:	000416c0 	call	416c <altera_avalon_jtag_uart_read>
+      fd->fd_flags);
+}
+    3b8c:	e037883a 	mov	sp,fp
+    3b90:	dfc00117 	ldw	ra,4(sp)
+    3b94:	df000017 	ldw	fp,0(sp)
+    3b98:	dec00204 	addi	sp,sp,8
+    3b9c:	f800283a 	ret
+
+00003ba0 <altera_avalon_jtag_uart_write_fd>:
+
+int 
+altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space)
+{
+    3ba0:	defffa04 	addi	sp,sp,-24
+    3ba4:	dfc00515 	stw	ra,20(sp)
+    3ba8:	df000415 	stw	fp,16(sp)
+    3bac:	df000404 	addi	fp,sp,16
+    3bb0:	e13ffe15 	stw	r4,-8(fp)
+    3bb4:	e17ffd15 	stw	r5,-12(fp)
+    3bb8:	e1bffc15 	stw	r6,-16(fp)
+    altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
+    3bbc:	e0bffe17 	ldw	r2,-8(fp)
+    3bc0:	10800017 	ldw	r2,0(r2)
+    3bc4:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_jtag_uart_write(&dev->state, buffer, space,
+    3bc8:	e0bfff17 	ldw	r2,-4(fp)
+    3bcc:	10c00a04 	addi	r3,r2,40
+    3bd0:	e0bffe17 	ldw	r2,-8(fp)
+    3bd4:	10800217 	ldw	r2,8(r2)
+    3bd8:	100f883a 	mov	r7,r2
+    3bdc:	e1bffc17 	ldw	r6,-16(fp)
+    3be0:	e17ffd17 	ldw	r5,-12(fp)
+    3be4:	1809883a 	mov	r4,r3
+    3be8:	000438c0 	call	438c <altera_avalon_jtag_uart_write>
+      fd->fd_flags);
+}
+    3bec:	e037883a 	mov	sp,fp
+    3bf0:	dfc00117 	ldw	ra,4(sp)
+    3bf4:	df000017 	ldw	fp,0(sp)
+    3bf8:	dec00204 	addi	sp,sp,8
+    3bfc:	f800283a 	ret
+
+00003c00 <altera_avalon_jtag_uart_close_fd>:
+
+#ifndef ALTERA_AVALON_JTAG_UART_SMALL
+
+int 
+altera_avalon_jtag_uart_close_fd(alt_fd* fd)
+{
+    3c00:	defffc04 	addi	sp,sp,-16
+    3c04:	dfc00315 	stw	ra,12(sp)
+    3c08:	df000215 	stw	fp,8(sp)
+    3c0c:	df000204 	addi	fp,sp,8
+    3c10:	e13ffe15 	stw	r4,-8(fp)
+    altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; 
+    3c14:	e0bffe17 	ldw	r2,-8(fp)
+    3c18:	10800017 	ldw	r2,0(r2)
+    3c1c:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags);
+    3c20:	e0bfff17 	ldw	r2,-4(fp)
+    3c24:	10c00a04 	addi	r3,r2,40
+    3c28:	e0bffe17 	ldw	r2,-8(fp)
+    3c2c:	10800217 	ldw	r2,8(r2)
+    3c30:	100b883a 	mov	r5,r2
+    3c34:	1809883a 	mov	r4,r3
+    3c38:	00040100 	call	4010 <altera_avalon_jtag_uart_close>
+}
+    3c3c:	e037883a 	mov	sp,fp
+    3c40:	dfc00117 	ldw	ra,4(sp)
+    3c44:	df000017 	ldw	fp,0(sp)
+    3c48:	dec00204 	addi	sp,sp,8
+    3c4c:	f800283a 	ret
+
+00003c50 <altera_avalon_jtag_uart_ioctl_fd>:
+
+int 
+altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg)
+{
+    3c50:	defffa04 	addi	sp,sp,-24
+    3c54:	dfc00515 	stw	ra,20(sp)
+    3c58:	df000415 	stw	fp,16(sp)
+    3c5c:	df000404 	addi	fp,sp,16
+    3c60:	e13ffe15 	stw	r4,-8(fp)
+    3c64:	e17ffd15 	stw	r5,-12(fp)
+    3c68:	e1bffc15 	stw	r6,-16(fp)
+    altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev;
+    3c6c:	e0bffe17 	ldw	r2,-8(fp)
+    3c70:	10800017 	ldw	r2,0(r2)
+    3c74:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg);
+    3c78:	e0bfff17 	ldw	r2,-4(fp)
+    3c7c:	10800a04 	addi	r2,r2,40
+    3c80:	e1bffc17 	ldw	r6,-16(fp)
+    3c84:	e17ffd17 	ldw	r5,-12(fp)
+    3c88:	1009883a 	mov	r4,r2
+    3c8c:	00040780 	call	4078 <altera_avalon_jtag_uart_ioctl>
+}
+    3c90:	e037883a 	mov	sp,fp
+    3c94:	dfc00117 	ldw	ra,4(sp)
+    3c98:	df000017 	ldw	fp,0(sp)
+    3c9c:	dec00204 	addi	sp,sp,8
+    3ca0:	f800283a 	ret
+
+00003ca4 <altera_avalon_jtag_uart_init>:
+ * Return 1 on sucessful IRQ register and 0 on failure.
+ */
+
+void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, 
+                                  int irq_controller_id, int irq)
+{
+    3ca4:	defffa04 	addi	sp,sp,-24
+    3ca8:	dfc00515 	stw	ra,20(sp)
+    3cac:	df000415 	stw	fp,16(sp)
+    3cb0:	df000404 	addi	fp,sp,16
+    3cb4:	e13fff15 	stw	r4,-4(fp)
+    3cb8:	e17ffe15 	stw	r5,-8(fp)
+    3cbc:	e1bffd15 	stw	r6,-12(fp)
+  ALT_FLAG_CREATE(&sp->events, 0);
+  ALT_SEM_CREATE(&sp->read_lock, 1);
+  ALT_SEM_CREATE(&sp->write_lock, 1);
+
+  /* enable read interrupts at the device */
+  sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
+    3cc0:	e0bfff17 	ldw	r2,-4(fp)
+    3cc4:	00c00044 	movi	r3,1
+    3cc8:	10c00815 	stw	r3,32(r2)
+
+  IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); 
+    3ccc:	e0bfff17 	ldw	r2,-4(fp)
+    3cd0:	10800017 	ldw	r2,0(r2)
+    3cd4:	10800104 	addi	r2,r2,4
+    3cd8:	1007883a 	mov	r3,r2
+    3cdc:	e0bfff17 	ldw	r2,-4(fp)
+    3ce0:	10800817 	ldw	r2,32(r2)
+    3ce4:	18800035 	stwio	r2,0(r3)
+  
+  /* register the interrupt handler */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, 
+    3ce8:	e0bffe17 	ldw	r2,-8(fp)
+    3cec:	e0fffd17 	ldw	r3,-12(fp)
+    3cf0:	d8000015 	stw	zero,0(sp)
+    3cf4:	e1ffff17 	ldw	r7,-4(fp)
+    3cf8:	01800034 	movhi	r6,0
+    3cfc:	318f5904 	addi	r6,r6,15716
+    3d00:	180b883a 	mov	r5,r3
+    3d04:	1009883a 	mov	r4,r2
+    3d08:	00049940 	call	4994 <alt_ic_isr_register>
+#else
+  alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq);
+#endif  
+
+  /* Register an alarm to go off every second to check for presence of host */
+  sp->host_inactive = 0;
+    3d0c:	e0bfff17 	ldw	r2,-4(fp)
+    3d10:	10000915 	stw	zero,36(r2)
+
+  if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), 
+    3d14:	e0bfff17 	ldw	r2,-4(fp)
+    3d18:	10800204 	addi	r2,r2,8
+ * Obtain the system clock rate in ticks/s. 
+ */
+
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void)
+{
+  return _alt_tick_rate;
+    3d1c:	d0e01617 	ldw	r3,-32680(gp)
+    3d20:	e1ffff17 	ldw	r7,-4(fp)
+    3d24:	01800034 	movhi	r6,0
+    3d28:	318fdc04 	addi	r6,r6,16240
+    3d2c:	180b883a 	mov	r5,r3
+    3d30:	1009883a 	mov	r4,r2
+    3d34:	00046b40 	call	46b4 <alt_alarm_start>
+    3d38:	1000040e 	bge	r2,zero,3d4c <altera_avalon_jtag_uart_init+0xa8>
+    &altera_avalon_jtag_uart_timeout, sp) < 0)
+  {
+    /* If we can't set the alarm then record "don't know if host present" 
+     * and behave as though the host is present.
+     */
+    sp->timeout = INT_MAX;
+    3d3c:	e0ffff17 	ldw	r3,-4(fp)
+    3d40:	00a00034 	movhi	r2,32768
+    3d44:	10bfffc4 	addi	r2,r2,-1
+    3d48:	18800115 	stw	r2,4(r3)
+  }
+
+  /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ 
+  ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base);
+}
+    3d4c:	0001883a 	nop
+    3d50:	e037883a 	mov	sp,fp
+    3d54:	dfc00117 	ldw	ra,4(sp)
+    3d58:	df000017 	ldw	fp,0(sp)
+    3d5c:	dec00204 	addi	sp,sp,8
+    3d60:	f800283a 	ret
+
+00003d64 <altera_avalon_jtag_uart_irq>:
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void altera_avalon_jtag_uart_irq(void* context)
+#else
+static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id)
+#endif
+{
+    3d64:	defff804 	addi	sp,sp,-32
+    3d68:	df000715 	stw	fp,28(sp)
+    3d6c:	df000704 	addi	fp,sp,28
+    3d70:	e13ff915 	stw	r4,-28(fp)
+  altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context;
+    3d74:	e0bff917 	ldw	r2,-28(fp)
+    3d78:	e0bffd15 	stw	r2,-12(fp)
+  unsigned int base = sp->base;
+    3d7c:	e0bffd17 	ldw	r2,-12(fp)
+    3d80:	10800017 	ldw	r2,0(r2)
+    3d84:	e0bffc15 	stw	r2,-16(fp)
+  /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ 
+  ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp);
+
+  for ( ; ; )
+  {
+    unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
+    3d88:	e0bffc17 	ldw	r2,-16(fp)
+    3d8c:	10800104 	addi	r2,r2,4
+    3d90:	10800037 	ldwio	r2,0(r2)
+    3d94:	e0bffb15 	stw	r2,-20(fp)
+
+    /* Return once nothing more to do */
+    if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0)
+    3d98:	e0bffb17 	ldw	r2,-20(fp)
+    3d9c:	1080c00c 	andi	r2,r2,768
+    3da0:	10006d26 	beq	r2,zero,3f58 <altera_avalon_jtag_uart_irq+0x1f4>
+      break;
+
+    if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK)
+    3da4:	e0bffb17 	ldw	r2,-20(fp)
+    3da8:	1080400c 	andi	r2,r2,256
+    3dac:	10003526 	beq	r2,zero,3e84 <altera_avalon_jtag_uart_irq+0x120>
+    {
+      /* process a read irq.  Start by assuming that there is data in the
+       * receive FIFO (otherwise why would we have been interrupted?)
+       */
+      unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST;
+    3db0:	00800074 	movhi	r2,1
+    3db4:	e0bfff15 	stw	r2,-4(fp)
+      for ( ; ; )
+      {
+        /* Check whether there is space in the buffer.  If not then we must not
+         * read any characters from the buffer as they will be lost.
+         */
+        unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
+    3db8:	e0bffd17 	ldw	r2,-12(fp)
+    3dbc:	10800a17 	ldw	r2,40(r2)
+    3dc0:	10800044 	addi	r2,r2,1
+    3dc4:	1081ffcc 	andi	r2,r2,2047
+    3dc8:	e0bffa15 	stw	r2,-24(fp)
+        if (next == sp->rx_out)
+    3dcc:	e0bffd17 	ldw	r2,-12(fp)
+    3dd0:	10800b17 	ldw	r2,44(r2)
+    3dd4:	e0fffa17 	ldw	r3,-24(fp)
+    3dd8:	18801526 	beq	r3,r2,3e30 <altera_avalon_jtag_uart_irq+0xcc>
+          break;
+
+        /* Try to remove a character from the FIFO and find out whether there
+         * are any more characters remaining.
+         */
+        data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base);
+    3ddc:	e0bffc17 	ldw	r2,-16(fp)
+    3de0:	10800037 	ldwio	r2,0(r2)
+    3de4:	e0bfff15 	stw	r2,-4(fp)
+        
+        if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0)
+    3de8:	e0bfff17 	ldw	r2,-4(fp)
+    3dec:	10a0000c 	andi	r2,r2,32768
+    3df0:	10001126 	beq	r2,zero,3e38 <altera_avalon_jtag_uart_irq+0xd4>
+          break;
+
+        sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST;
+    3df4:	e0bffd17 	ldw	r2,-12(fp)
+    3df8:	10800a17 	ldw	r2,40(r2)
+    3dfc:	e0ffff17 	ldw	r3,-4(fp)
+    3e00:	1809883a 	mov	r4,r3
+    3e04:	e0fffd17 	ldw	r3,-12(fp)
+    3e08:	1885883a 	add	r2,r3,r2
+    3e0c:	11000e05 	stb	r4,56(r2)
+        sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
+    3e10:	e0bffd17 	ldw	r2,-12(fp)
+    3e14:	10800a17 	ldw	r2,40(r2)
+    3e18:	10800044 	addi	r2,r2,1
+    3e1c:	10c1ffcc 	andi	r3,r2,2047
+    3e20:	e0bffd17 	ldw	r2,-12(fp)
+    3e24:	10c00a15 	stw	r3,40(r2)
+ * HAL.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void)
+{
+  return 0;
+    3e28:	0001883a 	nop
+      {
+    3e2c:	003fe206 	br	3db8 <altera_avalon_jtag_uart_irq+0x54>
+          break;
+    3e30:	0001883a 	nop
+    3e34:	00000106 	br	3e3c <altera_avalon_jtag_uart_irq+0xd8>
+          break;
+    3e38:	0001883a 	nop
+
+        /* Post an event to notify jtag_uart_read that a character has been read */
+        ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET);
+      }
+
+      if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK)
+    3e3c:	e0bfff17 	ldw	r2,-4(fp)
+    3e40:	10bfffec 	andhi	r2,r2,65535
+    3e44:	10000f26 	beq	r2,zero,3e84 <altera_avalon_jtag_uart_irq+0x120>
+      {
+        /* If there is still data available here then the buffer is full 
+         * so turn off receive interrupts until some space becomes available.
+         */
+        sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
+    3e48:	e0bffd17 	ldw	r2,-12(fp)
+    3e4c:	10c00817 	ldw	r3,32(r2)
+    3e50:	00bfff84 	movi	r2,-2
+    3e54:	1886703a 	and	r3,r3,r2
+    3e58:	e0bffd17 	ldw	r2,-12(fp)
+    3e5c:	10c00815 	stw	r3,32(r2)
+        IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable);
+    3e60:	e0bffc17 	ldw	r2,-16(fp)
+    3e64:	10800104 	addi	r2,r2,4
+    3e68:	1007883a 	mov	r3,r2
+    3e6c:	e0bffd17 	ldw	r2,-12(fp)
+    3e70:	10800817 	ldw	r2,32(r2)
+    3e74:	18800035 	stwio	r2,0(r3)
+        
+        /* Dummy read to ensure IRQ is cleared prior to ISR completion */
+        IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
+    3e78:	e0bffc17 	ldw	r2,-16(fp)
+    3e7c:	10800104 	addi	r2,r2,4
+    3e80:	10800037 	ldwio	r2,0(r2)
+      }
+    }
+
+    if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)
+    3e84:	e0bffb17 	ldw	r2,-20(fp)
+    3e88:	1080800c 	andi	r2,r2,512
+    3e8c:	103fbe26 	beq	r2,zero,3d88 <altera_avalon_jtag_uart_irq+0x24>
+    {
+      /* process a write irq */
+      unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST;
+    3e90:	e0bffb17 	ldw	r2,-20(fp)
+    3e94:	1004d43a 	srli	r2,r2,16
+    3e98:	e0bffe15 	stw	r2,-8(fp)
+
+      while (space > 0 && sp->tx_out != sp->tx_in)
+    3e9c:	00001406 	br	3ef0 <altera_avalon_jtag_uart_irq+0x18c>
+      {
+        IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]);
+    3ea0:	e0bffc17 	ldw	r2,-16(fp)
+    3ea4:	e0fffd17 	ldw	r3,-12(fp)
+    3ea8:	18c00d17 	ldw	r3,52(r3)
+    3eac:	e13ffd17 	ldw	r4,-12(fp)
+    3eb0:	20c7883a 	add	r3,r4,r3
+    3eb4:	18c20e03 	ldbu	r3,2104(r3)
+    3eb8:	18c03fcc 	andi	r3,r3,255
+    3ebc:	18c0201c 	xori	r3,r3,128
+    3ec0:	18ffe004 	addi	r3,r3,-128
+    3ec4:	10c00035 	stwio	r3,0(r2)
+
+        sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
+    3ec8:	e0bffd17 	ldw	r2,-12(fp)
+    3ecc:	10800d17 	ldw	r2,52(r2)
+    3ed0:	10800044 	addi	r2,r2,1
+    3ed4:	10c1ffcc 	andi	r3,r2,2047
+    3ed8:	e0bffd17 	ldw	r2,-12(fp)
+    3edc:	10c00d15 	stw	r3,52(r2)
+    3ee0:	0001883a 	nop
+
+        /* Post an event to notify jtag_uart_write that a character has been written */
+        ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET);
+
+        space--;
+    3ee4:	e0bffe17 	ldw	r2,-8(fp)
+    3ee8:	10bfffc4 	addi	r2,r2,-1
+    3eec:	e0bffe15 	stw	r2,-8(fp)
+      while (space > 0 && sp->tx_out != sp->tx_in)
+    3ef0:	e0bffe17 	ldw	r2,-8(fp)
+    3ef4:	10000526 	beq	r2,zero,3f0c <altera_avalon_jtag_uart_irq+0x1a8>
+    3ef8:	e0bffd17 	ldw	r2,-12(fp)
+    3efc:	10c00d17 	ldw	r3,52(r2)
+    3f00:	e0bffd17 	ldw	r2,-12(fp)
+    3f04:	10800c17 	ldw	r2,48(r2)
+    3f08:	18bfe51e 	bne	r3,r2,3ea0 <altera_avalon_jtag_uart_irq+0x13c>
+      }
+
+      if (space > 0)
+    3f0c:	e0bffe17 	ldw	r2,-8(fp)
+    3f10:	103f9d26 	beq	r2,zero,3d88 <altera_avalon_jtag_uart_irq+0x24>
+      {
+        /* If we don't have any more data available then turn off the TX interrupt */
+        sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK;
+    3f14:	e0bffd17 	ldw	r2,-12(fp)
+    3f18:	10c00817 	ldw	r3,32(r2)
+    3f1c:	00bfff44 	movi	r2,-3
+    3f20:	1886703a 	and	r3,r3,r2
+    3f24:	e0bffd17 	ldw	r2,-12(fp)
+    3f28:	10c00815 	stw	r3,32(r2)
+        IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
+    3f2c:	e0bffd17 	ldw	r2,-12(fp)
+    3f30:	10800017 	ldw	r2,0(r2)
+    3f34:	10800104 	addi	r2,r2,4
+    3f38:	1007883a 	mov	r3,r2
+    3f3c:	e0bffd17 	ldw	r2,-12(fp)
+    3f40:	10800817 	ldw	r2,32(r2)
+    3f44:	18800035 	stwio	r2,0(r3)
+        
+        /* Dummy read to ensure IRQ is cleared prior to ISR completion */
+        IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
+    3f48:	e0bffc17 	ldw	r2,-16(fp)
+    3f4c:	10800104 	addi	r2,r2,4
+    3f50:	10800037 	ldwio	r2,0(r2)
+  {
+    3f54:	003f8c06 	br	3d88 <altera_avalon_jtag_uart_irq+0x24>
+      break;
+    3f58:	0001883a 	nop
+      }
+    }
+  }
+}
+    3f5c:	0001883a 	nop
+    3f60:	e037883a 	mov	sp,fp
+    3f64:	df000017 	ldw	fp,0(sp)
+    3f68:	dec00104 	addi	sp,sp,4
+    3f6c:	f800283a 	ret
+
+00003f70 <altera_avalon_jtag_uart_timeout>:
+ * Timeout routine is called every second
+ */
+
+static alt_u32 
+altera_avalon_jtag_uart_timeout(void* context) 
+{
+    3f70:	defffc04 	addi	sp,sp,-16
+    3f74:	df000315 	stw	fp,12(sp)
+    3f78:	df000304 	addi	fp,sp,12
+    3f7c:	e13ffd15 	stw	r4,-12(fp)
+  altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context;
+    3f80:	e0bffd17 	ldw	r2,-12(fp)
+    3f84:	e0bfff15 	stw	r2,-4(fp)
+
+  unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base);
+    3f88:	e0bfff17 	ldw	r2,-4(fp)
+    3f8c:	10800017 	ldw	r2,0(r2)
+    3f90:	10800104 	addi	r2,r2,4
+    3f94:	10800037 	ldwio	r2,0(r2)
+    3f98:	e0bffe15 	stw	r2,-8(fp)
+
+  if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK)
+    3f9c:	e0bffe17 	ldw	r2,-8(fp)
+    3fa0:	1081000c 	andi	r2,r2,1024
+    3fa4:	10000b26 	beq	r2,zero,3fd4 <altera_avalon_jtag_uart_timeout+0x64>
+  {
+    IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK);
+    3fa8:	e0bfff17 	ldw	r2,-4(fp)
+    3fac:	10800017 	ldw	r2,0(r2)
+    3fb0:	10800104 	addi	r2,r2,4
+    3fb4:	1007883a 	mov	r3,r2
+    3fb8:	e0bfff17 	ldw	r2,-4(fp)
+    3fbc:	10800817 	ldw	r2,32(r2)
+    3fc0:	10810014 	ori	r2,r2,1024
+    3fc4:	18800035 	stwio	r2,0(r3)
+    sp->host_inactive = 0;
+    3fc8:	e0bfff17 	ldw	r2,-4(fp)
+    3fcc:	10000915 	stw	zero,36(r2)
+    3fd0:	00000a06 	br	3ffc <altera_avalon_jtag_uart_timeout+0x8c>
+  }
+  else if (sp->host_inactive < INT_MAX - 2) {
+    3fd4:	e0bfff17 	ldw	r2,-4(fp)
+    3fd8:	10c00917 	ldw	r3,36(r2)
+    3fdc:	00a00034 	movhi	r2,32768
+    3fe0:	10bfff04 	addi	r2,r2,-4
+    3fe4:	10c00536 	bltu	r2,r3,3ffc <altera_avalon_jtag_uart_timeout+0x8c>
+    sp->host_inactive++;
+    3fe8:	e0bfff17 	ldw	r2,-4(fp)
+    3fec:	10800917 	ldw	r2,36(r2)
+    3ff0:	10c00044 	addi	r3,r2,1
+    3ff4:	e0bfff17 	ldw	r2,-4(fp)
+    3ff8:	10c00915 	stw	r3,36(r2)
+    3ffc:	d0a01617 	ldw	r2,-32680(gp)
+      ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET);
+    }
+  }
+
+  return alt_ticks_per_second();
+}
+    4000:	e037883a 	mov	sp,fp
+    4004:	df000017 	ldw	fp,0(sp)
+    4008:	dec00104 	addi	sp,sp,4
+    400c:	f800283a 	ret
+
+00004010 <altera_avalon_jtag_uart_close>:
+ * The close routine is not implemented for the small driver; instead it will
+ * map to null. This is because the small driver simply waits while characters
+ * are transmitted; there is no interrupt-serviced buffer to empty 
+ */
+int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags)
+{
+    4010:	defffd04 	addi	sp,sp,-12
+    4014:	df000215 	stw	fp,8(sp)
+    4018:	df000204 	addi	fp,sp,8
+    401c:	e13fff15 	stw	r4,-4(fp)
+    4020:	e17ffe15 	stw	r5,-8(fp)
+  /* 
+   * Wait for all transmit data to be emptied by the JTAG UART ISR, or
+   * for a host-inactivity timeout, in which case transmit data will be lost
+   */
+  while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) {
+    4024:	00000506 	br	403c <altera_avalon_jtag_uart_close+0x2c>
+    if (flags & O_NONBLOCK) {
+    4028:	e0bffe17 	ldw	r2,-8(fp)
+    402c:	1090000c 	andi	r2,r2,16384
+    4030:	10000226 	beq	r2,zero,403c <altera_avalon_jtag_uart_close+0x2c>
+      return -EWOULDBLOCK; 
+    4034:	00bffd44 	movi	r2,-11
+    4038:	00000b06 	br	4068 <altera_avalon_jtag_uart_close+0x58>
+  while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) {
+    403c:	e0bfff17 	ldw	r2,-4(fp)
+    4040:	10c00d17 	ldw	r3,52(r2)
+    4044:	e0bfff17 	ldw	r2,-4(fp)
+    4048:	10800c17 	ldw	r2,48(r2)
+    404c:	18800526 	beq	r3,r2,4064 <altera_avalon_jtag_uart_close+0x54>
+    4050:	e0bfff17 	ldw	r2,-4(fp)
+    4054:	10c00917 	ldw	r3,36(r2)
+    4058:	e0bfff17 	ldw	r2,-4(fp)
+    405c:	10800117 	ldw	r2,4(r2)
+    4060:	18bff136 	bltu	r3,r2,4028 <altera_avalon_jtag_uart_close+0x18>
+    }
+  }
+
+  return 0;
+    4064:	0005883a 	mov	r2,zero
+}
+    4068:	e037883a 	mov	sp,fp
+    406c:	df000017 	ldw	fp,0(sp)
+    4070:	dec00104 	addi	sp,sp,4
+    4074:	f800283a 	ret
+
+00004078 <altera_avalon_jtag_uart_ioctl>:
+/* ----------------------------------------------------------- */
+
+int 
+altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req,
+  void* arg)
+{
+    4078:	defffa04 	addi	sp,sp,-24
+    407c:	df000515 	stw	fp,20(sp)
+    4080:	df000504 	addi	fp,sp,20
+    4084:	e13ffd15 	stw	r4,-12(fp)
+    4088:	e17ffc15 	stw	r5,-16(fp)
+    408c:	e1bffb15 	stw	r6,-20(fp)
+  int rc = -ENOTTY;
+    4090:	00bff9c4 	movi	r2,-25
+    4094:	e0bfff15 	stw	r2,-4(fp)
+
+  switch (req)
+    4098:	e0bffc17 	ldw	r2,-16(fp)
+    409c:	109a8060 	cmpeqi	r2,r2,27137
+    40a0:	1000041e 	bne	r2,zero,40b4 <altera_avalon_jtag_uart_ioctl+0x3c>
+    40a4:	e0bffc17 	ldw	r2,-16(fp)
+    40a8:	109a80a0 	cmpeqi	r2,r2,27138
+    40ac:	1000181e 	bne	r2,zero,4110 <altera_avalon_jtag_uart_ioctl+0x98>
+      rc = 0;
+    }
+    break;
+
+  default:
+    break;
+    40b0:	00002906 	br	4158 <altera_avalon_jtag_uart_ioctl+0xe0>
+    if (sp->timeout != INT_MAX)
+    40b4:	e0bffd17 	ldw	r2,-12(fp)
+    40b8:	10c00117 	ldw	r3,4(r2)
+    40bc:	00a00034 	movhi	r2,32768
+    40c0:	10bfffc4 	addi	r2,r2,-1
+    40c4:	18802126 	beq	r3,r2,414c <altera_avalon_jtag_uart_ioctl+0xd4>
+      int timeout = *((int *)arg);
+    40c8:	e0bffb17 	ldw	r2,-20(fp)
+    40cc:	10800017 	ldw	r2,0(r2)
+    40d0:	e0bffe15 	stw	r2,-8(fp)
+      sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1;
+    40d4:	e0bffe17 	ldw	r2,-8(fp)
+    40d8:	10800090 	cmplti	r2,r2,2
+    40dc:	1000061e 	bne	r2,zero,40f8 <altera_avalon_jtag_uart_ioctl+0x80>
+    40e0:	e0fffe17 	ldw	r3,-8(fp)
+    40e4:	00a00034 	movhi	r2,32768
+    40e8:	10bfffc4 	addi	r2,r2,-1
+    40ec:	18800226 	beq	r3,r2,40f8 <altera_avalon_jtag_uart_ioctl+0x80>
+    40f0:	e0bffe17 	ldw	r2,-8(fp)
+    40f4:	00000206 	br	4100 <altera_avalon_jtag_uart_ioctl+0x88>
+    40f8:	00a00034 	movhi	r2,32768
+    40fc:	10bfff84 	addi	r2,r2,-2
+    4100:	e0fffd17 	ldw	r3,-12(fp)
+    4104:	18800115 	stw	r2,4(r3)
+      rc = 0;
+    4108:	e03fff15 	stw	zero,-4(fp)
+    break;
+    410c:	00000f06 	br	414c <altera_avalon_jtag_uart_ioctl+0xd4>
+    if (sp->timeout != INT_MAX)
+    4110:	e0bffd17 	ldw	r2,-12(fp)
+    4114:	10c00117 	ldw	r3,4(r2)
+    4118:	00a00034 	movhi	r2,32768
+    411c:	10bfffc4 	addi	r2,r2,-1
+    4120:	18800c26 	beq	r3,r2,4154 <altera_avalon_jtag_uart_ioctl+0xdc>
+      *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0;
+    4124:	e0bffd17 	ldw	r2,-12(fp)
+    4128:	10c00917 	ldw	r3,36(r2)
+    412c:	e0bffd17 	ldw	r2,-12(fp)
+    4130:	10800117 	ldw	r2,4(r2)
+    4134:	1885803a 	cmpltu	r2,r3,r2
+    4138:	10c03fcc 	andi	r3,r2,255
+    413c:	e0bffb17 	ldw	r2,-20(fp)
+    4140:	10c00015 	stw	r3,0(r2)
+      rc = 0;
+    4144:	e03fff15 	stw	zero,-4(fp)
+    break;
+    4148:	00000206 	br	4154 <altera_avalon_jtag_uart_ioctl+0xdc>
+    break;
+    414c:	0001883a 	nop
+    4150:	00000106 	br	4158 <altera_avalon_jtag_uart_ioctl+0xe0>
+    break;
+    4154:	0001883a 	nop
+  }
+
+  return rc;
+    4158:	e0bfff17 	ldw	r2,-4(fp)
+}
+    415c:	e037883a 	mov	sp,fp
+    4160:	df000017 	ldw	fp,0(sp)
+    4164:	dec00104 	addi	sp,sp,4
+    4168:	f800283a 	ret
+
+0000416c <altera_avalon_jtag_uart_read>:
+/* ----------------------------------------------------------- */
+
+int 
+altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, 
+  char * buffer, int space, int flags)
+{
+    416c:	defff304 	addi	sp,sp,-52
+    4170:	dfc00c15 	stw	ra,48(sp)
+    4174:	df000b15 	stw	fp,44(sp)
+    4178:	df000b04 	addi	fp,sp,44
+    417c:	e13ff815 	stw	r4,-32(fp)
+    4180:	e17ff715 	stw	r5,-36(fp)
+    4184:	e1bff615 	stw	r6,-40(fp)
+    4188:	e1fff515 	stw	r7,-44(fp)
+  char * ptr = buffer;
+    418c:	e0bff717 	ldw	r2,-36(fp)
+    4190:	e0bfff15 	stw	r2,-4(fp)
+   * When running in a multi threaded environment, obtain the "read_lock"
+   * semaphore. This ensures that reading from the device is thread-safe.
+   */
+  ALT_SEM_PEND (sp->read_lock, 0);
+
+  while (space > 0)
+    4194:	00004706 	br	42b4 <altera_avalon_jtag_uart_read+0x148>
+    unsigned int in, out;
+
+    /* Read as much data as possible */
+    do
+    {
+      in  = sp->rx_in;
+    4198:	e0bff817 	ldw	r2,-32(fp)
+    419c:	10800a17 	ldw	r2,40(r2)
+    41a0:	e0bffd15 	stw	r2,-12(fp)
+      out = sp->rx_out;
+    41a4:	e0bff817 	ldw	r2,-32(fp)
+    41a8:	10800b17 	ldw	r2,44(r2)
+    41ac:	e0bffc15 	stw	r2,-16(fp)
+
+      if (in >= out)
+    41b0:	e0fffd17 	ldw	r3,-12(fp)
+    41b4:	e0bffc17 	ldw	r2,-16(fp)
+    41b8:	18800536 	bltu	r3,r2,41d0 <altera_avalon_jtag_uart_read+0x64>
+        n = in - out;
+    41bc:	e0fffd17 	ldw	r3,-12(fp)
+    41c0:	e0bffc17 	ldw	r2,-16(fp)
+    41c4:	1885c83a 	sub	r2,r3,r2
+    41c8:	e0bffe15 	stw	r2,-8(fp)
+    41cc:	00000406 	br	41e0 <altera_avalon_jtag_uart_read+0x74>
+      else
+        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out;
+    41d0:	00c20004 	movi	r3,2048
+    41d4:	e0bffc17 	ldw	r2,-16(fp)
+    41d8:	1885c83a 	sub	r2,r3,r2
+    41dc:	e0bffe15 	stw	r2,-8(fp)
+
+      if (n == 0)
+    41e0:	e0bffe17 	ldw	r2,-8(fp)
+    41e4:	10001e26 	beq	r2,zero,4260 <altera_avalon_jtag_uart_read+0xf4>
+        break; /* No more data available */
+
+      if (n > space)
+    41e8:	e0fff617 	ldw	r3,-40(fp)
+    41ec:	e0bffe17 	ldw	r2,-8(fp)
+    41f0:	1880022e 	bgeu	r3,r2,41fc <altera_avalon_jtag_uart_read+0x90>
+        n = space;
+    41f4:	e0bff617 	ldw	r2,-40(fp)
+    41f8:	e0bffe15 	stw	r2,-8(fp)
+
+      memcpy(ptr, sp->rx_buf + out, n);
+    41fc:	e0bff817 	ldw	r2,-32(fp)
+    4200:	10c00e04 	addi	r3,r2,56
+    4204:	e0bffc17 	ldw	r2,-16(fp)
+    4208:	1885883a 	add	r2,r3,r2
+    420c:	e1bffe17 	ldw	r6,-8(fp)
+    4210:	100b883a 	mov	r5,r2
+    4214:	e13fff17 	ldw	r4,-4(fp)
+    4218:	00016f40 	call	16f4 <memcpy>
+      ptr   += n;
+    421c:	e0ffff17 	ldw	r3,-4(fp)
+    4220:	e0bffe17 	ldw	r2,-8(fp)
+    4224:	1885883a 	add	r2,r3,r2
+    4228:	e0bfff15 	stw	r2,-4(fp)
+      space -= n;
+    422c:	e0fff617 	ldw	r3,-40(fp)
+    4230:	e0bffe17 	ldw	r2,-8(fp)
+    4234:	1885c83a 	sub	r2,r3,r2
+    4238:	e0bff615 	stw	r2,-40(fp)
+
+      sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
+    423c:	e0fffc17 	ldw	r3,-16(fp)
+    4240:	e0bffe17 	ldw	r2,-8(fp)
+    4244:	1885883a 	add	r2,r3,r2
+    4248:	10c1ffcc 	andi	r3,r2,2047
+    424c:	e0bff817 	ldw	r2,-32(fp)
+    4250:	10c00b15 	stw	r3,44(r2)
+    }
+    while (space > 0);
+    4254:	e0bff617 	ldw	r2,-40(fp)
+    4258:	00bfcf16 	blt	zero,r2,4198 <altera_avalon_jtag_uart_read+0x2c>
+    425c:	00000106 	br	4264 <altera_avalon_jtag_uart_read+0xf8>
+        break; /* No more data available */
+    4260:	0001883a 	nop
+
+    /* If we read any data then return it */
+    if (ptr != buffer)
+    4264:	e0ffff17 	ldw	r3,-4(fp)
+    4268:	e0bff717 	ldw	r2,-36(fp)
+    426c:	1880141e 	bne	r3,r2,42c0 <altera_avalon_jtag_uart_read+0x154>
+      break;
+
+    /* If in non-blocking mode then return error */
+    if (flags & O_NONBLOCK)
+    4270:	e0bff517 	ldw	r2,-44(fp)
+    4274:	1090000c 	andi	r2,r2,16384
+    4278:	1000131e 	bne	r2,zero,42c8 <altera_avalon_jtag_uart_read+0x15c>
+      while (in == sp->rx_in && sp->host_inactive < sp->timeout)
+        ;
+    }
+#else
+    /* No OS: Always spin */
+    while (in == sp->rx_in && sp->host_inactive < sp->timeout)
+    427c:	0001883a 	nop
+    4280:	e0bff817 	ldw	r2,-32(fp)
+    4284:	10800a17 	ldw	r2,40(r2)
+    4288:	e0fffd17 	ldw	r3,-12(fp)
+    428c:	1880051e 	bne	r3,r2,42a4 <altera_avalon_jtag_uart_read+0x138>
+    4290:	e0bff817 	ldw	r2,-32(fp)
+    4294:	10c00917 	ldw	r3,36(r2)
+    4298:	e0bff817 	ldw	r2,-32(fp)
+    429c:	10800117 	ldw	r2,4(r2)
+    42a0:	18bff736 	bltu	r3,r2,4280 <altera_avalon_jtag_uart_read+0x114>
+      ;
+#endif /* __ucosii__ */
+
+    if (in == sp->rx_in)
+    42a4:	e0bff817 	ldw	r2,-32(fp)
+    42a8:	10800a17 	ldw	r2,40(r2)
+    42ac:	e0fffd17 	ldw	r3,-12(fp)
+    42b0:	18800726 	beq	r3,r2,42d0 <altera_avalon_jtag_uart_read+0x164>
+  while (space > 0)
+    42b4:	e0bff617 	ldw	r2,-40(fp)
+    42b8:	00bfb716 	blt	zero,r2,4198 <altera_avalon_jtag_uart_read+0x2c>
+    42bc:	00000506 	br	42d4 <altera_avalon_jtag_uart_read+0x168>
+      break;
+    42c0:	0001883a 	nop
+    42c4:	00000306 	br	42d4 <altera_avalon_jtag_uart_read+0x168>
+      break;
+    42c8:	0001883a 	nop
+    42cc:	00000106 	br	42d4 <altera_avalon_jtag_uart_read+0x168>
+      break;
+    42d0:	0001883a 	nop
+   * semaphore so that other threads can access the buffer.
+   */
+
+  ALT_SEM_POST (sp->read_lock);
+
+  if (ptr != buffer)
+    42d4:	e0ffff17 	ldw	r3,-4(fp)
+    42d8:	e0bff717 	ldw	r2,-36(fp)
+    42dc:	18801926 	beq	r3,r2,4344 <altera_avalon_jtag_uart_read+0x1d8>
+  NIOS2_READ_STATUS (context);
+    42e0:	0005303a 	rdctl	r2,status
+    42e4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    42e8:	e0fff917 	ldw	r3,-28(fp)
+    42ec:	00bfff84 	movi	r2,-2
+    42f0:	1884703a 	and	r2,r3,r2
+    42f4:	1001703a 	wrctl	status,r2
+  return context;
+    42f8:	e0bff917 	ldw	r2,-28(fp)
+  {
+    /* If we read any data then there is space in the buffer so enable interrupts */
+    context = alt_irq_disable_all();
+    42fc:	e0bffb15 	stw	r2,-20(fp)
+    sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK;
+    4300:	e0bff817 	ldw	r2,-32(fp)
+    4304:	10800817 	ldw	r2,32(r2)
+    4308:	10c00054 	ori	r3,r2,1
+    430c:	e0bff817 	ldw	r2,-32(fp)
+    4310:	10c00815 	stw	r3,32(r2)
+    IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
+    4314:	e0bff817 	ldw	r2,-32(fp)
+    4318:	10800017 	ldw	r2,0(r2)
+    431c:	10800104 	addi	r2,r2,4
+    4320:	1007883a 	mov	r3,r2
+    4324:	e0bff817 	ldw	r2,-32(fp)
+    4328:	10800817 	ldw	r2,32(r2)
+    432c:	18800035 	stwio	r2,0(r3)
+    4330:	e0bffb17 	ldw	r2,-20(fp)
+    4334:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+    4338:	e0bffa17 	ldw	r2,-24(fp)
+    433c:	1001703a 	wrctl	status,r2
+}
+    4340:	0001883a 	nop
+    alt_irq_enable_all(context);
+  }
+
+  if (ptr != buffer)
+    4344:	e0ffff17 	ldw	r3,-4(fp)
+    4348:	e0bff717 	ldw	r2,-36(fp)
+    434c:	18800426 	beq	r3,r2,4360 <altera_avalon_jtag_uart_read+0x1f4>
+    return ptr - buffer;
+    4350:	e0ffff17 	ldw	r3,-4(fp)
+    4354:	e0bff717 	ldw	r2,-36(fp)
+    4358:	1885c83a 	sub	r2,r3,r2
+    435c:	00000606 	br	4378 <altera_avalon_jtag_uart_read+0x20c>
+  else if (flags & O_NONBLOCK)
+    4360:	e0bff517 	ldw	r2,-44(fp)
+    4364:	1090000c 	andi	r2,r2,16384
+    4368:	10000226 	beq	r2,zero,4374 <altera_avalon_jtag_uart_read+0x208>
+    return -EWOULDBLOCK;
+    436c:	00bffd44 	movi	r2,-11
+    4370:	00000106 	br	4378 <altera_avalon_jtag_uart_read+0x20c>
+  else
+    return -EIO;
+    4374:	00bffec4 	movi	r2,-5
+}
+    4378:	e037883a 	mov	sp,fp
+    437c:	dfc00117 	ldw	ra,4(sp)
+    4380:	df000017 	ldw	fp,0(sp)
+    4384:	dec00204 	addi	sp,sp,8
+    4388:	f800283a 	ret
+
+0000438c <altera_avalon_jtag_uart_write>:
+/* ----------------------------------------------------------- */
+
+int 
+altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, 
+  const char * ptr, int count, int flags)
+{
+    438c:	defff304 	addi	sp,sp,-52
+    4390:	dfc00c15 	stw	ra,48(sp)
+    4394:	df000b15 	stw	fp,44(sp)
+    4398:	df000b04 	addi	fp,sp,44
+    439c:	e13ff815 	stw	r4,-32(fp)
+    43a0:	e17ff715 	stw	r5,-36(fp)
+    43a4:	e1bff615 	stw	r6,-40(fp)
+    43a8:	e1fff515 	stw	r7,-44(fp)
+  /* Remove warning at optimisation level 03 by seting out to 0 */
+  unsigned int in, out=0;
+    43ac:	e03fff15 	stw	zero,-4(fp)
+  unsigned int n;
+  alt_irq_context context;
+
+  const char * start = ptr;
+    43b0:	e0bff717 	ldw	r2,-36(fp)
+    43b4:	e0bffd15 	stw	r2,-12(fp)
+  ALT_SEM_PEND (sp->write_lock, 0);
+
+  do
+  {
+    /* Copy as much as we can into the transmit buffer */
+    while (count > 0)
+    43b8:	00003706 	br	4498 <altera_avalon_jtag_uart_write+0x10c>
+    {
+      /* We need a stable value of the out pointer to calculate the space available */
+      in  = sp->tx_in;
+    43bc:	e0bff817 	ldw	r2,-32(fp)
+    43c0:	10800c17 	ldw	r2,48(r2)
+    43c4:	e0bffc15 	stw	r2,-16(fp)
+      out = sp->tx_out;
+    43c8:	e0bff817 	ldw	r2,-32(fp)
+    43cc:	10800d17 	ldw	r2,52(r2)
+    43d0:	e0bfff15 	stw	r2,-4(fp)
+
+      if (in < out)
+    43d4:	e0fffc17 	ldw	r3,-16(fp)
+    43d8:	e0bfff17 	ldw	r2,-4(fp)
+    43dc:	1880062e 	bgeu	r3,r2,43f8 <altera_avalon_jtag_uart_write+0x6c>
+        n = out - 1 - in;
+    43e0:	e0ffff17 	ldw	r3,-4(fp)
+    43e4:	e0bffc17 	ldw	r2,-16(fp)
+    43e8:	1885c83a 	sub	r2,r3,r2
+    43ec:	10bfffc4 	addi	r2,r2,-1
+    43f0:	e0bffe15 	stw	r2,-8(fp)
+    43f4:	00000b06 	br	4424 <altera_avalon_jtag_uart_write+0x98>
+      else if (out > 0)
+    43f8:	e0bfff17 	ldw	r2,-4(fp)
+    43fc:	10000526 	beq	r2,zero,4414 <altera_avalon_jtag_uart_write+0x88>
+        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in;
+    4400:	00c20004 	movi	r3,2048
+    4404:	e0bffc17 	ldw	r2,-16(fp)
+    4408:	1885c83a 	sub	r2,r3,r2
+    440c:	e0bffe15 	stw	r2,-8(fp)
+    4410:	00000406 	br	4424 <altera_avalon_jtag_uart_write+0x98>
+      else
+        n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in;
+    4414:	00c1ffc4 	movi	r3,2047
+    4418:	e0bffc17 	ldw	r2,-16(fp)
+    441c:	1885c83a 	sub	r2,r3,r2
+    4420:	e0bffe15 	stw	r2,-8(fp)
+
+      if (n == 0)
+    4424:	e0bffe17 	ldw	r2,-8(fp)
+    4428:	10001e26 	beq	r2,zero,44a4 <altera_avalon_jtag_uart_write+0x118>
+        break;
+
+      if (n > count)
+    442c:	e0fff617 	ldw	r3,-40(fp)
+    4430:	e0bffe17 	ldw	r2,-8(fp)
+    4434:	1880022e 	bgeu	r3,r2,4440 <altera_avalon_jtag_uart_write+0xb4>
+        n = count;
+    4438:	e0bff617 	ldw	r2,-40(fp)
+    443c:	e0bffe15 	stw	r2,-8(fp)
+
+      memcpy(sp->tx_buf + in, ptr, n);
+    4440:	e0bff817 	ldw	r2,-32(fp)
+    4444:	10c20e04 	addi	r3,r2,2104
+    4448:	e0bffc17 	ldw	r2,-16(fp)
+    444c:	1885883a 	add	r2,r3,r2
+    4450:	e1bffe17 	ldw	r6,-8(fp)
+    4454:	e17ff717 	ldw	r5,-36(fp)
+    4458:	1009883a 	mov	r4,r2
+    445c:	00016f40 	call	16f4 <memcpy>
+      ptr   += n;
+    4460:	e0fff717 	ldw	r3,-36(fp)
+    4464:	e0bffe17 	ldw	r2,-8(fp)
+    4468:	1885883a 	add	r2,r3,r2
+    446c:	e0bff715 	stw	r2,-36(fp)
+      count -= n;
+    4470:	e0fff617 	ldw	r3,-40(fp)
+    4474:	e0bffe17 	ldw	r2,-8(fp)
+    4478:	1885c83a 	sub	r2,r3,r2
+    447c:	e0bff615 	stw	r2,-40(fp)
+
+      sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN;
+    4480:	e0fffc17 	ldw	r3,-16(fp)
+    4484:	e0bffe17 	ldw	r2,-8(fp)
+    4488:	1885883a 	add	r2,r3,r2
+    448c:	10c1ffcc 	andi	r3,r2,2047
+    4490:	e0bff817 	ldw	r2,-32(fp)
+    4494:	10c00c15 	stw	r3,48(r2)
+    while (count > 0)
+    4498:	e0bff617 	ldw	r2,-40(fp)
+    449c:	00bfc716 	blt	zero,r2,43bc <altera_avalon_jtag_uart_write+0x30>
+    44a0:	00000106 	br	44a8 <altera_avalon_jtag_uart_write+0x11c>
+        break;
+    44a4:	0001883a 	nop
+  NIOS2_READ_STATUS (context);
+    44a8:	0005303a 	rdctl	r2,status
+    44ac:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    44b0:	e0fff917 	ldw	r3,-28(fp)
+    44b4:	00bfff84 	movi	r2,-2
+    44b8:	1884703a 	and	r2,r3,r2
+    44bc:	1001703a 	wrctl	status,r2
+  return context;
+    44c0:	e0bff917 	ldw	r2,-28(fp)
+     * to enable interrupts if there is no space left in the FIFO
+     *
+     * For now kick the interrupt routine every time to make it transmit 
+     * the data 
+     */
+    context = alt_irq_disable_all();
+    44c4:	e0bffb15 	stw	r2,-20(fp)
+    sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK;
+    44c8:	e0bff817 	ldw	r2,-32(fp)
+    44cc:	10800817 	ldw	r2,32(r2)
+    44d0:	10c00094 	ori	r3,r2,2
+    44d4:	e0bff817 	ldw	r2,-32(fp)
+    44d8:	10c00815 	stw	r3,32(r2)
+    IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable);
+    44dc:	e0bff817 	ldw	r2,-32(fp)
+    44e0:	10800017 	ldw	r2,0(r2)
+    44e4:	10800104 	addi	r2,r2,4
+    44e8:	1007883a 	mov	r3,r2
+    44ec:	e0bff817 	ldw	r2,-32(fp)
+    44f0:	10800817 	ldw	r2,32(r2)
+    44f4:	18800035 	stwio	r2,0(r3)
+    44f8:	e0bffb17 	ldw	r2,-20(fp)
+    44fc:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+    4500:	e0bffa17 	ldw	r2,-24(fp)
+    4504:	1001703a 	wrctl	status,r2
+}
+    4508:	0001883a 	nop
+    /* 
+     * If there is any data left then either return now or block until 
+     * some has been sent 
+     */
+    /* consider: test whether there is anything there while doing this and delay for at most 2s. */
+    if (count > 0)
+    450c:	e0bff617 	ldw	r2,-40(fp)
+    4510:	0080100e 	bge	zero,r2,4554 <altera_avalon_jtag_uart_write+0x1c8>
+    {
+      if (flags & O_NONBLOCK)
+    4514:	e0bff517 	ldw	r2,-44(fp)
+    4518:	1090000c 	andi	r2,r2,16384
+    451c:	1000101e 	bne	r2,zero,4560 <altera_avalon_jtag_uart_write+0x1d4>
+      /*
+       * No OS present: Always wait for data to be removed from buffer.  Once
+       * the interrupt routine has removed some data then we will be able to
+       * insert some more.
+       */
+      while (out == sp->tx_out && sp->host_inactive < sp->timeout)
+    4520:	0001883a 	nop
+    4524:	e0bff817 	ldw	r2,-32(fp)
+    4528:	10800d17 	ldw	r2,52(r2)
+    452c:	e0ffff17 	ldw	r3,-4(fp)
+    4530:	1880051e 	bne	r3,r2,4548 <altera_avalon_jtag_uart_write+0x1bc>
+    4534:	e0bff817 	ldw	r2,-32(fp)
+    4538:	10c00917 	ldw	r3,36(r2)
+    453c:	e0bff817 	ldw	r2,-32(fp)
+    4540:	10800117 	ldw	r2,4(r2)
+    4544:	18bff736 	bltu	r3,r2,4524 <altera_avalon_jtag_uart_write+0x198>
+        ;
+#endif /* __ucosii__ */
+
+      if  (sp->host_inactive)
+    4548:	e0bff817 	ldw	r2,-32(fp)
+    454c:	10800917 	ldw	r2,36(r2)
+    4550:	1000051e 	bne	r2,zero,4568 <altera_avalon_jtag_uart_write+0x1dc>
+         break;
+    }
+  }
+  while (count > 0);
+    4554:	e0bff617 	ldw	r2,-40(fp)
+    4558:	00bfcf16 	blt	zero,r2,4498 <altera_avalon_jtag_uart_write+0x10c>
+    455c:	00000306 	br	456c <altera_avalon_jtag_uart_write+0x1e0>
+        break;
+    4560:	0001883a 	nop
+    4564:	00000106 	br	456c <altera_avalon_jtag_uart_write+0x1e0>
+         break;
+    4568:	0001883a 	nop
+   * Now that access to the circular buffer is complete, release the write
+   * semaphore so that other threads can access the buffer.
+   */
+  ALT_SEM_POST (sp->write_lock);
+
+  if (ptr != start)
+    456c:	e0fff717 	ldw	r3,-36(fp)
+    4570:	e0bffd17 	ldw	r2,-12(fp)
+    4574:	18800426 	beq	r3,r2,4588 <altera_avalon_jtag_uart_write+0x1fc>
+    return ptr - start;
+    4578:	e0fff717 	ldw	r3,-36(fp)
+    457c:	e0bffd17 	ldw	r2,-12(fp)
+    4580:	1885c83a 	sub	r2,r3,r2
+    4584:	00000606 	br	45a0 <altera_avalon_jtag_uart_write+0x214>
+  else if (flags & O_NONBLOCK)
+    4588:	e0bff517 	ldw	r2,-44(fp)
+    458c:	1090000c 	andi	r2,r2,16384
+    4590:	10000226 	beq	r2,zero,459c <altera_avalon_jtag_uart_write+0x210>
+    return -EWOULDBLOCK;
+    4594:	00bffd44 	movi	r2,-11
+    4598:	00000106 	br	45a0 <altera_avalon_jtag_uart_write+0x214>
+    sp->tx_out = sp->tx_in = 0;
+    return ptr - start + count;
+  }
+#endif
+  else
+    return -EIO; /* Host not connected */
+    459c:	00bffec4 	movi	r2,-5
+}
+    45a0:	e037883a 	mov	sp,fp
+    45a4:	dfc00117 	ldw	ra,4(sp)
+    45a8:	df000017 	ldw	fp,0(sp)
+    45ac:	dec00204 	addi	sp,sp,8
+    45b0:	f800283a 	ret
+
+000045b4 <alt_avalon_timer_sc_irq>:
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void alt_avalon_timer_sc_irq (void* base)
+#else
+static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
+#endif
+{
+    45b4:	defffa04 	addi	sp,sp,-24
+    45b8:	dfc00515 	stw	ra,20(sp)
+    45bc:	df000415 	stw	fp,16(sp)
+    45c0:	df000404 	addi	fp,sp,16
+    45c4:	e13ffc15 	stw	r4,-16(fp)
+  alt_irq_context cpu_sr;
+  
+  /* clear the interrupt */
+  IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
+    45c8:	0007883a 	mov	r3,zero
+    45cc:	e0bffc17 	ldw	r2,-16(fp)
+    45d0:	10c00035 	stwio	r3,0(r2)
+  /* 
+   * Dummy read to ensure IRQ is negated before the ISR returns.
+   * The control register is read because reading the status
+   * register has side-effects per the register map documentation.
+   */
+  IORD_ALTERA_AVALON_TIMER_CONTROL (base);
+    45d4:	e0bffc17 	ldw	r2,-16(fp)
+    45d8:	10800104 	addi	r2,r2,4
+    45dc:	10800037 	ldwio	r2,0(r2)
+  NIOS2_READ_STATUS (context);
+    45e0:	0005303a 	rdctl	r2,status
+    45e4:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    45e8:	e0fffd17 	ldw	r3,-12(fp)
+    45ec:	00bfff84 	movi	r2,-2
+    45f0:	1884703a 	and	r2,r3,r2
+    45f4:	1001703a 	wrctl	status,r2
+  return context;
+    45f8:	e0bffd17 	ldw	r2,-12(fp)
+
+  /* 
+   * Notify the system of a clock tick. disable interrupts 
+   * during this time to safely support ISR preemption
+   */
+  cpu_sr = alt_irq_disable_all();
+    45fc:	e0bfff15 	stw	r2,-4(fp)
+  alt_tick ();
+    4600:	00050980 	call	5098 <alt_tick>
+    4604:	e0bfff17 	ldw	r2,-4(fp)
+    4608:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+    460c:	e0bffe17 	ldw	r2,-8(fp)
+    4610:	1001703a 	wrctl	status,r2
+}
+    4614:	0001883a 	nop
+  alt_irq_enable_all(cpu_sr);
+}
+    4618:	0001883a 	nop
+    461c:	e037883a 	mov	sp,fp
+    4620:	dfc00117 	ldw	ra,4(sp)
+    4624:	df000017 	ldw	fp,0(sp)
+    4628:	dec00204 	addi	sp,sp,8
+    462c:	f800283a 	ret
+
+00004630 <alt_avalon_timer_sc_init>:
+ * auto-generated alt_sys_init() function.
+ */
+
+void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, 
+                                alt_u32 irq, alt_u32 freq)
+{
+    4630:	defff804 	addi	sp,sp,-32
+    4634:	dfc00715 	stw	ra,28(sp)
+    4638:	df000615 	stw	fp,24(sp)
+    463c:	df000604 	addi	fp,sp,24
+    4640:	e13ffe15 	stw	r4,-8(fp)
+    4644:	e17ffd15 	stw	r5,-12(fp)
+    4648:	e1bffc15 	stw	r6,-16(fp)
+    464c:	e1fffb15 	stw	r7,-20(fp)
+    4650:	e0bffb17 	ldw	r2,-20(fp)
+    4654:	e0bfff15 	stw	r2,-4(fp)
+ * in order to initialise the value of the clock frequency.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks)
+{
+  if (! _alt_tick_rate)
+    4658:	d0a01617 	ldw	r2,-32680(gp)
+    465c:	1000031e 	bne	r2,zero,466c <alt_avalon_timer_sc_init+0x3c>
+  {
+    _alt_tick_rate = nticks;
+    4660:	e0bfff17 	ldw	r2,-4(fp)
+    4664:	d0a01615 	stw	r2,-32680(gp)
+    return 0;
+    4668:	00000106 	br	4670 <alt_avalon_timer_sc_init+0x40>
+  }
+  else
+  {
+    return -1;
+    466c:	0001883a 	nop
+  
+  alt_sysclk_init (freq);
+  
+  /* set to free running mode */
+  
+  IOWR_ALTERA_AVALON_TIMER_CONTROL (base, 
+    4670:	e0bffe17 	ldw	r2,-8(fp)
+    4674:	10800104 	addi	r2,r2,4
+    4678:	00c001c4 	movi	r3,7
+    467c:	10c00035 	stwio	r3,0(r2)
+            ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
+            ALTERA_AVALON_TIMER_CONTROL_START_MSK);
+
+  /* register the interrupt handler, and enable the interrupt */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, 
+    4680:	d8000015 	stw	zero,0(sp)
+    4684:	e1fffe17 	ldw	r7,-8(fp)
+    4688:	01800034 	movhi	r6,0
+    468c:	31916d04 	addi	r6,r6,17844
+    4690:	e17ffc17 	ldw	r5,-16(fp)
+    4694:	e13ffd17 	ldw	r4,-12(fp)
+    4698:	00049940 	call	4994 <alt_ic_isr_register>
+                      base, NULL);
+#else
+  alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
+#endif  
+}
+    469c:	0001883a 	nop
+    46a0:	e037883a 	mov	sp,fp
+    46a4:	dfc00117 	ldw	ra,4(sp)
+    46a8:	df000017 	ldw	fp,0(sp)
+    46ac:	dec00204 	addi	sp,sp,8
+    46b0:	f800283a 	ret
+
+000046b4 <alt_alarm_start>:
+ */ 
+
+int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks,
+                     alt_u32 (*callback) (void* context),
+                     void* context)
+{
+    46b4:	defff504 	addi	sp,sp,-44
+    46b8:	df000a15 	stw	fp,40(sp)
+    46bc:	df000a04 	addi	fp,sp,40
+    46c0:	e13ff915 	stw	r4,-28(fp)
+    46c4:	e17ff815 	stw	r5,-32(fp)
+    46c8:	e1bff715 	stw	r6,-36(fp)
+    46cc:	e1fff615 	stw	r7,-40(fp)
+  alt_irq_context irq_context;
+  alt_u32 current_nticks = 0;
+    46d0:	e03fff15 	stw	zero,-4(fp)
+  return _alt_tick_rate;
+    46d4:	d0a01617 	ldw	r2,-32680(gp)
+  
+  if (alt_ticks_per_second ())
+    46d8:	10003e26 	beq	r2,zero,47d4 <alt_alarm_start+0x120>
+  {
+    if (alarm)
+    46dc:	e0bff917 	ldw	r2,-28(fp)
+    46e0:	10003a26 	beq	r2,zero,47cc <alt_alarm_start+0x118>
+    {
+      alarm->callback = callback;
+    46e4:	e0bff917 	ldw	r2,-28(fp)
+    46e8:	e0fff717 	ldw	r3,-36(fp)
+    46ec:	10c00315 	stw	r3,12(r2)
+      alarm->context  = context;
+    46f0:	e0bff917 	ldw	r2,-28(fp)
+    46f4:	e0fff617 	ldw	r3,-40(fp)
+    46f8:	10c00515 	stw	r3,20(r2)
+  NIOS2_READ_STATUS (context);
+    46fc:	0005303a 	rdctl	r2,status
+    4700:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    4704:	e0fffd17 	ldw	r3,-12(fp)
+    4708:	00bfff84 	movi	r2,-2
+    470c:	1884703a 	and	r2,r3,r2
+    4710:	1001703a 	wrctl	status,r2
+  return context;
+    4714:	e0bffd17 	ldw	r2,-12(fp)
+ 
+      irq_context = alt_irq_disable_all ();
+    4718:	e0bffe15 	stw	r2,-8(fp)
+ * alt_nticks() returns the elapsed number of system clock ticks since reset.
+ */
+
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void)
+{
+  return _alt_nticks;
+    471c:	d0a01717 	ldw	r2,-32676(gp)
+      
+      current_nticks = alt_nticks();
+    4720:	e0bfff15 	stw	r2,-4(fp)
+      
+      alarm->time = nticks + current_nticks + 1; 
+    4724:	e0fff817 	ldw	r3,-32(fp)
+    4728:	e0bfff17 	ldw	r2,-4(fp)
+    472c:	1885883a 	add	r2,r3,r2
+    4730:	10c00044 	addi	r3,r2,1
+    4734:	e0bff917 	ldw	r2,-28(fp)
+    4738:	10c00215 	stw	r3,8(r2)
+      /* 
+       * If the desired alarm time causes a roll-over, set the rollover
+       * flag. This will prevent the subsequent tick event from causing
+       * an alarm too early.
+       */
+      if(alarm->time < current_nticks)
+    473c:	e0bff917 	ldw	r2,-28(fp)
+    4740:	10c00217 	ldw	r3,8(r2)
+    4744:	e0bfff17 	ldw	r2,-4(fp)
+    4748:	1880042e 	bgeu	r3,r2,475c <alt_alarm_start+0xa8>
+      {
+        alarm->rollover = 1;
+    474c:	e0bff917 	ldw	r2,-28(fp)
+    4750:	00c00044 	movi	r3,1
+    4754:	10c00405 	stb	r3,16(r2)
+    4758:	00000206 	br	4764 <alt_alarm_start+0xb0>
+      }
+      else
+      {
+        alarm->rollover = 0;
+    475c:	e0bff917 	ldw	r2,-28(fp)
+    4760:	10000405 	stb	zero,16(r2)
+      }
+    
+      alt_llist_insert (&alt_alarm_list, &alarm->llist);
+    4764:	e0bff917 	ldw	r2,-28(fp)
+    4768:	d0e00c04 	addi	r3,gp,-32720
+    476c:	e0fffb15 	stw	r3,-20(fp)
+    4770:	e0bffa15 	stw	r2,-24(fp)
+ */
+
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, 
+                alt_llist* entry)
+{
+  entry->previous = list;
+    4774:	e0bffa17 	ldw	r2,-24(fp)
+    4778:	e0fffb17 	ldw	r3,-20(fp)
+    477c:	10c00115 	stw	r3,4(r2)
+  entry->next     = list->next;
+    4780:	e0bffb17 	ldw	r2,-20(fp)
+    4784:	10c00017 	ldw	r3,0(r2)
+    4788:	e0bffa17 	ldw	r2,-24(fp)
+    478c:	10c00015 	stw	r3,0(r2)
+
+  list->next->previous = entry;
+    4790:	e0bffb17 	ldw	r2,-20(fp)
+    4794:	10800017 	ldw	r2,0(r2)
+    4798:	e0fffa17 	ldw	r3,-24(fp)
+    479c:	10c00115 	stw	r3,4(r2)
+  list->next           = entry;
+    47a0:	e0bffb17 	ldw	r2,-20(fp)
+    47a4:	e0fffa17 	ldw	r3,-24(fp)
+    47a8:	10c00015 	stw	r3,0(r2)
+}
+    47ac:	0001883a 	nop
+    47b0:	e0bffe17 	ldw	r2,-8(fp)
+    47b4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+    47b8:	e0bffc17 	ldw	r2,-16(fp)
+    47bc:	1001703a 	wrctl	status,r2
+}
+    47c0:	0001883a 	nop
+      alt_irq_enable_all (irq_context);
+
+      return 0;
+    47c4:	0005883a 	mov	r2,zero
+    47c8:	00000306 	br	47d8 <alt_alarm_start+0x124>
+    }
+    else
+    {
+      return -EINVAL;
+    47cc:	00bffa84 	movi	r2,-22
+    47d0:	00000106 	br	47d8 <alt_alarm_start+0x124>
+    }
+  }
+  else
+  {
+    return -ENOTSUP;
+    47d4:	00bfde84 	movi	r2,-134
+  }
+}
+    47d8:	e037883a 	mov	sp,fp
+    47dc:	df000017 	ldw	fp,0(sp)
+    47e0:	dec00104 	addi	sp,sp,4
+    47e4:	f800283a 	ret
+
+000047e8 <alt_get_errno>:
+{
+    47e8:	defffe04 	addi	sp,sp,-8
+    47ec:	dfc00115 	stw	ra,4(sp)
+    47f0:	df000015 	stw	fp,0(sp)
+    47f4:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    47f8:	d0a00917 	ldw	r2,-32732(gp)
+    47fc:	10000326 	beq	r2,zero,480c <alt_get_errno+0x24>
+    4800:	d0a00917 	ldw	r2,-32732(gp)
+    4804:	103ee83a 	callr	r2
+    4808:	00000106 	br	4810 <alt_get_errno+0x28>
+    480c:	d0a01104 	addi	r2,gp,-32700
+}
+    4810:	e037883a 	mov	sp,fp
+    4814:	dfc00117 	ldw	ra,4(sp)
+    4818:	df000017 	ldw	fp,0(sp)
+    481c:	dec00204 	addi	sp,sp,8
+    4820:	f800283a 	ret
+
+00004824 <alt_dev_llist_insert>:
+/*
+ *
+ */
+
+int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list)
+{
+    4824:	defffa04 	addi	sp,sp,-24
+    4828:	dfc00515 	stw	ra,20(sp)
+    482c:	df000415 	stw	fp,16(sp)
+    4830:	df000404 	addi	fp,sp,16
+    4834:	e13ffd15 	stw	r4,-12(fp)
+    4838:	e17ffc15 	stw	r5,-16(fp)
+  /*
+   * check that the device exists, and that it has a valid name.
+   */
+
+  if (!dev || !dev->name)
+    483c:	e0bffd17 	ldw	r2,-12(fp)
+    4840:	10000326 	beq	r2,zero,4850 <alt_dev_llist_insert+0x2c>
+    4844:	e0bffd17 	ldw	r2,-12(fp)
+    4848:	10800217 	ldw	r2,8(r2)
+    484c:	1000061e 	bne	r2,zero,4868 <alt_dev_llist_insert+0x44>
+  {
+    ALT_ERRNO = EINVAL;
+    4850:	00047e80 	call	47e8 <alt_get_errno>
+    4854:	1007883a 	mov	r3,r2
+    4858:	00800584 	movi	r2,22
+    485c:	18800015 	stw	r2,0(r3)
+    return -EINVAL;
+    4860:	00bffa84 	movi	r2,-22
+    4864:	00001406 	br	48b8 <alt_dev_llist_insert+0x94>
+  
+  /*
+   * register the device.
+   */
+  
+  alt_llist_insert(list, &dev->llist);
+    4868:	e0bffd17 	ldw	r2,-12(fp)
+    486c:	e0fffc17 	ldw	r3,-16(fp)
+    4870:	e0ffff15 	stw	r3,-4(fp)
+    4874:	e0bffe15 	stw	r2,-8(fp)
+  entry->previous = list;
+    4878:	e0bffe17 	ldw	r2,-8(fp)
+    487c:	e0ffff17 	ldw	r3,-4(fp)
+    4880:	10c00115 	stw	r3,4(r2)
+  entry->next     = list->next;
+    4884:	e0bfff17 	ldw	r2,-4(fp)
+    4888:	10c00017 	ldw	r3,0(r2)
+    488c:	e0bffe17 	ldw	r2,-8(fp)
+    4890:	10c00015 	stw	r3,0(r2)
+  list->next->previous = entry;
+    4894:	e0bfff17 	ldw	r2,-4(fp)
+    4898:	10800017 	ldw	r2,0(r2)
+    489c:	e0fffe17 	ldw	r3,-8(fp)
+    48a0:	10c00115 	stw	r3,4(r2)
+  list->next           = entry;
+    48a4:	e0bfff17 	ldw	r2,-4(fp)
+    48a8:	e0fffe17 	ldw	r3,-8(fp)
+    48ac:	10c00015 	stw	r3,0(r2)
+}
+    48b0:	0001883a 	nop
+
+  return 0;  
+    48b4:	0005883a 	mov	r2,zero
+}
+    48b8:	e037883a 	mov	sp,fp
+    48bc:	dfc00117 	ldw	ra,4(sp)
+    48c0:	df000017 	ldw	fp,0(sp)
+    48c4:	dec00204 	addi	sp,sp,8
+    48c8:	f800283a 	ret
+
+000048cc <_do_ctors>:
+/*
+ * Run the C++ static constructors.
+ */
+
+void _do_ctors(void)
+{
+    48cc:	defffd04 	addi	sp,sp,-12
+    48d0:	dfc00215 	stw	ra,8(sp)
+    48d4:	df000115 	stw	fp,4(sp)
+    48d8:	df000104 	addi	fp,sp,4
+  constructor* ctor;
+
+  for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
+    48dc:	00800034 	movhi	r2,0
+    48e0:	1095d404 	addi	r2,r2,22352
+    48e4:	e0bfff15 	stw	r2,-4(fp)
+    48e8:	00000606 	br	4904 <_do_ctors+0x38>
+        (*ctor) (); 
+    48ec:	e0bfff17 	ldw	r2,-4(fp)
+    48f0:	10800017 	ldw	r2,0(r2)
+    48f4:	103ee83a 	callr	r2
+  for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
+    48f8:	e0bfff17 	ldw	r2,-4(fp)
+    48fc:	10bfff04 	addi	r2,r2,-4
+    4900:	e0bfff15 	stw	r2,-4(fp)
+    4904:	e0ffff17 	ldw	r3,-4(fp)
+    4908:	00800034 	movhi	r2,0
+    490c:	1095d504 	addi	r2,r2,22356
+    4910:	18bff62e 	bgeu	r3,r2,48ec <_do_ctors+0x20>
+}
+    4914:	0001883a 	nop
+    4918:	0001883a 	nop
+    491c:	e037883a 	mov	sp,fp
+    4920:	dfc00117 	ldw	ra,4(sp)
+    4924:	df000017 	ldw	fp,0(sp)
+    4928:	dec00204 	addi	sp,sp,8
+    492c:	f800283a 	ret
+
+00004930 <_do_dtors>:
+/*
+ * Run the C++ static destructors.
+ */
+
+void _do_dtors(void)
+{
+    4930:	defffd04 	addi	sp,sp,-12
+    4934:	dfc00215 	stw	ra,8(sp)
+    4938:	df000115 	stw	fp,4(sp)
+    493c:	df000104 	addi	fp,sp,4
+  destructor* dtor;
+
+  for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
+    4940:	00800034 	movhi	r2,0
+    4944:	1095d404 	addi	r2,r2,22352
+    4948:	e0bfff15 	stw	r2,-4(fp)
+    494c:	00000606 	br	4968 <_do_dtors+0x38>
+        (*dtor) (); 
+    4950:	e0bfff17 	ldw	r2,-4(fp)
+    4954:	10800017 	ldw	r2,0(r2)
+    4958:	103ee83a 	callr	r2
+  for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
+    495c:	e0bfff17 	ldw	r2,-4(fp)
+    4960:	10bfff04 	addi	r2,r2,-4
+    4964:	e0bfff15 	stw	r2,-4(fp)
+    4968:	e0ffff17 	ldw	r3,-4(fp)
+    496c:	00800034 	movhi	r2,0
+    4970:	1095d504 	addi	r2,r2,22356
+    4974:	18bff62e 	bgeu	r3,r2,4950 <_do_dtors+0x20>
+}
+    4978:	0001883a 	nop
+    497c:	0001883a 	nop
+    4980:	e037883a 	mov	sp,fp
+    4984:	dfc00117 	ldw	ra,4(sp)
+    4988:	df000017 	ldw	fp,0(sp)
+    498c:	dec00204 	addi	sp,sp,8
+    4990:	f800283a 	ret
+
+00004994 <alt_ic_isr_register>:
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+    4994:	defff904 	addi	sp,sp,-28
+    4998:	dfc00615 	stw	ra,24(sp)
+    499c:	df000515 	stw	fp,20(sp)
+    49a0:	df000504 	addi	fp,sp,20
+    49a4:	e13fff15 	stw	r4,-4(fp)
+    49a8:	e17ffe15 	stw	r5,-8(fp)
+    49ac:	e1bffd15 	stw	r6,-12(fp)
+    49b0:	e1fffc15 	stw	r7,-16(fp)
+    return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags);
+    49b4:	e0800217 	ldw	r2,8(fp)
+    49b8:	d8800015 	stw	r2,0(sp)
+    49bc:	e1fffc17 	ldw	r7,-16(fp)
+    49c0:	e1bffd17 	ldw	r6,-12(fp)
+    49c4:	e17ffe17 	ldw	r5,-8(fp)
+    49c8:	e13fff17 	ldw	r4,-4(fp)
+    49cc:	0004b440 	call	4b44 <alt_iic_isr_register>
+}  
+    49d0:	e037883a 	mov	sp,fp
+    49d4:	dfc00117 	ldw	ra,4(sp)
+    49d8:	df000017 	ldw	fp,0(sp)
+    49dc:	dec00204 	addi	sp,sp,8
+    49e0:	f800283a 	ret
+
+000049e4 <alt_ic_irq_enable>:
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq)
+{
+    49e4:	defff904 	addi	sp,sp,-28
+    49e8:	df000615 	stw	fp,24(sp)
+    49ec:	df000604 	addi	fp,sp,24
+    49f0:	e13ffb15 	stw	r4,-20(fp)
+    49f4:	e17ffa15 	stw	r5,-24(fp)
+    49f8:	e0bffa17 	ldw	r2,-24(fp)
+    49fc:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+    4a00:	0005303a 	rdctl	r2,status
+    4a04:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    4a08:	e0fffe17 	ldw	r3,-8(fp)
+    4a0c:	00bfff84 	movi	r2,-2
+    4a10:	1884703a 	and	r2,r3,r2
+    4a14:	1001703a 	wrctl	status,r2
+  return context;
+    4a18:	e0bffe17 	ldw	r2,-8(fp)
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id)
+{
+  alt_irq_context  status;
+  extern volatile alt_u32 alt_irq_active;
+
+  status = alt_irq_disable_all ();
+    4a1c:	e0bffd15 	stw	r2,-12(fp)
+
+  alt_irq_active |= (1 << id);
+    4a20:	00c00044 	movi	r3,1
+    4a24:	e0bfff17 	ldw	r2,-4(fp)
+    4a28:	1884983a 	sll	r2,r3,r2
+    4a2c:	1007883a 	mov	r3,r2
+    4a30:	d0a01517 	ldw	r2,-32684(gp)
+    4a34:	1884b03a 	or	r2,r3,r2
+    4a38:	d0a01515 	stw	r2,-32684(gp)
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+    4a3c:	d0a01517 	ldw	r2,-32684(gp)
+    4a40:	100170fa 	wrctl	ienable,r2
+    4a44:	e0bffd17 	ldw	r2,-12(fp)
+    4a48:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+    4a4c:	e0bffc17 	ldw	r2,-16(fp)
+    4a50:	1001703a 	wrctl	status,r2
+}
+    4a54:	0001883a 	nop
+
+  alt_irq_enable_all(status);
+
+  return 0;
+    4a58:	0005883a 	mov	r2,zero
+    return alt_irq_enable(irq);
+}
+    4a5c:	e037883a 	mov	sp,fp
+    4a60:	df000017 	ldw	fp,0(sp)
+    4a64:	dec00104 	addi	sp,sp,4
+    4a68:	f800283a 	ret
+
+00004a6c <alt_ic_irq_disable>:
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq)
+{
+    4a6c:	defff904 	addi	sp,sp,-28
+    4a70:	df000615 	stw	fp,24(sp)
+    4a74:	df000604 	addi	fp,sp,24
+    4a78:	e13ffb15 	stw	r4,-20(fp)
+    4a7c:	e17ffa15 	stw	r5,-24(fp)
+    4a80:	e0bffa17 	ldw	r2,-24(fp)
+    4a84:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+    4a88:	0005303a 	rdctl	r2,status
+    4a8c:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    4a90:	e0fffe17 	ldw	r3,-8(fp)
+    4a94:	00bfff84 	movi	r2,-2
+    4a98:	1884703a 	and	r2,r3,r2
+    4a9c:	1001703a 	wrctl	status,r2
+  return context;
+    4aa0:	e0bffe17 	ldw	r2,-8(fp)
+  status = alt_irq_disable_all ();
+    4aa4:	e0bffd15 	stw	r2,-12(fp)
+  alt_irq_active &= ~(1 << id);
+    4aa8:	00c00044 	movi	r3,1
+    4aac:	e0bfff17 	ldw	r2,-4(fp)
+    4ab0:	1884983a 	sll	r2,r3,r2
+    4ab4:	0084303a 	nor	r2,zero,r2
+    4ab8:	1007883a 	mov	r3,r2
+    4abc:	d0a01517 	ldw	r2,-32684(gp)
+    4ac0:	1884703a 	and	r2,r3,r2
+    4ac4:	d0a01515 	stw	r2,-32684(gp)
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+    4ac8:	d0a01517 	ldw	r2,-32684(gp)
+    4acc:	100170fa 	wrctl	ienable,r2
+    4ad0:	e0bffd17 	ldw	r2,-12(fp)
+    4ad4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+    4ad8:	e0bffc17 	ldw	r2,-16(fp)
+    4adc:	1001703a 	wrctl	status,r2
+}
+    4ae0:	0001883a 	nop
+  return 0;
+    4ae4:	0005883a 	mov	r2,zero
+    return alt_irq_disable(irq);
+}
+    4ae8:	e037883a 	mov	sp,fp
+    4aec:	df000017 	ldw	fp,0(sp)
+    4af0:	dec00104 	addi	sp,sp,4
+    4af4:	f800283a 	ret
+
+00004af8 <alt_ic_irq_enabled>:
+  * @param irq              IRQ number
+  * @return                 Zero if corresponding interrupt is disabled and
+  *                         non-zero otherwise.
+  */
+alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq)
+{
+    4af8:	defffc04 	addi	sp,sp,-16
+    4afc:	df000315 	stw	fp,12(sp)
+    4b00:	df000304 	addi	fp,sp,12
+    4b04:	e13ffe15 	stw	r4,-8(fp)
+    4b08:	e17ffd15 	stw	r5,-12(fp)
+    alt_u32 irq_enabled;
+
+    NIOS2_READ_IENABLE(irq_enabled);
+    4b0c:	000530fa 	rdctl	r2,ienable
+    4b10:	e0bfff15 	stw	r2,-4(fp)
+
+    return (irq_enabled & (1 << irq)) ? 1: 0;
+    4b14:	00c00044 	movi	r3,1
+    4b18:	e0bffd17 	ldw	r2,-12(fp)
+    4b1c:	1884983a 	sll	r2,r3,r2
+    4b20:	1007883a 	mov	r3,r2
+    4b24:	e0bfff17 	ldw	r2,-4(fp)
+    4b28:	1884703a 	and	r2,r3,r2
+    4b2c:	1004c03a 	cmpne	r2,r2,zero
+    4b30:	10803fcc 	andi	r2,r2,255
+}
+    4b34:	e037883a 	mov	sp,fp
+    4b38:	df000017 	ldw	fp,0(sp)
+    4b3c:	dec00104 	addi	sp,sp,4
+    4b40:	f800283a 	ret
+
+00004b44 <alt_iic_isr_register>:
+  * @param flags            
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+    4b44:	defff504 	addi	sp,sp,-44
+    4b48:	dfc00a15 	stw	ra,40(sp)
+    4b4c:	df000915 	stw	fp,36(sp)
+    4b50:	df000904 	addi	fp,sp,36
+    4b54:	e13ffa15 	stw	r4,-24(fp)
+    4b58:	e17ff915 	stw	r5,-28(fp)
+    4b5c:	e1bff815 	stw	r6,-32(fp)
+    4b60:	e1fff715 	stw	r7,-36(fp)
+  int rc = -EINVAL;  
+    4b64:	00bffa84 	movi	r2,-22
+    4b68:	e0bfff15 	stw	r2,-4(fp)
+  int id = irq;             /* IRQ interpreted as the interrupt ID. */
+    4b6c:	e0bff917 	ldw	r2,-28(fp)
+    4b70:	e0bffe15 	stw	r2,-8(fp)
+  alt_irq_context status;
+
+  if (id < ALT_NIRQ)
+    4b74:	e0bffe17 	ldw	r2,-8(fp)
+    4b78:	10800808 	cmpgei	r2,r2,32
+    4b7c:	1000251e 	bne	r2,zero,4c14 <alt_iic_isr_register+0xd0>
+  NIOS2_READ_STATUS (context);
+    4b80:	0005303a 	rdctl	r2,status
+    4b84:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    4b88:	e0fffc17 	ldw	r3,-16(fp)
+    4b8c:	00bfff84 	movi	r2,-2
+    4b90:	1884703a 	and	r2,r3,r2
+    4b94:	1001703a 	wrctl	status,r2
+  return context;
+    4b98:	e0bffc17 	ldw	r2,-16(fp)
+     * interrupts are disabled while the handler tables are updated to ensure
+     * that an interrupt doesn't occur while the tables are in an inconsistant
+     * state.
+     */
+
+    status = alt_irq_disable_all();
+    4b9c:	e0bffd15 	stw	r2,-12(fp)
+
+    alt_irq[id].handler = isr;
+    4ba0:	e0bffe17 	ldw	r2,-8(fp)
+    4ba4:	100890fa 	slli	r4,r2,3
+    4ba8:	e0fff817 	ldw	r3,-32(fp)
+    4bac:	00800034 	movhi	r2,0
+    4bb0:	2085883a 	add	r2,r4,r2
+    4bb4:	10dca315 	stw	r3,29324(r2)
+    alt_irq[id].context = isr_context;
+    4bb8:	e0bffe17 	ldw	r2,-8(fp)
+    4bbc:	100890fa 	slli	r4,r2,3
+    4bc0:	e0fff717 	ldw	r3,-36(fp)
+    4bc4:	00800034 	movhi	r2,0
+    4bc8:	2085883a 	add	r2,r4,r2
+    4bcc:	10dca415 	stw	r3,29328(r2)
+
+    rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
+    4bd0:	e0bff817 	ldw	r2,-32(fp)
+    4bd4:	10000526 	beq	r2,zero,4bec <alt_iic_isr_register+0xa8>
+    4bd8:	e0bffe17 	ldw	r2,-8(fp)
+    4bdc:	100b883a 	mov	r5,r2
+    4be0:	e13ffa17 	ldw	r4,-24(fp)
+    4be4:	00049e40 	call	49e4 <alt_ic_irq_enable>
+    4be8:	00000406 	br	4bfc <alt_iic_isr_register+0xb8>
+    4bec:	e0bffe17 	ldw	r2,-8(fp)
+    4bf0:	100b883a 	mov	r5,r2
+    4bf4:	e13ffa17 	ldw	r4,-24(fp)
+    4bf8:	0004a6c0 	call	4a6c <alt_ic_irq_disable>
+    4bfc:	e0bfff15 	stw	r2,-4(fp)
+    4c00:	e0bffd17 	ldw	r2,-12(fp)
+    4c04:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+    4c08:	e0bffb17 	ldw	r2,-20(fp)
+    4c0c:	1001703a 	wrctl	status,r2
+}
+    4c10:	0001883a 	nop
+
+    alt_irq_enable_all(status);
+  }
+
+  return rc; 
+    4c14:	e0bfff17 	ldw	r2,-4(fp)
+}
+    4c18:	e037883a 	mov	sp,fp
+    4c1c:	dfc00117 	ldw	ra,4(sp)
+    4c20:	df000017 	ldw	fp,0(sp)
+    4c24:	dec00204 	addi	sp,sp,8
+    4c28:	f800283a 	ret
+
+00004c2c <alt_open_fd>:
+ * If the device can not be succesfully opened, then the input file descriptor
+ * remains unchanged.
+ */
+
+static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode)
+{
+    4c2c:	defff904 	addi	sp,sp,-28
+    4c30:	dfc00615 	stw	ra,24(sp)
+    4c34:	df000515 	stw	fp,20(sp)
+    4c38:	df000504 	addi	fp,sp,20
+    4c3c:	e13ffe15 	stw	r4,-8(fp)
+    4c40:	e17ffd15 	stw	r5,-12(fp)
+    4c44:	e1bffc15 	stw	r6,-16(fp)
+    4c48:	e1fffb15 	stw	r7,-20(fp)
+  int old;
+
+  old = open (name, flags, mode);
+    4c4c:	e1bffb17 	ldw	r6,-20(fp)
+    4c50:	e17ffc17 	ldw	r5,-16(fp)
+    4c54:	e13ffd17 	ldw	r4,-12(fp)
+    4c58:	0004e940 	call	4e94 <open>
+    4c5c:	e0bfff15 	stw	r2,-4(fp)
+
+  if (old >= 0)
+    4c60:	e0bfff17 	ldw	r2,-4(fp)
+    4c64:	10002016 	blt	r2,zero,4ce8 <alt_open_fd+0xbc>
+  {
+    fd->dev      = alt_fd_list[old].dev;
+    4c68:	e0ffff17 	ldw	r3,-4(fp)
+    4c6c:	1805883a 	mov	r2,r3
+    4c70:	1085883a 	add	r2,r2,r2
+    4c74:	10c5883a 	add	r2,r2,r3
+    4c78:	100490ba 	slli	r2,r2,2
+    4c7c:	00c00034 	movhi	r3,0
+    4c80:	10c7883a 	add	r3,r2,r3
+    4c84:	18d80817 	ldw	r3,24608(r3)
+    4c88:	e0bffe17 	ldw	r2,-8(fp)
+    4c8c:	10c00015 	stw	r3,0(r2)
+    fd->priv     = alt_fd_list[old].priv;
+    4c90:	e0ffff17 	ldw	r3,-4(fp)
+    4c94:	1805883a 	mov	r2,r3
+    4c98:	1085883a 	add	r2,r2,r2
+    4c9c:	10c5883a 	add	r2,r2,r3
+    4ca0:	100490ba 	slli	r2,r2,2
+    4ca4:	00c00034 	movhi	r3,0
+    4ca8:	10c7883a 	add	r3,r2,r3
+    4cac:	18d80917 	ldw	r3,24612(r3)
+    4cb0:	e0bffe17 	ldw	r2,-8(fp)
+    4cb4:	10c00115 	stw	r3,4(r2)
+    fd->fd_flags = alt_fd_list[old].fd_flags;
+    4cb8:	e0ffff17 	ldw	r3,-4(fp)
+    4cbc:	1805883a 	mov	r2,r3
+    4cc0:	1085883a 	add	r2,r2,r2
+    4cc4:	10c5883a 	add	r2,r2,r3
+    4cc8:	100490ba 	slli	r2,r2,2
+    4ccc:	00c00034 	movhi	r3,0
+    4cd0:	10c7883a 	add	r3,r2,r3
+    4cd4:	18d80a17 	ldw	r3,24616(r3)
+    4cd8:	e0bffe17 	ldw	r2,-8(fp)
+    4cdc:	10c00215 	stw	r3,8(r2)
+
+    alt_release_fd (old);
+    4ce0:	e13fff17 	ldw	r4,-4(fp)
+    4ce4:	00038080 	call	3808 <alt_release_fd>
+  }
+} 
+    4ce8:	0001883a 	nop
+    4cec:	e037883a 	mov	sp,fp
+    4cf0:	dfc00117 	ldw	ra,4(sp)
+    4cf4:	df000017 	ldw	fp,0(sp)
+    4cf8:	dec00204 	addi	sp,sp,8
+    4cfc:	f800283a 	ret
+
+00004d00 <alt_io_redirect>:
+ */
+ 
+void alt_io_redirect(const char* stdout_dev, 
+                     const char* stdin_dev, 
+                     const char* stderr_dev)
+{
+    4d00:	defffb04 	addi	sp,sp,-20
+    4d04:	dfc00415 	stw	ra,16(sp)
+    4d08:	df000315 	stw	fp,12(sp)
+    4d0c:	df000304 	addi	fp,sp,12
+    4d10:	e13fff15 	stw	r4,-4(fp)
+    4d14:	e17ffe15 	stw	r5,-8(fp)
+    4d18:	e1bffd15 	stw	r6,-12(fp)
+  /* Redirect the channels */
+
+  alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777);
+    4d1c:	01c07fc4 	movi	r7,511
+    4d20:	01800044 	movi	r6,1
+    4d24:	e17fff17 	ldw	r5,-4(fp)
+    4d28:	01000034 	movhi	r4,0
+    4d2c:	21180b04 	addi	r4,r4,24620
+    4d30:	0004c2c0 	call	4c2c <alt_open_fd>
+  alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777);
+    4d34:	01c07fc4 	movi	r7,511
+    4d38:	000d883a 	mov	r6,zero
+    4d3c:	e17ffe17 	ldw	r5,-8(fp)
+    4d40:	01000034 	movhi	r4,0
+    4d44:	21180804 	addi	r4,r4,24608
+    4d48:	0004c2c0 	call	4c2c <alt_open_fd>
+  alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777);
+    4d4c:	01c07fc4 	movi	r7,511
+    4d50:	01800044 	movi	r6,1
+    4d54:	e17ffd17 	ldw	r5,-12(fp)
+    4d58:	01000034 	movhi	r4,0
+    4d5c:	21180e04 	addi	r4,r4,24632
+    4d60:	0004c2c0 	call	4c2c <alt_open_fd>
+}  
+    4d64:	0001883a 	nop
+    4d68:	e037883a 	mov	sp,fp
+    4d6c:	dfc00117 	ldw	ra,4(sp)
+    4d70:	df000017 	ldw	fp,0(sp)
+    4d74:	dec00204 	addi	sp,sp,8
+    4d78:	f800283a 	ret
+
+00004d7c <alt_get_errno>:
+{
+    4d7c:	defffe04 	addi	sp,sp,-8
+    4d80:	dfc00115 	stw	ra,4(sp)
+    4d84:	df000015 	stw	fp,0(sp)
+    4d88:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+    4d8c:	d0a00917 	ldw	r2,-32732(gp)
+    4d90:	10000326 	beq	r2,zero,4da0 <alt_get_errno+0x24>
+    4d94:	d0a00917 	ldw	r2,-32732(gp)
+    4d98:	103ee83a 	callr	r2
+    4d9c:	00000106 	br	4da4 <alt_get_errno+0x28>
+    4da0:	d0a01104 	addi	r2,gp,-32700
+}
+    4da4:	e037883a 	mov	sp,fp
+    4da8:	dfc00117 	ldw	ra,4(sp)
+    4dac:	df000017 	ldw	fp,0(sp)
+    4db0:	dec00204 	addi	sp,sp,8
+    4db4:	f800283a 	ret
+
+00004db8 <alt_file_locked>:
+ * performed for devices. Filesystems are required to handle the ioctl() call
+ * themselves, and report the error from the filesystems open() function. 
+ */ 
+
+static int alt_file_locked (alt_fd* fd)
+{
+    4db8:	defffd04 	addi	sp,sp,-12
+    4dbc:	df000215 	stw	fp,8(sp)
+    4dc0:	df000204 	addi	fp,sp,8
+    4dc4:	e13ffe15 	stw	r4,-8(fp)
+
+  /*
+   * Mark the file descriptor as belonging to a device.
+   */
+
+  fd->fd_flags |= ALT_FD_DEV;
+    4dc8:	e0bffe17 	ldw	r2,-8(fp)
+    4dcc:	10800217 	ldw	r2,8(r2)
+    4dd0:	10d00034 	orhi	r3,r2,16384
+    4dd4:	e0bffe17 	ldw	r2,-8(fp)
+    4dd8:	10c00215 	stw	r3,8(r2)
+  /*
+   * Loop through all current file descriptors searching for one that's locked
+   * for exclusive access. If a match is found, generate an error.
+   */
+
+  for (i = 0; i <= alt_max_fd; i++)
+    4ddc:	e03fff15 	stw	zero,-4(fp)
+    4de0:	00002306 	br	4e70 <alt_file_locked+0xb8>
+  {
+    if ((alt_fd_list[i].dev == fd->dev) &&
+    4de4:	e0ffff17 	ldw	r3,-4(fp)
+    4de8:	1805883a 	mov	r2,r3
+    4dec:	1085883a 	add	r2,r2,r2
+    4df0:	10c5883a 	add	r2,r2,r3
+    4df4:	100490ba 	slli	r2,r2,2
+    4df8:	00c00034 	movhi	r3,0
+    4dfc:	10c7883a 	add	r3,r2,r3
+    4e00:	18d80817 	ldw	r3,24608(r3)
+    4e04:	e0bffe17 	ldw	r2,-8(fp)
+    4e08:	10800017 	ldw	r2,0(r2)
+    4e0c:	1880151e 	bne	r3,r2,4e64 <alt_file_locked+0xac>
+        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+    4e10:	e0ffff17 	ldw	r3,-4(fp)
+    4e14:	1805883a 	mov	r2,r3
+    4e18:	1085883a 	add	r2,r2,r2
+    4e1c:	10c5883a 	add	r2,r2,r3
+    4e20:	100490ba 	slli	r2,r2,2
+    4e24:	00c00034 	movhi	r3,0
+    4e28:	10c7883a 	add	r3,r2,r3
+    4e2c:	18980a17 	ldw	r2,24616(r3)
+    if ((alt_fd_list[i].dev == fd->dev) &&
+    4e30:	10000c0e 	bge	r2,zero,4e64 <alt_file_locked+0xac>
+        (&alt_fd_list[i] != fd))
+    4e34:	e0ffff17 	ldw	r3,-4(fp)
+    4e38:	1805883a 	mov	r2,r3
+    4e3c:	1085883a 	add	r2,r2,r2
+    4e40:	10c5883a 	add	r2,r2,r3
+    4e44:	100490ba 	slli	r2,r2,2
+    4e48:	00c00034 	movhi	r3,0
+    4e4c:	18d80804 	addi	r3,r3,24608
+    4e50:	10c5883a 	add	r2,r2,r3
+        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+    4e54:	e0fffe17 	ldw	r3,-8(fp)
+    4e58:	18800226 	beq	r3,r2,4e64 <alt_file_locked+0xac>
+    {
+      return -EACCES;
+    4e5c:	00bffcc4 	movi	r2,-13
+    4e60:	00000806 	br	4e84 <alt_file_locked+0xcc>
+  for (i = 0; i <= alt_max_fd; i++)
+    4e64:	e0bfff17 	ldw	r2,-4(fp)
+    4e68:	10800044 	addi	r2,r2,1
+    4e6c:	e0bfff15 	stw	r2,-4(fp)
+    4e70:	d0a00817 	ldw	r2,-32736(gp)
+    4e74:	1007883a 	mov	r3,r2
+    4e78:	e0bfff17 	ldw	r2,-4(fp)
+    4e7c:	18bfd92e 	bgeu	r3,r2,4de4 <alt_file_locked+0x2c>
+    }
+  }
+  
+  /* The device is not locked */
+ 
+  return 0;
+    4e80:	0005883a 	mov	r2,zero
+}
+    4e84:	e037883a 	mov	sp,fp
+    4e88:	df000017 	ldw	fp,0(sp)
+    4e8c:	dec00104 	addi	sp,sp,4
+    4e90:	f800283a 	ret
+
+00004e94 <open>:
+ *
+ * ALT_OPEN is mapped onto the open() system call in alt_syscall.h
+ */
+ 
+int ALT_OPEN (const char* file, int flags, int mode)
+{ 
+    4e94:	defff604 	addi	sp,sp,-40
+    4e98:	dfc00915 	stw	ra,36(sp)
+    4e9c:	df000815 	stw	fp,32(sp)
+    4ea0:	df000804 	addi	fp,sp,32
+    4ea4:	e13ffa15 	stw	r4,-24(fp)
+    4ea8:	e17ff915 	stw	r5,-28(fp)
+    4eac:	e1bff815 	stw	r6,-32(fp)
+  alt_dev* dev;
+  alt_fd*  fd;
+  int index  = -1;
+    4eb0:	00bfffc4 	movi	r2,-1
+    4eb4:	e0bffe15 	stw	r2,-8(fp)
+  int status = -ENODEV;
+    4eb8:	00bffb44 	movi	r2,-19
+    4ebc:	e0bffd15 	stw	r2,-12(fp)
+  int isafs = 0;
+    4ec0:	e03ffc15 	stw	zero,-16(fp)
+  /* 
+   * Check the device list, to see if a device with a matching name is 
+   * registered.
+   */
+  
+  if (!(dev = alt_find_dev (file, &alt_dev_list)))
+    4ec4:	d1600604 	addi	r5,gp,-32744
+    4ec8:	e13ffa17 	ldw	r4,-24(fp)
+    4ecc:	00051c40 	call	51c4 <alt_find_dev>
+    4ed0:	e0bfff15 	stw	r2,-4(fp)
+    4ed4:	e0bfff17 	ldw	r2,-4(fp)
+    4ed8:	1000051e 	bne	r2,zero,4ef0 <open+0x5c>
+  {
+    /* No matching device, so try the filesystem list */
+
+    dev   = alt_find_file (file);
+    4edc:	e13ffa17 	ldw	r4,-24(fp)
+    4ee0:	00052540 	call	5254 <alt_find_file>
+    4ee4:	e0bfff15 	stw	r2,-4(fp)
+    isafs = 1;
+    4ee8:	00800044 	movi	r2,1
+    4eec:	e0bffc15 	stw	r2,-16(fp)
+
+  /* 
+   * If a matching device or filesystem is found, allocate a file descriptor. 
+   */
+
+  if (dev)
+    4ef0:	e0bfff17 	ldw	r2,-4(fp)
+    4ef4:	10002c26 	beq	r2,zero,4fa8 <open+0x114>
+  {
+    if ((index = alt_get_fd (dev)) < 0)
+    4ef8:	e13fff17 	ldw	r4,-4(fp)
+    4efc:	000535c0 	call	535c <alt_get_fd>
+    4f00:	e0bffe15 	stw	r2,-8(fp)
+    4f04:	e0bffe17 	ldw	r2,-8(fp)
+    4f08:	1000030e 	bge	r2,zero,4f18 <open+0x84>
+    {
+      status = index;
+    4f0c:	e0bffe17 	ldw	r2,-8(fp)
+    4f10:	e0bffd15 	stw	r2,-12(fp)
+    4f14:	00002606 	br	4fb0 <open+0x11c>
+    }
+    else
+    {
+      fd = &alt_fd_list[index];
+    4f18:	e0fffe17 	ldw	r3,-8(fp)
+    4f1c:	1805883a 	mov	r2,r3
+    4f20:	1085883a 	add	r2,r2,r2
+    4f24:	10c5883a 	add	r2,r2,r3
+    4f28:	100490ba 	slli	r2,r2,2
+    4f2c:	00c00034 	movhi	r3,0
+    4f30:	18d80804 	addi	r3,r3,24608
+    4f34:	10c5883a 	add	r2,r2,r3
+    4f38:	e0bffb15 	stw	r2,-20(fp)
+      fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK);
+    4f3c:	e0fff917 	ldw	r3,-28(fp)
+    4f40:	00900034 	movhi	r2,16384
+    4f44:	10bfffc4 	addi	r2,r2,-1
+    4f48:	1886703a 	and	r3,r3,r2
+    4f4c:	e0bffb17 	ldw	r2,-20(fp)
+    4f50:	10c00215 	stw	r3,8(r2)
+      
+      /* If this is a device, ensure it isn't already locked */
+
+      if (isafs || ((status = alt_file_locked (fd)) >= 0))
+    4f54:	e0bffc17 	ldw	r2,-16(fp)
+    4f58:	1000051e 	bne	r2,zero,4f70 <open+0xdc>
+    4f5c:	e13ffb17 	ldw	r4,-20(fp)
+    4f60:	0004db80 	call	4db8 <alt_file_locked>
+    4f64:	e0bffd15 	stw	r2,-12(fp)
+    4f68:	e0bffd17 	ldw	r2,-12(fp)
+    4f6c:	10001016 	blt	r2,zero,4fb0 <open+0x11c>
+        /* 
+         * If the device or filesystem provides an open() callback function,
+         * call it now to perform any device/filesystem specific operations.
+         */
+    
+        status = (dev->open) ? dev->open(fd, file, flags, mode): 0;
+    4f70:	e0bfff17 	ldw	r2,-4(fp)
+    4f74:	10800317 	ldw	r2,12(r2)
+    4f78:	10000826 	beq	r2,zero,4f9c <open+0x108>
+    4f7c:	e0bfff17 	ldw	r2,-4(fp)
+    4f80:	10800317 	ldw	r2,12(r2)
+    4f84:	e1fff817 	ldw	r7,-32(fp)
+    4f88:	e1bff917 	ldw	r6,-28(fp)
+    4f8c:	e17ffa17 	ldw	r5,-24(fp)
+    4f90:	e13ffb17 	ldw	r4,-20(fp)
+    4f94:	103ee83a 	callr	r2
+    4f98:	00000106 	br	4fa0 <open+0x10c>
+    4f9c:	0005883a 	mov	r2,zero
+    4fa0:	e0bffd15 	stw	r2,-12(fp)
+    4fa4:	00000206 	br	4fb0 <open+0x11c>
+      }
+    }
+  }
+  else
+  {
+    status = -ENODEV;
+    4fa8:	00bffb44 	movi	r2,-19
+    4fac:	e0bffd15 	stw	r2,-12(fp)
+  }
+
+  /* Allocation failed, so clean up and return an error */ 
+
+  if (status < 0)
+    4fb0:	e0bffd17 	ldw	r2,-12(fp)
+    4fb4:	1000090e 	bge	r2,zero,4fdc <open+0x148>
+  {
+    alt_release_fd (index);  
+    4fb8:	e13ffe17 	ldw	r4,-8(fp)
+    4fbc:	00038080 	call	3808 <alt_release_fd>
+    ALT_ERRNO = -status;
+    4fc0:	0004d7c0 	call	4d7c <alt_get_errno>
+    4fc4:	1007883a 	mov	r3,r2
+    4fc8:	e0bffd17 	ldw	r2,-12(fp)
+    4fcc:	0085c83a 	sub	r2,zero,r2
+    4fd0:	18800015 	stw	r2,0(r3)
+    return -1;
+    4fd4:	00bfffc4 	movi	r2,-1
+    4fd8:	00000106 	br	4fe0 <open+0x14c>
+  }
+  
+  /* return the reference upon success */
+
+  return index;
+    4fdc:	e0bffe17 	ldw	r2,-8(fp)
+}
+    4fe0:	e037883a 	mov	sp,fp
+    4fe4:	dfc00117 	ldw	ra,4(sp)
+    4fe8:	df000017 	ldw	fp,0(sp)
+    4fec:	dec00204 	addi	sp,sp,8
+    4ff0:	f800283a 	ret
+
+00004ff4 <alt_alarm_stop>:
+ * alarms. Alternatively an alarm can unregister itself by returning zero when 
+ * the alarm executes.
+ */
+
+void alt_alarm_stop (alt_alarm* alarm)
+{
+    4ff4:	defffa04 	addi	sp,sp,-24
+    4ff8:	df000515 	stw	fp,20(sp)
+    4ffc:	df000504 	addi	fp,sp,20
+    5000:	e13ffb15 	stw	r4,-20(fp)
+  NIOS2_READ_STATUS (context);
+    5004:	0005303a 	rdctl	r2,status
+    5008:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+    500c:	e0fffc17 	ldw	r3,-16(fp)
+    5010:	00bfff84 	movi	r2,-2
+    5014:	1884703a 	and	r2,r3,r2
+    5018:	1001703a 	wrctl	status,r2
+  return context;
+    501c:	e0bffc17 	ldw	r2,-16(fp)
+  alt_irq_context irq_context;
+
+  irq_context = alt_irq_disable_all();
+    5020:	e0bfff15 	stw	r2,-4(fp)
+  alt_llist_remove (&alarm->llist);
+    5024:	e0bffb17 	ldw	r2,-20(fp)
+    5028:	e0bffd15 	stw	r2,-12(fp)
+ * input argument is the element to remove.
+ */
+     
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry)
+{
+  entry->next->previous = entry->previous;
+    502c:	e0bffd17 	ldw	r2,-12(fp)
+    5030:	10800017 	ldw	r2,0(r2)
+    5034:	e0fffd17 	ldw	r3,-12(fp)
+    5038:	18c00117 	ldw	r3,4(r3)
+    503c:	10c00115 	stw	r3,4(r2)
+  entry->previous->next = entry->next;
+    5040:	e0bffd17 	ldw	r2,-12(fp)
+    5044:	10800117 	ldw	r2,4(r2)
+    5048:	e0fffd17 	ldw	r3,-12(fp)
+    504c:	18c00017 	ldw	r3,0(r3)
+    5050:	10c00015 	stw	r3,0(r2)
+  /* 
+   * Set the entry to point to itself, so that any further calls to
+   * alt_llist_remove() are harmless.
+   */
+
+  entry->previous = entry;
+    5054:	e0bffd17 	ldw	r2,-12(fp)
+    5058:	e0fffd17 	ldw	r3,-12(fp)
+    505c:	10c00115 	stw	r3,4(r2)
+  entry->next     = entry;
+    5060:	e0bffd17 	ldw	r2,-12(fp)
+    5064:	e0fffd17 	ldw	r3,-12(fp)
+    5068:	10c00015 	stw	r3,0(r2)
+} 
+    506c:	0001883a 	nop
+    5070:	e0bfff17 	ldw	r2,-4(fp)
+    5074:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+    5078:	e0bffe17 	ldw	r2,-8(fp)
+    507c:	1001703a 	wrctl	status,r2
+}
+    5080:	0001883a 	nop
+  alt_irq_enable_all (irq_context);
+}
+    5084:	0001883a 	nop
+    5088:	e037883a 	mov	sp,fp
+    508c:	df000017 	ldw	fp,0(sp)
+    5090:	dec00104 	addi	sp,sp,4
+    5094:	f800283a 	ret
+
+00005098 <alt_tick>:
+ * 
+ * alt_tick() is expected to run at interrupt level.
+ */
+
+void alt_tick (void)
+{
+    5098:	defffb04 	addi	sp,sp,-20
+    509c:	dfc00415 	stw	ra,16(sp)
+    50a0:	df000315 	stw	fp,12(sp)
+    50a4:	df000304 	addi	fp,sp,12
+  alt_alarm* next;
+  alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next;
+    50a8:	d0a00c17 	ldw	r2,-32720(gp)
+    50ac:	e0bfff15 	stw	r2,-4(fp)
+
+  alt_u32    next_callback;
+
+  /* update the tick counter */
+
+  _alt_nticks++;
+    50b0:	d0a01717 	ldw	r2,-32676(gp)
+    50b4:	10800044 	addi	r2,r2,1
+    50b8:	d0a01715 	stw	r2,-32676(gp)
+
+  /* process the registered callbacks */
+
+  while (alarm != (alt_alarm*) &alt_alarm_list)
+    50bc:	00002e06 	br	5178 <alt_tick+0xe0>
+  {
+    next = (alt_alarm*) alarm->llist.next;
+    50c0:	e0bfff17 	ldw	r2,-4(fp)
+    50c4:	10800017 	ldw	r2,0(r2)
+    50c8:	e0bffe15 	stw	r2,-8(fp)
+    /* 
+     * Upon the tick-counter rolling over it is safe to clear the 
+     * roll-over flag; once the flag is cleared this (or subsequnt)
+     * tick events are enabled to generate an alarm event. 
+     */
+    if ((alarm->rollover) && (_alt_nticks == 0))
+    50cc:	e0bfff17 	ldw	r2,-4(fp)
+    50d0:	10800403 	ldbu	r2,16(r2)
+    50d4:	10803fcc 	andi	r2,r2,255
+    50d8:	10000426 	beq	r2,zero,50ec <alt_tick+0x54>
+    50dc:	d0a01717 	ldw	r2,-32676(gp)
+    50e0:	1000021e 	bne	r2,zero,50ec <alt_tick+0x54>
+    {
+      alarm->rollover = 0;
+    50e4:	e0bfff17 	ldw	r2,-4(fp)
+    50e8:	10000405 	stb	zero,16(r2)
+    }
+    
+    /* if the alarm period has expired, make the callback */    
+    if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0))
+    50ec:	e0bfff17 	ldw	r2,-4(fp)
+    50f0:	10800217 	ldw	r2,8(r2)
+    50f4:	d0e01717 	ldw	r3,-32676(gp)
+    50f8:	18801d36 	bltu	r3,r2,5170 <alt_tick+0xd8>
+    50fc:	e0bfff17 	ldw	r2,-4(fp)
+    5100:	10800403 	ldbu	r2,16(r2)
+    5104:	10803fcc 	andi	r2,r2,255
+    5108:	1000191e 	bne	r2,zero,5170 <alt_tick+0xd8>
+    {
+      next_callback = alarm->callback (alarm->context);
+    510c:	e0bfff17 	ldw	r2,-4(fp)
+    5110:	10800317 	ldw	r2,12(r2)
+    5114:	e0ffff17 	ldw	r3,-4(fp)
+    5118:	18c00517 	ldw	r3,20(r3)
+    511c:	1809883a 	mov	r4,r3
+    5120:	103ee83a 	callr	r2
+    5124:	e0bffd15 	stw	r2,-12(fp)
+
+      /* deactivate the alarm if the return value is zero */
+
+      if (next_callback == 0)
+    5128:	e0bffd17 	ldw	r2,-12(fp)
+    512c:	1000031e 	bne	r2,zero,513c <alt_tick+0xa4>
+      {
+        alt_alarm_stop (alarm);
+    5130:	e13fff17 	ldw	r4,-4(fp)
+    5134:	0004ff40 	call	4ff4 <alt_alarm_stop>
+    5138:	00000d06 	br	5170 <alt_tick+0xd8>
+      }
+      else
+      {
+        alarm->time += next_callback;
+    513c:	e0bfff17 	ldw	r2,-4(fp)
+    5140:	10c00217 	ldw	r3,8(r2)
+    5144:	e0bffd17 	ldw	r2,-12(fp)
+    5148:	1887883a 	add	r3,r3,r2
+    514c:	e0bfff17 	ldw	r2,-4(fp)
+    5150:	10c00215 	stw	r3,8(r2)
+        /* 
+         * If the desired alarm time causes a roll-over, set the rollover
+         * flag. This will prevent the subsequent tick event from causing
+         * an alarm too early.
+         */
+        if(alarm->time < _alt_nticks)
+    5154:	e0bfff17 	ldw	r2,-4(fp)
+    5158:	10c00217 	ldw	r3,8(r2)
+    515c:	d0a01717 	ldw	r2,-32676(gp)
+    5160:	1880032e 	bgeu	r3,r2,5170 <alt_tick+0xd8>
+        {
+          alarm->rollover = 1;
+    5164:	e0bfff17 	ldw	r2,-4(fp)
+    5168:	00c00044 	movi	r3,1
+    516c:	10c00405 	stb	r3,16(r2)
+        }
+      }
+    }
+    alarm = next;
+    5170:	e0bffe17 	ldw	r2,-8(fp)
+    5174:	e0bfff15 	stw	r2,-4(fp)
+  while (alarm != (alt_alarm*) &alt_alarm_list)
+    5178:	e0ffff17 	ldw	r3,-4(fp)
+    517c:	d0a00c04 	addi	r2,gp,-32720
+    5180:	18bfcf1e 	bne	r3,r2,50c0 <alt_tick+0x28>
+
+  /* 
+   * Update the operating system specific timer facilities.
+   */
+
+  ALT_OS_TIME_TICK();
+    5184:	0001883a 	nop
+}
+    5188:	0001883a 	nop
+    518c:	e037883a 	mov	sp,fp
+    5190:	dfc00117 	ldw	ra,4(sp)
+    5194:	df000017 	ldw	fp,0(sp)
+    5198:	dec00204 	addi	sp,sp,8
+    519c:	f800283a 	ret
+
+000051a0 <altera_nios2_gen2_irq_init>:
+/*
+ * To initialize the internal interrupt controller, just clear the IENABLE
+ * register so that all possible IRQs are disabled.
+ */
+void altera_nios2_gen2_irq_init(void) 
+{
+    51a0:	deffff04 	addi	sp,sp,-4
+    51a4:	df000015 	stw	fp,0(sp)
+    51a8:	d839883a 	mov	fp,sp
+    NIOS2_WRITE_IENABLE(0);
+    51ac:	000170fa 	wrctl	ienable,zero
+}
+    51b0:	0001883a 	nop
+    51b4:	e037883a 	mov	sp,fp
+    51b8:	df000017 	ldw	fp,0(sp)
+    51bc:	dec00104 	addi	sp,sp,4
+    51c0:	f800283a 	ret
+
+000051c4 <alt_find_dev>:
+ * "name" must be an exact match for the devices registered name for a match to
+ * be found.
+ */
+ 
+alt_dev* alt_find_dev(const char* name, alt_llist* llist)
+{
+    51c4:	defffa04 	addi	sp,sp,-24
+    51c8:	dfc00515 	stw	ra,20(sp)
+    51cc:	df000415 	stw	fp,16(sp)
+    51d0:	df000404 	addi	fp,sp,16
+    51d4:	e13ffd15 	stw	r4,-12(fp)
+    51d8:	e17ffc15 	stw	r5,-16(fp)
+  alt_dev* next = (alt_dev*) llist->next;
+    51dc:	e0bffc17 	ldw	r2,-16(fp)
+    51e0:	10800017 	ldw	r2,0(r2)
+    51e4:	e0bfff15 	stw	r2,-4(fp)
+  alt_32 len;
+
+  len  = strlen(name) + 1;
+    51e8:	e13ffd17 	ldw	r4,-12(fp)
+    51ec:	00003f80 	call	3f8 <strlen>
+    51f0:	10800044 	addi	r2,r2,1
+    51f4:	e0bffe15 	stw	r2,-8(fp)
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+
+  while (next != (alt_dev*) llist)
+    51f8:	00000d06 	br	5230 <alt_find_dev+0x6c>
+    /* 
+     * memcmp() is used here rather than strcmp() in order to reduce the size
+     * of the executable.
+     */
+
+    if (!memcmp (next->name, name, len))
+    51fc:	e0bfff17 	ldw	r2,-4(fp)
+    5200:	10800217 	ldw	r2,8(r2)
+    5204:	e0fffe17 	ldw	r3,-8(fp)
+    5208:	180d883a 	mov	r6,r3
+    520c:	e17ffd17 	ldw	r5,-12(fp)
+    5210:	1009883a 	mov	r4,r2
+    5214:	00054f40 	call	54f4 <memcmp>
+    5218:	1000021e 	bne	r2,zero,5224 <alt_find_dev+0x60>
+    {
+      /* match found */
+
+      return next;
+    521c:	e0bfff17 	ldw	r2,-4(fp)
+    5220:	00000706 	br	5240 <alt_find_dev+0x7c>
+    }
+    next = (alt_dev*) next->llist.next;
+    5224:	e0bfff17 	ldw	r2,-4(fp)
+    5228:	10800017 	ldw	r2,0(r2)
+    522c:	e0bfff15 	stw	r2,-4(fp)
+  while (next != (alt_dev*) llist)
+    5230:	e0ffff17 	ldw	r3,-4(fp)
+    5234:	e0bffc17 	ldw	r2,-16(fp)
+    5238:	18bff01e 	bne	r3,r2,51fc <alt_find_dev+0x38>
+  }
+  
+  /* No match found */
+  
+  return NULL;
+    523c:	0005883a 	mov	r2,zero
+}
+    5240:	e037883a 	mov	sp,fp
+    5244:	dfc00117 	ldw	ra,4(sp)
+    5248:	df000017 	ldw	fp,0(sp)
+    524c:	dec00204 	addi	sp,sp,8
+    5250:	f800283a 	ret
+
+00005254 <alt_find_file>:
+ * either '/' or '\0' is the prefix of the filename. For example the filename:
+ * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". 
+ */
+ 
+alt_dev* alt_find_file (const char* name)
+{
+    5254:	defffb04 	addi	sp,sp,-20
+    5258:	dfc00415 	stw	ra,16(sp)
+    525c:	df000315 	stw	fp,12(sp)
+    5260:	df000304 	addi	fp,sp,12
+    5264:	e13ffd15 	stw	r4,-12(fp)
+  alt_dev* next = (alt_dev*) alt_fs_list.next;   
+    5268:	d0a00417 	ldw	r2,-32752(gp)
+    526c:	e0bfff15 	stw	r2,-4(fp)
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+ 
+  while (next != (alt_dev*) &alt_fs_list)
+    5270:	00003106 	br	5338 <alt_find_file+0xe4>
+  {
+    len = strlen(next->name);
+    5274:	e0bfff17 	ldw	r2,-4(fp)
+    5278:	10800217 	ldw	r2,8(r2)
+    527c:	1009883a 	mov	r4,r2
+    5280:	00003f80 	call	3f8 <strlen>
+    5284:	e0bffe15 	stw	r2,-8(fp)
+    
+    if (next->name[len-1] == '/')
+    5288:	e0bfff17 	ldw	r2,-4(fp)
+    528c:	10c00217 	ldw	r3,8(r2)
+    5290:	e0bffe17 	ldw	r2,-8(fp)
+    5294:	10bfffc4 	addi	r2,r2,-1
+    5298:	1885883a 	add	r2,r3,r2
+    529c:	10800003 	ldbu	r2,0(r2)
+    52a0:	10803fcc 	andi	r2,r2,255
+    52a4:	1080201c 	xori	r2,r2,128
+    52a8:	10bfe004 	addi	r2,r2,-128
+    52ac:	10800bd8 	cmpnei	r2,r2,47
+    52b0:	1000031e 	bne	r2,zero,52c0 <alt_find_file+0x6c>
+    {
+      len -= 1;
+    52b4:	e0bffe17 	ldw	r2,-8(fp)
+    52b8:	10bfffc4 	addi	r2,r2,-1
+    52bc:	e0bffe15 	stw	r2,-8(fp)
+    }
+
+    if (((name[len] == '/') || (name[len] == '\0')) && 
+    52c0:	e0bffe17 	ldw	r2,-8(fp)
+    52c4:	e0fffd17 	ldw	r3,-12(fp)
+    52c8:	1885883a 	add	r2,r3,r2
+    52cc:	10800003 	ldbu	r2,0(r2)
+    52d0:	10803fcc 	andi	r2,r2,255
+    52d4:	1080201c 	xori	r2,r2,128
+    52d8:	10bfe004 	addi	r2,r2,-128
+    52dc:	10800be0 	cmpeqi	r2,r2,47
+    52e0:	1000081e 	bne	r2,zero,5304 <alt_find_file+0xb0>
+    52e4:	e0bffe17 	ldw	r2,-8(fp)
+    52e8:	e0fffd17 	ldw	r3,-12(fp)
+    52ec:	1885883a 	add	r2,r3,r2
+    52f0:	10800003 	ldbu	r2,0(r2)
+    52f4:	10803fcc 	andi	r2,r2,255
+    52f8:	1080201c 	xori	r2,r2,128
+    52fc:	10bfe004 	addi	r2,r2,-128
+    5300:	10000a1e 	bne	r2,zero,532c <alt_find_file+0xd8>
+        !memcmp (next->name, name, len))
+    5304:	e0bfff17 	ldw	r2,-4(fp)
+    5308:	10800217 	ldw	r2,8(r2)
+    530c:	e0fffe17 	ldw	r3,-8(fp)
+    5310:	180d883a 	mov	r6,r3
+    5314:	e17ffd17 	ldw	r5,-12(fp)
+    5318:	1009883a 	mov	r4,r2
+    531c:	00054f40 	call	54f4 <memcmp>
+    if (((name[len] == '/') || (name[len] == '\0')) && 
+    5320:	1000021e 	bne	r2,zero,532c <alt_find_file+0xd8>
+    {
+      /* match found */
+
+      return next;
+    5324:	e0bfff17 	ldw	r2,-4(fp)
+    5328:	00000706 	br	5348 <alt_find_file+0xf4>
+    }
+    next = (alt_dev*) next->llist.next;
+    532c:	e0bfff17 	ldw	r2,-4(fp)
+    5330:	10800017 	ldw	r2,0(r2)
+    5334:	e0bfff15 	stw	r2,-4(fp)
+  while (next != (alt_dev*) &alt_fs_list)
+    5338:	e0ffff17 	ldw	r3,-4(fp)
+    533c:	d0a00404 	addi	r2,gp,-32752
+    5340:	18bfcc1e 	bne	r3,r2,5274 <alt_find_file+0x20>
+  }
+  
+  /* No match found */
+  
+  return NULL;     
+    5344:	0005883a 	mov	r2,zero
+}
+    5348:	e037883a 	mov	sp,fp
+    534c:	dfc00117 	ldw	ra,4(sp)
+    5350:	df000017 	ldw	fp,0(sp)
+    5354:	dec00204 	addi	sp,sp,8
+    5358:	f800283a 	ret
+
+0000535c <alt_get_fd>:
+ * the offset of the file descriptor within the file descriptor array). A
+ * negative value indicates failure.
+ */
+
+int alt_get_fd (alt_dev* dev)
+{
+    535c:	defffc04 	addi	sp,sp,-16
+    5360:	df000315 	stw	fp,12(sp)
+    5364:	df000304 	addi	fp,sp,12
+    5368:	e13ffd15 	stw	r4,-12(fp)
+  alt_32 i;
+  int rc = -EMFILE;
+    536c:	00bffa04 	movi	r2,-24
+    5370:	e0bffe15 	stw	r2,-8(fp)
+   * indicates the highest file descriptor ever allocated. This is used to
+   * improve efficency when searching the file descriptor list, and 
+   * therefore reduce contention on the alt_fd_list_lock semaphore. 
+   */
+
+  for (i = 0; i < ALT_MAX_FD; i++)
+    5374:	e03fff15 	stw	zero,-4(fp)
+    5378:	00001d06 	br	53f0 <alt_get_fd+0x94>
+  {
+    if (!alt_fd_list[i].dev)
+    537c:	e0ffff17 	ldw	r3,-4(fp)
+    5380:	1805883a 	mov	r2,r3
+    5384:	1085883a 	add	r2,r2,r2
+    5388:	10c5883a 	add	r2,r2,r3
+    538c:	100490ba 	slli	r2,r2,2
+    5390:	00c00034 	movhi	r3,0
+    5394:	10c7883a 	add	r3,r2,r3
+    5398:	18980817 	ldw	r2,24608(r3)
+    539c:	1000111e 	bne	r2,zero,53e4 <alt_get_fd+0x88>
+    {
+      alt_fd_list[i].dev = dev;
+    53a0:	e0ffff17 	ldw	r3,-4(fp)
+    53a4:	1805883a 	mov	r2,r3
+    53a8:	1085883a 	add	r2,r2,r2
+    53ac:	10c5883a 	add	r2,r2,r3
+    53b0:	100490ba 	slli	r2,r2,2
+    53b4:	e13ffd17 	ldw	r4,-12(fp)
+    53b8:	00c00034 	movhi	r3,0
+    53bc:	10c7883a 	add	r3,r2,r3
+    53c0:	19180815 	stw	r4,24608(r3)
+      if (i > alt_max_fd)
+    53c4:	d0e00817 	ldw	r3,-32736(gp)
+    53c8:	e0bfff17 	ldw	r2,-4(fp)
+    53cc:	1880020e 	bge	r3,r2,53d8 <alt_get_fd+0x7c>
+      {
+        alt_max_fd = i;
+    53d0:	e0bfff17 	ldw	r2,-4(fp)
+    53d4:	d0a00815 	stw	r2,-32736(gp)
+      }
+      rc = i;
+    53d8:	e0bfff17 	ldw	r2,-4(fp)
+    53dc:	e0bffe15 	stw	r2,-8(fp)
+      goto alt_get_fd_exit;
+    53e0:	00000706 	br	5400 <alt_get_fd+0xa4>
+  for (i = 0; i < ALT_MAX_FD; i++)
+    53e4:	e0bfff17 	ldw	r2,-4(fp)
+    53e8:	10800044 	addi	r2,r2,1
+    53ec:	e0bfff15 	stw	r2,-4(fp)
+    53f0:	e0bfff17 	ldw	r2,-4(fp)
+    53f4:	10800810 	cmplti	r2,r2,32
+    53f8:	103fe01e 	bne	r2,zero,537c <alt_get_fd+0x20>
+    }
+  }
+
+ alt_get_fd_exit:
+    53fc:	0001883a 	nop
+   * file descriptor pool.
+   */
+
+  ALT_SEM_POST(alt_fd_list_lock);
+
+  return rc;
+    5400:	e0bffe17 	ldw	r2,-8(fp)
+}
+    5404:	e037883a 	mov	sp,fp
+    5408:	df000017 	ldw	fp,0(sp)
+    540c:	dec00104 	addi	sp,sp,4
+    5410:	f800283a 	ret
+
+00005414 <alt_exception_cause_generated_bad_addr>:
+ * Return: 1: BADADDR (bad_addr argument to handler) is valid
+ *         0: BADADDR is not valid
+ */
+int 
+alt_exception_cause_generated_bad_addr(alt_exception_cause cause)
+{
+    5414:	defffe04 	addi	sp,sp,-8
+    5418:	df000115 	stw	fp,4(sp)
+    541c:	df000104 	addi	fp,sp,4
+    5420:	e13fff15 	stw	r4,-4(fp)
+    5424:	e0bfff17 	ldw	r2,-4(fp)
+    5428:	10bffe84 	addi	r2,r2,-6
+    542c:	10c00428 	cmpgeui	r3,r2,16
+    5430:	1800191e 	bne	r3,zero,5498 <alt_exception_cause_generated_bad_addr+0x84>
+    5434:	100690ba 	slli	r3,r2,2
+    5438:	00800034 	movhi	r2,0
+    543c:	1885883a 	add	r2,r3,r2
+    5440:	10951217 	ldw	r2,21576(r2)
+    5444:	1000683a 	jmp	r2
+    5448:	00005488 	cmpgei	zero,zero,338
+    544c:	00005488 	cmpgei	zero,zero,338
+    5450:	00005498 	cmpnei	zero,zero,338
+    5454:	00005498 	cmpnei	zero,zero,338
+    5458:	00005498 	cmpnei	zero,zero,338
+    545c:	00005488 	cmpgei	zero,zero,338
+    5460:	00005490 	cmplti	zero,zero,338
+    5464:	00005498 	cmpnei	zero,zero,338
+    5468:	00005488 	cmpgei	zero,zero,338
+    546c:	00005488 	cmpgei	zero,zero,338
+    5470:	00005498 	cmpnei	zero,zero,338
+    5474:	00005488 	cmpgei	zero,zero,338
+    5478:	00005490 	cmplti	zero,zero,338
+    547c:	00005498 	cmpnei	zero,zero,338
+    5480:	00005498 	cmpnei	zero,zero,338
+    5484:	00005488 	cmpgei	zero,zero,338
+  case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC:
+  case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION:
+  case NIOS2_EXCEPTION_ECC_DATA_ERR:
+    return 1;
+    5488:	00800044 	movi	r2,1
+    548c:	00000306 	br	549c <alt_exception_cause_generated_bad_addr+0x88>
+
+  case NIOS2_EXCEPTION_TLB_MISS:
+  case NIOS2_EXCEPTION_ECC_TLB_ERR:
+    return 0;
+    5490:	0005883a 	mov	r2,zero
+    5494:	00000106 	br	549c <alt_exception_cause_generated_bad_addr+0x88>
+
+  default:
+    return 0;
+    5498:	0005883a 	mov	r2,zero
+  }
+}
+    549c:	e037883a 	mov	sp,fp
+    54a0:	df000017 	ldw	fp,0(sp)
+    54a4:	dec00104 	addi	sp,sp,4
+    54a8:	f800283a 	ret
+
+000054ac <atexit>:
+    54ac:	200b883a 	mov	r5,r4
+    54b0:	000f883a 	mov	r7,zero
+    54b4:	000d883a 	mov	r6,zero
+    54b8:	0009883a 	mov	r4,zero
+    54bc:	000556c1 	jmpi	556c <__register_exitproc>
+
+000054c0 <exit>:
+    54c0:	defffe04 	addi	sp,sp,-8
+    54c4:	000b883a 	mov	r5,zero
+    54c8:	dc000015 	stw	r16,0(sp)
+    54cc:	dfc00115 	stw	ra,4(sp)
+    54d0:	2021883a 	mov	r16,r4
+    54d4:	00055fc0 	call	55fc <__call_exitprocs>
+    54d8:	00800034 	movhi	r2,0
+    54dc:	111c8017 	ldw	r4,29184(r2)
+    54e0:	20800f17 	ldw	r2,60(r4)
+    54e4:	10000126 	beq	r2,zero,54ec <exit+0x2c>
+    54e8:	103ee83a 	callr	r2
+    54ec:	8009883a 	mov	r4,r16
+    54f0:	000571c0 	call	571c <_exit>
+
+000054f4 <memcmp>:
+    54f4:	30800130 	cmpltui	r2,r6,4
+    54f8:	10000b1e 	bne	r2,zero,5528 <memcmp+0x34>
+    54fc:	2144b03a 	or	r2,r4,r5
+    5500:	108000cc 	andi	r2,r2,3
+    5504:	1000171e 	bne	r2,zero,5564 <memcmp+0x70>
+    5508:	20c00017 	ldw	r3,0(r4)
+    550c:	28800017 	ldw	r2,0(r5)
+    5510:	1880141e 	bne	r3,r2,5564 <memcmp+0x70>
+    5514:	31bfff04 	addi	r6,r6,-4
+    5518:	30800128 	cmpgeui	r2,r6,4
+    551c:	21000104 	addi	r4,r4,4
+    5520:	29400104 	addi	r5,r5,4
+    5524:	103ff81e 	bne	r2,zero,5508 <memcmp+0x14>
+    5528:	30bfffc4 	addi	r2,r6,-1
+    552c:	30000b26 	beq	r6,zero,555c <memcmp+0x68>
+    5530:	11800044 	addi	r6,r2,1
+    5534:	218d883a 	add	r6,r4,r6
+    5538:	00000106 	br	5540 <memcmp+0x4c>
+    553c:	21800726 	beq	r4,r6,555c <memcmp+0x68>
+    5540:	20800003 	ldbu	r2,0(r4)
+    5544:	28c00003 	ldbu	r3,0(r5)
+    5548:	21000044 	addi	r4,r4,1
+    554c:	29400044 	addi	r5,r5,1
+    5550:	10fffa26 	beq	r2,r3,553c <memcmp+0x48>
+    5554:	10c5c83a 	sub	r2,r2,r3
+    5558:	f800283a 	ret
+    555c:	0005883a 	mov	r2,zero
+    5560:	f800283a 	ret
+    5564:	30bfffc4 	addi	r2,r6,-1
+    5568:	003ff106 	br	5530 <memcmp+0x3c>
+
+0000556c <__register_exitproc>:
+    556c:	00800034 	movhi	r2,0
+    5570:	10dc8017 	ldw	r3,29184(r2)
+    5574:	18805217 	ldw	r2,328(r3)
+    5578:	10001726 	beq	r2,zero,55d8 <__register_exitproc+0x6c>
+    557c:	10c00117 	ldw	r3,4(r2)
+    5580:	1a000808 	cmpgei	r8,r3,32
+    5584:	40001b1e 	bne	r8,zero,55f4 <__register_exitproc+0x88>
+    5588:	20000b26 	beq	r4,zero,55b8 <__register_exitproc+0x4c>
+    558c:	181090ba 	slli	r8,r3,2
+    5590:	02400044 	movi	r9,1
+    5594:	48d2983a 	sll	r9,r9,r3
+    5598:	1211883a 	add	r8,r2,r8
+    559c:	41802215 	stw	r6,136(r8)
+    55a0:	11806217 	ldw	r6,392(r2)
+    55a4:	21000098 	cmpnei	r4,r4,2
+    55a8:	324cb03a 	or	r6,r6,r9
+    55ac:	11806215 	stw	r6,392(r2)
+    55b0:	41c04215 	stw	r7,264(r8)
+    55b4:	20000b26 	beq	r4,zero,55e4 <__register_exitproc+0x78>
+    55b8:	19000084 	addi	r4,r3,2
+    55bc:	200890ba 	slli	r4,r4,2
+    55c0:	18c00044 	addi	r3,r3,1
+    55c4:	10c00115 	stw	r3,4(r2)
+    55c8:	1105883a 	add	r2,r2,r4
+    55cc:	11400015 	stw	r5,0(r2)
+    55d0:	0005883a 	mov	r2,zero
+    55d4:	f800283a 	ret
+    55d8:	18805304 	addi	r2,r3,332
+    55dc:	18805215 	stw	r2,328(r3)
+    55e0:	003fe606 	br	557c <__register_exitproc+0x10>
+    55e4:	11006317 	ldw	r4,396(r2)
+    55e8:	2252b03a 	or	r9,r4,r9
+    55ec:	12406315 	stw	r9,396(r2)
+    55f0:	003ff106 	br	55b8 <__register_exitproc+0x4c>
+    55f4:	00bfffc4 	movi	r2,-1
+    55f8:	f800283a 	ret
+
+000055fc <__call_exitprocs>:
+    55fc:	defff704 	addi	sp,sp,-36
+    5600:	00800034 	movhi	r2,0
+    5604:	dcc00315 	stw	r19,12(sp)
+    5608:	14dc8017 	ldw	r19,29184(r2)
+    560c:	dc800215 	stw	r18,8(sp)
+    5610:	dfc00815 	stw	ra,32(sp)
+    5614:	9c805217 	ldw	r18,328(r19)
+    5618:	ddc00715 	stw	r23,28(sp)
+    561c:	dd800615 	stw	r22,24(sp)
+    5620:	dd400515 	stw	r21,20(sp)
+    5624:	dd000415 	stw	r20,16(sp)
+    5628:	dc400115 	stw	r17,4(sp)
+    562c:	dc000015 	stw	r16,0(sp)
+    5630:	90001026 	beq	r18,zero,5674 <__call_exitprocs+0x78>
+    5634:	202b883a 	mov	r21,r4
+    5638:	282d883a 	mov	r22,r5
+    563c:	05000044 	movi	r20,1
+    5640:	94000117 	ldw	r16,4(r18)
+    5644:	847fffc4 	addi	r17,r16,-1
+    5648:	88000a16 	blt	r17,zero,5674 <__call_exitprocs+0x78>
+    564c:	84000044 	addi	r16,r16,1
+    5650:	802090ba 	slli	r16,r16,2
+    5654:	9421883a 	add	r16,r18,r16
+    5658:	b0001126 	beq	r22,zero,56a0 <__call_exitprocs+0xa4>
+    565c:	80804017 	ldw	r2,256(r16)
+    5660:	15800f26 	beq	r2,r22,56a0 <__call_exitprocs+0xa4>
+    5664:	8c7fffc4 	addi	r17,r17,-1
+    5668:	88bfffd8 	cmpnei	r2,r17,-1
+    566c:	843fff04 	addi	r16,r16,-4
+    5670:	103ff91e 	bne	r2,zero,5658 <__call_exitprocs+0x5c>
+    5674:	dfc00817 	ldw	ra,32(sp)
+    5678:	ddc00717 	ldw	r23,28(sp)
+    567c:	dd800617 	ldw	r22,24(sp)
+    5680:	dd400517 	ldw	r21,20(sp)
+    5684:	dd000417 	ldw	r20,16(sp)
+    5688:	dcc00317 	ldw	r19,12(sp)
+    568c:	dc800217 	ldw	r18,8(sp)
+    5690:	dc400117 	ldw	r17,4(sp)
+    5694:	dc000017 	ldw	r16,0(sp)
+    5698:	dec00904 	addi	sp,sp,36
+    569c:	f800283a 	ret
+    56a0:	90800117 	ldw	r2,4(r18)
+    56a4:	81800017 	ldw	r6,0(r16)
+    56a8:	10bfffc4 	addi	r2,r2,-1
+    56ac:	14401726 	beq	r2,r17,570c <__call_exitprocs+0x110>
+    56b0:	80000015 	stw	zero,0(r16)
+    56b4:	303feb26 	beq	r6,zero,5664 <__call_exitprocs+0x68>
+    56b8:	a446983a 	sll	r3,r20,r17
+    56bc:	90806217 	ldw	r2,392(r18)
+    56c0:	95c00117 	ldw	r23,4(r18)
+    56c4:	1884703a 	and	r2,r3,r2
+    56c8:	1000081e 	bne	r2,zero,56ec <__call_exitprocs+0xf0>
+    56cc:	303ee83a 	callr	r6
+    56d0:	90c00117 	ldw	r3,4(r18)
+    56d4:	98805217 	ldw	r2,328(r19)
+    56d8:	1dc0011e 	bne	r3,r23,56e0 <__call_exitprocs+0xe4>
+    56dc:	90bfe126 	beq	r18,r2,5664 <__call_exitprocs+0x68>
+    56e0:	103fe426 	beq	r2,zero,5674 <__call_exitprocs+0x78>
+    56e4:	1025883a 	mov	r18,r2
+    56e8:	003fd506 	br	5640 <__call_exitprocs+0x44>
+    56ec:	90806317 	ldw	r2,396(r18)
+    56f0:	81002017 	ldw	r4,128(r16)
+    56f4:	1886703a 	and	r3,r3,r2
+    56f8:	1800061e 	bne	r3,zero,5714 <__call_exitprocs+0x118>
+    56fc:	200b883a 	mov	r5,r4
+    5700:	a809883a 	mov	r4,r21
+    5704:	303ee83a 	callr	r6
+    5708:	003ff106 	br	56d0 <__call_exitprocs+0xd4>
+    570c:	94400115 	stw	r17,4(r18)
+    5710:	003fe806 	br	56b4 <__call_exitprocs+0xb8>
+    5714:	303ee83a 	callr	r6
+    5718:	003fed06 	br	56d0 <__call_exitprocs+0xd4>
+
+0000571c <_exit>:
+ *
+ * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h
+ */
+
+void ALT_EXIT (int exit_code)
+{
+    571c:	defffd04 	addi	sp,sp,-12
+    5720:	df000215 	stw	fp,8(sp)
+    5724:	df000204 	addi	fp,sp,8
+    5728:	e13ffe15 	stw	r4,-8(fp)
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n");
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code);
+  /* Stop all other threads */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n");
+  ALT_OS_STOP();
+    572c:	0001883a 	nop
+    5730:	e0bffe17 	ldw	r2,-8(fp)
+    5734:	e0bfff15 	stw	r2,-4(fp)
+/*
+ * Routine called on exit.
+ */
+static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code)
+{
+  register int r2 asm ("r2") = exit_code;
+    5738:	e0bfff17 	ldw	r2,-4(fp)
+  __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */
+
+  __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA );
+
+#else /* !DEBUG_STUB */
+  if (r2) {
+    573c:	10000226 	beq	r2,zero,5748 <_exit+0x2c>
+    ALT_SIM_FAIL();
+    5740:	002af070 	cmpltui	zero,zero,43969
+  } else {
+    ALT_SIM_PASS();
+  }
+#endif /* DEBUG_STUB */
+}
+    5744:	00000106 	br	574c <_exit+0x30>
+    ALT_SIM_PASS();
+    5748:	002af0b0 	cmpltui	zero,zero,43970
+}
+    574c:	0001883a 	nop
+  ALT_SIM_HALT(exit_code);
+
+  /* spin forever, since there's no where to go back to */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n");
+  while (1);
+    5750:	003fff06 	br	5750 <_exit+0x34>
diff --git a/Top/software/semafor/transcript b/Top/software/semafor/transcript
index 168b708..f205801 100644
--- a/Top/software/semafor/transcript
+++ b/Top/software/semafor/transcript
@@ -1,8 +1,8 @@
-# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
-# vsim -gui null_sim.mpf 
-# Start time: 01:19:59 on Dec 24,2022
-# ** Error (suppressible): (vsim-19) Failed to access library 'null_sim' at "null_sim".
-# No such file or directory. (errno = ENOENT)
-# Error loading design
-# End time: 01:19:59 on Dec 24,2022, Elapsed time: 0:00:00
-# Errors: 1, Warnings: 0
+# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
+# vsim -gui null_sim.mpf 
+# Start time: 01:19:59 on Dec 24,2022
+# ** Error (suppressible): (vsim-19) Failed to access library 'null_sim' at "null_sim".
+# No such file or directory. (errno = ENOENT)
+# Error loading design
+# End time: 01:19:59 on Dec 24,2022, Elapsed time: 0:00:00
+# Errors: 1, Warnings: 0
diff --git a/Top/software/semafor_bsp/.cproject b/Top/software/semafor_bsp/.cproject
index 57d4df5..d1707c8 100644
--- a/Top/software/semafor_bsp/.cproject
+++ b/Top/software/semafor_bsp/.cproject
@@ -1,56 +1,56 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
-			<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings"/>
-		</buildSystem>
-		<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
-					<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529." name="/" resourcePath="">
-						<toolChain id="altera.nios2.mingw.gcc4.1075875993" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
-							<targetPlatform id="altera.nios2.mingw.gcc4.199526272" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
-							<builder buildPath="${workspace_loc://semafor_bsp}" id="altera.tool.gnu.builder.mingw.739389354" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
-							<tool id="altera.tool.gnu.c.compiler.mingw.1217641548" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2069582818" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
-							</tool>
-							<tool id="altera.tool.gnu.cpp.compiler.mingw.1496541669" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
-							</tool>
-							<tool id="altera.tool.gnu.archiver.mingw.2037617920" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
-							<tool id="altera.tool.gnu.c.linker.mingw.1007181127" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
-							<tool id="altera.tool.gnu.assembler.mingw.1082928765" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
-								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.2052885548" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
-							</tool>
-						</toolChain>
-					</folderInfo>
-				</configuration>
-			</storageModule>
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="semafor_bsp.null.1473022277" name="semafor_bsp"/>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="scannerConfiguration">
-		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.cpp.compiler.mingw.1496541669;cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.c.compiler.mingw.1217641548;cdt.managedbuild.tool.gnu.c.compiler.input.2069582818">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-	</storageModule>
-</cproject>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
+			<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings"/>
+		</buildSystem>
+		<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529." name="/" resourcePath="">
+						<toolChain id="altera.nios2.mingw.gcc4.1075875993" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
+							<targetPlatform id="altera.nios2.mingw.gcc4.199526272" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
+							<builder buildPath="${workspace_loc://semafor_bsp}" id="altera.tool.gnu.builder.mingw.739389354" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
+							<tool id="altera.tool.gnu.c.compiler.mingw.1217641548" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2069582818" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.cpp.compiler.mingw.1496541669" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.archiver.mingw.2037617920" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
+							<tool id="altera.tool.gnu.c.linker.mingw.1007181127" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
+							<tool id="altera.tool.gnu.assembler.mingw.1082928765" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.2052885548" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="semafor_bsp.null.1473022277" name="semafor_bsp"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.cpp.compiler.mingw.1496541669;cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.c.compiler.mingw.1217641548;cdt.managedbuild.tool.gnu.c.compiler.input.2069582818">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/Top/software/semafor_bsp/.project b/Top/software/semafor_bsp/.project
index 8a3a489..c628f29 100644
--- a/Top/software/semafor_bsp/.project
+++ b/Top/software/semafor_bsp/.project
@@ -1,29 +1,29 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>semafor_bsp</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.cdt.core.ccnature</nature>
-		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
-		<nature>com.altera.sbtgui.project.SBTGUIBspNature</nature>
-	</natures>
-</projectDescription>
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>semafor_bsp</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIBspNature</nature>
+	</natures>
+</projectDescription>
diff --git a/Top/software/semafor_bsp/.settings/language.settings.xml b/Top/software/semafor_bsp/.settings/language.settings.xml
index 8c49b53..a7d17d7 100644
--- a/Top/software/semafor_bsp/.settings/language.settings.xml
+++ b/Top/software/semafor_bsp/.settings/language.settings.xml
@@ -2,13 +2,12 @@
 <project>
 	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1220411458136844691" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
 		</extension>
 	</configuration>
diff --git a/Top/software/semafor_bsp/Makefile b/Top/software/semafor_bsp/Makefile
index ff47f19..e1b3809 100644
--- a/Top/software/semafor_bsp/Makefile
+++ b/Top/software/semafor_bsp/Makefile
@@ -19,27 +19,27 @@ SPACE := $(empty) $(empty)
 
 #------------------------------------------------------------------------------
 #                         The adjust-path macro
-# 
-# If COMSPEC is defined, Make is launched from Windows through
-# Cygwin.  This adjust-path macro will call 'cygpath -u' on all
-# paths to ensure they are readable by Make.
 #
-# If COMSPEC is not defined, Make is launched from *nix, and no adjustment
-# is necessary
+# If Make is launched from Windows through
+# Windows Subsystem for Linux (WSL).  The adjust-path macro converts absolute windows 
+# paths into unix style paths (Example: c:/dir -> /c/dir). 
+# The adjust_path_mixed function converts WSL path to Windows path.
+# This will ensure paths are readable by GNU Make.
 #------------------------------------------------------------------------------
 
-ifndef COMSPEC
-ifdef ComSpec
-COMSPEC = $(ComSpec)
-endif # ComSpec
-endif # !COMSPEC
+UNAME = $(shell uname -r)
+ifeq ($(findstring Microsoft,$(UNAME)),Microsoft)
+	WINDOWS_EXE = .exe
+endif
 
-ifdef COMSPEC
-	adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1"))
-	adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1"))
-else
-	adjust-path = $(subst $(SPACE),\$(SPACE),$1)
-	adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1)
+eq = $(and $(findstring $(1),$(2)),$(findstring $(2),$(1)))
+
+ifdef WINDOWS_EXE 
+	adjust-path = $(if $1,$(shell wslpath "$1"),)
+	adjust-path-mixed = $(if $(call eq,$(shell echo $1 | head -c 5),/mnt/),$(shell echo $1 | sed 's/\/mnt\///g;s/\//:\//1'),$1)
+else # !WINDOWS_EXE
+	adjust-path = $1
+	adjust-path-mixed = $1
 endif
 
 #------------------------------------------------------------------------------
@@ -62,7 +62,7 @@ all:
 BSP_ROOT_DIR := .
 
 # Define absolute path to the root of the BSP.
-ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd))
+ABS_BSP_ROOT := $(shell pwd)
 
 # Stash all BSP object files here
 OBJ_DIR := ./obj
@@ -93,12 +93,12 @@ OBJ_DIR := ./obj
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 18.1
-ACDS_VERSION := 18.1
+# ACDS_VERSION: 20.1
+ACDS_VERSION := 20.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 625
+# BUILD_NUMBER: 720
 
 SETTINGS_FILE := settings.bsp
 SOPC_FILE := ../../niosII.sopcinfo
@@ -112,10 +112,10 @@ SOPC_FILE := ../../niosII.sopcinfo
 #-------------------------------------------------------------------------------
 
 # Archiver command. Creates library files. 
-AR = nios2-elf-ar
+AR = nios2-elf-ar$(WINDOWS_EXE)
 
 # Assembler command. Note that CC is used for .S files. 
-AS = nios2-elf-gcc
+AS = nios2-elf-gcc$(WINDOWS_EXE)
 
 # Custom flags only passed to the archiver. This content of this variable is 
 # directly passed to the archiver rather than the more standard "ARFLAGS". The 
@@ -145,10 +145,10 @@ BSP_CFLAGS_OPTIMIZATION = -O0
 BSP_CFLAGS_WARNINGS = -Wall
 
 # C compiler command. 
-CC = nios2-elf-gcc -xc
+CC = nios2-elf-gcc$(WINDOWS_EXE) -xc
 
 # C++ compiler command. 
-CXX = nios2-elf-gcc -xc++
+CXX = nios2-elf-gcc$(WINDOWS_EXE) -xc++
 
 # Command used to remove files during 'clean' target. 
 RM = rm -f
@@ -516,13 +516,13 @@ build_post_process :
 # Skip this check when clean is the only target
 ifneq ($(MAKECMDGOALS),clean)
 
-ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE))
+ifneq ($(wildcard $(call adjust-path,$(SETTINGS_FILE))),$(call adjust-path,$(SETTINGS_FILE)))
 $(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.)
 endif
 
-Makefile: $(wildcard $(SETTINGS_FILE))
+Makefile: $(wildcard $(call adjust-path,$(SETTINGS_FILE)))
 	@$(ECHO) Makefile not up to date.
-	@$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
+	@$(ECHO) $(call adjust-path,$(SETTINGS_FILE)) has been modified since the BSP Makefile was generated.
 	@$(ECHO)
 	@$(ECHO) Generate the BSP to update the Makefile, and then build again.
 	@$(ECHO)
@@ -535,13 +535,13 @@ Makefile: $(wildcard $(SETTINGS_FILE))
 	@$(ECHO)
 	@exit 1
 
-ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE))
+ifneq ($(wildcard $(call adjust-path,$(SOPC_FILE))),$(call adjust-path,$(SOPC_FILE)))
 $(warning Warning: SOPC File $(SOPC_FILE) could not be found.)
 endif
 
-public.mk: $(wildcard $(SOPC_FILE))
+public.mk: $(wildcard $(call adjust-path,$(SOPC_FILE)))
 	@$(ECHO) Makefile not up to date.
-	@$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
+	@$(ECHO) $(call adjust-path,$(SOPC_FILE)) has been modified since the BSP was generated.
 	@$(ECHO)
 	@$(ECHO) Generate the BSP to update the Makefile, and then build again.
 	@$(ECHO)
diff --git a/Top/software/semafor_bsp/create-this-bsp b/Top/software/semafor_bsp/create-this-bsp
index b6c0227..5cee54f 100644
--- a/Top/software/semafor_bsp/create-this-bsp
+++ b/Top/software/semafor_bsp/create-this-bsp
@@ -1,52 +1,52 @@
-#!/bin/bash
-#
-# This script creates the ucosii_net_zipfs Board Support Package (BSP).
-
-BSP_TYPE=hal
-BSP_DIR=.
-SOPC_DIR=../../
-SOPC_FILE=../../niosII.sopcinfo
-NIOS2_BSP_ARGS=""
-CPU_NAME=
-
-if [ -n "$CPU_NAME" ]; then
-  NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME"
-fi
-
-# Don't run make if create-this-app script is called with --no-make arg
-SKIP_MAKE=
-while [ $# -gt 0 ]
-do
-  case "$1" in
-		--no-make)
-        	SKIP_MAKE=1
-        	;;
-		*)
-			NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1"
-			;;
-  esac
-  shift
-done
-
-
-# Run nios2-bsp utility to create a hal BSP in this directory
-# for the system with a .sopc file in $SOPC_FILE.
-# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist.
-
-if [ -z "$SOPC_FILE" ]; then
-	echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path."
-	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS"
-else
-	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS"
-fi
-
-
-echo "create-this-bsp: Running \"$cmd\""
-$cmd || {
-    echo "$cmd failed"
-    exit 1
-}
-if [ -z "$SKIP_MAKE" ]; then
-	echo "create-this-bsp: Running make"
-	make
-fi
+#!/bin/bash
+#
+# This script creates the ucosii_net_zipfs Board Support Package (BSP).
+
+BSP_TYPE=hal
+BSP_DIR=.
+SOPC_DIR=../../
+SOPC_FILE=../../niosII.sopcinfo
+NIOS2_BSP_ARGS=""
+CPU_NAME=
+
+if [ -n "$CPU_NAME" ]; then
+  NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME"
+fi
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+  case "$1" in
+		--no-make)
+        	SKIP_MAKE=1
+        	;;
+		*)
+			NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1"
+			;;
+  esac
+  shift
+done
+
+
+# Run nios2-bsp utility to create a hal BSP in this directory
+# for the system with a .sopc file in $SOPC_FILE.
+# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist.
+
+if [ -z "$SOPC_FILE" ]; then
+	echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path."
+	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS"
+else
+	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS"
+fi
+
+
+echo "create-this-bsp: Running \"$cmd\""
+$cmd || {
+    echo "$cmd failed"
+    exit 1
+}
+if [ -z "$SKIP_MAKE" ]; then
+	echo "create-this-bsp: Running make"
+	make
+fi
diff --git a/Top/software/semafor_bsp/libhal_bsp.a b/Top/software/semafor_bsp/libhal_bsp.a
index 63131b7..a9a79e9 100644
Binary files a/Top/software/semafor_bsp/libhal_bsp.a and b/Top/software/semafor_bsp/libhal_bsp.a differ
diff --git a/Top/software/semafor_bsp/mem_init.mk b/Top/software/semafor_bsp/mem_init.mk
index 32d8d72..133f943 100644
--- a/Top/software/semafor_bsp/mem_init.mk
+++ b/Top/software/semafor_bsp/mem_init.mk
@@ -22,6 +22,32 @@
 #
 #########################################################################
 
+#------------------------------------------------------------------------------
+#                         The adjust-path macro
+#
+# If Make is launched from Windows through
+# Windows Subsystem for Linux (WSL).  The adjust-path macro converts absolute windows 
+# paths into unix style paths (Example: c:/dir -> /c/dir). 
+# The adjust_path_mixed function converts WSL path to Windows path.
+# This will ensure paths are readable by GNU Make.
+#------------------------------------------------------------------------------
+
+UNAME = $(shell uname -r)
+ifeq ($(findstring Microsoft,$(UNAME)),Microsoft)
+	WINDOWS_EXE = .exe
+endif
+
+eq = $(and $(findstring $(1),$(2)),$(findstring $(2),$(1)))
+
+ifdef WINDOWS_EXE 
+	adjust-path = $(if $1,$(shell wslpath "$1"),)
+	adjust-path-mixed = $(if $(call eq,$(shell echo $1 | head -c 5),/mnt/),$(shell echo $1 | sed 's/\/mnt\///g;s/\//:\//1'),$1)
+else # !WINDOWS_EXE
+	adjust-path = $1
+	adjust-path-mixed = $1
+endif
+
+
 ifeq ($(MEM_INIT_FILE),)
 # MEM_INIT_FILE should be set equal to the working relative path to this
 # mem_init.mk makefile fragment
@@ -33,11 +59,11 @@ ELF2DAT := elf2dat
 endif
 
 ifeq ($(ELF2HEX),)
-ELF2HEX := elf2hex
+ELF2HEX := elf2hex$(WINDOWS_EXE)
 endif
 
 ifeq ($(ELF2FLASH),)
-ELF2FLASH := elf2flash
+ELF2FLASH := elf2flash$(WINDOWS_EXE)
 endif
 
 ifeq ($(FLASH2DAT),)
@@ -45,11 +71,11 @@ FLASH2DAT := flash2dat
 endif
 
 ifeq ($(ALT_FILE_CONVERT),)
-ALT_FILE_CONVERT := alt-file-convert
+ALT_FILE_CONVERT := alt-file-convert$(WINDOWS_EXE)
 endif
 
 ifeq ($(NM),)
-NM := nios2-elf-nm
+NM := nios2-elf-nm$(WINDOWS_EXE)
 endif
 
 ifeq ($(MKDIR),)
@@ -87,9 +113,16 @@ MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip
 #-------------------------------------
 
 BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2
-BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec
-BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec
+BOOT_LOADER_CFI_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec
+BOOT_LOADER_CFI_BE_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec
 
+ifdef WINDOWS_EXE
+	BOOT_LOADER_CFI=$(shell wslpath -w $(BOOT_LOADER_CFI_LOC))
+	BOOT_LOADER_CFI_BE=$(shell wslpath -w $(BOOT_LOADER_CFI_BE_LOC))
+else # !WINDOWS_EXE
+	BOOT_LOADER_CFI=$(BOOT_LOADER_CFI_LOC)
+	BOOT_LOADER_CFI_BE=$(BOOT_LOADER_CFI_BE_LOC)
+endif
 
 #-------------------------------------
 # Default Target
@@ -150,15 +183,15 @@ flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 18.1
-ACDS_VERSION := 18.1
+# ACDS_VERSION: 20.1
+ACDS_VERSION := 20.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 625
+# BUILD_NUMBER: 720
 
 # Optimize for simulation
-SIM_OPTIMIZE ?= 1
+SIM_OPTIMIZE ?= 0
 
 # The CPU reset address as needed by elf2flash
 RESET_ADDRESS ?= 0x00000000
@@ -259,25 +292,25 @@ flash: check_elf_exists $(FLASH_FILES)
 #-------------------------------------
 
 .PHONY: check_elf_exists
-check_elf_exists: $(ELF)
+check_elf_exists: $(call adjust-path,$(ELF))
 ifeq ($(ELF),)
 	$(error ELF var not set in mem_init.mk)
 endif
 
-$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF)
+$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(call adjust-path,$(ELF))
 	$(post-process-info)
 	@$(MKDIR) $(@D)
-	$(ELF2DAT) --infile=$< --outfile=$@ \
+	$(ELF2DAT) --infile=$(call adjust-path-mixed,$<) --outfile=$@ \
 		--base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \
 		$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)
 
 $(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat
 	@true
 
-ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \
+ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $(call adjust-path-mixed,$<) $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \
 			$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@
 			
-ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$< --output=$@ \
+ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$(call adjust-path-mixed,$<) --output=$@ \
 			--base=$(mem_start_address) --end=$(mem_end_address) --reset=$(RESET_ADDRESS) \
 			--out-data-width=$(mem_hex_width) $(flash_mem_boot_loader_flag)
 
@@ -286,21 +319,20 @@ ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
 	$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
 	))
 
-$(HEX_FILES): %.hex: $(ELF)
+$(HEX_FILES): %.hex: $(call adjust-path,$(ELF))
 	$(post-process-info)
 	@$(MKDIR) $(@D)
 	$(ELF_TO_HEX_CMD)
 
-$(SYM_FILES): %.sym: $(ELF)
+$(SYM_FILES): %.sym: $(call adjust-path,$(ELF))
 	$(post-process-info)
 	@$(MKDIR) $(@D)
-	$(NM) -n $< > $@
+	$(NM) -n $(call adjust-path-mixed,$<) > $@
 
-$(FLASH_FILES): %.flash: $(ELF)
+$(FLASH_FILES): %.flash: $(call adjust-path,$(ELF))
 	$(post-process-info)
 	@$(MKDIR) $(@D)
-	$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \
-		$(elf2flash_extra_args)
+	$(ELF2FLASH) --input=$(call adjust-path-mixed,$<) --output=$@ --sim_optimize=$(SIM_OPTIMIZE) $(elf2flash_extra_args)
 
 #
 # Function generate_spd_entry
diff --git a/Top/software/semafor_bsp/public.mk b/Top/software/semafor_bsp/public.mk
index c72f769..dedc3d1 100644
--- a/Top/software/semafor_bsp/public.mk
+++ b/Top/software/semafor_bsp/public.mk
@@ -77,12 +77,12 @@ ALT_CPPFLAGS += -pipe
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 18.1
-ACDS_VERSION := 18.1
+# ACDS_VERSION: 20.1
+ACDS_VERSION := 20.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 625
+# BUILD_NUMBER: 720
 
 # Qsys--generated SOPCINFO file. Required for resolving node instance ID's with 
 # design component names. 
@@ -221,8 +221,7 @@ ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION
 # loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When 
 # this setting is true, the BSP shouldn't be used to build applications that 
 # are expected to run real hardware. 
-# setting hal.enable_sim_optimize is true
-ALT_CPPFLAGS += -DALT_SIM_OPTIMIZE
+# setting hal.enable_sim_optimize is false
 
 # Causes the small newlib (C library) to be used. This reduces code and data 
 # footprint at the expense of reduced functionality. Several newlib features 
diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp
index ac01443..2fbba99 100644
--- a/Top/software/semafor_bsp/settings.bsp
+++ b/Top/software/semafor_bsp/settings.bsp
@@ -2,11 +2,11 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>24.12.2022 2:19:40</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1671833980256</BspGeneratedUnixTimeStamp>
-        <BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
+        <BspGeneratedTimeStamp>Jan 24, 2023 12:06:33 PM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1674551193679</BspGeneratedUnixTimeStamp>
+        <BspGeneratedLocation>/run/media/user/B225-3235/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
-        <SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
+        <SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>
         <JdiFile>default</JdiFile>
         <Cpu>cpu</Cpu>
         <SchemaVersion>1.9</SchemaVersion>
@@ -830,7 +830,7 @@
                 <SettingName>hal.enable_sim_optimize</SettingName>
                 <Identifier>ALT_SIM_OPTIMIZE</Identifier>
                 <Type>Boolean</Type>
-                <Value>1</Value>
+                <Value>0</Value>
                 <DefaultValue>0</DefaultValue>
                 <DestinationFile>public_mk_define</DestinationFile>
                 <Description>The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.</Description>
diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html
index 6387456..e9d5f2c 100644
--- a/Top/software/semafor_bsp/summary.html
+++ b/Top/software/semafor_bsp/summary.html
@@ -7,7 +7,7 @@
 <td width="20%" bgcolor="#77BBFF">BSP Type:</td><td>hal</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>..\..\niosII.sopcinfo</td>
+<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>../../niosII.sopcinfo</td>
 </tr>
 <tr mode="wrap">
 <td width="20%" bgcolor="#77BBFF">Quartus JDI File:</td><td>default</td>
@@ -22,13 +22,13 @@
 <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.12.2022 2:19:40</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Jan 24, 2023 12:06:33 PM</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671833980256</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1674551193679</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/run/media/user/B225-3235/Lab2/Top/software/semafor_bsp</td>
 </tr>
 </table>
 <br>
@@ -423,7 +423,7 @@
 <td width="20%">Default Value:</td><td>0</td>
 </tr>
 <tr>
-<td width="20%">Value:</td><td>1</td>
+<td width="20%">Value:</td><td>0</td>
 </tr>
 <tr>
 <td width="20%">Type:</td><td>Boolean</td>
diff --git a/Top/top.sv b/Top/top.sv
new file mode 100644
index 0000000..fde5a5b
--- /dev/null
+++ b/Top/top.sv
@@ -0,0 +1,20 @@
+module top
+(
+	input logic clk,
+	input logic train,
+	output logic green,
+	output logic red,
+	output logic yellow
+);
+ 
+  niosII u0 (
+        .clk_clk           (clk),           //        clk.clk
+        .reset_reset_n     (1'b1),     //      reset.reset_n
+        .sem_export_train  (~train),  // sem_export.train
+        .sem_export_red    (red),    //           .red
+        .sem_export_yellow (yellow), //           .yellow
+        .sem_export_green  (green)   //           .green
+    );
+
+	 
+endmodule 
\ No newline at end of file