diff --git a/HDL/sdmod.sv b/HDL/sdmod.sv
index 60fdb70..4349509 100644
--- a/HDL/sdmod.sv
+++ b/HDL/sdmod.sv
@@ -7,17 +7,17 @@ module sdmod (
 
 logic out;
 logic signed [7:0] eps;
-logic signed [7:0] un;
+logic signed [8:0] un;
 
 always_ff @(posedge clk, negedge reset) begin
 	if (~reset) begin
-		un <= 8'd0;
+		un <= 9'd0;
 	end else begin		
 		un <= val - eps;
 	end
 end
 
-assign out  = (un >= $signed(8'd0)) ? 1'd1                 : 1'd0;
-assign eps  = (un >= $signed(8'd0)) ? $signed(8'd126) - un : $signed(-8'd126) - un;
+assign out  = (un >= $signed(9'd0)) ? 1'd1                 : 1'd0;
+assign eps  = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
 assign daco = out;
 endmodule
diff --git a/HDL/sigdel.sv b/HDL/sigdel.sv
index 5acf7e3..0571985 100644
--- a/HDL/sigdel.sv
+++ b/HDL/sigdel.sv
@@ -1,7 +1,7 @@
 //top-level module
 module sigdel
 #(
-    PHACC_WIDTH = 14
+    PHACC_WIDTH = 27
 ) (
 	//clock and reset
 	input logic clk, clr_n,
@@ -24,7 +24,7 @@ module sigdel
 		end
 	end
 
-	phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
+	phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
 	defparam phacc_inst.WIDTH = PHACC_WIDTH;
 	
 	sinelut sinelut_inst (
diff --git a/Testbench/sigdel/sigdel.qsf b/Testbench/sigdel/sigdel.qsf
index 7a6d160..e322d06 100644
--- a/Testbench/sigdel/sigdel.qsf
+++ b/Testbench/sigdel/sigdel.qsf
@@ -37,16 +37,15 @@
 
 
 set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE6E22A7
+set_global_assignment -name DEVICE EP4CE15F23C8
 set_global_assignment -name TOP_LEVEL_ENTITY sigdel
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23  JANUARY 27, 2023"
 set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
@@ -74,4 +73,7 @@ set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simula
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
 set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
+set_location_assignment PIN_T2 -to clk
+set_location_assignment PIN_E4 -to clr_n
+set_location_assignment PIN_E3 -to fout
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Testbench/sigdel/sigdel.qws b/Testbench/sigdel/sigdel.qws
index 51e4133..2bf3548 100644
Binary files a/Testbench/sigdel/sigdel.qws and b/Testbench/sigdel/sigdel.qws differ
diff --git a/Top/niosII.qsys b/Top/niosII.qsys
index e6b84d0..57f7a41 100644
--- a/Top/niosII.qsys
+++ b/Top/niosII.qsys
@@ -105,6 +105,14 @@
          type = "String";
       }
    }
+   element niosII
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone IV E";
+         type = "String";
+      }
+   }
    element sigdel_0
    {
       datum _sortIndex
@@ -401,7 +409,7 @@
   <parameter name="writable" value="true" />
  </module>
  <module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
-  <parameter name="PHACC_WIDTH" value="14" />
+  <parameter name="PHACC_WIDTH" value="26" />
  </module>
  <module
    name="sys_clk_timer"
diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo
index 29ac151..53d6461 100644
--- a/Top/niosII.sopcinfo
+++ b/Top/niosII.sopcinfo
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2023.02.07.13:18:47 -->
+ <!-- 2023.02.07.17:03:00 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1675761526</value>
+  <value>1675774980</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -5649,7 +5649,7 @@ parameters are a RESULT of the module parameters. -->
 the requested settings for a module instance. -->
   <parameter name="PHACC_WIDTH">
    <type>int</type>
-   <value>14</value>
+   <value>26</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html
index ab6189e..5d25fbe 100644
--- a/Top/niosII/niosII.html
+++ b/Top/niosII/niosII.html
@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2023.02.07.13:18:47</td>
+    <td class="l">2023.02.07.17:03:00</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -1800,7 +1800,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <table>
        <tr>
         <td class="parametername">PHACC_WIDTH</td>
-        <td class="parametervalue">14</td>
+        <td class="parametervalue">26</td>
        </tr>
        <tr>
         <td class="parametername">deviceFamily</td>
@@ -2018,7 +2018,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.02 seconds</td>
+    <td class="r">rendering took 0.03 seconds</td>
    </tr>
   </table>
  </body>
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml
index 43d38a6..b9dbb0f 100644
--- a/Top/niosII/niosII.xml
+++ b/Top/niosII/niosII.xml
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <deploy
- date="2023.02.07.13:18:51"
+ date="2023.02.07.17:03:05"
  outputDirectory="/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/niosII/">
  <perimeter>
   <parameter
@@ -74,13 +74,13 @@
  </perimeter>
  <entity
    path=""
-   parameterizationKey="niosII:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1675761526,AUTO_UNIQUE_ID=(clock_source:18.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_nios2_gen2:18.1:AUTO_CLK_CLOCK_DOMAIN=1,AUTO_CLK_RESET_DOMAIN=1,AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_SPEEDGRADE=8,bht_ramBlockType=Automatic,breakAbsoluteAddr=34848,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=16,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x9000&apos; end=&apos;0x9020&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x9020&apos; end=&apos;0x9028&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;slave name=&apos;sigdel_0.avalon_slave&apos; start=&apos;0x9028&apos; end=&apos;0x902C&apos; type=&apos;sigdel.avalon_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=32,exceptionOffset=32,exceptionSlave=mem.s1,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=4096,icache_tagramBlockType=Automatic,impl=Tiny,instAddrWidth=16,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=3,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=None,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=2,mul_64_impl=0,mul_shift_choice=0,multiplierType=no_mul,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=0,resetOffset=0,resetSlave=mem.s1,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=false,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=false,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=true,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=true,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=true,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=1,shifterType=medium_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=(altera_clock_bridge:18.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:18.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:18.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=34848,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=16,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x9000&apos; end=&apos;0x9020&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x9020&apos; end=&apos;0x9028&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;slave name=&apos;sigdel_0.avalon_slave&apos; start=&apos;0x9028&apos; end=&apos;0x902C&apos; type=&apos;sigdel.avalon_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=32,exceptionOffset=32,exceptionSlave=mem.s1,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=4096,icache_tagramBlockType=Automatic,impl=Tiny,instAddrWidth=16,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=3,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=None,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=no_mul,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=0,resetOffset=0,resetSlave=mem.s1,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=false,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=false,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=true,setting_disableocitrace=false,setting_dtcm_ecc_present=true,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=true,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=medium_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=)(clock:18.1:)(clock:18.1:)(reset:18.1:))(altera_avalon_jtag_uart:18.1:allowMultipleConnections=false,avalonSpec=2.0,clkFreq=50000000,enableInteractiveInput=false,enableInteractiveOutput=false,hubInstanceID=0,legacySignalAllow=false,readBufferDepth=64,readIRQThreshold=8,simInputCharacterStream=,simInteractiveOptions=NO_INTERACTIVE_WINDOWS,useRegistersForReadBuffer=false,useRegistersForWriteBuffer=false,useRelativePathForSimFile=false,writeBufferDepth=64,writeIRQThreshold=8)(altera_avalon_onchip_memory2:18.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=niosII_mem,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=niosII_mem.hex,derived_is_hardcopy=false,derived_set_addr_width=13,derived_set_addr_width2=13,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=true,deviceFamily=Cyclone IV E,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=32768,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=true,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(sigdel:1.0:PHACC_WIDTH=14)(altera_avalon_timer:18.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=49999,mult=0.001,period=1,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=1000.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9020,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9028,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x8800,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9000,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x8800,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(clock:18.1:)(clock:18.1:)(clock:18.1:)(clock:18.1:)(clock:18.1:)(interrupt:18.1:irqNumber=0)(interrupt:18.1:irqNumber=1)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)"
+   parameterizationKey="niosII:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1675774980,AUTO_UNIQUE_ID=(clock_source:18.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_nios2_gen2:18.1:AUTO_CLK_CLOCK_DOMAIN=1,AUTO_CLK_RESET_DOMAIN=1,AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_SPEEDGRADE=8,bht_ramBlockType=Automatic,breakAbsoluteAddr=34848,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=16,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x9000&apos; end=&apos;0x9020&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x9020&apos; end=&apos;0x9028&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;slave name=&apos;sigdel_0.avalon_slave&apos; start=&apos;0x9028&apos; end=&apos;0x902C&apos; type=&apos;sigdel.avalon_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=32,exceptionOffset=32,exceptionSlave=mem.s1,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=4096,icache_tagramBlockType=Automatic,impl=Tiny,instAddrWidth=16,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=3,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=None,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=2,mul_64_impl=0,mul_shift_choice=0,multiplierType=no_mul,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=0,resetOffset=0,resetSlave=mem.s1,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=false,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=false,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=true,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=true,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=true,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=1,shifterType=medium_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=(altera_clock_bridge:18.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:18.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:18.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=34848,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=16,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x9000&apos; end=&apos;0x9020&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x9020&apos; end=&apos;0x9028&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;slave name=&apos;sigdel_0.avalon_slave&apos; start=&apos;0x9028&apos; end=&apos;0x902C&apos; type=&apos;sigdel.avalon_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=32,exceptionOffset=32,exceptionSlave=mem.s1,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=4096,icache_tagramBlockType=Automatic,impl=Tiny,instAddrWidth=16,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x8000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x8800&apos; end=&apos;0x9000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=3,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=None,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=no_mul,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=0,resetOffset=0,resetSlave=mem.s1,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=false,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=false,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=true,setting_disableocitrace=false,setting_dtcm_ecc_present=true,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=true,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=medium_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=)(clock:18.1:)(clock:18.1:)(reset:18.1:))(altera_avalon_jtag_uart:18.1:allowMultipleConnections=false,avalonSpec=2.0,clkFreq=50000000,enableInteractiveInput=false,enableInteractiveOutput=false,hubInstanceID=0,legacySignalAllow=false,readBufferDepth=64,readIRQThreshold=8,simInputCharacterStream=,simInteractiveOptions=NO_INTERACTIVE_WINDOWS,useRegistersForReadBuffer=false,useRegistersForWriteBuffer=false,useRelativePathForSimFile=false,writeBufferDepth=64,writeIRQThreshold=8)(altera_avalon_onchip_memory2:18.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=niosII_mem,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=niosII_mem.hex,derived_is_hardcopy=false,derived_set_addr_width=13,derived_set_addr_width2=13,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=true,deviceFamily=Cyclone IV E,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=32768,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=true,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(sigdel:1.0:PHACC_WIDTH=26)(altera_avalon_timer:18.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=49999,mult=0.001,period=1,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=1000.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9020,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9028,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x8800,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x9000,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x8800,defaultConnection=false)(avalon:18.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(clock:18.1:)(clock:18.1:)(clock:18.1:)(clock:18.1:)(clock:18.1:)(interrupt:18.1:irqNumber=0)(interrupt:18.1:irqNumber=1)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)(reset:18.1:)"
    instancePathKey="niosII"
    kind="niosII"
    version="1.0"
    name="niosII">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_GENERATION_ID" value="1675761526" />
+  <parameter name="AUTO_GENERATION_ID" value="1675774980" />
   <parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
@@ -598,33 +598,33 @@
    <message level="Info" culprit="cpu"><![CDATA["<b>niosII</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 52 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
    <message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
-   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*) Starting Nios II generation</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*)   Checking for plaintext license.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Plaintext license not found.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   No license required to generate encrypted Nios II/e.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Elaborating CPU configuration settings</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating all objects for CPU</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Generating RTL from CPU objects</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating plain-text RTL</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:51 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Checking for plaintext license.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Plaintext license not found.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   No license required to generate encrypted Nios II/e.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*) Done Nios II generation</message>
    <message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
    <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart"</message>
    <message level="Info" culprit="jtag_uart">Starting RTL generation for module 'niosII_jtag_uart'</message>
-   <message level="Info" culprit="jtag_uart">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=/tmp/alt9395_1147342592986019742.dir/0002_jtag_uart_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0002_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="jtag_uart">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=/tmp/alt9395_3377339592384121778.dir/0002_jtag_uart_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0002_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="jtag_uart">Done RTL generation for module 'niosII_jtag_uart'</message>
    <message level="Info" culprit="jtag_uart"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem"</message>
    <message level="Info" culprit="mem">Starting RTL generation for module 'niosII_mem'</message>
-   <message level="Info" culprit="mem">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=/tmp/alt9395_1147342592986019742.dir/0003_mem_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0003_mem_gen//niosII_mem_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="mem">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=/tmp/alt9395_3377339592384121778.dir/0003_mem_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0003_mem_gen//niosII_mem_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="mem">Done RTL generation for module 'niosII_mem'</message>
    <message level="Info" culprit="mem"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>mem</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 5 starting:sigdel "submodules/sigdel"</message>
    <message level="Info" culprit="sigdel_0"><![CDATA["<b>niosII</b>" instantiated <b>sigdel</b> "<b>sigdel_0</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer"</message>
    <message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'niosII_sys_clk_timer'</message>
-   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=/tmp/alt9395_1147342592986019742.dir/0005_sys_clk_timer_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0005_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=/tmp/alt9395_3377339592384121778.dir/0005_sys_clk_timer_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0005_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'niosII_sys_clk_timer'</message>
    <message level="Info" culprit="sys_clk_timer"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0"</message>
@@ -844,17 +844,17 @@
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.002s</message>
    <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.015s/0.020s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
-   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
-   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.013s/0.025s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.007s/0.008s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
@@ -862,20 +862,20 @@
    <message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
    <message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.002s</message>
-   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.008s/0.009s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.006s/0.007s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
    <message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
    <message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.008s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
-   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.002s</message>
    <message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.006s/0.007s</message>
@@ -884,9 +884,9 @@
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.004s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.007s/0.009s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.006s/0.007s</message>
    <message
        level="Debug"
        culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>54</b> modules, <b>175</b> connections]]></message>
@@ -1282,16 +1282,16 @@
    <message level="Info" culprit="cpu"><![CDATA["<b>niosII</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
    <message level="Debug" culprit="niosII">queue size: 52 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
    <message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
-   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*) Starting Nios II generation</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*)   Checking for plaintext license.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Plaintext license not found.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   No license required to generate encrypted Nios II/e.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Elaborating CPU configuration settings</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating all objects for CPU</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Generating RTL from CPU objects</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating plain-text RTL</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:51 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Checking for plaintext license.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Plaintext license not found.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   No license required to generate encrypted Nios II/e.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*) Done Nios II generation</message>
    <message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
    <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
   </messages>
@@ -1335,7 +1335,7 @@
   <messages>
    <message level="Debug" culprit="niosII">queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart"</message>
    <message level="Info" culprit="jtag_uart">Starting RTL generation for module 'niosII_jtag_uart'</message>
-   <message level="Info" culprit="jtag_uart">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=/tmp/alt9395_1147342592986019742.dir/0002_jtag_uart_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0002_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="jtag_uart">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=/tmp/alt9395_3377339592384121778.dir/0002_jtag_uart_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0002_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="jtag_uart">Done RTL generation for module 'niosII_jtag_uart'</message>
    <message level="Info" culprit="jtag_uart"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>"]]></message>
   </messages>
@@ -1404,19 +1404,19 @@
   <messages>
    <message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem"</message>
    <message level="Info" culprit="mem">Starting RTL generation for module 'niosII_mem'</message>
-   <message level="Info" culprit="mem">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=/tmp/alt9395_1147342592986019742.dir/0003_mem_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0003_mem_gen//niosII_mem_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="mem">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=/tmp/alt9395_3377339592384121778.dir/0003_mem_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0003_mem_gen//niosII_mem_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="mem">Done RTL generation for module 'niosII_mem'</message>
    <message level="Info" culprit="mem"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>mem</b>"]]></message>
   </messages>
  </entity>
  <entity
    path="submodules/"
-   parameterizationKey="sigdel:1.0:PHACC_WIDTH=14"
+   parameterizationKey="sigdel:1.0:PHACC_WIDTH=26"
    instancePathKey="niosII:.:sigdel_0"
    kind="sigdel"
    version="1.0"
    name="sigdel">
-  <parameter name="PHACC_WIDTH" value="14" />
+  <parameter name="PHACC_WIDTH" value="26" />
   <generatedFiles>
    <file
        path="/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/niosII/synthesis/submodules/phacc.sv"
@@ -1490,7 +1490,7 @@
   <messages>
    <message level="Debug" culprit="niosII">queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer"</message>
    <message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'niosII_sys_clk_timer'</message>
-   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=/tmp/alt9395_1147342592986019742.dir/0005_sys_clk_timer_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_1147342592986019742.dir/0005_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/bin/perl -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=/tmp/alt9395_3377339592384121778.dir/0005_sys_clk_timer_gen/ --quartus_dir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus --verilog --config=/tmp/alt9395_3377339592384121778.dir/0005_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
    <message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'niosII_sys_clk_timer'</message>
    <message level="Info" culprit="sys_clk_timer"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
   </messages>
@@ -2040,17 +2040,17 @@
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.002s</message>
    <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.015s/0.020s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
-   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
-   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.013s/0.025s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.007s/0.008s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
@@ -2058,20 +2058,20 @@
    <message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
    <message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.002s</message>
-   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.008s/0.009s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.006s/0.007s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
    <message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
    <message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.008s</message>
    <message level="Progress" culprit="min"></message>
    <message level="Progress" culprit="max"></message>
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
-   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
    <message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.002s</message>
    <message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.006s/0.007s</message>
@@ -2080,9 +2080,9 @@
    <message level="Progress" culprit="current"></message>
    <message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
    <message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.004s</message>
-   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.007s/0.009s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.006s/0.007s</message>
    <message
        level="Debug"
        culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>54</b> modules, <b>175</b> connections]]></message>
@@ -2501,16 +2501,16 @@
   <messages>
    <message level="Debug" culprit="niosII">queue size: 52 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
    <message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
-   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_1147342592986019742.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*) Starting Nios II generation</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:49 (*)   Checking for plaintext license.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Plaintext license not found.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   No license required to generate encrypted Nios II/e.</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Elaborating CPU configuration settings</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating all objects for CPU</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Generating RTL from CPU objects</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:50 (*)   Creating plain-text RTL</message>
-   <message level="Info" culprit="cpu"># 2023.02.07 12:18:51 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//eperlcmd -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64//perl/lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/europa -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin/perl_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/sopc_builder/bin -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen/ --quartus_bindir=/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/linux64/ --verilog --config=/tmp/alt9395_3377339592384121778.dir/0008_cpu_gen//niosII_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Checking for plaintext license.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Plaintext license not found.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   No license required to generate encrypted Nios II/e.</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:03 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2023.02.07 16:03:04 (*) Done Nios II generation</message>
    <message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
    <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
   </messages>
diff --git a/Top/niosII/synthesis/niosII.debuginfo b/Top/niosII/synthesis/niosII.debuginfo
index 466a071..0ca1f59 100644
--- a/Top/niosII/synthesis/niosII.debuginfo
+++ b/Top/niosII/synthesis/niosII.debuginfo
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2023.02.07.13:18:51 -->
+ <!-- 2023.02.07.17:03:05 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1675761526</value>
+  <value>1675774980</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -5678,7 +5678,7 @@ parameters are a RESULT of the module parameters. -->
 the requested settings for a module instance. -->
   <parameter name="PHACC_WIDTH">
    <type>int</type>
-   <value>14</value>
+   <value>26</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
@@ -12167,5 +12167,5 @@ parameters are a RESULT of the module parameters. -->
   <version>18.1</version>
  </plugin>
  <reportVersion>18.1 625</reportVersion>
- <uniqueIdentifier>CE053227F4B7000001862B2BACF3</uniqueIdentifier>
+ <uniqueIdentifier>CE053227F4B7000001862BF8F68D</uniqueIdentifier>
 </EnsembleReport>
diff --git a/Top/niosII/synthesis/niosII.qip b/Top/niosII/synthesis/niosII.qip
index 4766ae6..cccf95a 100644
--- a/Top/niosII/synthesis/niosII.qip
+++ b/Top/niosII/synthesis/niosII.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
 set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
-set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1675761526"
+set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1675774980"
 set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
 set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
 set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NTc2MTUyNg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NTc3NDk4MA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxNUYyM0M4::QXV0byBERVZJQ0U="
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -667,7 +667,7 @@ set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_DISP
 set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_PARAMETER "UEhBQ0NfV0lEVEg=::MTQ=::UEhBQ0NfV0lEVEg="
+set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_PARAMETER "UEhBQ0NfV0lEVEg=::MjY=::UEhBQ0NfV0lEVEg="
 set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ=="
 set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
diff --git a/Top/niosII/synthesis/niosII.v b/Top/niosII/synthesis/niosII.v
index 14af4e4..e69e854 100644
--- a/Top/niosII/synthesis/niosII.v
+++ b/Top/niosII/synthesis/niosII.v
@@ -128,7 +128,7 @@ module niosII (
 	);
 
 	sigdel #(
-		.PHACC_WIDTH (14)
+		.PHACC_WIDTH (26)
 	) sigdel_0 (
 		.clk     (clk_clk),                                           //        clock.clk
 		.clr_n   (~rst_controller_reset_out_reset),                   //   reset_sink.reset_n
diff --git a/Top/semafor.qsf b/Top/semafor.qsf
index 0b605b0..6c59e59 100644
--- a/Top/semafor.qsf
+++ b/Top/semafor.qsf
@@ -61,4 +61,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
 set_location_assignment PIN_T2 -to CLOCK_50
 set_location_assignment PIN_E3 -to LEDG[0]
+set_location_assignment PIN_C21 -to FOUTA
+set_location_assignment PIN_E4 -to nreset
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Top/semafor.qws b/Top/semafor.qws
deleted file mode 100644
index 9b2fc2e..0000000
Binary files a/Top/semafor.qws and /dev/null differ
diff --git a/Top/sigdel_hw.tcl b/Top/sigdel_hw.tcl
index b1595aa..1b95d05 100644
--- a/Top/sigdel_hw.tcl
+++ b/Top/sigdel_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 18.1
-# Fri Jan 27 18:48:38 MSK 2023
+# Tue Feb 07 16:48:35 MSK 2023
 # DO NOT MODIFY
 
 
 # 
 # sigdel "Sigma-Delta Modulator" v1.0
-#  2023.01.27.18:48:38
+#  2023.02.07.16:48:35
 # 
 # 
 
diff --git a/Top/sigdel_hw.tcl~ b/Top/sigdel_hw.tcl~
new file mode 100644
index 0000000..b1595aa
--- /dev/null
+++ b/Top/sigdel_hw.tcl~
@@ -0,0 +1,143 @@
+# TCL File Generated by Component Editor 18.1
+# Fri Jan 27 18:48:38 MSK 2023
+# DO NOT MODIFY
+
+
+# 
+# sigdel "Sigma-Delta Modulator" v1.0
+#  2023.01.27.18:48:38
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module sigdel
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME sigdel
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "User Logic"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
+add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
+add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
+add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
+add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
+
+
+# 
+# parameters
+# 
+add_parameter PHACC_WIDTH INTEGER 14
+set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
+set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
+set_parameter_property PHACC_WIDTH TYPE INTEGER
+set_parameter_property PHACC_WIDTH UNITS None
+set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property PHACC_WIDTH HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink clr_n reset_n Input 1
+
+
+# 
+# connection point conduit_end
+# 
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock ""
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end fout writeresponsevalid_n Output 1
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset_sink
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave maximumPendingWriteTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave wr_n write_n Input 1
+add_interface_port avalon_slave wr_data writedata Input 32
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+
diff --git a/Top/software/deltasigma/deltasigma.elf b/Top/software/deltasigma/deltasigma.elf
index 0581bb8..ad7a1f2 100644
Binary files a/Top/software/deltasigma/deltasigma.elf and b/Top/software/deltasigma/deltasigma.elf differ
diff --git a/Top/software/deltasigma/deltasigma.objdump b/Top/software/deltasigma/deltasigma.objdump
index bf7124b..bc3466b 100644
--- a/Top/software/deltasigma/deltasigma.objdump
+++ b/Top/software/deltasigma/deltasigma.objdump
@@ -489,7 +489,7 @@ Disassembly of section .text:
      26c:	dfc00115 	stw	ra,4(sp)
      270:	df000015 	stw	fp,0(sp)
      274:	d839883a 	mov	fp,sp
-     278:	00c00974 	movhi	r3,37
+     278:	00c80004 	movi	r3,8192
      27c:	00a40a14 	movui	r2,36904
      280:	10c00035 	stwio	r3,0(r2)
      284:	01000034 	movhi	r4,0
diff --git a/Top/software/deltasigma/main.c b/Top/software/deltasigma/main.c
index 5f18f9d..9200927 100644
--- a/Top/software/deltasigma/main.c
+++ b/Top/software/deltasigma/main.c
@@ -15,7 +15,7 @@
 
 int main() {
 
-	IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x250000);
+	IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x2000);
 	printf("Ready\n");
 	while (1) {}
 	return 0;
diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp
index 15c98c3..8c2b187 100644
--- a/Top/software/semafor_bsp/settings.bsp
+++ b/Top/software/semafor_bsp/settings.bsp
@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Feb 7, 2023 2:27:07 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1675765627575</BspGeneratedUnixTimeStamp>
+        <BspGeneratedTimeStamp>Feb 7, 2023 4:54:12 PM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1675774452122</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>
diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html
index da57c57..d61fe4f 100644
--- a/Top/software/semafor_bsp/summary.html
+++ b/Top/software/semafor_bsp/summary.html
@@ -22,10 +22,10 @@
 <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Feb 7, 2023 2:27:07 PM</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Feb 7, 2023 4:54:12 PM</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1675765627575</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1675774452122</td>
 </tr>
 <tr mode="wrap">
 <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</td>
diff --git a/Top/top.sv b/Top/top.sv
index 264aeb9..4267723 100644
--- a/Top/top.sv
+++ b/Top/top.sv
@@ -18,6 +18,9 @@ module top
 
 (
 
+// reset
+nreset,
+
 	//////////// CLOCK //////////
 	CLOCK_50,
 	CLOCK2_50,
@@ -34,6 +37,7 @@ output							FOUTA;
 input 		          		CLOCK_50;
 input 		          		CLOCK2_50;
 input 		          		CLOCK3_50;
+input nreset;
 
 //////////// LED //////////
 output		     [8:0]		LEDG;
@@ -42,7 +46,7 @@ output		    [17:0]		LEDR;
     niosII u0 (
         .clk_clk                          (CLOCK_50), //         clk.clk
         .conduit_end_writeresponsevalid_n (LEDG[0]),  // conduit_end.writeresponsevalid_n
-        .reset_reset_n                    (1'b1)      //       reset.reset_n
+        .reset_reset_n                    (nreset)      //       reset.reset_n
     );