From ec65e89bbb5f5b536e97b4a8c2a1b205d9ab7e33 Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Tue, 18 Oct 2022 16:10:29 +0300 Subject: [PATCH] pt 1. initial sources --- HDL/IP/periodram.qip | 5 + HDL/IP/periodram.v | 214 ++++++++++++++++++++++++++++++++++++++++ HDL/IP/periodram_inst.v | 8 ++ HDL/dec.sv | 132 +++++++++++++++++++++++++ Testbench/dec/dec_tb.sv | 128 ++++++++++++++++++++++++ 5 files changed, 487 insertions(+) create mode 100644 HDL/IP/periodram.qip create mode 100644 HDL/IP/periodram.v create mode 100644 HDL/IP/periodram_inst.v create mode 100644 HDL/dec.sv create mode 100644 Testbench/dec/dec_tb.sv diff --git a/HDL/IP/periodram.qip b/HDL/IP/periodram.qip new file mode 100644 index 0000000..1e64f90 --- /dev/null +++ b/HDL/IP/periodram.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "14.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"] diff --git a/HDL/IP/periodram.v b/HDL/IP/periodram.v new file mode 100644 index 0000000..7f94151 --- /dev/null +++ b/HDL/IP/periodram.v @@ -0,0 +1,214 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: periodram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 14.0.2 Build 209 09/17/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus II License Agreement, +//the Altera MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Altera and sold by Altera or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module periodram ( + clock, + data, + rdaddress, + wraddress, + wren, + q); + + input clock; + input [31:0] data; + input [3:0] rdaddress; + input [1:0] wraddress; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({8{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4, + altsyncram_component.numwords_b = 16, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = 2, + altsyncram_component.widthad_b = 4, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "1" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" +// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0 +// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/HDL/IP/periodram_inst.v b/HDL/IP/periodram_inst.v new file mode 100644 index 0000000..9fa36ba --- /dev/null +++ b/HDL/IP/periodram_inst.v @@ -0,0 +1,8 @@ +periodram periodram_inst ( + .clock ( clock_sig ), + .data ( data_sig ), + .rdaddress ( rdaddress_sig ), + .wraddress ( wraddress_sig ), + .wren ( wren_sig ), + .q ( q_sig ) + ); diff --git a/HDL/dec.sv b/HDL/dec.sv new file mode 100644 index 0000000..93e7541 --- /dev/null +++ b/HDL/dec.sv @@ -0,0 +1,132 @@ +module dec +#(m = 8) +( + //clock and reset + input logic clk, clrn, + //control slave + input logic ctl_wr, ctl_rd, + input logic ctl_addr, + input logic [31:0] ctl_wrdata, + output logic [31:0] ctl_rddata, + //memory slave + input logic ram_wr, + input logic [1:0] ram_addr, + input logic [31:0] ram_wrdata, + //external ports + input logic train, + output logic red, yellow, green +); + + logic run; + logic [1:0] divider; + + logic [m-1:0] divisor; + logic [1:0] contr; + logic [2:0] colors; + logic [m-1:0] cntdiv; + logic enacnt; + + //control slave logic + always_ff @ (posedge clk or negedge clrn) + begin + if (!clrn) + begin + run <= 0; + divider <= 0; + end + else + begin + if (ctl_wr) + begin + case (ctl_addr) + 1'b0: run <= ctl_wrdata[0]; + 1'b1: divider <= ctl_wrdata[1:0]; + endcase + end + end + end + + always_comb + begin + case (ctl_addr) + 1'b0: ctl_rddata = {31'b0,run}; + 1'b1: ctl_rddata = {30'b0,divider}; + default: ctl_rddata = 'bx; + endcase + end + + //semaphore logic + + always_ff @ (posedge clk or negedge clrn) + begin + if (!clrn) cntdiv<=0; + else + begin + if (train | ~run) cntdiv<=0; + else + begin + if (enacnt) cntdiv<=0; + else cntdiv<=cntdiv+1; + end + end + end + + always_comb + begin + enacnt=(cntdiv==divisor); + end + + always_ff @ (posedge clk or negedge clrn) + begin + if (!clrn) + begin + colors <= 3'b100; + end + else + begin + if (train | ~run) + begin + colors <= 3'b100; + end + else + begin + if (enacnt) + begin + case (colors) + 3'b100: colors <= 3'b010; + 3'b010: colors <= 3'b011; + 3'b011: colors <= 3'b001; + 3'b001: colors <= 3'b001; + default: colors <= 3'b100; + endcase + end + end + end + end + + always_comb + begin + case (colors) + 3'b100: contr = 2'b00; + 3'b010: contr = 2'b01; + 3'b011: contr = 2'b10; + 3'b001: contr = 2'b11; + default : contr = 2'b00; + endcase + end + + assign red = colors[2]; + assign yellow = colors[1]; + assign green = colors[0]; + + periodram b2v_inst3( + .clock(clk), + .data (ram_wrdata), + .wraddress (ram_addr), + .wren (ram_wr), + .rdaddress({divider,contr}), + .q(divisor) + ); + +endmodule + diff --git a/Testbench/dec/dec_tb.sv b/Testbench/dec/dec_tb.sv new file mode 100644 index 0000000..31200fa --- /dev/null +++ b/Testbench/dec/dec_tb.sv @@ -0,0 +1,128 @@ +`timescale 1 ns/1 ns + +module dec_tb(); + + // Wires and variables to connect to UUT (unit under test) + logic clk, clrn, train; + logic r, y, g; + logic [1:0] div; + logic ctl_wr, ctl_rd; + logic ctl_addr; + logic [31:0] ctl_wrdata; + logic [31:0] ctl_rddata; + logic ram_wr; + logic [1:0] ram_addr; + logic [31:0] ram_wrdata; + + logic [31:0] divisor[3:0] = { + {8'd10, 8'd70, 8'd50, 8'd20}, + {8'd10, 8'd30, 8'd40, 8'd30}, + {8'd10, 8'd30, 8'd10, 8'd100}, + {8'd10, 8'd60, 8'd80, 8'd50} + }; + + // Instantiate UUT + dec my_sem( + .clk(clk), .clrn(clrn), + .ctl_wr(ctl_wr), .ctl_rd(ctl_rd), + .ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata), + .ram_wr(ram_wr), + .ram_addr(ram_addr), .ram_wrdata(ram_wrdata), + .train(train), .red(r), .yellow(y), .green(g) + ); + + // Clock definition + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Divisor and train definition + initial begin + //initial reset + clrn = 0; + div = 0; + train = 0; + //take reset off + @(negedge clk) clrn = 1; + //configure semaphore + for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM + write_reg_transaction(1,div); //write initial divisor + write_reg_transaction(0,1); //enable semaphore + //run trains + repeat (4) + begin + repeat (10) @(posedge clk); + train=1; + repeat (4) @(posedge clk); + train=0; + wait ({r,y,g}==3'b001); + repeat (10) @(posedge clk); + write_reg_transaction(1,div); + div=div+1; + end + //wait a little + repeat (10) @(posedge clk); + $stop; + end + + //Single register write transaction task + task write_reg_transaction; + //input signals + input [1:0] offs; + input [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ctl_wr = 1; + ctl_addr = offs; + ctl_wrdata = val; + @(posedge clk); + //deassert signals + ctl_wr = 0; + ctl_addr = 'bx; + ctl_wrdata = 'bx; + end + endtask + + //Single register read transaction task + task read_reg_transaction; + //input signals + input [1:0] offs; + output [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ctl_rd = 1; + ctl_addr = offs; + @(posedge clk); + val = ctl_rddata; + //deassert signals + ctl_rd = 0; + ctl_addr = 'bx; + end + endtask + + //RAM write transaction task + task write_ram_transaction; + //input signals + input [1:0] offs; + input [31:0] val; + //transaction implementation + begin + @(posedge clk); + //assert signals for one clock cycle + ram_wr = 1; + ram_addr = offs; + ram_wrdata = val; + @(posedge clk); + //deassert signals + ram_wr = 0; + ram_addr = 'bx; + ram_wrdata = 'bx; + end + endtask + +endmodule