diff --git a/Top/Semafor_hw.tcl b/Top/Semafor_hw.tcl index 7151172..8fa8006 100644 --- a/Top/Semafor_hw.tcl +++ b/Top/Semafor_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Wed Oct 19 14:56:56 MSK 2022 +# Mon Oct 24 17:47:36 MSK 2022 # DO NOT MODIFY # -# Semafor "Semafor" v1.0 -# 2022.10.19.14:56:56 +# sem "Semafor" v1.0 +# 2022.10.24.17:47:36 # # @@ -16,10 +16,10 @@ package require -exact qsys 16.1 # -# module Semafor +# module sem # set_module_property DESCRIPTION "" -set_module_property NAME Semafor +set_module_property NAME sem set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true @@ -44,6 +44,7 @@ add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL dec set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv diff --git a/Top/Semafor_hw.tcl~ b/Top/Semafor_hw.tcl~ index 12e61bf..1dec36b 100644 --- a/Top/Semafor_hw.tcl~ +++ b/Top/Semafor_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Wed Oct 19 14:12:17 MSK 2022 +# Mon Oct 24 14:36:52 MSK 2022 # DO NOT MODIFY # -# Semafor "Semafor" v1.0 -# 2022.10.19.14:12:17 +# sem "Semafor" v1.0 +# 2022.10.24.14:36:52 # # @@ -16,10 +16,10 @@ package require -exact qsys 16.1 # -# module Semafor +# module sem # set_module_property DESCRIPTION "" -set_module_property NAME Semafor +set_module_property NAME sem set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true @@ -43,6 +43,13 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL dec +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv +add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v + # # parameters @@ -52,6 +59,7 @@ set_parameter_property m DEFAULT_VALUE 8 set_parameter_property m DISPLAY_NAME m set_parameter_property m TYPE INTEGER set_parameter_property m UNITS None +set_parameter_property m ALLOWED_RANGES -2147483648:2147483647 set_parameter_property m HDL_PARAMETER true diff --git a/Top/niosII.qsys b/Top/niosII.qsys index 5971194..94898cb 100644 --- a/Top/niosII.qsys +++ b/Top/niosII.qsys @@ -73,6 +73,14 @@ type = "String"; } } + element niosII + { + datum _originalDeviceFamily + { + value = "Cyclone IV E"; + type = "String"; + } + } element sem { datum _sortIndex @@ -163,7 +171,7 @@ - ]]> + ]]> @@ -346,7 +354,7 @@ version="18.1" enabled="1"> - + @@ -372,7 +380,7 @@ - + - + java.lang.Integer - 1666177115 + 1666621523 false true false @@ -2034,7 +2034,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -5652,7 +5652,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -8346,7 +8346,7 @@ parameters are a RESULT of the module parameters. --> 1 - Semafor + sem com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Semafor diff --git a/Top/niosII/niosII.bsf b/Top/niosII/niosII.bsf index 3f01ac6..c61f1b7 100644 --- a/Top/niosII/niosII.bsf +++ b/Top/niosII/niosII.bsf @@ -75,7 +75,7 @@ refer to the applicable agreement for further details. (text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0))) (text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0))) (text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0))) - (text " system " (rect 253 216 554 442)(font "Arial" )) + (text " niosII " (rect 262 216 572 442)(font "Arial" )) (line (pt 112 32)(pt 176 32)(line_width 1)) (line (pt 176 32)(pt 176 216)(line_width 1)) (line (pt 112 216)(pt 176 216)(line_width 1)) diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html index 4bc3b02..2a603dd 100644 --- a/Top/niosII/niosII.html +++ b/Top/niosII/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.10.19.14:20:532022.10.24.17:48:01 Datasheet
@@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord altera_avalon_onchip_memory2 18.1
   sem - Semafor 1.0 + sem 1.0
   sys_clk_timer altera_avalon_timer 18.1 @@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord dataSlaveMapParam - <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> + <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> tightlyCoupledDataMaster0MapParam @@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

sem

Semafor v1.0 +

sem

sem v1.0
@@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- +
generation took 0,01 secondsrendering took 0,11 secondsrendering took 0,04 seconds
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml index ce1ee7a..c4f8dad 100644 --- a/Top/niosII/niosII.xml +++ b/Top/niosII/niosII.xml @@ -1,6 +1,6 @@ - + @@ -585,7 +585,7 @@ niosII" reuses altera_nios2_gen2 "submodules/niosII_cpu"]]> niosII" reuses altera_avalon_jtag_uart "submodules/niosII_jtag_uart"]]> niosII" reuses altera_avalon_onchip_memory2 "submodules/niosII_mem"]]> - niosII" reuses Semafor "submodules/dec"]]> + niosII" reuses sem "submodules/dec"]]> niosII" reuses altera_avalon_timer "submodules/niosII_sys_clk_timer"]]> niosII" reuses altera_mm_interconnect "submodules/niosII_mm_interconnect_0"]]> niosII" reuses altera_irq_mapper "submodules/niosII_irq_mapper"]]> @@ -607,36 +607,36 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.10.19 13:21:19 (*) Starting Nios II generation - # 2022.10.19 13:21:19 (*) Checking for plaintext license. - # 2022.10.19 13:21:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.10.19 13:21:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.10.19 13:21:20 (*) LM_LICENSE_FILE environment variable is empty - # 2022.10.19 13:21:20 (*) Plaintext license not found. - # 2022.10.19 13:21:20 (*) No license required to generate encrypted Nios II/e. - # 2022.10.19 13:21:20 (*) Elaborating CPU configuration settings - # 2022.10.19 13:21:20 (*) Creating all objects for CPU - # 2022.10.19 13:21:22 (*) Generating RTL from CPU objects - # 2022.10.19 13:21:22 (*) Creating plain-text RTL - # 2022.10.19 13:21:23 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.10.24 16:48:27 (*) Starting Nios II generation + # 2022.10.24 16:48:27 (*) Checking for plaintext license. + # 2022.10.24 16:48:28 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.10.24 16:48:28 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.10.24 16:48:28 (*) LM_LICENSE_FILE environment variable is empty + # 2022.10.24 16:48:28 (*) Plaintext license not found. + # 2022.10.24 16:48:28 (*) No license required to generate encrypted Nios II/e. + # 2022.10.24 16:48:28 (*) Elaborating CPU configuration settings + # 2022.10.24 16:48:28 (*) Creating all objects for CPU + # 2022.10.24 16:48:30 (*) Generating RTL from CPU objects + # 2022.10.24 16:48:30 (*) Creating plain-text RTL + # 2022.10.24 16:48:31 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> - queue size: 5 starting:Semafor "submodules/dec" - niosII" instantiated Semafor "sem"]]> + queue size: 5 starting:sem "submodules/dec" + niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" @@ -882,16 +882,16 @@ Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.080s/0.119s + Timing: ELA:1/0.011s + Timing: COM:3/0.073s/0.105s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.002s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.012s - Timing: COM:3/0.028s/0.032s + Timing: ELA:1/0.001s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.013s + Timing: COM:3/0.030s/0.037s @@ -899,39 +899,39 @@ Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.028s + Timing: COM:3/0.028s/0.035s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s + Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s - Timing: COM:3/0.025s/0.033s + Timing: COM:3/0.030s/0.035s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.022s/0.028s + Timing: ELA:2/0.002s/0.002s + Timing: ELA:1/0.009s + Timing: COM:3/0.024s/0.025s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.021s/0.025s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.011s + Timing: COM:3/0.030s/0.040s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.014s - Timing: COM:3/0.032s/0.050s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.010s + Timing: COM:3/0.024s/0.028s 61 modules, 199 connections]]> @@ -1058,7 +1058,7 @@ + value="<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>" /> @@ -1334,19 +1334,19 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.10.19 13:21:19 (*) Starting Nios II generation - # 2022.10.19 13:21:19 (*) Checking for plaintext license. - # 2022.10.19 13:21:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.10.19 13:21:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.10.19 13:21:20 (*) LM_LICENSE_FILE environment variable is empty - # 2022.10.19 13:21:20 (*) Plaintext license not found. - # 2022.10.19 13:21:20 (*) No license required to generate encrypted Nios II/e. - # 2022.10.19 13:21:20 (*) Elaborating CPU configuration settings - # 2022.10.19 13:21:20 (*) Creating all objects for CPU - # 2022.10.19 13:21:22 (*) Generating RTL from CPU objects - # 2022.10.19 13:21:22 (*) Creating plain-text RTL - # 2022.10.19 13:21:23 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.10.24 16:48:27 (*) Starting Nios II generation + # 2022.10.24 16:48:27 (*) Checking for plaintext license. + # 2022.10.24 16:48:28 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.10.24 16:48:28 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.10.24 16:48:28 (*) LM_LICENSE_FILE environment variable is empty + # 2022.10.24 16:48:28 (*) Plaintext license not found. + # 2022.10.24 16:48:28 (*) No license required to generate encrypted Nios II/e. + # 2022.10.24 16:48:28 (*) Elaborating CPU configuration settings + # 2022.10.24 16:48:28 (*) Creating all objects for CPU + # 2022.10.24 16:48:30 (*) Generating RTL from CPU objects + # 2022.10.24 16:48:30 (*) Creating plain-text RTL + # 2022.10.24 16:48:31 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> @@ -1390,7 +1390,7 @@ queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0003_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0003_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> @@ -1459,16 +1459,16 @@ queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0004_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0004_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> @@ -1489,8 +1489,8 @@ - queue size: 5 starting:Semafor "submodules/dec" - niosII" instantiated Semafor "sem"]]> + queue size: 5 starting:sem "submodules/dec" + niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0006_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0006_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> @@ -2130,16 +2130,16 @@ Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.080s/0.119s + Timing: ELA:1/0.011s + Timing: COM:3/0.073s/0.105s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.002s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.012s - Timing: COM:3/0.028s/0.032s + Timing: ELA:1/0.001s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.013s + Timing: COM:3/0.030s/0.037s @@ -2147,39 +2147,39 @@ Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.028s + Timing: COM:3/0.028s/0.035s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s + Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s - Timing: COM:3/0.025s/0.033s + Timing: COM:3/0.030s/0.035s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.022s/0.028s + Timing: ELA:2/0.002s/0.002s + Timing: ELA:1/0.009s + Timing: COM:3/0.024s/0.025s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.002s - Timing: ELA:1/0.013s - Timing: COM:3/0.021s/0.025s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.011s + Timing: COM:3/0.030s/0.040s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.014s - Timing: COM:3/0.032s/0.050s + Timing: ELA:2/0.001s/0.002s + Timing: ELA:1/0.010s + Timing: COM:3/0.024s/0.028s 61 modules, 199 connections]]> @@ -2364,7 +2364,7 @@ + value="<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>" /> @@ -2605,19 +2605,19 @@ queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9284_1154445688588331824.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.10.19 13:21:19 (*) Starting Nios II generation - # 2022.10.19 13:21:19 (*) Checking for plaintext license. - # 2022.10.19 13:21:20 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.10.19 13:21:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.10.19 13:21:20 (*) LM_LICENSE_FILE environment variable is empty - # 2022.10.19 13:21:20 (*) Plaintext license not found. - # 2022.10.19 13:21:20 (*) No license required to generate encrypted Nios II/e. - # 2022.10.19 13:21:20 (*) Elaborating CPU configuration settings - # 2022.10.19 13:21:20 (*) Creating all objects for CPU - # 2022.10.19 13:21:22 (*) Generating RTL from CPU objects - # 2022.10.19 13:21:22 (*) Creating plain-text RTL - # 2022.10.19 13:21:23 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9289_5316253009415989539.dir/0009_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.10.24 16:48:27 (*) Starting Nios II generation + # 2022.10.24 16:48:27 (*) Checking for plaintext license. + # 2022.10.24 16:48:28 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.10.24 16:48:28 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.10.24 16:48:28 (*) LM_LICENSE_FILE environment variable is empty + # 2022.10.24 16:48:28 (*) Plaintext license not found. + # 2022.10.24 16:48:28 (*) No license required to generate encrypted Nios II/e. + # 2022.10.24 16:48:28 (*) Elaborating CPU configuration settings + # 2022.10.24 16:48:28 (*) Creating all objects for CPU + # 2022.10.24 16:48:30 (*) Generating RTL from CPU objects + # 2022.10.24 16:48:30 (*) Creating plain-text RTL + # 2022.10.24 16:48:31 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> diff --git a/Top/niosII/synthesis/niosII.debuginfo b/Top/niosII/synthesis/niosII.debuginfo index 7d0beb1..eb4baf7 100644 --- a/Top/niosII/synthesis/niosII.debuginfo +++ b/Top/niosII/synthesis/niosII.debuginfo @@ -1,7 +1,7 @@ - + com.altera.sopcmodel.ensemble.EClockAdapter @@ -53,7 +53,7 @@ int - 1666174853 + 1666619281 false true true @@ -2110,7 +2110,7 @@ the requested settings for a module instance. --> java.lang.String - ]]> + ]]> false true false @@ -5673,7 +5673,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -12830,7 +12830,7 @@ parameters are a RESULT of the module parameters. --> 1 - Semafor + sem com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Semafor @@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. --> 18.1 18.1 625 - 7831C1D0809000000183EFC2B97A + 7A31C1D08890000001840A4024CB diff --git a/Top/niosII/synthesis/niosII.qip b/Top/niosII/synthesis/niosII.qip index 8dabd6b..3e7c915 100644 --- a/Top/niosII/synthesis/niosII.qip +++ b/Top/niosII/synthesis/niosII.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] -set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666174853" +set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666619281" set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] @@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjE3NDg1Mw==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjYxOTI4MQ==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" @@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" -set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" +set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" @@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" -set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" +set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" diff --git a/Top/niosII/testbench/mentor/msim_setup.tcl b/Top/niosII/testbench/mentor/msim_setup.tcl index dfb0e0e..7595bbc 100644 --- a/Top/niosII/testbench/mentor/msim_setup.tcl +++ b/Top/niosII/testbench/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.10.19.14:59:25 +# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ---------------------------------------- # Initialize variables diff --git a/Top/niosII/testbench/niosII.html b/Top/niosII/testbench/niosII.html index 768a9f8..eecb47d 100644 --- a/Top/niosII/testbench/niosII.html +++ b/Top/niosII/testbench/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.10.19.14:58:352022.10.24.18:25:23 Datasheet
@@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord altera_avalon_onchip_memory2 18.1
   sem - Semafor 1.0 + sem 1.0
   sys_clk_timer altera_avalon_timer 18.1 @@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord dataSlaveMapParam - <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> + <address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> tightlyCoupledDataMaster0MapParam @@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

sem

Semafor v1.0 +

sem

sem v1.0
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- - + +
generation took 0,02 secondsrendering took 0,09 secondsgeneration took 0,00 secondsrendering took 0,04 seconds
diff --git a/Top/niosII/testbench/niosII_tb.html b/Top/niosII/testbench/niosII_tb.html index 644007f..70de2fa 100644 --- a/Top/niosII/testbench/niosII_tb.html +++ b/Top/niosII/testbench/niosII_tb.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.10.19.14:58:472022.10.24.18:25:32 Datasheet
@@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord altera_avalon_onchip_memory2 18.1
   niosII_inst_sem - Semafor 1.0 + sem 1.0
   niosII_inst_sys_clk_timer altera_avalon_timer 18.1 @@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -1323,7 +1323,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -1982,7 +1982,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

niosII_inst_sem

Semafor v1.0 +

niosII_inst_sem

sem v1.0
AUTO_GENERATION_ID16661771261666621532
AUTO_UNIQUE_ID
dataSlaveMapParam<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>
tightlyCoupledDataMaster0MapParam
@@ -2360,7 +2360,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- +
generation took 0,00 secondsrendering took 0,08 secondsrendering took 0,05 seconds
diff --git a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh index 287ff16..d1d4184 100644 --- a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh +++ b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.10.19.14:59:25 +# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.10.19.14:59:25 +# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh index d91e3a4..bcd9ede 100644 --- a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh +++ b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.10.19.14:59:25 +# ACDS 18.1 625 win32 2022.10.24.18:26:03 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.10.19.14:59:25 +# ACDS 18.1 625 win32 2022.10.24.18:26:03 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII_tb.csv b/Top/niosII_tb.csv index 9f41a86..101c794 100644 --- a/Top/niosII_tb.csv +++ b/Top/niosII_tb.csv @@ -1,12 +1,12 @@ -# system info niosII_tb on 2022.10.19.14:59:23 +# system info niosII_tb on 2022.10.24.18:26:01 system_info: name,value DEVICE,EP4CE115F29C7 DEVICE_FAMILY,Cyclone IV E -GENERATION_ID,1666177126 +GENERATION_ID,1666621532 # # -# Files generated for niosII_tb on 2022.10.19.14:59:23 +# Files generated for niosII_tb on 2022.10.24.18:26:01 files: filepath,kind,attributes,module,is_top niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true @@ -19,8 +19,8 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cp niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false -niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,niosII_sem,false -niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,niosII_sem,false +niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false +niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false @@ -76,7 +76,7 @@ niosII_tb.niosII_inst.cpu,niosII_cpu niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart niosII_tb.niosII_inst.mem,niosII_mem -niosII_tb.niosII_inst.sem,niosII_sem +niosII_tb.niosII_inst.sem,dec niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0 niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator diff --git a/Top/semafor.qsf b/Top/semafor.qsf index f0105f3..26a840b 100644 --- a/Top/semafor.qsf +++ b/Top/semafor.qsf @@ -53,7 +53,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name QSYS_FILE niosII.qsys set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Top/software/semafor/.settings/language.settings.xml b/Top/software/semafor/.settings/language.settings.xml index dc6ee09..c1cbc39 100644 --- a/Top/software/semafor/.settings/language.settings.xml +++ b/Top/software/semafor/.settings/language.settings.xml @@ -6,7 +6,7 @@ - + diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf new file mode 100644 index 0000000..ff5e47d Binary files /dev/null and b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf differ diff --git a/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map new file mode 100644 index 0000000..1524a94 --- /dev/null +++ b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map @@ -0,0 +1,1645 @@ +Archive member included to satisfy reference by file (symbol) + +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) + obj/default/sem.o (puts) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (strlen) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (__sinit) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) (__sfvwrite_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_fwalk) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-impure.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_global_impure_ptr) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_malloc_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memchr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memchr) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcpy.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memcpy) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memmove.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (memmove) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memset.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (memset) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (_realloc_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) (_sbrk_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (__sread) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_write_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (__swsetup_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_close_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (_fclose_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o) (__sflush_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (_free_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (errno) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_lseek_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) (__smakebuf_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_read_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) (_fstat_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) (_isatty_r) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) (__divsi3) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) (__mulsi3) +../semafor_bsp/\libhal_bsp.a(alt_close.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(closer.o) (close) +../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o) + obj/default/sem.o (alt_dcache_flush) +../semafor_bsp/\libhal_bsp.a(alt_dev.o) + ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_fd_list) +../semafor_bsp/\libhal_bsp.a(alt_errno.o) + ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_errno) +../semafor_bsp/\libhal_bsp.a(alt_fstat.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) (fstat) +../semafor_bsp/\libhal_bsp.a(alt_isatty.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) (isatty) +../semafor_bsp/\libhal_bsp.a(alt_lseek.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) (lseek) +../semafor_bsp/\libhal_bsp.a(alt_main.o) + ../semafor_bsp//obj/HAL/src/crt0.o (alt_main) +../semafor_bsp/\libhal_bsp.a(alt_malloc_lock.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) (__malloc_lock) +../semafor_bsp/\libhal_bsp.a(alt_read.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) (read) +../semafor_bsp/\libhal_bsp.a(alt_release_fd.o) + ../semafor_bsp/\libhal_bsp.a(alt_close.o) (alt_release_fd) +../semafor_bsp/\libhal_bsp.a(alt_sbrk.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (sbrk) +../semafor_bsp/\libhal_bsp.a(alt_write.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) (write) +../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (alt_irq_init) +../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../semafor_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o) + ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init) +../semafor_bsp/\libhal_bsp.a(alt_alarm_start.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../semafor_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../semafor_bsp/\libhal_bsp.a(alt_do_ctors.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (_do_ctors) +../semafor_bsp/\libhal_bsp.a(alt_do_dtors.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (_do_dtors) +../semafor_bsp/\libhal_bsp.a(alt_iic.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register) +../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + ../semafor_bsp/\libhal_bsp.a(alt_iic.o) (alt_iic_isr_register) +../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (alt_io_redirect) +../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry) +../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o) + ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq) +../semafor_bsp/\libhal_bsp.a(alt_irq_vars.o) + ../semafor_bsp/\libhal_bsp.a(alt_iic.o) (alt_irq_active) +../semafor_bsp/\libhal_bsp.a(alt_open.o) + ../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o) (open) +../semafor_bsp/\libhal_bsp.a(alt_tick.o) + ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../semafor_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) + ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_nios2_gen2_irq_init) +../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) (alt_exception) +../semafor_bsp/\libhal_bsp.a(alt_find_dev.o) + ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_find_dev) +../semafor_bsp/\libhal_bsp.a(alt_find_file.o) + ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_find_file) +../semafor_bsp/\libhal_bsp.a(alt_get_fd.o) + ../semafor_bsp/\libhal_bsp.a(alt_open.o) (alt_get_fd) +../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) (alt_instruction_exception_entry) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (atexit) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + ../semafor_bsp/\libhal_bsp.a(alt_main.o) (exit) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + ../semafor_bsp/\libhal_bsp.a(alt_find_dev.o) (memcmp) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (__call_exitprocs) +../semafor_bsp/\libhal_bsp.a(alt_exit.o) + c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (_exit) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o) +errno 0x4 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x0000000000000000 0x0000000000000020 +mem 0x0000000000000020 0x000000000001ffe0 +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD ../semafor_bsp//obj/HAL/src/crt0.o +LOAD obj/default/sem.o +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libstdc++.a +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libm.a +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a +START GROUP +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a +LOAD ../semafor_bsp/\libhal_bsp.a +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libm.a +END GROUP +LOAD c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a + 0x0000000000000000 __alt_mem_mem = 0x0 + +.entry 0x0000000000000000 0x20 + *(.entry) + .entry 0x0000000000000000 0x20 ../semafor_bsp//obj/HAL/src/crt0.o + 0x0000000000000000 __reset + +.exceptions 0x0000000000000020 0x210 + [!provide] PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x0000000000000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x0000000000000020 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + 0x0000000000000020 alt_irq_entry + .exceptions.entry.label + 0x0000000000000020 0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + 0x0000000000000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry.ecc_fatal) + *(.exceptions.entry) + .exceptions.entry + 0x0000000000000020 0x54 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x0000000000000074 0x10 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x0000000000000084 0x4 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x0000000000000088 0x4 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x000000000000008c 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x000000000000008c 0x8 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x0000000000000094 0x14 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x00000000000000a8 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x00000000000000a8 0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x00000000000000a8 0x54 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x00000000000000fc 0xd4 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o) + 0x00000000000000fc alt_irq_handler + .exceptions 0x00000000000001d0 0x60 ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + 0x00000000000001d0 alt_instruction_exception_entry + [!provide] PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + [!provide] PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x0000000000000230 0x55a8 + [!provide] PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata 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c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) + .text._read_r 0x0000000000002e50 0x60 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) + 0x0000000000002e50 _read_r + .text 0x0000000000002eb0 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) + .text._fstat_r + 0x0000000000002eb0 0x5c c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) + 0x0000000000002eb0 _fstat_r + .text 0x0000000000002f0c 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) + .text._isatty_r + 0x0000000000002f0c 0x54 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) + 0x0000000000002f0c _isatty_r + .text 0x0000000000002f60 0x1b4 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-divmod.o) + 0x0000000000002f60 __divsi3 + 0x0000000000002fe4 __modsi3 + 0x0000000000003058 __udivsi3 + 0x00000000000030bc __umodsi3 + .text 0x0000000000003114 0x28 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/mno-hw-mul\libgcc.a(lib2-mul.o) + 0x0000000000003114 __mulsi3 + .text 0x000000000000313c 0x114 ../semafor_bsp/\libhal_bsp.a(alt_close.o) + 0x0000000000003178 close + .text 0x0000000000003250 0x28 ../semafor_bsp/\libhal_bsp.a(alt_dcache_flush.o) + 0x0000000000003250 alt_dcache_flush + .text 0x0000000000003278 0x2c ../semafor_bsp/\libhal_bsp.a(alt_dev.o) + .text 0x00000000000032a4 0x0 ../semafor_bsp/\libhal_bsp.a(alt_errno.o) + .text 0x00000000000032a4 0xf4 ../semafor_bsp/\libhal_bsp.a(alt_fstat.o) + 0x00000000000032e0 fstat + .text 0x0000000000003398 0xe8 ../semafor_bsp/\libhal_bsp.a(alt_isatty.o) + 0x00000000000033d4 isatty + .text 0x0000000000003480 0x118 ../semafor_bsp/\libhal_bsp.a(alt_lseek.o) + 0x00000000000034bc lseek + .text 0x0000000000003598 0x7c ../semafor_bsp/\libhal_bsp.a(alt_main.o) + 0x0000000000003598 alt_main + .text 0x0000000000003614 0x48 ../semafor_bsp/\libhal_bsp.a(alt_malloc_lock.o) + 0x0000000000003614 __malloc_lock + 0x0000000000003638 __malloc_unlock + .text 0x000000000000365c 0x140 ../semafor_bsp/\libhal_bsp.a(alt_read.o) + 0x0000000000003698 read + .text 0x000000000000379c 0x84 ../semafor_bsp/\libhal_bsp.a(alt_release_fd.o) + 0x000000000000379c alt_release_fd + .text 0x0000000000003820 0xb0 ../semafor_bsp/\libhal_bsp.a(alt_sbrk.o) + 0x0000000000003820 sbrk + .text 0x00000000000038d0 0x13c ../semafor_bsp/\libhal_bsp.a(alt_write.o) + 0x000000000000390c write + .text 0x0000000000003a0c 0xcc ../semafor_bsp/\libhal_bsp.a(alt_sys_init.o) + 0x0000000000003a40 alt_irq_init + 0x0000000000003a78 alt_sys_init + .text 0x0000000000003ad8 0x164 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x0000000000003ad8 altera_avalon_jtag_uart_read_fd + 0x0000000000003b38 altera_avalon_jtag_uart_write_fd + 0x0000000000003b98 altera_avalon_jtag_uart_close_fd + 0x0000000000003be8 altera_avalon_jtag_uart_ioctl_fd + .text 0x0000000000003c3c 0x3d4 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + 0x0000000000003c3c altera_avalon_jtag_uart_init + 0x0000000000003fa8 altera_avalon_jtag_uart_close + .text 0x0000000000004010 0xf0 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x0000000000004010 altera_avalon_jtag_uart_ioctl + .text 0x0000000000004100 0x21c ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + 0x0000000000004100 altera_avalon_jtag_uart_read + .text 0x000000000000431c 0x224 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + 0x000000000000431c altera_avalon_jtag_uart_write + .text 0x0000000000004540 0xf4 ../semafor_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o) + 0x00000000000045b8 alt_avalon_timer_sc_init + .text 0x0000000000004634 0x12c ../semafor_bsp/\libhal_bsp.a(alt_alarm_start.o) + 0x0000000000004634 alt_alarm_start + .text 0x0000000000004760 0xe0 ../semafor_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + 0x000000000000479c alt_dev_llist_insert + .text 0x0000000000004840 0x60 ../semafor_bsp/\libhal_bsp.a(alt_do_ctors.o) + 0x0000000000004840 _do_ctors + .text 0x00000000000048a0 0x60 ../semafor_bsp/\libhal_bsp.a(alt_do_dtors.o) + 0x00000000000048a0 _do_dtors + .text 0x0000000000004900 0x1b0 ../semafor_bsp/\libhal_bsp.a(alt_iic.o) + 0x0000000000004900 alt_ic_isr_register + 0x0000000000004950 alt_ic_irq_enable + 0x00000000000049d8 alt_ic_irq_disable + 0x0000000000004a64 alt_ic_irq_enabled + .text 0x0000000000004ab0 0xf0 ../semafor_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + 0x0000000000004ab0 alt_iic_isr_register + .text 0x0000000000004ba0 0x160 ../semafor_bsp/\libhal_bsp.a(alt_io_redirect.o) + 0x0000000000004c84 alt_io_redirect + .text 0x0000000000004d00 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + .text 0x0000000000004d00 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o) + .text 0x0000000000004d00 0x0 ../semafor_bsp/\libhal_bsp.a(alt_irq_vars.o) + .text 0x0000000000004d00 0x284 ../semafor_bsp/\libhal_bsp.a(alt_open.o) + 0x0000000000004e28 open + .text 0x0000000000004f84 0x1a4 ../semafor_bsp/\libhal_bsp.a(alt_tick.o) + 0x0000000000004f84 alt_alarm_stop + 0x0000000000005020 alt_tick + .text 0x0000000000005128 0x24 ../semafor_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) + 0x0000000000005128 altera_nios2_gen2_irq_init + .text 0x000000000000514c 0x0 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + .text 0x000000000000514c 0x90 ../semafor_bsp/\libhal_bsp.a(alt_find_dev.o) + 0x000000000000514c alt_find_dev + .text 0x00000000000051dc 0x108 ../semafor_bsp/\libhal_bsp.a(alt_find_file.o) + 0x00000000000051dc alt_find_file + .text 0x00000000000052e4 0xc4 ../semafor_bsp/\libhal_bsp.a(alt_get_fd.o) + 0x00000000000052e4 alt_get_fd + .text 0x00000000000053a8 0x9c ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + 0x00000000000053a8 alt_exception_cause_generated_bad_addr + .text 0x0000000000005444 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + .text.atexit 0x0000000000005444 0x14 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + 0x0000000000005444 atexit + .text 0x0000000000005458 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + .text.exit 0x0000000000005458 0x38 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + 0x0000000000005458 exit + .text 0x0000000000005490 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + .text.memcmp 0x0000000000005490 0x7c c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + 0x0000000000005490 memcmp + .text 0x000000000000550c 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + .text.__register_exitproc + 0x000000000000550c 0x118 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + 0x000000000000550c __register_exitproc + .text 0x0000000000005624 0x0 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + .text.__call_exitprocs + 0x0000000000005624 0x180 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + 0x0000000000005624 __call_exitprocs + .text 0x00000000000057a4 0x34 ../semafor_bsp/\libhal_bsp.a(alt_exit.o) + 0x00000000000057a4 _exit + *(.gnu.warning.*) + *(.fini) + [!provide] PROVIDE (__etext, ABSOLUTE (.)) + [!provide] PROVIDE (_etext, ABSOLUTE (.)) + [!provide] PROVIDE (etext, ABSOLUTE (.)) + *(.eh_frame_hdr) + 0x00000000000057d8 . = ALIGN (0x4) + [!provide] PROVIDE (__preinit_array_start, ABSOLUTE (.)) + *(.preinit_array) + [!provide] PROVIDE (__preinit_array_end, ABSOLUTE (.)) + [!provide] PROVIDE (__init_array_start, ABSOLUTE (.)) + *(.init_array) + [!provide] PROVIDE (__init_array_end, ABSOLUTE (.)) + [!provide] PROVIDE (__fini_array_start, ABSOLUTE (.)) + *(.fini_array) + [!provide] PROVIDE (__fini_array_end, ABSOLUTE (.)) + *(.eh_frame) + *(.gcc_except_table .gcc_except_table.*) + *(.dynamic) + 0x00000000000057d8 PROVIDE (__CTOR_LIST__, ABSOLUTE (.)) + *(.ctors) + *(SORT(.ctors.*)) + 0x00000000000057d8 PROVIDE (__CTOR_END__, ABSOLUTE (.)) + 0x00000000000057d8 PROVIDE (__DTOR_LIST__, ABSOLUTE (.)) + *(.dtors) + *(SORT(.dtors.*)) + 0x00000000000057d8 PROVIDE (__DTOR_END__, ABSOLUTE (.)) + *(.jcr) + 0x00000000000057d8 . = ALIGN (0x4) + +.rodata 0x00000000000057d8 0x4c + [!provide] PROVIDE (__ram_rodata_start, ABSOLUTE (.)) + 0x00000000000057d8 . = ALIGN (0x4) + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata 0x00000000000057d8 0x16 obj/default/sem.o + 0x00000000000057d8 divisors + *fill* 0x00000000000057ee 0x2 + .rodata.str1.4 + 0x00000000000057f0 0x2 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-puts.o) + *fill* 0x00000000000057f2 0x2 + .rodata.str1.4 + 0x00000000000057f4 0x4 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c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + .debug_loc 0x000000000000490c 0x1ce c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_alt_sim_info + *(.debug_alt_sim_info) + 0x0000000000020000 __alt_data_end = 0x20000 + 0x0000000000020000 PROVIDE (__alt_stack_pointer, __alt_data_end) + [!provide] PROVIDE (__alt_stack_limit, __alt_stack_base) + 0x00000000000073e4 PROVIDE (__alt_heap_start, end) + 0x0000000000020000 PROVIDE (__alt_heap_limit, 0x20000) +OUTPUT(RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf elf32-littlenios2) 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+ .debug_ranges 0x0000000000000548 0x30 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_ranges 0x0000000000000578 0x18 ../semafor_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + .debug_ranges 0x0000000000000590 0x28 ../semafor_bsp/\libhal_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00000000000005b8 0x10 ../semafor_bsp/\libhal_bsp.a(alt_irq_handler.o) + .debug_ranges 0x00000000000005c8 0x30 ../semafor_bsp/\libhal_bsp.a(alt_exception_entry.o) + .debug_ranges 0x00000000000005f8 0x18 ../semafor_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + .debug_ranges 0x0000000000000610 0x10 c:/software/intelfpga_lite/18.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + .debug_ranges 0x0000000000000620 0x10 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index 0000000..c083ff6 --- /dev/null +++ b/Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump @@ -0,0 +1,8377 @@ + +RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf: file format elf32-littlenios2 +RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf +architecture: nios2:r1, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x00000230 + +Program Header: + LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + LOAD off 0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12 + filesz 0x00007270 memsz 0x000073c4 flags rwx + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 00000000 00000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 00000210 00000020 00000020 00001020 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 000055a8 00000230 00000230 00001230 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 0000004c 000057d8 000057d8 000067d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 00001a6c 00005824 00005824 00006824 2**2 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00000154 00007290 00007290 00008290 2**2 + ALLOC, SMALL_DATA + 6 .mem 00000000 000073e4 000073e4 00008290 2**0 + CONTENTS + 7 .comment 00000023 00000000 00000000 00008290 2**0 + CONTENTS, READONLY + 8 .debug_aranges 000009f0 00000000 00000000 000082b8 2**3 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 00016367 00000000 00000000 00008ca8 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00005fe5 00000000 00000000 0001f00f 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 00006941 00000000 00000000 00024ff4 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_frame 00001504 00000000 00000000 0002b938 2**2 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 00002692 00000000 00000000 0002ce3c 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 00004ada 00000000 00000000 0002f4ce 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00000680 00000000 00000000 00033fa8 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .thread_model 00000003 00000000 00000000 000368be 2**0 + CONTENTS, READONLY + 17 .cpu 00000003 00000000 00000000 000368c1 2**0 + CONTENTS, READONLY + 18 .qsys 00000001 00000000 00000000 000368c4 2**0 + CONTENTS, READONLY + 19 .simulation_enabled 00000001 00000000 00000000 000368c5 2**0 + CONTENTS, READONLY + 20 .stderr_dev 00000009 00000000 00000000 000368c6 2**0 + CONTENTS, READONLY + 21 .stdin_dev 00000009 00000000 00000000 000368cf 2**0 + CONTENTS, READONLY + 22 .stdout_dev 00000009 00000000 00000000 000368d8 2**0 + CONTENTS, READONLY + 23 .sopc_system_name 00000006 00000000 00000000 000368e1 2**0 + CONTENTS, READONLY + 24 .quartus_project_dir 00000021 00000000 00000000 000368e7 2**0 + CONTENTS, READONLY + 25 .jdi 0000438e 00000000 00000000 00036908 2**0 + CONTENTS, READONLY + 26 .sopcinfo 0003cf5b 00000000 00000000 0003ac96 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +00000000 l d .entry 00000000 .entry +00000020 l d .exceptions 00000000 .exceptions +00000230 l d .text 00000000 .text +000057d8 l d .rodata 00000000 .rodata +00005824 l d .rwdata 00000000 .rwdata +00007290 l d .bss 00000000 .bss +000073e4 l d .mem 00000000 .mem +00000000 l d .comment 00000000 .comment +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l df *ABS* 00000000 ../semafor_bsp//obj/HAL/src/crt0.o +00000244 l .text 00000000 alt_after_alt_main +00000000 l df *ABS* 00000000 alt_irq_handler.c +00000000 l df *ABS* 00000000 alt_instruction_exception_entry.c +00000000 l df *ABS* 00000000 sem.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 findfp.c +0000049c l F .text 00000008 __fp_unlock +000004b0 l F .text 0000019c __sinit.part.1 +0000064c l F .text 00000008 __fp_lock +00000000 l df *ABS* 00000000 fvwrite.c +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 impure.c +00005824 l O .rwdata 00000424 impure_data +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 memcpy.c +00000000 l df *ABS* 00000000 memmove.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 fclose.c +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 int_errno.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 lib2-divmod.c +00000000 l df *ABS* 00000000 lib2-mul.c +00000000 l df *ABS* 00000000 alt_close.c +0000313c l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_dcache_flush.c +00000000 l df *ABS* 00000000 alt_dev.c +00003278 l F .text 0000002c alt_dev_null_write +00000000 l df *ABS* 00000000 alt_errno.c +00000000 l df *ABS* 00000000 alt_fstat.c +000032a4 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_isatty.c +00003398 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_lseek.c +00003480 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_main.c +00000000 l df *ABS* 00000000 alt_malloc_lock.c +00000000 l df *ABS* 00000000 alt_read.c +0000365c l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_release_fd.c +00000000 l df *ABS* 00000000 alt_sbrk.c +00007280 l O .rwdata 00000004 heap_end +00000000 l df *ABS* 00000000 alt_write.c +000038d0 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_sys_init.c +00003a0c l F .text 00000034 alt_dev_reg +000061f8 l O .rwdata 00001060 jtag_uart +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_fd.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_init.c +00003cfc l F .text 0000020c altera_avalon_jtag_uart_irq +00003f08 l F .text 000000a0 altera_avalon_jtag_uart_timeout +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_ioctl.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_read.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_write.c +00000000 l df *ABS* 00000000 altera_avalon_timer_sc.c +00004540 l F .text 00000078 alt_avalon_timer_sc_irq +00000000 l df *ABS* 00000000 alt_alarm_start.c +00000000 l df *ABS* 00000000 alt_dev_llist_insert.c +00004760 l F .text 0000003c alt_get_errno +00000000 l df *ABS* 00000000 alt_do_ctors.c +00000000 l df *ABS* 00000000 alt_do_dtors.c +00000000 l df *ABS* 00000000 alt_iic.c +00000000 l df *ABS* 00000000 alt_iic_isr_register.c +00000000 l df *ABS* 00000000 alt_io_redirect.c +00004ba0 l F .text 000000e4 alt_open_fd +00000000 l df *ABS* 00000000 alt_irq_vars.c +00000000 l df *ABS* 00000000 alt_open.c +00004d00 l F .text 0000003c alt_get_errno +00004d3c l F .text 000000ec alt_file_locked +00000000 l df *ABS* 00000000 alt_tick.c +00000000 l df *ABS* 00000000 altera_nios2_gen2_irq.c +00000000 l df *ABS* 00000000 alt_find_dev.c +00000000 l df *ABS* 00000000 alt_find_file.c +00000000 l df *ABS* 00000000 alt_get_fd.c +00000000 l df *ABS* 00000000 atexit.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 memcmp.c +00000000 l df *ABS* 00000000 __atexit.c +00000000 l df *ABS* 00000000 __call_atexit.c +00000000 l df *ABS* 00000000 alt_exit.c +000072b8 g O .bss 00000004 alt_instruction_exception_handler +00002f0c g F .text 00000054 _isatty_r +00003598 g F .text 0000007c alt_main +00000330 g F .text 000000c0 _puts_r +000072e4 g O .bss 00000100 alt_irq +00002c34 g F .text 00000060 _lseek_r +000073e4 g *ABS* 00000000 __alt_heap_start +000021e8 g F .text 0000005c __sseek +000007fc g F .text 00000010 __sinit +00000654 g F .text 00000078 __sfmoreglue +00003638 g F .text 00000024 __malloc_unlock +000057d8 g O .rodata 00000010 divisors +000018d4 g F .text 0000015c memmove +000007e4 g F .text 00000018 _cleanup +00005128 g F .text 00000024 altera_nios2_gen2_irq_init +00000000 g F .entry 0000000c __reset +00002eb0 g F .text 0000005c _fstat_r +0000729c g O .bss 00000004 errno +00002164 g F .text 00000008 __seofread +000072a4 g O .bss 00000004 alt_argv +0000f258 g *ABS* 00000000 _gp +00006078 g O .rwdata 00000180 alt_fd_list +0000514c g F .text 00000090 alt_find_dev +0000178c g F .text 00000148 memcpy +000004a4 g F .text 0000000c _cleanup_r +00004c84 g F .text 0000007c alt_io_redirect +000057d8 g *ABS* 00000000 __DTOR_END__ +000003f0 g F .text 00000014 puts +000053a8 g F .text 0000009c alt_exception_cause_generated_bad_addr +00004100 g F .text 0000021c altera_avalon_jtag_uart_read +00003058 g F .text 00000064 .hidden __udivsi3 +000033d4 g F .text 000000ac isatty +00007298 g O .bss 00000004 __malloc_top_pad +0000084c g F .text 000004c8 __sfvwrite_r +000020bc g F .text 00000054 _sbrk_r +00002e50 g F .text 00000060 _read_r +00003250 g F .text 00000028 alt_dcache_flush +00007278 g O .rwdata 00000004 alt_max_fd +00002454 g F .text 000000f0 _fclose_r +000027d0 g F .text 00000030 fflush +00007294 g O .bss 00000004 __malloc_max_sbrked_mem +000034bc g F .text 000000dc lseek +00007258 g O .rwdata 00000004 _global_impure_ptr +00001b58 g F .text 00000564 _realloc_r +000073e4 g *ABS* 00000000 __bss_end +00004ab0 g F .text 000000f0 alt_iic_isr_register +00005020 g F .text 00000108 alt_tick +0000081c g F .text 00000018 __fp_lock_all +00004a64 g F .text 0000004c alt_ic_irq_enabled +00000000 g *ABS* 00000000 __alt_mem_mem +00004f84 g F .text 0000009c alt_alarm_stop +000072ac g O .bss 00000004 alt_irq_active +000000fc g F .exceptions 000000d4 alt_irq_handler +00006050 g O .rwdata 00000028 alt_dev_null +00007270 g O .rwdata 00000008 alt_dev_list +0000390c g F .text 00000100 write +000032e0 g F .text 000000b8 fstat +000030bc g F .text 00000058 .hidden __umodsi3 +000073e4 g *ABS* 00000000 end +00003c3c g F .text 000000c0 altera_avalon_jtag_uart_init +000001d0 g F .exceptions 00000060 alt_instruction_exception_entry +000057d8 g *ABS* 00000000 __CTOR_LIST__ +00020000 g *ABS* 00000000 __alt_stack_pointer +000045b8 g F .text 0000007c alt_avalon_timer_sc_init +0000431c g F .text 00000224 altera_avalon_jtag_uart_write +0000080c g F .text 00000004 __sfp_lock_acquire +000016a8 g F .text 000000e4 memchr +00002924 g F .text 00000310 _free_r +00005624 g F .text 00000180 __call_exitprocs +00007260 g O .rwdata 00000004 __malloc_sbrk_base +00000230 g F .text 00000018 _start +000072b0 g O .bss 00000004 _alt_tick_rate +000072b4 g O .bss 00000004 _alt_nticks +00003698 g F .text 00000104 read +00003a78 g F .text 00000060 alt_sys_init +0000550c g F .text 00000118 __register_exitproc +00003fa8 g F .text 00000068 altera_avalon_jtag_uart_close +00003114 g F .text 00000028 .hidden __mulsi3 +000072bc g O .bss 00000028 __malloc_current_mallinfo +00003ad8 g F .text 00000060 altera_avalon_jtag_uart_read_fd +000052e4 g F .text 000000c4 alt_get_fd +00002400 g F .text 00000054 _close_r +00005490 g F .text 0000007c memcmp +00003b98 g F .text 00000050 altera_avalon_jtag_uart_close_fd +000073e4 g *ABS* 00000000 __alt_stack_base +00003be8 g F .text 00000054 altera_avalon_jtag_uart_ioctl_fd +000022ac g F .text 00000154 __swsetup_r +000006cc g F .text 00000118 __sfp +00005c48 g O .rwdata 00000408 __malloc_av_ +00000818 g F .text 00000004 __sinit_lock_release +00002110 g F .text 00000054 __sread +000051dc g F .text 00000108 alt_find_file +0000479c g F .text 000000a4 alt_dev_llist_insert +00003614 g F .text 00000024 __malloc_lock +00003820 g F .text 000000b0 sbrk +00002774 g F .text 0000005c _fflush_r +00007290 g *ABS* 00000000 __bss_start +00001a30 g F .text 00000128 memset +00000248 g F .text 000000e8 main +000072a8 g O .bss 00000004 alt_envp +00007290 g O .bss 00000004 __malloc_max_total_mem +00003b38 g F .text 00000060 altera_avalon_jtag_uart_write_fd +00002244 g F .text 00000008 __sclose +00020000 g *ABS* 00000000 __alt_heap_limit +00002544 g F .text 00000014 fclose +00000e9c g F .text 0000080c _malloc_r +0000727c g O .rwdata 00000004 alt_errno +00000d14 g F .text 000000c4 _fwalk +00002f60 g F .text 00000084 .hidden __divsi3 +00002800 g F .text 00000124 _malloc_trim_r +000057d8 g *ABS* 00000000 __CTOR_END__ +000057d8 g *ABS* 00000000 __DTOR_LIST__ +00003a40 g F .text 00000038 alt_irq_init +0000379c g F .text 00000084 alt_release_fd +00005444 g F .text 00000014 atexit +0000224c g F .text 00000060 _write_r +0000725c g O .rwdata 00000004 _impure_ptr +000072a0 g O .bss 00000004 alt_argc +00002558 g F .text 0000021c __sflush_r +000048a0 g F .text 00000060 _do_dtors +00000020 g .exceptions 00000000 alt_irq_entry +00000834 g F .text 00000018 __fp_unlock_all +00007268 g O .rwdata 00000008 alt_fs_list +00004900 g F .text 00000050 alt_ic_isr_register +00007290 g *ABS* 00000000 _edata +000073e4 g *ABS* 00000000 _end +00004010 g F .text 000000f0 altera_avalon_jtag_uart_ioctl +000049d8 g F .text 0000008c alt_ic_irq_disable +0000216c g F .text 0000007c __swrite +00007264 g O .rwdata 00000004 __malloc_trim_threshold +00005458 g F .text 00000038 exit +00000dd8 g F .text 000000c4 _fwalk_reent +00002fe4 g F .text 00000074 .hidden __modsi3 +00020000 g *ABS* 00000000 __alt_data_end +00000020 g F .exceptions 00000000 alt_exception +00000810 g F .text 00000004 __sfp_lock_release +000057a4 g F .text 00000034 _exit +00004634 g F .text 0000012c alt_alarm_start +00002c94 g F .text 000001bc __smakebuf_r +00000404 g F .text 00000098 strlen +00004e28 g F .text 0000015c open +00007284 g O .rwdata 00000004 alt_priority_mask +00004950 g F .text 00000088 alt_ic_irq_enable +00007288 g O .rwdata 00000008 alt_alarm_list +00004840 g F .text 00000060 _do_ctors +00003178 g F .text 000000d8 close +00000814 g F .text 00000004 __sinit_lock_acquire + + + +Disassembly of section .entry: + +00000000 <__reset>: + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + 0: 00400034 movhi at,0 + ori r1, r1, %lo(_start) + 4: 08408c14 ori at,at,560 + jmp r1 + 8: 0800683a jmp at + ... + +Disassembly of section .exceptions: + +00000020 : + +#else /* ALT_EXCEPTION_STACK disabled */ + /* + * Reserve space on normal stack for registers about to be pushed. + */ + addi sp, sp, -76 + 20: deffed04 addi sp,sp,-76 + * documentation for details). + * + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + stw ra, 0(sp) + 24: dfc00015 stw ra,0(sp) + stw r1, 8(sp) + 28: d8400215 stw at,8(sp) + stw r2, 12(sp) + 2c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 30: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 34: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 38: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 3c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 40: d9c00815 stw r7,32(sp) + rdctl r5, estatus /* Read early to avoid usage stall */ + 44: 000b307a rdctl r5,estatus + stw r8, 36(sp) + 48: da000915 stw r8,36(sp) + stw r9, 40(sp) + 4c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 50: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 54: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 58: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 5c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 60: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 64: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 68: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 6c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 70: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 74: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 78: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 7c: 10000326 beq r2,zero,8c + beq r4, zero, .Lnot_irq + 80: 20000226 beq r4,zero,8c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 84: 00000fc0 call fc + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 88: 00000706 br a8 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */ + 8c: df401215 stw ea,72(sp) +.Lunknown_16bit: + addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */ + stw r4, 72(sp) + +#else /* CDX is not Enabled and all instructions are 32bits */ + ldw r2, -4(ea) /* Instruction value that caused exception */ + 90: e8bfff17 ldw r2,-4(ea) + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + 94: e93fff04 addi r4,ea,-4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + 98: 00001d00 call 1d0 + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + 9c: 1000021e bne r2,zero,a8 + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + a0: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + a4: dbc01215 stw r15,72(sp) + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + a8: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ac: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + b0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + b4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + b8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + bc: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + c0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + c4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + c8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + cc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + d0: d9c00817 ldw r7,32(sp) + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw r8, 36(sp) + d4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + d8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + dc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + e0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + e4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + e8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + ec: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + f0: dbc01017 ldw r15,64(sp) + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif /* ALT_STACK_CHECK */ + ldw sp, 76(sp) +#else /* ALT_EXCEPTION_STACK disabled */ + addi sp, sp, 76 + f4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + f8: ef80083a eret + +000000fc : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + fc: defff904 addi sp,sp,-28 + 100: dfc00615 stw ra,24(sp) + 104: df000515 stw fp,20(sp) + 108: df000504 addi fp,sp,20 + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + 10c: 0001883a nop +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 110: 0005313a rdctl r2,ipending + 114: e0bffe15 stw r2,-8(fp) + + return active; + 118: e0bffe17 ldw r2,-8(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 11c: e0bffb15 stw r2,-20(fp) + + do + { + i = 0; + 120: e03ffd15 stw zero,-12(fp) + mask = 1; + 124: 00800044 movi r2,1 + 128: e0bffc15 stw r2,-16(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 12c: e0fffb17 ldw r3,-20(fp) + 130: e0bffc17 ldw r2,-16(fp) + 134: 1884703a and r2,r3,r2 + 138: 10001426 beq r2,zero,18c + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); + 13c: 00800034 movhi r2,0 + 140: 109cb904 addi r2,r2,29412 + 144: e0fffd17 ldw r3,-12(fp) + 148: 180690fa slli r3,r3,3 + 14c: 10c5883a add r2,r2,r3 + 150: 10c00017 ldw r3,0(r2) + 154: 00800034 movhi r2,0 + 158: 109cb904 addi r2,r2,29412 + 15c: e13ffd17 ldw r4,-12(fp) + 160: 200890fa slli r4,r4,3 + 164: 1105883a add r2,r2,r4 + 168: 10800104 addi r2,r2,4 + 16c: 10800017 ldw r2,0(r2) + 170: 1009883a mov r4,r2 + 174: 183ee83a callr r3 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + 178: 0001883a nop +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 17c: 0005313a rdctl r2,ipending + 180: e0bfff15 stw r2,-4(fp) + + return active; + 184: e0bfff17 ldw r2,-4(fp) + 188: 00000706 br 1a8 + } + mask <<= 1; + 18c: e0bffc17 ldw r2,-16(fp) + 190: 1085883a add r2,r2,r2 + 194: e0bffc15 stw r2,-16(fp) + i++; + 198: e0bffd17 ldw r2,-12(fp) + 19c: 10800044 addi r2,r2,1 + 1a0: e0bffd15 stw r2,-12(fp) + + } while (1); + 1a4: 003fe106 br 12c <__alt_data_end+0xfffe012c> + + active = alt_irq_pending (); + 1a8: e0bffb15 stw r2,-20(fp) + + } while (active); + 1ac: e0bffb17 ldw r2,-20(fp) + 1b0: 103fdb1e bne r2,zero,120 <__alt_data_end+0xfffe0120> + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); + 1b4: 0001883a nop +} + 1b8: 0001883a nop + 1bc: e037883a mov sp,fp + 1c0: dfc00117 ldw ra,4(sp) + 1c4: df000017 ldw fp,0(sp) + 1c8: dec00204 addi sp,sp,8 + 1cc: f800283a ret + +000001d0 : + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int +alt_instruction_exception_entry (alt_u32 exception_pc) +{ + 1d0: defffb04 addi sp,sp,-20 + 1d4: dfc00415 stw ra,16(sp) + 1d8: df000315 stw fp,12(sp) + 1dc: df000304 addi fp,sp,12 + 1e0: e13fff15 stw r4,-4(fp) + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + 1e4: 00bfffc4 movi r2,-1 + 1e8: e0bffd15 stw r2,-12(fp) + badaddr = 0; + 1ec: e03ffe15 stw zero,-8(fp) +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + 1f0: d0a01817 ldw r2,-32672(gp) + 1f4: 10000726 beq r2,zero,214 + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + 1f8: d0a01817 ldw r2,-32672(gp) + 1fc: e0fffd17 ldw r3,-12(fp) + 200: e1bffe17 ldw r6,-8(fp) + 204: e17fff17 ldw r5,-4(fp) + 208: 1809883a mov r4,r3 + 20c: 103ee83a callr r2 + 210: 00000206 br 21c + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); + 214: 003da03a break 0 + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; + 218: 0005883a mov r2,zero +} + 21c: e037883a mov sp,fp + 220: dfc00117 ldw ra,4(sp) + 224: df000017 ldw fp,0(sp) + 228: dec00204 addi sp,sp,8 + 22c: f800283a ret + +Disassembly of section .text: + +00000230 <_start>: + + /* + * Now that the caches are initialized, set up the stack pointer and global pointer. + * The values provided by the linker are assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 230: 06c000b4 movhi sp,2 + ori sp, sp, %lo(__alt_stack_pointer) + 234: dec00014 ori sp,sp,0 + movhi gp, %hi(_gp) + 238: 06800034 movhi gp,0 + ori gp, gp, %lo(_gp) + 23c: d6bc9614 ori gp,gp,62040 + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 240: 00035980 call 3598 + +00000244 : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 244: 003fff06 br 244 <__alt_data_end+0xfffe0244> + +00000248
: + {150,250,200,10}, + {250,250,250,10} +}; + +int main() +{ + 248: defffa04 addi sp,sp,-24 + 24c: dfc00515 stw ra,20(sp) + 250: df000415 stw fp,16(sp) + 254: df000404 addi fp,sp,16 + int i,j; + volatile alt_u32 *p; + alt_u32 tmp; + + //program divisors + p = (alt_u32*) SEM_RAM_SLAVE_BASE; + 258: 008000b4 movhi r2,2 + 25c: 10840804 addi r2,r2,4128 + 260: e0bffe15 stw r2,-8(fp) + for (i=0; i + { + tmp = 0; + 26c: e03fff15 stw zero,-4(fp) + for (j=TIME_STATES; j>0; j--) + 270: 00800104 movi r2,4 + 274: e0bffd15 stw r2,-12(fp) + 278: 00001206 br 2c4 + { + tmp = (tmp << 8) | divisors[i][j-1]; + 27c: e0bfff17 ldw r2,-4(fp) + 280: 1008923a slli r4,r2,8 + 284: e0bffd17 ldw r2,-12(fp) + 288: 117fffc4 addi r5,r2,-1 + 28c: 00800034 movhi r2,0 + 290: 1095f604 addi r2,r2,22488 + 294: e0fffc17 ldw r3,-16(fp) + 298: 18c7883a add r3,r3,r3 + 29c: 18c7883a add r3,r3,r3 + 2a0: 10c5883a add r2,r2,r3 + 2a4: 1145883a add r2,r2,r5 + 2a8: 10800003 ldbu r2,0(r2) + 2ac: 10803fcc andi r2,r2,255 + 2b0: 2084b03a or r2,r4,r2 + 2b4: e0bfff15 stw r2,-4(fp) + //program divisors + p = (alt_u32*) SEM_RAM_SLAVE_BASE; + for (i=0; i0; j--) + 2b8: e0bffd17 ldw r2,-12(fp) + 2bc: 10bfffc4 addi r2,r2,-1 + 2c0: e0bffd15 stw r2,-12(fp) + 2c4: e0bffd17 ldw r2,-12(fp) + 2c8: 00bfec16 blt zero,r2,27c <__alt_data_end+0xfffe027c> + { + tmp = (tmp << 8) | divisors[i][j-1]; + } + *p=tmp; + 2cc: e0bffe17 ldw r2,-8(fp) + 2d0: e0ffff17 ldw r3,-4(fp) + 2d4: 10c00015 stw r3,0(r2) + p++; + 2d8: e0bffe17 ldw r2,-8(fp) + 2dc: 10800104 addi r2,r2,4 + 2e0: e0bffe15 stw r2,-8(fp) + volatile alt_u32 *p; + alt_u32 tmp; + + //program divisors + p = (alt_u32*) SEM_RAM_SLAVE_BASE; + for (i=0; i + *p=tmp; + p++; + } + //since we use pointers (cached data access) to write divisor RAM, + //and not direct i/o access with IOWR, we need to flush cache + alt_dcache_flush(); + 2fc: 00032500 call 3250 + + //select timeset and run semafor + IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00); + 300: 0007883a mov r3,zero + 304: 008000b4 movhi r2,2 + 308: 10840d04 addi r2,r2,4148 + 30c: 10c00035 stwio r3,0(r2) + IOWR_ALTERA_AVALON_SEM_CTL(SEM_CTL_SLAVE_BASE,0x01); + 310: 00c00044 movi r3,1 + 314: 008000b4 movhi r2,2 + 318: 10840c04 addi r2,r2,4144 + 31c: 10c00035 stwio r3,0(r2) + + printf("Ready\n"); + 320: 01000034 movhi r4,0 + 324: 2115fa04 addi r4,r4,22504 + 328: 00003f00 call 3f0 + + while (1) + { + ; + } + 32c: 003fff06 br 32c <__alt_data_end+0xfffe032c> + +00000330 <_puts_r>: + 330: defff604 addi sp,sp,-40 + 334: dc000715 stw r16,28(sp) + 338: 2021883a mov r16,r4 + 33c: 2809883a mov r4,r5 + 340: dc400815 stw r17,32(sp) + 344: dfc00915 stw ra,36(sp) + 348: 2823883a mov r17,r5 + 34c: 00004040 call 404 + 350: 10c00044 addi r3,r2,1 + 354: d8800115 stw r2,4(sp) + 358: 00800034 movhi r2,0 + 35c: 1095fc04 addi r2,r2,22512 + 360: d8800215 stw r2,8(sp) + 364: 00800044 movi r2,1 + 368: d8800315 stw r2,12(sp) + 36c: 00800084 movi r2,2 + 370: dc400015 stw r17,0(sp) + 374: d8c00615 stw r3,24(sp) + 378: dec00415 stw sp,16(sp) + 37c: d8800515 stw r2,20(sp) + 380: 80000226 beq r16,zero,38c <_puts_r+0x5c> + 384: 80800e17 ldw r2,56(r16) + 388: 10001426 beq r2,zero,3dc <_puts_r+0xac> + 38c: 81400217 ldw r5,8(r16) + 390: 2880030b ldhu r2,12(r5) + 394: 10c8000c andi r3,r2,8192 + 398: 1800061e bne r3,zero,3b4 <_puts_r+0x84> + 39c: 29001917 ldw r4,100(r5) + 3a0: 00f7ffc4 movi r3,-8193 + 3a4: 10880014 ori r2,r2,8192 + 3a8: 20c6703a and r3,r4,r3 + 3ac: 2880030d sth r2,12(r5) + 3b0: 28c01915 stw r3,100(r5) + 3b4: d9800404 addi r6,sp,16 + 3b8: 8009883a mov r4,r16 + 3bc: 000084c0 call 84c <__sfvwrite_r> + 3c0: 1000091e bne r2,zero,3e8 <_puts_r+0xb8> + 3c4: 00800284 movi r2,10 + 3c8: dfc00917 ldw ra,36(sp) + 3cc: dc400817 ldw r17,32(sp) + 3d0: dc000717 ldw r16,28(sp) + 3d4: dec00a04 addi sp,sp,40 + 3d8: f800283a ret + 3dc: 8009883a mov r4,r16 + 3e0: 00007fc0 call 7fc <__sinit> + 3e4: 003fe906 br 38c <__alt_data_end+0xfffe038c> + 3e8: 00bfffc4 movi r2,-1 + 3ec: 003ff606 br 3c8 <__alt_data_end+0xfffe03c8> + +000003f0 : + 3f0: 00800034 movhi r2,0 + 3f4: 109c9704 addi r2,r2,29276 + 3f8: 200b883a mov r5,r4 + 3fc: 11000017 ldw r4,0(r2) + 400: 00003301 jmpi 330 <_puts_r> + +00000404 : + 404: 208000cc andi r2,r4,3 + 408: 10002026 beq r2,zero,48c + 40c: 20800007 ldb r2,0(r4) + 410: 10002026 beq r2,zero,494 + 414: 2005883a mov r2,r4 + 418: 00000206 br 424 + 41c: 10c00007 ldb r3,0(r2) + 420: 18001826 beq r3,zero,484 + 424: 10800044 addi r2,r2,1 + 428: 10c000cc andi r3,r2,3 + 42c: 183ffb1e bne r3,zero,41c <__alt_data_end+0xfffe041c> + 430: 10c00017 ldw r3,0(r2) + 434: 01ffbff4 movhi r7,65279 + 438: 39ffbfc4 addi r7,r7,-257 + 43c: 00ca303a nor r5,zero,r3 + 440: 01a02074 movhi r6,32897 + 444: 19c7883a add r3,r3,r7 + 448: 31a02004 addi r6,r6,-32640 + 44c: 1946703a and r3,r3,r5 + 450: 1986703a and r3,r3,r6 + 454: 1800091e bne r3,zero,47c + 458: 10800104 addi r2,r2,4 + 45c: 10c00017 ldw r3,0(r2) + 460: 19cb883a add r5,r3,r7 + 464: 00c6303a nor r3,zero,r3 + 468: 28c6703a and r3,r5,r3 + 46c: 1986703a and r3,r3,r6 + 470: 183ff926 beq r3,zero,458 <__alt_data_end+0xfffe0458> + 474: 00000106 br 47c + 478: 10800044 addi r2,r2,1 + 47c: 10c00007 ldb r3,0(r2) + 480: 183ffd1e bne r3,zero,478 <__alt_data_end+0xfffe0478> + 484: 1105c83a sub r2,r2,r4 + 488: f800283a ret + 48c: 2005883a mov r2,r4 + 490: 003fe706 br 430 <__alt_data_end+0xfffe0430> + 494: 0005883a mov r2,zero + 498: f800283a ret + +0000049c <__fp_unlock>: + 49c: 0005883a mov r2,zero + 4a0: f800283a ret + +000004a4 <_cleanup_r>: + 4a4: 01400034 movhi r5,0 + 4a8: 29491504 addi r5,r5,9300 + 4ac: 0000dd81 jmpi dd8 <_fwalk_reent> + +000004b0 <__sinit.part.1>: + 4b0: defff704 addi sp,sp,-36 + 4b4: 00c00034 movhi r3,0 + 4b8: dfc00815 stw ra,32(sp) + 4bc: ddc00715 stw r23,28(sp) + 4c0: dd800615 stw r22,24(sp) + 4c4: dd400515 stw r21,20(sp) + 4c8: dd000415 stw r20,16(sp) + 4cc: dcc00315 stw r19,12(sp) + 4d0: dc800215 stw r18,8(sp) + 4d4: dc400115 stw r17,4(sp) + 4d8: dc000015 stw r16,0(sp) + 4dc: 18c12904 addi r3,r3,1188 + 4e0: 24000117 ldw r16,4(r4) + 4e4: 20c00f15 stw r3,60(r4) + 4e8: 2080bb04 addi r2,r4,748 + 4ec: 00c000c4 movi r3,3 + 4f0: 20c0b915 stw r3,740(r4) + 4f4: 2080ba15 stw r2,744(r4) + 4f8: 2000b815 stw zero,736(r4) + 4fc: 05c00204 movi r23,8 + 500: 00800104 movi r2,4 + 504: 2025883a mov r18,r4 + 508: b80d883a mov r6,r23 + 50c: 81001704 addi r4,r16,92 + 510: 000b883a mov r5,zero + 514: 80000015 stw zero,0(r16) + 518: 80000115 stw zero,4(r16) + 51c: 80000215 stw zero,8(r16) + 520: 8080030d sth r2,12(r16) + 524: 80001915 stw zero,100(r16) + 528: 8000038d sth zero,14(r16) + 52c: 80000415 stw zero,16(r16) + 530: 80000515 stw zero,20(r16) + 534: 80000615 stw zero,24(r16) + 538: 0001a300 call 1a30 + 53c: 05800034 movhi r22,0 + 540: 94400217 ldw r17,8(r18) + 544: 05400034 movhi r21,0 + 548: 05000034 movhi r20,0 + 54c: 04c00034 movhi r19,0 + 550: b5884404 addi r22,r22,8464 + 554: ad485b04 addi r21,r21,8556 + 558: a5087a04 addi r20,r20,8680 + 55c: 9cc89104 addi r19,r19,8772 + 560: 85800815 stw r22,32(r16) + 564: 85400915 stw r21,36(r16) + 568: 85000a15 stw r20,40(r16) + 56c: 84c00b15 stw r19,44(r16) + 570: 84000715 stw r16,28(r16) + 574: 00800284 movi r2,10 + 578: 8880030d sth r2,12(r17) + 57c: 00800044 movi r2,1 + 580: b80d883a mov r6,r23 + 584: 89001704 addi r4,r17,92 + 588: 000b883a mov r5,zero + 58c: 88000015 stw zero,0(r17) + 590: 88000115 stw zero,4(r17) + 594: 88000215 stw zero,8(r17) + 598: 88001915 stw zero,100(r17) + 59c: 8880038d sth r2,14(r17) + 5a0: 88000415 stw zero,16(r17) + 5a4: 88000515 stw zero,20(r17) + 5a8: 88000615 stw zero,24(r17) + 5ac: 0001a300 call 1a30 + 5b0: 94000317 ldw r16,12(r18) + 5b4: 00800484 movi r2,18 + 5b8: 8c400715 stw r17,28(r17) + 5bc: 8d800815 stw r22,32(r17) + 5c0: 8d400915 stw r21,36(r17) + 5c4: 8d000a15 stw r20,40(r17) + 5c8: 8cc00b15 stw r19,44(r17) + 5cc: 8080030d sth r2,12(r16) + 5d0: 00800084 movi r2,2 + 5d4: 80000015 stw zero,0(r16) + 5d8: 80000115 stw zero,4(r16) + 5dc: 80000215 stw zero,8(r16) + 5e0: 80001915 stw zero,100(r16) + 5e4: 8080038d sth r2,14(r16) + 5e8: 80000415 stw zero,16(r16) + 5ec: 80000515 stw zero,20(r16) + 5f0: 80000615 stw zero,24(r16) + 5f4: b80d883a mov r6,r23 + 5f8: 000b883a mov r5,zero + 5fc: 81001704 addi r4,r16,92 + 600: 0001a300 call 1a30 + 604: 00800044 movi r2,1 + 608: 84000715 stw r16,28(r16) + 60c: 85800815 stw r22,32(r16) + 610: 85400915 stw r21,36(r16) + 614: 85000a15 stw r20,40(r16) + 618: 84c00b15 stw r19,44(r16) + 61c: 90800e15 stw r2,56(r18) + 620: dfc00817 ldw ra,32(sp) + 624: ddc00717 ldw r23,28(sp) + 628: dd800617 ldw r22,24(sp) + 62c: dd400517 ldw r21,20(sp) + 630: dd000417 ldw r20,16(sp) + 634: dcc00317 ldw r19,12(sp) + 638: dc800217 ldw r18,8(sp) + 63c: dc400117 ldw r17,4(sp) + 640: dc000017 ldw r16,0(sp) + 644: dec00904 addi sp,sp,36 + 648: f800283a ret + +0000064c <__fp_lock>: + 64c: 0005883a mov r2,zero + 650: f800283a ret + +00000654 <__sfmoreglue>: + 654: defffc04 addi sp,sp,-16 + 658: dc800215 stw r18,8(sp) + 65c: 2825883a mov r18,r5 + 660: dc000015 stw r16,0(sp) + 664: 01401a04 movi r5,104 + 668: 2021883a mov r16,r4 + 66c: 913fffc4 addi r4,r18,-1 + 670: dfc00315 stw ra,12(sp) + 674: dc400115 stw r17,4(sp) + 678: 00031140 call 3114 <__mulsi3> + 67c: 8009883a mov r4,r16 + 680: 11401d04 addi r5,r2,116 + 684: 1023883a mov r17,r2 + 688: 0000e9c0 call e9c <_malloc_r> + 68c: 1021883a mov r16,r2 + 690: 10000726 beq r2,zero,6b0 <__sfmoreglue+0x5c> + 694: 11000304 addi r4,r2,12 + 698: 10000015 stw zero,0(r2) + 69c: 14800115 stw r18,4(r2) + 6a0: 11000215 stw r4,8(r2) + 6a4: 89801a04 addi r6,r17,104 + 6a8: 000b883a mov r5,zero + 6ac: 0001a300 call 1a30 + 6b0: 8005883a mov r2,r16 + 6b4: dfc00317 ldw ra,12(sp) + 6b8: dc800217 ldw r18,8(sp) + 6bc: dc400117 ldw r17,4(sp) + 6c0: dc000017 ldw r16,0(sp) + 6c4: dec00404 addi sp,sp,16 + 6c8: f800283a ret + +000006cc <__sfp>: + 6cc: defffb04 addi sp,sp,-20 + 6d0: dc000015 stw r16,0(sp) + 6d4: 04000034 movhi r16,0 + 6d8: 841c9604 addi r16,r16,29272 + 6dc: dcc00315 stw r19,12(sp) + 6e0: 2027883a mov r19,r4 + 6e4: 81000017 ldw r4,0(r16) + 6e8: dfc00415 stw ra,16(sp) + 6ec: dc800215 stw r18,8(sp) + 6f0: 20800e17 ldw r2,56(r4) + 6f4: dc400115 stw r17,4(sp) + 6f8: 1000021e bne r2,zero,704 <__sfp+0x38> + 6fc: 00004b00 call 4b0 <__sinit.part.1> + 700: 81000017 ldw r4,0(r16) + 704: 2480b804 addi r18,r4,736 + 708: 047fffc4 movi r17,-1 + 70c: 91000117 ldw r4,4(r18) + 710: 94000217 ldw r16,8(r18) + 714: 213fffc4 addi r4,r4,-1 + 718: 20000a16 blt r4,zero,744 <__sfp+0x78> + 71c: 8080030f ldh r2,12(r16) + 720: 10000c26 beq r2,zero,754 <__sfp+0x88> + 724: 80c01d04 addi r3,r16,116 + 728: 00000206 br 734 <__sfp+0x68> + 72c: 18bfe60f ldh r2,-104(r3) + 730: 10000826 beq r2,zero,754 <__sfp+0x88> + 734: 213fffc4 addi r4,r4,-1 + 738: 1c3ffd04 addi r16,r3,-12 + 73c: 18c01a04 addi r3,r3,104 + 740: 247ffa1e bne r4,r17,72c <__alt_data_end+0xfffe072c> + 744: 90800017 ldw r2,0(r18) + 748: 10001d26 beq r2,zero,7c0 <__sfp+0xf4> + 74c: 1025883a mov r18,r2 + 750: 003fee06 br 70c <__alt_data_end+0xfffe070c> + 754: 00bfffc4 movi r2,-1 + 758: 8080038d sth r2,14(r16) + 75c: 00800044 movi r2,1 + 760: 8080030d sth r2,12(r16) + 764: 80001915 stw zero,100(r16) + 768: 80000015 stw zero,0(r16) + 76c: 80000215 stw zero,8(r16) + 770: 80000115 stw zero,4(r16) + 774: 80000415 stw zero,16(r16) + 778: 80000515 stw zero,20(r16) + 77c: 80000615 stw zero,24(r16) + 780: 01800204 movi r6,8 + 784: 000b883a mov r5,zero + 788: 81001704 addi r4,r16,92 + 78c: 0001a300 call 1a30 + 790: 8005883a mov r2,r16 + 794: 80000c15 stw zero,48(r16) + 798: 80000d15 stw zero,52(r16) + 79c: 80001115 stw zero,68(r16) + 7a0: 80001215 stw zero,72(r16) + 7a4: dfc00417 ldw ra,16(sp) + 7a8: dcc00317 ldw r19,12(sp) + 7ac: dc800217 ldw r18,8(sp) + 7b0: dc400117 ldw r17,4(sp) + 7b4: dc000017 ldw r16,0(sp) + 7b8: dec00504 addi sp,sp,20 + 7bc: f800283a ret + 7c0: 01400104 movi r5,4 + 7c4: 9809883a mov r4,r19 + 7c8: 00006540 call 654 <__sfmoreglue> + 7cc: 90800015 stw r2,0(r18) + 7d0: 103fde1e bne r2,zero,74c <__alt_data_end+0xfffe074c> + 7d4: 00800304 movi r2,12 + 7d8: 98800015 stw r2,0(r19) + 7dc: 0005883a mov r2,zero + 7e0: 003ff006 br 7a4 <__alt_data_end+0xfffe07a4> + +000007e4 <_cleanup>: + 7e4: 00800034 movhi r2,0 + 7e8: 109c9604 addi r2,r2,29272 + 7ec: 11000017 ldw r4,0(r2) + 7f0: 01400034 movhi r5,0 + 7f4: 29491504 addi r5,r5,9300 + 7f8: 0000dd81 jmpi dd8 <_fwalk_reent> + +000007fc <__sinit>: + 7fc: 20800e17 ldw r2,56(r4) + 800: 10000126 beq r2,zero,808 <__sinit+0xc> + 804: f800283a ret + 808: 00004b01 jmpi 4b0 <__sinit.part.1> + +0000080c <__sfp_lock_acquire>: + 80c: f800283a ret + +00000810 <__sfp_lock_release>: + 810: f800283a ret + +00000814 <__sinit_lock_acquire>: + 814: f800283a ret + +00000818 <__sinit_lock_release>: + 818: f800283a ret + +0000081c <__fp_lock_all>: + 81c: 00800034 movhi r2,0 + 820: 109c9704 addi r2,r2,29276 + 824: 11000017 ldw r4,0(r2) + 828: 01400034 movhi r5,0 + 82c: 29419304 addi r5,r5,1612 + 830: 0000d141 jmpi d14 <_fwalk> + +00000834 <__fp_unlock_all>: + 834: 00800034 movhi r2,0 + 838: 109c9704 addi r2,r2,29276 + 83c: 11000017 ldw r4,0(r2) + 840: 01400034 movhi r5,0 + 844: 29412704 addi r5,r5,1180 + 848: 0000d141 jmpi d14 <_fwalk> + +0000084c <__sfvwrite_r>: + 84c: 30800217 ldw r2,8(r6) + 850: 10006726 beq r2,zero,9f0 <__sfvwrite_r+0x1a4> + 854: 28c0030b ldhu r3,12(r5) + 858: defff404 addi sp,sp,-48 + 85c: dd400715 stw r21,28(sp) + 860: dd000615 stw r20,24(sp) + 864: dc000215 stw r16,8(sp) + 868: dfc00b15 stw ra,44(sp) + 86c: df000a15 stw fp,40(sp) + 870: ddc00915 stw r23,36(sp) + 874: dd800815 stw r22,32(sp) + 878: dcc00515 stw r19,20(sp) + 87c: dc800415 stw r18,16(sp) + 880: dc400315 stw r17,12(sp) + 884: 1880020c andi r2,r3,8 + 888: 2821883a mov r16,r5 + 88c: 202b883a mov r21,r4 + 890: 3029883a mov r20,r6 + 894: 10002726 beq r2,zero,934 <__sfvwrite_r+0xe8> + 898: 28800417 ldw r2,16(r5) + 89c: 10002526 beq r2,zero,934 <__sfvwrite_r+0xe8> + 8a0: 1880008c andi r2,r3,2 + 8a4: a4400017 ldw r17,0(r20) + 8a8: 10002a26 beq r2,zero,954 <__sfvwrite_r+0x108> + 8ac: 05a00034 movhi r22,32768 + 8b0: 0027883a mov r19,zero + 8b4: 0025883a mov r18,zero + 8b8: b5bf0004 addi r22,r22,-1024 + 8bc: 980d883a mov r6,r19 + 8c0: a809883a mov r4,r21 + 8c4: 90004626 beq r18,zero,9e0 <__sfvwrite_r+0x194> + 8c8: 900f883a mov r7,r18 + 8cc: b480022e bgeu r22,r18,8d8 <__sfvwrite_r+0x8c> + 8d0: 01e00034 movhi r7,32768 + 8d4: 39ff0004 addi r7,r7,-1024 + 8d8: 80800917 ldw r2,36(r16) + 8dc: 81400717 ldw r5,28(r16) + 8e0: 103ee83a callr r2 + 8e4: 00805a0e bge zero,r2,a50 <__sfvwrite_r+0x204> + 8e8: a0c00217 ldw r3,8(r20) + 8ec: 98a7883a add r19,r19,r2 + 8f0: 90a5c83a sub r18,r18,r2 + 8f4: 1885c83a sub r2,r3,r2 + 8f8: a0800215 stw r2,8(r20) + 8fc: 103fef1e bne r2,zero,8bc <__alt_data_end+0xfffe08bc> + 900: 0005883a mov r2,zero + 904: dfc00b17 ldw ra,44(sp) + 908: df000a17 ldw fp,40(sp) + 90c: ddc00917 ldw r23,36(sp) + 910: dd800817 ldw r22,32(sp) + 914: dd400717 ldw r21,28(sp) + 918: dd000617 ldw r20,24(sp) + 91c: dcc00517 ldw r19,20(sp) + 920: dc800417 ldw r18,16(sp) + 924: dc400317 ldw r17,12(sp) + 928: dc000217 ldw r16,8(sp) + 92c: dec00c04 addi sp,sp,48 + 930: f800283a ret + 934: 800b883a mov r5,r16 + 938: a809883a mov r4,r21 + 93c: 00022ac0 call 22ac <__swsetup_r> + 940: 1000ee1e bne r2,zero,cfc <__sfvwrite_r+0x4b0> + 944: 80c0030b ldhu r3,12(r16) + 948: a4400017 ldw r17,0(r20) + 94c: 1880008c andi r2,r3,2 + 950: 103fd61e bne r2,zero,8ac <__alt_data_end+0xfffe08ac> + 954: 1880004c andi r2,r3,1 + 958: 1000421e bne r2,zero,a64 <__sfvwrite_r+0x218> + 95c: 0039883a mov fp,zero + 960: 0025883a mov r18,zero + 964: 90001a26 beq r18,zero,9d0 <__sfvwrite_r+0x184> + 968: 1880800c andi r2,r3,512 + 96c: 84c00217 ldw r19,8(r16) + 970: 10002126 beq r2,zero,9f8 <__sfvwrite_r+0x1ac> + 974: 982f883a mov r23,r19 + 978: 94c09636 bltu r18,r19,bd4 <__sfvwrite_r+0x388> + 97c: 1881200c andi r2,r3,1152 + 980: 1000a11e bne r2,zero,c08 <__sfvwrite_r+0x3bc> + 984: 81000017 ldw r4,0(r16) + 988: b80d883a mov r6,r23 + 98c: e00b883a mov r5,fp + 990: 00018d40 call 18d4 + 994: 80c00217 ldw r3,8(r16) + 998: 81000017 ldw r4,0(r16) + 99c: 9005883a mov r2,r18 + 9a0: 1ce7c83a sub r19,r3,r19 + 9a4: 25cf883a add r7,r4,r23 + 9a8: 84c00215 stw r19,8(r16) + 9ac: 81c00015 stw r7,0(r16) + 9b0: a0c00217 ldw r3,8(r20) + 9b4: e0b9883a add fp,fp,r2 + 9b8: 90a5c83a sub r18,r18,r2 + 9bc: 18a7c83a sub r19,r3,r2 + 9c0: a4c00215 stw r19,8(r20) + 9c4: 983fce26 beq r19,zero,900 <__alt_data_end+0xfffe0900> + 9c8: 80c0030b ldhu r3,12(r16) + 9cc: 903fe61e bne r18,zero,968 <__alt_data_end+0xfffe0968> + 9d0: 8f000017 ldw fp,0(r17) + 9d4: 8c800117 ldw r18,4(r17) + 9d8: 8c400204 addi r17,r17,8 + 9dc: 003fe106 br 964 <__alt_data_end+0xfffe0964> + 9e0: 8cc00017 ldw r19,0(r17) + 9e4: 8c800117 ldw r18,4(r17) + 9e8: 8c400204 addi r17,r17,8 + 9ec: 003fb306 br 8bc <__alt_data_end+0xfffe08bc> + 9f0: 0005883a mov r2,zero + 9f4: f800283a ret + 9f8: 81000017 ldw r4,0(r16) + 9fc: 80800417 ldw r2,16(r16) + a00: 11005a36 bltu r2,r4,b6c <__sfvwrite_r+0x320> + a04: 85c00517 ldw r23,20(r16) + a08: 95c05836 bltu r18,r23,b6c <__sfvwrite_r+0x320> + a0c: 00a00034 movhi r2,32768 + a10: 10bfffc4 addi r2,r2,-1 + a14: 9009883a mov r4,r18 + a18: 1480012e bgeu r2,r18,a20 <__sfvwrite_r+0x1d4> + a1c: 1009883a mov r4,r2 + a20: b80b883a mov r5,r23 + a24: 0002f600 call 2f60 <__divsi3> + a28: b80b883a mov r5,r23 + a2c: 1009883a mov r4,r2 + a30: 00031140 call 3114 <__mulsi3> + a34: 81400717 ldw r5,28(r16) + a38: 80c00917 ldw r3,36(r16) + a3c: 100f883a mov r7,r2 + a40: e00d883a mov r6,fp + a44: a809883a mov r4,r21 + a48: 183ee83a callr r3 + a4c: 00bfd816 blt zero,r2,9b0 <__alt_data_end+0xfffe09b0> + a50: 8080030b ldhu r2,12(r16) + a54: 10801014 ori r2,r2,64 + a58: 8080030d sth r2,12(r16) + a5c: 00bfffc4 movi r2,-1 + a60: 003fa806 br 904 <__alt_data_end+0xfffe0904> + a64: 0027883a mov r19,zero + a68: 0011883a mov r8,zero + a6c: 0039883a mov fp,zero + a70: 0025883a mov r18,zero + a74: 90001f26 beq r18,zero,af4 <__sfvwrite_r+0x2a8> + a78: 40005a26 beq r8,zero,be4 <__sfvwrite_r+0x398> + a7c: 982d883a mov r22,r19 + a80: 94c0012e bgeu r18,r19,a88 <__sfvwrite_r+0x23c> + a84: 902d883a mov r22,r18 + a88: 81000017 ldw r4,0(r16) + a8c: 80800417 ldw r2,16(r16) + a90: b02f883a mov r23,r22 + a94: 81c00517 ldw r7,20(r16) + a98: 1100032e bgeu r2,r4,aa8 <__sfvwrite_r+0x25c> + a9c: 80c00217 ldw r3,8(r16) + aa0: 38c7883a add r3,r7,r3 + aa4: 1d801816 blt r3,r22,b08 <__sfvwrite_r+0x2bc> + aa8: b1c03e16 blt r22,r7,ba4 <__sfvwrite_r+0x358> + aac: 80800917 ldw r2,36(r16) + ab0: 81400717 ldw r5,28(r16) + ab4: e00d883a mov r6,fp + ab8: da000115 stw r8,4(sp) + abc: a809883a mov r4,r21 + ac0: 103ee83a callr r2 + ac4: 102f883a mov r23,r2 + ac8: da000117 ldw r8,4(sp) + acc: 00bfe00e bge zero,r2,a50 <__alt_data_end+0xfffe0a50> + ad0: 9de7c83a sub r19,r19,r23 + ad4: 98001f26 beq r19,zero,b54 <__sfvwrite_r+0x308> + ad8: a0800217 ldw r2,8(r20) + adc: e5f9883a add fp,fp,r23 + ae0: 95e5c83a sub r18,r18,r23 + ae4: 15efc83a sub r23,r2,r23 + ae8: a5c00215 stw r23,8(r20) + aec: b83f8426 beq r23,zero,900 <__alt_data_end+0xfffe0900> + af0: 903fe11e bne r18,zero,a78 <__alt_data_end+0xfffe0a78> + af4: 8f000017 ldw fp,0(r17) + af8: 8c800117 ldw r18,4(r17) + afc: 0011883a mov r8,zero + b00: 8c400204 addi r17,r17,8 + b04: 003fdb06 br a74 <__alt_data_end+0xfffe0a74> + b08: 180d883a mov r6,r3 + b0c: e00b883a mov r5,fp + b10: da000115 stw r8,4(sp) + b14: d8c00015 stw r3,0(sp) + b18: 00018d40 call 18d4 + b1c: d8c00017 ldw r3,0(sp) + b20: 80800017 ldw r2,0(r16) + b24: 800b883a mov r5,r16 + b28: a809883a mov r4,r21 + b2c: 10c5883a add r2,r2,r3 + b30: 80800015 stw r2,0(r16) + b34: d8c00015 stw r3,0(sp) + b38: 00027740 call 2774 <_fflush_r> + b3c: d8c00017 ldw r3,0(sp) + b40: da000117 ldw r8,4(sp) + b44: 103fc21e bne r2,zero,a50 <__alt_data_end+0xfffe0a50> + b48: 182f883a mov r23,r3 + b4c: 9de7c83a sub r19,r19,r23 + b50: 983fe11e bne r19,zero,ad8 <__alt_data_end+0xfffe0ad8> + b54: 800b883a mov r5,r16 + b58: a809883a mov r4,r21 + b5c: 00027740 call 2774 <_fflush_r> + b60: 103fbb1e bne r2,zero,a50 <__alt_data_end+0xfffe0a50> + b64: 0011883a mov r8,zero + b68: 003fdb06 br ad8 <__alt_data_end+0xfffe0ad8> + b6c: 94c0012e bgeu r18,r19,b74 <__sfvwrite_r+0x328> + b70: 9027883a mov r19,r18 + b74: 980d883a mov r6,r19 + b78: e00b883a mov r5,fp + b7c: 00018d40 call 18d4 + b80: 80800217 ldw r2,8(r16) + b84: 80c00017 ldw r3,0(r16) + b88: 14c5c83a sub r2,r2,r19 + b8c: 1cc7883a add r3,r3,r19 + b90: 80800215 stw r2,8(r16) + b94: 80c00015 stw r3,0(r16) + b98: 10004326 beq r2,zero,ca8 <__sfvwrite_r+0x45c> + b9c: 9805883a mov r2,r19 + ba0: 003f8306 br 9b0 <__alt_data_end+0xfffe09b0> + ba4: b00d883a mov r6,r22 + ba8: e00b883a mov r5,fp + bac: da000115 stw r8,4(sp) + bb0: 00018d40 call 18d4 + bb4: 80800217 ldw r2,8(r16) + bb8: 80c00017 ldw r3,0(r16) + bbc: da000117 ldw r8,4(sp) + bc0: 1585c83a sub r2,r2,r22 + bc4: 1dad883a add r22,r3,r22 + bc8: 80800215 stw r2,8(r16) + bcc: 85800015 stw r22,0(r16) + bd0: 003fbf06 br ad0 <__alt_data_end+0xfffe0ad0> + bd4: 81000017 ldw r4,0(r16) + bd8: 9027883a mov r19,r18 + bdc: 902f883a mov r23,r18 + be0: 003f6906 br 988 <__alt_data_end+0xfffe0988> + be4: 900d883a mov r6,r18 + be8: 01400284 movi r5,10 + bec: e009883a mov r4,fp + bf0: 00016a80 call 16a8 + bf4: 10003e26 beq r2,zero,cf0 <__sfvwrite_r+0x4a4> + bf8: 10800044 addi r2,r2,1 + bfc: 1727c83a sub r19,r2,fp + c00: 02000044 movi r8,1 + c04: 003f9d06 br a7c <__alt_data_end+0xfffe0a7c> + c08: 80800517 ldw r2,20(r16) + c0c: 81400417 ldw r5,16(r16) + c10: 81c00017 ldw r7,0(r16) + c14: 10a7883a add r19,r2,r2 + c18: 9885883a add r2,r19,r2 + c1c: 1026d7fa srli r19,r2,31 + c20: 396dc83a sub r22,r7,r5 + c24: b1000044 addi r4,r22,1 + c28: 9885883a add r2,r19,r2 + c2c: 1027d07a srai r19,r2,1 + c30: 2485883a add r2,r4,r18 + c34: 980d883a mov r6,r19 + c38: 9880022e bgeu r19,r2,c44 <__sfvwrite_r+0x3f8> + c3c: 1027883a mov r19,r2 + c40: 100d883a mov r6,r2 + c44: 18c1000c andi r3,r3,1024 + c48: 18001c26 beq r3,zero,cbc <__sfvwrite_r+0x470> + c4c: 300b883a mov r5,r6 + c50: a809883a mov r4,r21 + c54: 0000e9c0 call e9c <_malloc_r> + c58: 102f883a mov r23,r2 + c5c: 10002926 beq r2,zero,d04 <__sfvwrite_r+0x4b8> + c60: 81400417 ldw r5,16(r16) + c64: b00d883a mov r6,r22 + c68: 1009883a mov r4,r2 + c6c: 000178c0 call 178c + c70: 8080030b ldhu r2,12(r16) + c74: 00fedfc4 movi r3,-1153 + c78: 10c4703a and r2,r2,r3 + c7c: 10802014 ori r2,r2,128 + c80: 8080030d sth r2,12(r16) + c84: bd89883a add r4,r23,r22 + c88: 9d8fc83a sub r7,r19,r22 + c8c: 85c00415 stw r23,16(r16) + c90: 84c00515 stw r19,20(r16) + c94: 81000015 stw r4,0(r16) + c98: 9027883a mov r19,r18 + c9c: 81c00215 stw r7,8(r16) + ca0: 902f883a mov r23,r18 + ca4: 003f3806 br 988 <__alt_data_end+0xfffe0988> + ca8: 800b883a mov r5,r16 + cac: a809883a mov r4,r21 + cb0: 00027740 call 2774 <_fflush_r> + cb4: 103fb926 beq r2,zero,b9c <__alt_data_end+0xfffe0b9c> + cb8: 003f6506 br a50 <__alt_data_end+0xfffe0a50> + cbc: a809883a mov r4,r21 + cc0: 0001b580 call 1b58 <_realloc_r> + cc4: 102f883a mov r23,r2 + cc8: 103fee1e bne r2,zero,c84 <__alt_data_end+0xfffe0c84> + ccc: 81400417 ldw r5,16(r16) + cd0: a809883a mov r4,r21 + cd4: 00029240 call 2924 <_free_r> + cd8: 8080030b ldhu r2,12(r16) + cdc: 00ffdfc4 movi r3,-129 + ce0: 1884703a and r2,r3,r2 + ce4: 00c00304 movi r3,12 + ce8: a8c00015 stw r3,0(r21) + cec: 003f5906 br a54 <__alt_data_end+0xfffe0a54> + cf0: 94c00044 addi r19,r18,1 + cf4: 02000044 movi r8,1 + cf8: 003f6006 br a7c <__alt_data_end+0xfffe0a7c> + cfc: 00bfffc4 movi r2,-1 + d00: 003f0006 br 904 <__alt_data_end+0xfffe0904> + d04: 00800304 movi r2,12 + d08: a8800015 stw r2,0(r21) + d0c: 8080030b ldhu r2,12(r16) + d10: 003f5006 br a54 <__alt_data_end+0xfffe0a54> + +00000d14 <_fwalk>: + d14: defff704 addi sp,sp,-36 + d18: dd000415 stw r20,16(sp) + d1c: dfc00815 stw ra,32(sp) + d20: ddc00715 stw r23,28(sp) + d24: dd800615 stw r22,24(sp) + d28: dd400515 stw r21,20(sp) + d2c: dcc00315 stw r19,12(sp) + d30: dc800215 stw r18,8(sp) + d34: dc400115 stw r17,4(sp) + d38: dc000015 stw r16,0(sp) + d3c: 2500b804 addi r20,r4,736 + d40: a0002326 beq r20,zero,dd0 <_fwalk+0xbc> + d44: 282b883a mov r21,r5 + d48: 002f883a mov r23,zero + d4c: 05800044 movi r22,1 + d50: 04ffffc4 movi r19,-1 + d54: a4400117 ldw r17,4(r20) + d58: a4800217 ldw r18,8(r20) + d5c: 8c7fffc4 addi r17,r17,-1 + d60: 88000d16 blt r17,zero,d98 <_fwalk+0x84> + d64: 94000304 addi r16,r18,12 + d68: 94800384 addi r18,r18,14 + d6c: 8080000b ldhu r2,0(r16) + d70: 8c7fffc4 addi r17,r17,-1 + d74: 813ffd04 addi r4,r16,-12 + d78: b080042e bgeu r22,r2,d8c <_fwalk+0x78> + d7c: 9080000f ldh r2,0(r18) + d80: 14c00226 beq r2,r19,d8c <_fwalk+0x78> + d84: a83ee83a callr r21 + d88: b8aeb03a or r23,r23,r2 + d8c: 84001a04 addi r16,r16,104 + d90: 94801a04 addi r18,r18,104 + d94: 8cfff51e bne r17,r19,d6c <__alt_data_end+0xfffe0d6c> + d98: a5000017 ldw r20,0(r20) + d9c: a03fed1e bne r20,zero,d54 <__alt_data_end+0xfffe0d54> + da0: b805883a mov r2,r23 + da4: dfc00817 ldw ra,32(sp) + da8: ddc00717 ldw r23,28(sp) + dac: dd800617 ldw r22,24(sp) + db0: dd400517 ldw r21,20(sp) + db4: dd000417 ldw r20,16(sp) + db8: dcc00317 ldw r19,12(sp) + dbc: dc800217 ldw r18,8(sp) + dc0: dc400117 ldw r17,4(sp) + dc4: dc000017 ldw r16,0(sp) + dc8: dec00904 addi sp,sp,36 + dcc: f800283a ret + dd0: 002f883a mov r23,zero + dd4: 003ff206 br da0 <__alt_data_end+0xfffe0da0> + +00000dd8 <_fwalk_reent>: + dd8: defff704 addi sp,sp,-36 + ddc: dd000415 stw r20,16(sp) + de0: dfc00815 stw ra,32(sp) + de4: ddc00715 stw r23,28(sp) + de8: dd800615 stw r22,24(sp) + dec: dd400515 stw r21,20(sp) + df0: dcc00315 stw r19,12(sp) + df4: dc800215 stw r18,8(sp) + df8: dc400115 stw r17,4(sp) + dfc: dc000015 stw r16,0(sp) + e00: 2500b804 addi r20,r4,736 + e04: a0002326 beq r20,zero,e94 <_fwalk_reent+0xbc> + e08: 282b883a mov r21,r5 + e0c: 2027883a mov r19,r4 + e10: 002f883a mov r23,zero + e14: 05800044 movi r22,1 + e18: 04bfffc4 movi r18,-1 + e1c: a4400117 ldw r17,4(r20) + e20: a4000217 ldw r16,8(r20) + e24: 8c7fffc4 addi r17,r17,-1 + e28: 88000c16 blt r17,zero,e5c <_fwalk_reent+0x84> + e2c: 84000304 addi r16,r16,12 + e30: 8080000b ldhu r2,0(r16) + e34: 8c7fffc4 addi r17,r17,-1 + e38: 817ffd04 addi r5,r16,-12 + e3c: b080052e bgeu r22,r2,e54 <_fwalk_reent+0x7c> + e40: 8080008f ldh r2,2(r16) + e44: 9809883a mov r4,r19 + e48: 14800226 beq r2,r18,e54 <_fwalk_reent+0x7c> + e4c: a83ee83a callr r21 + e50: b8aeb03a or r23,r23,r2 + e54: 84001a04 addi r16,r16,104 + e58: 8cbff51e bne r17,r18,e30 <__alt_data_end+0xfffe0e30> + e5c: a5000017 ldw r20,0(r20) + e60: a03fee1e bne r20,zero,e1c <__alt_data_end+0xfffe0e1c> + e64: b805883a mov r2,r23 + e68: dfc00817 ldw ra,32(sp) + e6c: ddc00717 ldw r23,28(sp) + e70: dd800617 ldw r22,24(sp) + e74: dd400517 ldw r21,20(sp) + e78: dd000417 ldw r20,16(sp) + e7c: dcc00317 ldw r19,12(sp) + e80: dc800217 ldw r18,8(sp) + e84: dc400117 ldw r17,4(sp) + e88: dc000017 ldw r16,0(sp) + e8c: dec00904 addi sp,sp,36 + e90: f800283a ret + e94: 002f883a mov r23,zero + e98: 003ff206 br e64 <__alt_data_end+0xfffe0e64> + +00000e9c <_malloc_r>: + e9c: defff504 addi sp,sp,-44 + ea0: dc800315 stw r18,12(sp) + ea4: dfc00a15 stw ra,40(sp) + ea8: df000915 stw fp,36(sp) + eac: ddc00815 stw r23,32(sp) + eb0: dd800715 stw r22,28(sp) + eb4: dd400615 stw r21,24(sp) + eb8: dd000515 stw r20,20(sp) + ebc: dcc00415 stw r19,16(sp) + ec0: dc400215 stw r17,8(sp) + ec4: dc000115 stw r16,4(sp) + ec8: 288002c4 addi r2,r5,11 + ecc: 00c00584 movi r3,22 + ed0: 2025883a mov r18,r4 + ed4: 18807f2e bgeu r3,r2,10d4 <_malloc_r+0x238> + ed8: 047ffe04 movi r17,-8 + edc: 1462703a and r17,r2,r17 + ee0: 8800a316 blt r17,zero,1170 <_malloc_r+0x2d4> + ee4: 8940a236 bltu r17,r5,1170 <_malloc_r+0x2d4> + ee8: 00036140 call 3614 <__malloc_lock> + eec: 00807dc4 movi r2,503 + ef0: 1441e92e bgeu r2,r17,1698 <_malloc_r+0x7fc> + ef4: 8804d27a srli r2,r17,9 + ef8: 1000a126 beq r2,zero,1180 <_malloc_r+0x2e4> + efc: 00c00104 movi r3,4 + f00: 18811e36 bltu r3,r2,137c <_malloc_r+0x4e0> + f04: 8804d1ba srli r2,r17,6 + f08: 12000e44 addi r8,r2,57 + f0c: 11c00e04 addi r7,r2,56 + f10: 4209883a add r4,r8,r8 + f14: 04c00034 movhi r19,0 + f18: 2109883a add r4,r4,r4 + f1c: 9cd71204 addi r19,r19,23624 + f20: 2109883a add r4,r4,r4 + f24: 9909883a add r4,r19,r4 + f28: 24000117 ldw r16,4(r4) + f2c: 213ffe04 addi r4,r4,-8 + f30: 24009726 beq r4,r16,1190 <_malloc_r+0x2f4> + f34: 80800117 ldw r2,4(r16) + f38: 01bfff04 movi r6,-4 + f3c: 014003c4 movi r5,15 + f40: 1184703a and r2,r2,r6 + f44: 1447c83a sub r3,r2,r17 + f48: 28c00716 blt r5,r3,f68 <_malloc_r+0xcc> + f4c: 1800920e bge r3,zero,1198 <_malloc_r+0x2fc> + f50: 84000317 ldw r16,12(r16) + f54: 24008e26 beq r4,r16,1190 <_malloc_r+0x2f4> + f58: 80800117 ldw r2,4(r16) + f5c: 1184703a and r2,r2,r6 + f60: 1447c83a sub r3,r2,r17 + f64: 28fff90e bge r5,r3,f4c <__alt_data_end+0xfffe0f4c> + f68: 3809883a mov r4,r7 + f6c: 01800034 movhi r6,0 + f70: 9c000417 ldw r16,16(r19) + f74: 31971204 addi r6,r6,23624 + f78: 32000204 addi r8,r6,8 + f7c: 82013426 beq r16,r8,1450 <_malloc_r+0x5b4> + f80: 80c00117 ldw r3,4(r16) + f84: 00bfff04 movi r2,-4 + f88: 188e703a and r7,r3,r2 + f8c: 3c45c83a sub r2,r7,r17 + f90: 00c003c4 movi r3,15 + f94: 18811f16 blt r3,r2,1414 <_malloc_r+0x578> + f98: 32000515 stw r8,20(r6) + f9c: 32000415 stw r8,16(r6) + fa0: 10007f0e bge r2,zero,11a0 <_malloc_r+0x304> + fa4: 00807fc4 movi r2,511 + fa8: 11c0fd36 bltu r2,r7,13a0 <_malloc_r+0x504> + fac: 3806d0fa srli r3,r7,3 + fb0: 01c00044 movi r7,1 + fb4: 30800117 ldw r2,4(r6) + fb8: 19400044 addi r5,r3,1 + fbc: 294b883a add r5,r5,r5 + fc0: 1807d0ba srai r3,r3,2 + fc4: 294b883a add r5,r5,r5 + fc8: 294b883a add r5,r5,r5 + fcc: 298b883a add r5,r5,r6 + fd0: 38c6983a sll r3,r7,r3 + fd4: 29c00017 ldw r7,0(r5) + fd8: 2a7ffe04 addi r9,r5,-8 + fdc: 1886b03a or r3,r3,r2 + fe0: 82400315 stw r9,12(r16) + fe4: 81c00215 stw r7,8(r16) + fe8: 30c00115 stw r3,4(r6) + fec: 2c000015 stw r16,0(r5) + ff0: 3c000315 stw r16,12(r7) + ff4: 2005d0ba srai r2,r4,2 + ff8: 01400044 movi r5,1 + ffc: 288a983a sll r5,r5,r2 + 1000: 19406f36 bltu r3,r5,11c0 <_malloc_r+0x324> + 1004: 28c4703a and r2,r5,r3 + 1008: 10000a1e bne r2,zero,1034 <_malloc_r+0x198> + 100c: 00bfff04 movi r2,-4 + 1010: 294b883a add r5,r5,r5 + 1014: 2088703a and r4,r4,r2 + 1018: 28c4703a and r2,r5,r3 + 101c: 21000104 addi r4,r4,4 + 1020: 1000041e bne r2,zero,1034 <_malloc_r+0x198> + 1024: 294b883a add r5,r5,r5 + 1028: 28c4703a and r2,r5,r3 + 102c: 21000104 addi r4,r4,4 + 1030: 103ffc26 beq r2,zero,1024 <__alt_data_end+0xfffe1024> + 1034: 02bfff04 movi r10,-4 + 1038: 024003c4 movi r9,15 + 103c: 21800044 addi r6,r4,1 + 1040: 318d883a add r6,r6,r6 + 1044: 318d883a add r6,r6,r6 + 1048: 318d883a add r6,r6,r6 + 104c: 998d883a add r6,r19,r6 + 1050: 333ffe04 addi r12,r6,-8 + 1054: 2017883a mov r11,r4 + 1058: 31800104 addi r6,r6,4 + 105c: 34000017 ldw r16,0(r6) + 1060: 31fffd04 addi r7,r6,-12 + 1064: 81c0041e bne r16,r7,1078 <_malloc_r+0x1dc> + 1068: 0000fb06 br 1458 <_malloc_r+0x5bc> + 106c: 1801030e bge r3,zero,147c <_malloc_r+0x5e0> + 1070: 84000317 ldw r16,12(r16) + 1074: 81c0f826 beq r16,r7,1458 <_malloc_r+0x5bc> + 1078: 80800117 ldw r2,4(r16) + 107c: 1284703a and r2,r2,r10 + 1080: 1447c83a sub r3,r2,r17 + 1084: 48fff90e bge r9,r3,106c <__alt_data_end+0xfffe106c> + 1088: 80800317 ldw r2,12(r16) + 108c: 81000217 ldw r4,8(r16) + 1090: 89400054 ori r5,r17,1 + 1094: 81400115 stw r5,4(r16) + 1098: 20800315 stw r2,12(r4) + 109c: 11000215 stw r4,8(r2) + 10a0: 8463883a add r17,r16,r17 + 10a4: 9c400515 stw r17,20(r19) + 10a8: 9c400415 stw r17,16(r19) + 10ac: 18800054 ori r2,r3,1 + 10b0: 88800115 stw r2,4(r17) + 10b4: 8a000315 stw r8,12(r17) + 10b8: 8a000215 stw r8,8(r17) + 10bc: 88e3883a add r17,r17,r3 + 10c0: 88c00015 stw r3,0(r17) + 10c4: 9009883a mov r4,r18 + 10c8: 00036380 call 3638 <__malloc_unlock> + 10cc: 80800204 addi r2,r16,8 + 10d0: 00001b06 br 1140 <_malloc_r+0x2a4> + 10d4: 04400404 movi r17,16 + 10d8: 89402536 bltu r17,r5,1170 <_malloc_r+0x2d4> + 10dc: 00036140 call 3614 <__malloc_lock> + 10e0: 00800184 movi r2,6 + 10e4: 01000084 movi r4,2 + 10e8: 04c00034 movhi r19,0 + 10ec: 1085883a add r2,r2,r2 + 10f0: 9cd71204 addi r19,r19,23624 + 10f4: 1085883a add r2,r2,r2 + 10f8: 9885883a add r2,r19,r2 + 10fc: 14000117 ldw r16,4(r2) + 1100: 10fffe04 addi r3,r2,-8 + 1104: 80c0d926 beq r16,r3,146c <_malloc_r+0x5d0> + 1108: 80c00117 ldw r3,4(r16) + 110c: 81000317 ldw r4,12(r16) + 1110: 00bfff04 movi r2,-4 + 1114: 1884703a and r2,r3,r2 + 1118: 81400217 ldw r5,8(r16) + 111c: 8085883a add r2,r16,r2 + 1120: 10c00117 ldw r3,4(r2) + 1124: 29000315 stw r4,12(r5) + 1128: 21400215 stw r5,8(r4) + 112c: 18c00054 ori r3,r3,1 + 1130: 10c00115 stw r3,4(r2) + 1134: 9009883a mov r4,r18 + 1138: 00036380 call 3638 <__malloc_unlock> + 113c: 80800204 addi r2,r16,8 + 1140: dfc00a17 ldw ra,40(sp) + 1144: df000917 ldw fp,36(sp) + 1148: ddc00817 ldw r23,32(sp) + 114c: dd800717 ldw r22,28(sp) + 1150: dd400617 ldw r21,24(sp) + 1154: dd000517 ldw r20,20(sp) + 1158: dcc00417 ldw r19,16(sp) + 115c: dc800317 ldw r18,12(sp) + 1160: dc400217 ldw r17,8(sp) + 1164: dc000117 ldw r16,4(sp) + 1168: dec00b04 addi sp,sp,44 + 116c: f800283a ret + 1170: 00800304 movi r2,12 + 1174: 90800015 stw r2,0(r18) + 1178: 0005883a mov r2,zero + 117c: 003ff006 br 1140 <__alt_data_end+0xfffe1140> + 1180: 01002004 movi r4,128 + 1184: 02001004 movi r8,64 + 1188: 01c00fc4 movi r7,63 + 118c: 003f6106 br f14 <__alt_data_end+0xfffe0f14> + 1190: 4009883a mov r4,r8 + 1194: 003f7506 br f6c <__alt_data_end+0xfffe0f6c> + 1198: 81000317 ldw r4,12(r16) + 119c: 003fde06 br 1118 <__alt_data_end+0xfffe1118> + 11a0: 81c5883a add r2,r16,r7 + 11a4: 11400117 ldw r5,4(r2) + 11a8: 9009883a mov r4,r18 + 11ac: 29400054 ori r5,r5,1 + 11b0: 11400115 stw r5,4(r2) + 11b4: 00036380 call 3638 <__malloc_unlock> + 11b8: 80800204 addi r2,r16,8 + 11bc: 003fe006 br 1140 <__alt_data_end+0xfffe1140> + 11c0: 9c000217 ldw r16,8(r19) + 11c4: 00bfff04 movi r2,-4 + 11c8: 85800117 ldw r22,4(r16) + 11cc: b0ac703a and r22,r22,r2 + 11d0: b4400336 bltu r22,r17,11e0 <_malloc_r+0x344> + 11d4: b445c83a sub r2,r22,r17 + 11d8: 00c003c4 movi r3,15 + 11dc: 18805d16 blt r3,r2,1354 <_malloc_r+0x4b8> + 11e0: 05c00034 movhi r23,0 + 11e4: 00800034 movhi r2,0 + 11e8: 109ca604 addi r2,r2,29336 + 11ec: bddc9804 addi r23,r23,29280 + 11f0: 15400017 ldw r21,0(r2) + 11f4: b8c00017 ldw r3,0(r23) + 11f8: 00bfffc4 movi r2,-1 + 11fc: 858d883a add r6,r16,r22 + 1200: 8d6b883a add r21,r17,r21 + 1204: 1880ea26 beq r3,r2,15b0 <_malloc_r+0x714> + 1208: ad4403c4 addi r21,r21,4111 + 120c: 00bc0004 movi r2,-4096 + 1210: a8aa703a and r21,r21,r2 + 1214: a80b883a mov r5,r21 + 1218: 9009883a mov r4,r18 + 121c: d9800015 stw r6,0(sp) + 1220: 00020bc0 call 20bc <_sbrk_r> + 1224: 1029883a mov r20,r2 + 1228: 00bfffc4 movi r2,-1 + 122c: d9800017 ldw r6,0(sp) + 1230: a080e826 beq r20,r2,15d4 <_malloc_r+0x738> + 1234: a180a636 bltu r20,r6,14d0 <_malloc_r+0x634> + 1238: 07000034 movhi fp,0 + 123c: e71caf04 addi fp,fp,29372 + 1240: e0800017 ldw r2,0(fp) + 1244: a887883a add r3,r21,r2 + 1248: e0c00015 stw r3,0(fp) + 124c: 3500e626 beq r6,r20,15e8 <_malloc_r+0x74c> + 1250: b9000017 ldw r4,0(r23) + 1254: 00bfffc4 movi r2,-1 + 1258: 2080ee26 beq r4,r2,1614 <_malloc_r+0x778> + 125c: a185c83a sub r2,r20,r6 + 1260: 10c5883a add r2,r2,r3 + 1264: e0800015 stw r2,0(fp) + 1268: a0c001cc andi r3,r20,7 + 126c: 1800bc26 beq r3,zero,1560 <_malloc_r+0x6c4> + 1270: a0e9c83a sub r20,r20,r3 + 1274: 00840204 movi r2,4104 + 1278: a5000204 addi r20,r20,8 + 127c: 10c7c83a sub r3,r2,r3 + 1280: a545883a add r2,r20,r21 + 1284: 1083ffcc andi r2,r2,4095 + 1288: 18abc83a sub r21,r3,r2 + 128c: a80b883a mov r5,r21 + 1290: 9009883a mov r4,r18 + 1294: 00020bc0 call 20bc <_sbrk_r> + 1298: 00ffffc4 movi r3,-1 + 129c: 10c0e126 beq r2,r3,1624 <_malloc_r+0x788> + 12a0: 1505c83a sub r2,r2,r20 + 12a4: 1545883a add r2,r2,r21 + 12a8: 10800054 ori r2,r2,1 + 12ac: e0c00017 ldw r3,0(fp) + 12b0: 9d000215 stw r20,8(r19) + 12b4: a0800115 stw r2,4(r20) + 12b8: a8c7883a add r3,r21,r3 + 12bc: e0c00015 stw r3,0(fp) + 12c0: 84c00e26 beq r16,r19,12fc <_malloc_r+0x460> + 12c4: 018003c4 movi r6,15 + 12c8: 3580a72e bgeu r6,r22,1568 <_malloc_r+0x6cc> + 12cc: 81400117 ldw r5,4(r16) + 12d0: 013ffe04 movi r4,-8 + 12d4: b0bffd04 addi r2,r22,-12 + 12d8: 1104703a and r2,r2,r4 + 12dc: 2900004c andi r4,r5,1 + 12e0: 2088b03a or r4,r4,r2 + 12e4: 81000115 stw r4,4(r16) + 12e8: 01400144 movi r5,5 + 12ec: 8089883a add r4,r16,r2 + 12f0: 21400115 stw r5,4(r4) + 12f4: 21400215 stw r5,8(r4) + 12f8: 3080cd36 bltu r6,r2,1630 <_malloc_r+0x794> + 12fc: 00800034 movhi r2,0 + 1300: 109ca504 addi r2,r2,29332 + 1304: 11000017 ldw r4,0(r2) + 1308: 20c0012e bgeu r4,r3,1310 <_malloc_r+0x474> + 130c: 10c00015 stw r3,0(r2) + 1310: 00800034 movhi r2,0 + 1314: 109ca404 addi r2,r2,29328 + 1318: 11000017 ldw r4,0(r2) + 131c: 9c000217 ldw r16,8(r19) + 1320: 20c0012e bgeu r4,r3,1328 <_malloc_r+0x48c> + 1324: 10c00015 stw r3,0(r2) + 1328: 80c00117 ldw r3,4(r16) + 132c: 00bfff04 movi r2,-4 + 1330: 1886703a and r3,r3,r2 + 1334: 1c45c83a sub r2,r3,r17 + 1338: 1c400236 bltu r3,r17,1344 <_malloc_r+0x4a8> + 133c: 00c003c4 movi r3,15 + 1340: 18800416 blt r3,r2,1354 <_malloc_r+0x4b8> + 1344: 9009883a mov r4,r18 + 1348: 00036380 call 3638 <__malloc_unlock> + 134c: 0005883a mov r2,zero + 1350: 003f7b06 br 1140 <__alt_data_end+0xfffe1140> + 1354: 88c00054 ori r3,r17,1 + 1358: 80c00115 stw r3,4(r16) + 135c: 8463883a add r17,r16,r17 + 1360: 10800054 ori r2,r2,1 + 1364: 9c400215 stw r17,8(r19) + 1368: 88800115 stw r2,4(r17) + 136c: 9009883a mov r4,r18 + 1370: 00036380 call 3638 <__malloc_unlock> + 1374: 80800204 addi r2,r16,8 + 1378: 003f7106 br 1140 <__alt_data_end+0xfffe1140> + 137c: 00c00504 movi r3,20 + 1380: 18804a2e bgeu r3,r2,14ac <_malloc_r+0x610> + 1384: 00c01504 movi r3,84 + 1388: 18806e36 bltu r3,r2,1544 <_malloc_r+0x6a8> + 138c: 8804d33a srli r2,r17,12 + 1390: 12001bc4 addi r8,r2,111 + 1394: 11c01b84 addi r7,r2,110 + 1398: 4209883a add r4,r8,r8 + 139c: 003edd06 br f14 <__alt_data_end+0xfffe0f14> + 13a0: 3804d27a srli r2,r7,9 + 13a4: 00c00104 movi r3,4 + 13a8: 1880442e bgeu r3,r2,14bc <_malloc_r+0x620> + 13ac: 00c00504 movi r3,20 + 13b0: 18808136 bltu r3,r2,15b8 <_malloc_r+0x71c> + 13b4: 11401704 addi r5,r2,92 + 13b8: 10c016c4 addi r3,r2,91 + 13bc: 294b883a add r5,r5,r5 + 13c0: 294b883a add r5,r5,r5 + 13c4: 294b883a add r5,r5,r5 + 13c8: 994b883a add r5,r19,r5 + 13cc: 28800017 ldw r2,0(r5) + 13d0: 01800034 movhi r6,0 + 13d4: 297ffe04 addi r5,r5,-8 + 13d8: 31971204 addi r6,r6,23624 + 13dc: 28806526 beq r5,r2,1574 <_malloc_r+0x6d8> + 13e0: 01bfff04 movi r6,-4 + 13e4: 10c00117 ldw r3,4(r2) + 13e8: 1986703a and r3,r3,r6 + 13ec: 38c0022e bgeu r7,r3,13f8 <_malloc_r+0x55c> + 13f0: 10800217 ldw r2,8(r2) + 13f4: 28bffb1e bne r5,r2,13e4 <__alt_data_end+0xfffe13e4> + 13f8: 11400317 ldw r5,12(r2) + 13fc: 98c00117 ldw r3,4(r19) + 1400: 81400315 stw r5,12(r16) + 1404: 80800215 stw r2,8(r16) + 1408: 2c000215 stw r16,8(r5) + 140c: 14000315 stw r16,12(r2) + 1410: 003ef806 br ff4 <__alt_data_end+0xfffe0ff4> + 1414: 88c00054 ori r3,r17,1 + 1418: 80c00115 stw r3,4(r16) + 141c: 8463883a add r17,r16,r17 + 1420: 34400515 stw r17,20(r6) + 1424: 34400415 stw r17,16(r6) + 1428: 10c00054 ori r3,r2,1 + 142c: 8a000315 stw r8,12(r17) + 1430: 8a000215 stw r8,8(r17) + 1434: 88c00115 stw r3,4(r17) + 1438: 88a3883a add r17,r17,r2 + 143c: 88800015 stw r2,0(r17) + 1440: 9009883a mov r4,r18 + 1444: 00036380 call 3638 <__malloc_unlock> + 1448: 80800204 addi r2,r16,8 + 144c: 003f3c06 br 1140 <__alt_data_end+0xfffe1140> + 1450: 30c00117 ldw r3,4(r6) + 1454: 003ee706 br ff4 <__alt_data_end+0xfffe0ff4> + 1458: 5ac00044 addi r11,r11,1 + 145c: 588000cc andi r2,r11,3 + 1460: 31800204 addi r6,r6,8 + 1464: 103efd1e bne r2,zero,105c <__alt_data_end+0xfffe105c> + 1468: 00002406 br 14fc <_malloc_r+0x660> + 146c: 14000317 ldw r16,12(r2) + 1470: 143f251e bne r2,r16,1108 <__alt_data_end+0xfffe1108> + 1474: 21000084 addi r4,r4,2 + 1478: 003ebc06 br f6c <__alt_data_end+0xfffe0f6c> + 147c: 8085883a add r2,r16,r2 + 1480: 10c00117 ldw r3,4(r2) + 1484: 81000317 ldw r4,12(r16) + 1488: 81400217 ldw r5,8(r16) + 148c: 18c00054 ori r3,r3,1 + 1490: 10c00115 stw r3,4(r2) + 1494: 29000315 stw r4,12(r5) + 1498: 21400215 stw r5,8(r4) + 149c: 9009883a mov r4,r18 + 14a0: 00036380 call 3638 <__malloc_unlock> + 14a4: 80800204 addi r2,r16,8 + 14a8: 003f2506 br 1140 <__alt_data_end+0xfffe1140> + 14ac: 12001704 addi r8,r2,92 + 14b0: 11c016c4 addi r7,r2,91 + 14b4: 4209883a add r4,r8,r8 + 14b8: 003e9606 br f14 <__alt_data_end+0xfffe0f14> + 14bc: 3804d1ba srli r2,r7,6 + 14c0: 11400e44 addi r5,r2,57 + 14c4: 10c00e04 addi r3,r2,56 + 14c8: 294b883a add r5,r5,r5 + 14cc: 003fbc06 br 13c0 <__alt_data_end+0xfffe13c0> + 14d0: 84ff5926 beq r16,r19,1238 <__alt_data_end+0xfffe1238> + 14d4: 00800034 movhi r2,0 + 14d8: 10971204 addi r2,r2,23624 + 14dc: 14000217 ldw r16,8(r2) + 14e0: 00bfff04 movi r2,-4 + 14e4: 80c00117 ldw r3,4(r16) + 14e8: 1886703a and r3,r3,r2 + 14ec: 003f9106 br 1334 <__alt_data_end+0xfffe1334> + 14f0: 60800217 ldw r2,8(r12) + 14f4: 213fffc4 addi r4,r4,-1 + 14f8: 1300651e bne r2,r12,1690 <_malloc_r+0x7f4> + 14fc: 208000cc andi r2,r4,3 + 1500: 633ffe04 addi r12,r12,-8 + 1504: 103ffa1e bne r2,zero,14f0 <__alt_data_end+0xfffe14f0> + 1508: 98800117 ldw r2,4(r19) + 150c: 0146303a nor r3,zero,r5 + 1510: 1884703a and r2,r3,r2 + 1514: 98800115 stw r2,4(r19) + 1518: 294b883a add r5,r5,r5 + 151c: 117f2836 bltu r2,r5,11c0 <__alt_data_end+0xfffe11c0> + 1520: 283f2726 beq r5,zero,11c0 <__alt_data_end+0xfffe11c0> + 1524: 2886703a and r3,r5,r2 + 1528: 5809883a mov r4,r11 + 152c: 183ec31e bne r3,zero,103c <__alt_data_end+0xfffe103c> + 1530: 294b883a add r5,r5,r5 + 1534: 2886703a and r3,r5,r2 + 1538: 21000104 addi r4,r4,4 + 153c: 183ffc26 beq r3,zero,1530 <__alt_data_end+0xfffe1530> + 1540: 003ebe06 br 103c <__alt_data_end+0xfffe103c> + 1544: 00c05504 movi r3,340 + 1548: 18801236 bltu r3,r2,1594 <_malloc_r+0x6f8> + 154c: 8804d3fa srli r2,r17,15 + 1550: 12001e04 addi r8,r2,120 + 1554: 11c01dc4 addi r7,r2,119 + 1558: 4209883a add r4,r8,r8 + 155c: 003e6d06 br f14 <__alt_data_end+0xfffe0f14> + 1560: 00c40004 movi r3,4096 + 1564: 003f4606 br 1280 <__alt_data_end+0xfffe1280> + 1568: 00800044 movi r2,1 + 156c: a0800115 stw r2,4(r20) + 1570: 003f7406 br 1344 <__alt_data_end+0xfffe1344> + 1574: 1805d0ba srai r2,r3,2 + 1578: 01c00044 movi r7,1 + 157c: 30c00117 ldw r3,4(r6) + 1580: 388e983a sll r7,r7,r2 + 1584: 2805883a mov r2,r5 + 1588: 38c6b03a or r3,r7,r3 + 158c: 30c00115 stw r3,4(r6) + 1590: 003f9b06 br 1400 <__alt_data_end+0xfffe1400> + 1594: 00c15504 movi r3,1364 + 1598: 18801a36 bltu r3,r2,1604 <_malloc_r+0x768> + 159c: 8804d4ba srli r2,r17,18 + 15a0: 12001f44 addi r8,r2,125 + 15a4: 11c01f04 addi r7,r2,124 + 15a8: 4209883a add r4,r8,r8 + 15ac: 003e5906 br f14 <__alt_data_end+0xfffe0f14> + 15b0: ad400404 addi r21,r21,16 + 15b4: 003f1706 br 1214 <__alt_data_end+0xfffe1214> + 15b8: 00c01504 movi r3,84 + 15bc: 18802336 bltu r3,r2,164c <_malloc_r+0x7b0> + 15c0: 3804d33a srli r2,r7,12 + 15c4: 11401bc4 addi r5,r2,111 + 15c8: 10c01b84 addi r3,r2,110 + 15cc: 294b883a add r5,r5,r5 + 15d0: 003f7b06 br 13c0 <__alt_data_end+0xfffe13c0> + 15d4: 9c000217 ldw r16,8(r19) + 15d8: 00bfff04 movi r2,-4 + 15dc: 80c00117 ldw r3,4(r16) + 15e0: 1886703a and r3,r3,r2 + 15e4: 003f5306 br 1334 <__alt_data_end+0xfffe1334> + 15e8: 3083ffcc andi r2,r6,4095 + 15ec: 103f181e bne r2,zero,1250 <__alt_data_end+0xfffe1250> + 15f0: 99000217 ldw r4,8(r19) + 15f4: b545883a add r2,r22,r21 + 15f8: 10800054 ori r2,r2,1 + 15fc: 20800115 stw r2,4(r4) + 1600: 003f3e06 br 12fc <__alt_data_end+0xfffe12fc> + 1604: 01003f84 movi r4,254 + 1608: 02001fc4 movi r8,127 + 160c: 01c01f84 movi r7,126 + 1610: 003e4006 br f14 <__alt_data_end+0xfffe0f14> + 1614: 00800034 movhi r2,0 + 1618: 109c9804 addi r2,r2,29280 + 161c: 15000015 stw r20,0(r2) + 1620: 003f1106 br 1268 <__alt_data_end+0xfffe1268> + 1624: 00800044 movi r2,1 + 1628: 002b883a mov r21,zero + 162c: 003f1f06 br 12ac <__alt_data_end+0xfffe12ac> + 1630: 81400204 addi r5,r16,8 + 1634: 9009883a mov r4,r18 + 1638: 00029240 call 2924 <_free_r> + 163c: 00800034 movhi r2,0 + 1640: 109caf04 addi r2,r2,29372 + 1644: 10c00017 ldw r3,0(r2) + 1648: 003f2c06 br 12fc <__alt_data_end+0xfffe12fc> + 164c: 00c05504 movi r3,340 + 1650: 18800536 bltu r3,r2,1668 <_malloc_r+0x7cc> + 1654: 3804d3fa srli r2,r7,15 + 1658: 11401e04 addi r5,r2,120 + 165c: 10c01dc4 addi r3,r2,119 + 1660: 294b883a add r5,r5,r5 + 1664: 003f5606 br 13c0 <__alt_data_end+0xfffe13c0> + 1668: 00c15504 movi r3,1364 + 166c: 18800536 bltu r3,r2,1684 <_malloc_r+0x7e8> + 1670: 3804d4ba srli r2,r7,18 + 1674: 11401f44 addi r5,r2,125 + 1678: 10c01f04 addi r3,r2,124 + 167c: 294b883a add r5,r5,r5 + 1680: 003f4f06 br 13c0 <__alt_data_end+0xfffe13c0> + 1684: 01403f84 movi r5,254 + 1688: 00c01f84 movi r3,126 + 168c: 003f4c06 br 13c0 <__alt_data_end+0xfffe13c0> + 1690: 98800117 ldw r2,4(r19) + 1694: 003fa006 br 1518 <__alt_data_end+0xfffe1518> + 1698: 8808d0fa srli r4,r17,3 + 169c: 20800044 addi r2,r4,1 + 16a0: 1085883a add r2,r2,r2 + 16a4: 003e9006 br 10e8 <__alt_data_end+0xfffe10e8> + +000016a8 : + 16a8: 208000cc andi r2,r4,3 + 16ac: 280f883a mov r7,r5 + 16b0: 10003426 beq r2,zero,1784 + 16b4: 30bfffc4 addi r2,r6,-1 + 16b8: 30001a26 beq r6,zero,1724 + 16bc: 20c00003 ldbu r3,0(r4) + 16c0: 29803fcc andi r6,r5,255 + 16c4: 30c0051e bne r6,r3,16dc + 16c8: 00001806 br 172c + 16cc: 10001526 beq r2,zero,1724 + 16d0: 20c00003 ldbu r3,0(r4) + 16d4: 10bfffc4 addi r2,r2,-1 + 16d8: 30c01426 beq r6,r3,172c + 16dc: 21000044 addi r4,r4,1 + 16e0: 20c000cc andi r3,r4,3 + 16e4: 183ff91e bne r3,zero,16cc <__alt_data_end+0xfffe16cc> + 16e8: 020000c4 movi r8,3 + 16ec: 40801136 bltu r8,r2,1734 + 16f0: 10000c26 beq r2,zero,1724 + 16f4: 20c00003 ldbu r3,0(r4) + 16f8: 29403fcc andi r5,r5,255 + 16fc: 28c00b26 beq r5,r3,172c + 1700: 20c00044 addi r3,r4,1 + 1704: 39803fcc andi r6,r7,255 + 1708: 2089883a add r4,r4,r2 + 170c: 00000306 br 171c + 1710: 18c00044 addi r3,r3,1 + 1714: 197fffc3 ldbu r5,-1(r3) + 1718: 31400526 beq r6,r5,1730 + 171c: 1805883a mov r2,r3 + 1720: 20fffb1e bne r4,r3,1710 <__alt_data_end+0xfffe1710> + 1724: 0005883a mov r2,zero + 1728: f800283a ret + 172c: 2005883a mov r2,r4 + 1730: f800283a ret + 1734: 28c03fcc andi r3,r5,255 + 1738: 1812923a slli r9,r3,8 + 173c: 02ffbff4 movhi r11,65279 + 1740: 02a02074 movhi r10,32897 + 1744: 48d2b03a or r9,r9,r3 + 1748: 4806943a slli r3,r9,16 + 174c: 5affbfc4 addi r11,r11,-257 + 1750: 52a02004 addi r10,r10,-32640 + 1754: 48d2b03a or r9,r9,r3 + 1758: 20c00017 ldw r3,0(r4) + 175c: 48c6f03a xor r3,r9,r3 + 1760: 1acd883a add r6,r3,r11 + 1764: 00c6303a nor r3,zero,r3 + 1768: 30c6703a and r3,r6,r3 + 176c: 1a86703a and r3,r3,r10 + 1770: 183fe01e bne r3,zero,16f4 <__alt_data_end+0xfffe16f4> + 1774: 10bfff04 addi r2,r2,-4 + 1778: 21000104 addi r4,r4,4 + 177c: 40bff636 bltu r8,r2,1758 <__alt_data_end+0xfffe1758> + 1780: 003fdb06 br 16f0 <__alt_data_end+0xfffe16f0> + 1784: 3005883a mov r2,r6 + 1788: 003fd706 br 16e8 <__alt_data_end+0xfffe16e8> + +0000178c : + 178c: defffd04 addi sp,sp,-12 + 1790: dfc00215 stw ra,8(sp) + 1794: dc400115 stw r17,4(sp) + 1798: dc000015 stw r16,0(sp) + 179c: 00c003c4 movi r3,15 + 17a0: 2005883a mov r2,r4 + 17a4: 1980452e bgeu r3,r6,18bc + 17a8: 2906b03a or r3,r5,r4 + 17ac: 18c000cc andi r3,r3,3 + 17b0: 1800441e bne r3,zero,18c4 + 17b4: 347ffc04 addi r17,r6,-16 + 17b8: 8822d13a srli r17,r17,4 + 17bc: 28c00104 addi r3,r5,4 + 17c0: 23400104 addi r13,r4,4 + 17c4: 8820913a slli r16,r17,4 + 17c8: 2b000204 addi r12,r5,8 + 17cc: 22c00204 addi r11,r4,8 + 17d0: 84000504 addi r16,r16,20 + 17d4: 2a800304 addi r10,r5,12 + 17d8: 22400304 addi r9,r4,12 + 17dc: 2c21883a add r16,r5,r16 + 17e0: 2811883a mov r8,r5 + 17e4: 200f883a mov r7,r4 + 17e8: 41000017 ldw r4,0(r8) + 17ec: 1fc00017 ldw ra,0(r3) + 17f0: 63c00017 ldw r15,0(r12) + 17f4: 39000015 stw r4,0(r7) + 17f8: 53800017 ldw r14,0(r10) + 17fc: 6fc00015 stw ra,0(r13) + 1800: 5bc00015 stw r15,0(r11) + 1804: 4b800015 stw r14,0(r9) + 1808: 18c00404 addi r3,r3,16 + 180c: 39c00404 addi r7,r7,16 + 1810: 42000404 addi r8,r8,16 + 1814: 6b400404 addi r13,r13,16 + 1818: 63000404 addi r12,r12,16 + 181c: 5ac00404 addi r11,r11,16 + 1820: 52800404 addi r10,r10,16 + 1824: 4a400404 addi r9,r9,16 + 1828: 1c3fef1e bne r3,r16,17e8 <__alt_data_end+0xfffe17e8> + 182c: 89c00044 addi r7,r17,1 + 1830: 380e913a slli r7,r7,4 + 1834: 310003cc andi r4,r6,15 + 1838: 02c000c4 movi r11,3 + 183c: 11c7883a add r3,r2,r7 + 1840: 29cb883a add r5,r5,r7 + 1844: 5900212e bgeu r11,r4,18cc + 1848: 1813883a mov r9,r3 + 184c: 2811883a mov r8,r5 + 1850: 200f883a mov r7,r4 + 1854: 42800017 ldw r10,0(r8) + 1858: 4a400104 addi r9,r9,4 + 185c: 39ffff04 addi r7,r7,-4 + 1860: 4abfff15 stw r10,-4(r9) + 1864: 42000104 addi r8,r8,4 + 1868: 59fffa36 bltu r11,r7,1854 <__alt_data_end+0xfffe1854> + 186c: 213fff04 addi r4,r4,-4 + 1870: 2008d0ba srli r4,r4,2 + 1874: 318000cc andi r6,r6,3 + 1878: 21000044 addi r4,r4,1 + 187c: 2109883a add r4,r4,r4 + 1880: 2109883a add r4,r4,r4 + 1884: 1907883a add r3,r3,r4 + 1888: 290b883a add r5,r5,r4 + 188c: 30000626 beq r6,zero,18a8 + 1890: 198d883a add r6,r3,r6 + 1894: 29c00003 ldbu r7,0(r5) + 1898: 18c00044 addi r3,r3,1 + 189c: 29400044 addi r5,r5,1 + 18a0: 19ffffc5 stb r7,-1(r3) + 18a4: 19bffb1e bne r3,r6,1894 <__alt_data_end+0xfffe1894> + 18a8: dfc00217 ldw ra,8(sp) + 18ac: dc400117 ldw r17,4(sp) + 18b0: dc000017 ldw r16,0(sp) + 18b4: dec00304 addi sp,sp,12 + 18b8: f800283a ret + 18bc: 2007883a mov r3,r4 + 18c0: 003ff206 br 188c <__alt_data_end+0xfffe188c> + 18c4: 2007883a mov r3,r4 + 18c8: 003ff106 br 1890 <__alt_data_end+0xfffe1890> + 18cc: 200d883a mov r6,r4 + 18d0: 003fee06 br 188c <__alt_data_end+0xfffe188c> + +000018d4 : + 18d4: 2005883a mov r2,r4 + 18d8: 29000b2e bgeu r5,r4,1908 + 18dc: 298f883a add r7,r5,r6 + 18e0: 21c0092e bgeu r4,r7,1908 + 18e4: 2187883a add r3,r4,r6 + 18e8: 198bc83a sub r5,r3,r6 + 18ec: 30004826 beq r6,zero,1a10 + 18f0: 39ffffc4 addi r7,r7,-1 + 18f4: 39000003 ldbu r4,0(r7) + 18f8: 18ffffc4 addi r3,r3,-1 + 18fc: 19000005 stb r4,0(r3) + 1900: 28fffb1e bne r5,r3,18f0 <__alt_data_end+0xfffe18f0> + 1904: f800283a ret + 1908: 00c003c4 movi r3,15 + 190c: 1980412e bgeu r3,r6,1a14 + 1910: 2886b03a or r3,r5,r2 + 1914: 18c000cc andi r3,r3,3 + 1918: 1800401e bne r3,zero,1a1c + 191c: 33fffc04 addi r15,r6,-16 + 1920: 781ed13a srli r15,r15,4 + 1924: 28c00104 addi r3,r5,4 + 1928: 13400104 addi r13,r2,4 + 192c: 781c913a slli r14,r15,4 + 1930: 2b000204 addi r12,r5,8 + 1934: 12c00204 addi r11,r2,8 + 1938: 73800504 addi r14,r14,20 + 193c: 2a800304 addi r10,r5,12 + 1940: 12400304 addi r9,r2,12 + 1944: 2b9d883a add r14,r5,r14 + 1948: 2811883a mov r8,r5 + 194c: 100f883a mov r7,r2 + 1950: 41000017 ldw r4,0(r8) + 1954: 39c00404 addi r7,r7,16 + 1958: 18c00404 addi r3,r3,16 + 195c: 393ffc15 stw r4,-16(r7) + 1960: 193ffc17 ldw r4,-16(r3) + 1964: 6b400404 addi r13,r13,16 + 1968: 5ac00404 addi r11,r11,16 + 196c: 693ffc15 stw r4,-16(r13) + 1970: 61000017 ldw r4,0(r12) + 1974: 4a400404 addi r9,r9,16 + 1978: 42000404 addi r8,r8,16 + 197c: 593ffc15 stw r4,-16(r11) + 1980: 51000017 ldw r4,0(r10) + 1984: 63000404 addi r12,r12,16 + 1988: 52800404 addi r10,r10,16 + 198c: 493ffc15 stw r4,-16(r9) + 1990: 1bbfef1e bne r3,r14,1950 <__alt_data_end+0xfffe1950> + 1994: 79000044 addi r4,r15,1 + 1998: 2008913a slli r4,r4,4 + 199c: 328003cc andi r10,r6,15 + 19a0: 02c000c4 movi r11,3 + 19a4: 1107883a add r3,r2,r4 + 19a8: 290b883a add r5,r5,r4 + 19ac: 5a801e2e bgeu r11,r10,1a28 + 19b0: 1813883a mov r9,r3 + 19b4: 2811883a mov r8,r5 + 19b8: 500f883a mov r7,r10 + 19bc: 41000017 ldw r4,0(r8) + 19c0: 4a400104 addi r9,r9,4 + 19c4: 39ffff04 addi r7,r7,-4 + 19c8: 493fff15 stw r4,-4(r9) + 19cc: 42000104 addi r8,r8,4 + 19d0: 59fffa36 bltu r11,r7,19bc <__alt_data_end+0xfffe19bc> + 19d4: 513fff04 addi r4,r10,-4 + 19d8: 2008d0ba srli r4,r4,2 + 19dc: 318000cc andi r6,r6,3 + 19e0: 21000044 addi r4,r4,1 + 19e4: 2109883a add r4,r4,r4 + 19e8: 2109883a add r4,r4,r4 + 19ec: 1907883a add r3,r3,r4 + 19f0: 290b883a add r5,r5,r4 + 19f4: 30000b26 beq r6,zero,1a24 + 19f8: 198d883a add r6,r3,r6 + 19fc: 29c00003 ldbu r7,0(r5) + 1a00: 18c00044 addi r3,r3,1 + 1a04: 29400044 addi r5,r5,1 + 1a08: 19ffffc5 stb r7,-1(r3) + 1a0c: 19bffb1e bne r3,r6,19fc <__alt_data_end+0xfffe19fc> + 1a10: f800283a ret + 1a14: 1007883a mov r3,r2 + 1a18: 003ff606 br 19f4 <__alt_data_end+0xfffe19f4> + 1a1c: 1007883a mov r3,r2 + 1a20: 003ff506 br 19f8 <__alt_data_end+0xfffe19f8> + 1a24: f800283a ret + 1a28: 500d883a mov r6,r10 + 1a2c: 003ff106 br 19f4 <__alt_data_end+0xfffe19f4> + +00001a30 : + 1a30: 20c000cc andi r3,r4,3 + 1a34: 2005883a mov r2,r4 + 1a38: 18004426 beq r3,zero,1b4c + 1a3c: 31ffffc4 addi r7,r6,-1 + 1a40: 30004026 beq r6,zero,1b44 + 1a44: 2813883a mov r9,r5 + 1a48: 200d883a mov r6,r4 + 1a4c: 2007883a mov r3,r4 + 1a50: 00000406 br 1a64 + 1a54: 3a3fffc4 addi r8,r7,-1 + 1a58: 31800044 addi r6,r6,1 + 1a5c: 38003926 beq r7,zero,1b44 + 1a60: 400f883a mov r7,r8 + 1a64: 18c00044 addi r3,r3,1 + 1a68: 32400005 stb r9,0(r6) + 1a6c: 1a0000cc andi r8,r3,3 + 1a70: 403ff81e bne r8,zero,1a54 <__alt_data_end+0xfffe1a54> + 1a74: 010000c4 movi r4,3 + 1a78: 21c02d2e bgeu r4,r7,1b30 + 1a7c: 29003fcc andi r4,r5,255 + 1a80: 200c923a slli r6,r4,8 + 1a84: 3108b03a or r4,r6,r4 + 1a88: 200c943a slli r6,r4,16 + 1a8c: 218cb03a or r6,r4,r6 + 1a90: 010003c4 movi r4,15 + 1a94: 21c0182e bgeu r4,r7,1af8 + 1a98: 3b3ffc04 addi r12,r7,-16 + 1a9c: 6018d13a srli r12,r12,4 + 1aa0: 1a000104 addi r8,r3,4 + 1aa4: 1ac00204 addi r11,r3,8 + 1aa8: 6008913a slli r4,r12,4 + 1aac: 1a800304 addi r10,r3,12 + 1ab0: 1813883a mov r9,r3 + 1ab4: 21000504 addi r4,r4,20 + 1ab8: 1909883a add r4,r3,r4 + 1abc: 49800015 stw r6,0(r9) + 1ac0: 41800015 stw r6,0(r8) + 1ac4: 59800015 stw r6,0(r11) + 1ac8: 51800015 stw r6,0(r10) + 1acc: 42000404 addi r8,r8,16 + 1ad0: 4a400404 addi r9,r9,16 + 1ad4: 5ac00404 addi r11,r11,16 + 1ad8: 52800404 addi r10,r10,16 + 1adc: 413ff71e bne r8,r4,1abc <__alt_data_end+0xfffe1abc> + 1ae0: 63000044 addi r12,r12,1 + 1ae4: 6018913a slli r12,r12,4 + 1ae8: 39c003cc andi r7,r7,15 + 1aec: 010000c4 movi r4,3 + 1af0: 1b07883a add r3,r3,r12 + 1af4: 21c00e2e bgeu r4,r7,1b30 + 1af8: 1813883a mov r9,r3 + 1afc: 3811883a mov r8,r7 + 1b00: 010000c4 movi r4,3 + 1b04: 49800015 stw r6,0(r9) + 1b08: 423fff04 addi r8,r8,-4 + 1b0c: 4a400104 addi r9,r9,4 + 1b10: 223ffc36 bltu r4,r8,1b04 <__alt_data_end+0xfffe1b04> + 1b14: 393fff04 addi r4,r7,-4 + 1b18: 2008d0ba srli r4,r4,2 + 1b1c: 39c000cc andi r7,r7,3 + 1b20: 21000044 addi r4,r4,1 + 1b24: 2109883a add r4,r4,r4 + 1b28: 2109883a add r4,r4,r4 + 1b2c: 1907883a add r3,r3,r4 + 1b30: 38000526 beq r7,zero,1b48 + 1b34: 19cf883a add r7,r3,r7 + 1b38: 19400005 stb r5,0(r3) + 1b3c: 18c00044 addi r3,r3,1 + 1b40: 38fffd1e bne r7,r3,1b38 <__alt_data_end+0xfffe1b38> + 1b44: f800283a ret + 1b48: f800283a ret + 1b4c: 2007883a mov r3,r4 + 1b50: 300f883a mov r7,r6 + 1b54: 003fc706 br 1a74 <__alt_data_end+0xfffe1a74> + +00001b58 <_realloc_r>: + 1b58: defff604 addi sp,sp,-40 + 1b5c: dc800215 stw r18,8(sp) + 1b60: dfc00915 stw ra,36(sp) + 1b64: df000815 stw fp,32(sp) + 1b68: ddc00715 stw r23,28(sp) + 1b6c: dd800615 stw r22,24(sp) + 1b70: dd400515 stw r21,20(sp) + 1b74: dd000415 stw r20,16(sp) + 1b78: dcc00315 stw r19,12(sp) + 1b7c: dc400115 stw r17,4(sp) + 1b80: dc000015 stw r16,0(sp) + 1b84: 3025883a mov r18,r6 + 1b88: 2800b726 beq r5,zero,1e68 <_realloc_r+0x310> + 1b8c: 282b883a mov r21,r5 + 1b90: 2029883a mov r20,r4 + 1b94: 00036140 call 3614 <__malloc_lock> + 1b98: a8bfff17 ldw r2,-4(r21) + 1b9c: 043fff04 movi r16,-4 + 1ba0: 90c002c4 addi r3,r18,11 + 1ba4: 01000584 movi r4,22 + 1ba8: acfffe04 addi r19,r21,-8 + 1bac: 1420703a and r16,r2,r16 + 1bb0: 20c0332e bgeu r4,r3,1c80 <_realloc_r+0x128> + 1bb4: 047ffe04 movi r17,-8 + 1bb8: 1c62703a and r17,r3,r17 + 1bbc: 8807883a mov r3,r17 + 1bc0: 88005816 blt r17,zero,1d24 <_realloc_r+0x1cc> + 1bc4: 8c805736 bltu r17,r18,1d24 <_realloc_r+0x1cc> + 1bc8: 80c0300e bge r16,r3,1c8c <_realloc_r+0x134> + 1bcc: 07000034 movhi fp,0 + 1bd0: e7171204 addi fp,fp,23624 + 1bd4: e1c00217 ldw r7,8(fp) + 1bd8: 9c09883a add r4,r19,r16 + 1bdc: 22000117 ldw r8,4(r4) + 1be0: 21c06326 beq r4,r7,1d70 <_realloc_r+0x218> + 1be4: 017fff84 movi r5,-2 + 1be8: 414a703a and r5,r8,r5 + 1bec: 214b883a add r5,r4,r5 + 1bf0: 29800117 ldw r6,4(r5) + 1bf4: 3180004c andi r6,r6,1 + 1bf8: 30003f26 beq r6,zero,1cf8 <_realloc_r+0x1a0> + 1bfc: 1080004c andi r2,r2,1 + 1c00: 10008326 beq r2,zero,1e10 <_realloc_r+0x2b8> + 1c04: 900b883a mov r5,r18 + 1c08: a009883a mov r4,r20 + 1c0c: 0000e9c0 call e9c <_malloc_r> + 1c10: 1025883a mov r18,r2 + 1c14: 10011e26 beq r2,zero,2090 <_realloc_r+0x538> + 1c18: a93fff17 ldw r4,-4(r21) + 1c1c: 10fffe04 addi r3,r2,-8 + 1c20: 00bfff84 movi r2,-2 + 1c24: 2084703a and r2,r4,r2 + 1c28: 9885883a add r2,r19,r2 + 1c2c: 1880ee26 beq r3,r2,1fe8 <_realloc_r+0x490> + 1c30: 81bfff04 addi r6,r16,-4 + 1c34: 00800904 movi r2,36 + 1c38: 1180b836 bltu r2,r6,1f1c <_realloc_r+0x3c4> + 1c3c: 00c004c4 movi r3,19 + 1c40: 19809636 bltu r3,r6,1e9c <_realloc_r+0x344> + 1c44: 9005883a mov r2,r18 + 1c48: a807883a mov r3,r21 + 1c4c: 19000017 ldw r4,0(r3) + 1c50: 11000015 stw r4,0(r2) + 1c54: 19000117 ldw r4,4(r3) + 1c58: 11000115 stw r4,4(r2) + 1c5c: 18c00217 ldw r3,8(r3) + 1c60: 10c00215 stw r3,8(r2) + 1c64: a80b883a mov r5,r21 + 1c68: a009883a mov r4,r20 + 1c6c: 00029240 call 2924 <_free_r> + 1c70: a009883a mov r4,r20 + 1c74: 00036380 call 3638 <__malloc_unlock> + 1c78: 9005883a mov r2,r18 + 1c7c: 00001206 br 1cc8 <_realloc_r+0x170> + 1c80: 00c00404 movi r3,16 + 1c84: 1823883a mov r17,r3 + 1c88: 003fce06 br 1bc4 <__alt_data_end+0xfffe1bc4> + 1c8c: a825883a mov r18,r21 + 1c90: 8445c83a sub r2,r16,r17 + 1c94: 00c003c4 movi r3,15 + 1c98: 18802636 bltu r3,r2,1d34 <_realloc_r+0x1dc> + 1c9c: 99800117 ldw r6,4(r19) + 1ca0: 9c07883a add r3,r19,r16 + 1ca4: 3180004c andi r6,r6,1 + 1ca8: 3420b03a or r16,r6,r16 + 1cac: 9c000115 stw r16,4(r19) + 1cb0: 18800117 ldw r2,4(r3) + 1cb4: 10800054 ori r2,r2,1 + 1cb8: 18800115 stw r2,4(r3) + 1cbc: a009883a mov r4,r20 + 1cc0: 00036380 call 3638 <__malloc_unlock> + 1cc4: 9005883a mov r2,r18 + 1cc8: dfc00917 ldw ra,36(sp) + 1ccc: df000817 ldw fp,32(sp) + 1cd0: ddc00717 ldw r23,28(sp) + 1cd4: dd800617 ldw r22,24(sp) + 1cd8: dd400517 ldw r21,20(sp) + 1cdc: dd000417 ldw r20,16(sp) + 1ce0: dcc00317 ldw r19,12(sp) + 1ce4: dc800217 ldw r18,8(sp) + 1ce8: dc400117 ldw r17,4(sp) + 1cec: dc000017 ldw r16,0(sp) + 1cf0: dec00a04 addi sp,sp,40 + 1cf4: f800283a ret + 1cf8: 017fff04 movi r5,-4 + 1cfc: 414a703a and r5,r8,r5 + 1d00: 814d883a add r6,r16,r5 + 1d04: 30c01f16 blt r6,r3,1d84 <_realloc_r+0x22c> + 1d08: 20800317 ldw r2,12(r4) + 1d0c: 20c00217 ldw r3,8(r4) + 1d10: a825883a mov r18,r21 + 1d14: 3021883a mov r16,r6 + 1d18: 18800315 stw r2,12(r3) + 1d1c: 10c00215 stw r3,8(r2) + 1d20: 003fdb06 br 1c90 <__alt_data_end+0xfffe1c90> + 1d24: 00800304 movi r2,12 + 1d28: a0800015 stw r2,0(r20) + 1d2c: 0005883a mov r2,zero + 1d30: 003fe506 br 1cc8 <__alt_data_end+0xfffe1cc8> + 1d34: 98c00117 ldw r3,4(r19) + 1d38: 9c4b883a add r5,r19,r17 + 1d3c: 11000054 ori r4,r2,1 + 1d40: 18c0004c andi r3,r3,1 + 1d44: 1c62b03a or r17,r3,r17 + 1d48: 9c400115 stw r17,4(r19) + 1d4c: 29000115 stw r4,4(r5) + 1d50: 2885883a add r2,r5,r2 + 1d54: 10c00117 ldw r3,4(r2) + 1d58: 29400204 addi r5,r5,8 + 1d5c: a009883a mov r4,r20 + 1d60: 18c00054 ori r3,r3,1 + 1d64: 10c00115 stw r3,4(r2) + 1d68: 00029240 call 2924 <_free_r> + 1d6c: 003fd306 br 1cbc <__alt_data_end+0xfffe1cbc> + 1d70: 017fff04 movi r5,-4 + 1d74: 414a703a and r5,r8,r5 + 1d78: 89800404 addi r6,r17,16 + 1d7c: 8151883a add r8,r16,r5 + 1d80: 4180590e bge r8,r6,1ee8 <_realloc_r+0x390> + 1d84: 1080004c andi r2,r2,1 + 1d88: 103f9e1e bne r2,zero,1c04 <__alt_data_end+0xfffe1c04> + 1d8c: adbffe17 ldw r22,-8(r21) + 1d90: 00bfff04 movi r2,-4 + 1d94: 9dadc83a sub r22,r19,r22 + 1d98: b1800117 ldw r6,4(r22) + 1d9c: 3084703a and r2,r6,r2 + 1da0: 20002026 beq r4,zero,1e24 <_realloc_r+0x2cc> + 1da4: 80af883a add r23,r16,r2 + 1da8: b96f883a add r23,r23,r5 + 1dac: 21c05f26 beq r4,r7,1f2c <_realloc_r+0x3d4> + 1db0: b8c01c16 blt r23,r3,1e24 <_realloc_r+0x2cc> + 1db4: 20800317 ldw r2,12(r4) + 1db8: 20c00217 ldw r3,8(r4) + 1dbc: 81bfff04 addi r6,r16,-4 + 1dc0: 01000904 movi r4,36 + 1dc4: 18800315 stw r2,12(r3) + 1dc8: 10c00215 stw r3,8(r2) + 1dcc: b0c00217 ldw r3,8(r22) + 1dd0: b0800317 ldw r2,12(r22) + 1dd4: b4800204 addi r18,r22,8 + 1dd8: 18800315 stw r2,12(r3) + 1ddc: 10c00215 stw r3,8(r2) + 1de0: 21801b36 bltu r4,r6,1e50 <_realloc_r+0x2f8> + 1de4: 008004c4 movi r2,19 + 1de8: 1180352e bgeu r2,r6,1ec0 <_realloc_r+0x368> + 1dec: a8800017 ldw r2,0(r21) + 1df0: b0800215 stw r2,8(r22) + 1df4: a8800117 ldw r2,4(r21) + 1df8: b0800315 stw r2,12(r22) + 1dfc: 008006c4 movi r2,27 + 1e00: 11807f36 bltu r2,r6,2000 <_realloc_r+0x4a8> + 1e04: b0800404 addi r2,r22,16 + 1e08: ad400204 addi r21,r21,8 + 1e0c: 00002d06 br 1ec4 <_realloc_r+0x36c> + 1e10: adbffe17 ldw r22,-8(r21) + 1e14: 00bfff04 movi r2,-4 + 1e18: 9dadc83a sub r22,r19,r22 + 1e1c: b1000117 ldw r4,4(r22) + 1e20: 2084703a and r2,r4,r2 + 1e24: b03f7726 beq r22,zero,1c04 <__alt_data_end+0xfffe1c04> + 1e28: 80af883a add r23,r16,r2 + 1e2c: b8ff7516 blt r23,r3,1c04 <__alt_data_end+0xfffe1c04> + 1e30: b0800317 ldw r2,12(r22) + 1e34: b0c00217 ldw r3,8(r22) + 1e38: 81bfff04 addi r6,r16,-4 + 1e3c: 01000904 movi r4,36 + 1e40: 18800315 stw r2,12(r3) + 1e44: 10c00215 stw r3,8(r2) + 1e48: b4800204 addi r18,r22,8 + 1e4c: 21bfe52e bgeu r4,r6,1de4 <__alt_data_end+0xfffe1de4> + 1e50: a80b883a mov r5,r21 + 1e54: 9009883a mov r4,r18 + 1e58: 00018d40 call 18d4 + 1e5c: b821883a mov r16,r23 + 1e60: b027883a mov r19,r22 + 1e64: 003f8a06 br 1c90 <__alt_data_end+0xfffe1c90> + 1e68: 300b883a mov r5,r6 + 1e6c: dfc00917 ldw ra,36(sp) + 1e70: df000817 ldw fp,32(sp) + 1e74: ddc00717 ldw r23,28(sp) + 1e78: dd800617 ldw r22,24(sp) + 1e7c: dd400517 ldw r21,20(sp) + 1e80: dd000417 ldw r20,16(sp) + 1e84: dcc00317 ldw r19,12(sp) + 1e88: dc800217 ldw r18,8(sp) + 1e8c: dc400117 ldw r17,4(sp) + 1e90: dc000017 ldw r16,0(sp) + 1e94: dec00a04 addi sp,sp,40 + 1e98: 0000e9c1 jmpi e9c <_malloc_r> + 1e9c: a8c00017 ldw r3,0(r21) + 1ea0: 90c00015 stw r3,0(r18) + 1ea4: a8c00117 ldw r3,4(r21) + 1ea8: 90c00115 stw r3,4(r18) + 1eac: 00c006c4 movi r3,27 + 1eb0: 19804536 bltu r3,r6,1fc8 <_realloc_r+0x470> + 1eb4: 90800204 addi r2,r18,8 + 1eb8: a8c00204 addi r3,r21,8 + 1ebc: 003f6306 br 1c4c <__alt_data_end+0xfffe1c4c> + 1ec0: 9005883a mov r2,r18 + 1ec4: a8c00017 ldw r3,0(r21) + 1ec8: b821883a mov r16,r23 + 1ecc: b027883a mov r19,r22 + 1ed0: 10c00015 stw r3,0(r2) + 1ed4: a8c00117 ldw r3,4(r21) + 1ed8: 10c00115 stw r3,4(r2) + 1edc: a8c00217 ldw r3,8(r21) + 1ee0: 10c00215 stw r3,8(r2) + 1ee4: 003f6a06 br 1c90 <__alt_data_end+0xfffe1c90> + 1ee8: 9c67883a add r19,r19,r17 + 1eec: 4445c83a sub r2,r8,r17 + 1ef0: e4c00215 stw r19,8(fp) + 1ef4: 10800054 ori r2,r2,1 + 1ef8: 98800115 stw r2,4(r19) + 1efc: a8bfff17 ldw r2,-4(r21) + 1f00: a009883a mov r4,r20 + 1f04: 1080004c andi r2,r2,1 + 1f08: 1462b03a or r17,r2,r17 + 1f0c: ac7fff15 stw r17,-4(r21) + 1f10: 00036380 call 3638 <__malloc_unlock> + 1f14: a805883a mov r2,r21 + 1f18: 003f6b06 br 1cc8 <__alt_data_end+0xfffe1cc8> + 1f1c: a80b883a mov r5,r21 + 1f20: 9009883a mov r4,r18 + 1f24: 00018d40 call 18d4 + 1f28: 003f4e06 br 1c64 <__alt_data_end+0xfffe1c64> + 1f2c: 89000404 addi r4,r17,16 + 1f30: b93fbc16 blt r23,r4,1e24 <__alt_data_end+0xfffe1e24> + 1f34: b0800317 ldw r2,12(r22) + 1f38: b0c00217 ldw r3,8(r22) + 1f3c: 81bfff04 addi r6,r16,-4 + 1f40: 01000904 movi r4,36 + 1f44: 18800315 stw r2,12(r3) + 1f48: 10c00215 stw r3,8(r2) + 1f4c: b4800204 addi r18,r22,8 + 1f50: 21804336 bltu r4,r6,2060 <_realloc_r+0x508> + 1f54: 008004c4 movi r2,19 + 1f58: 11803f2e bgeu r2,r6,2058 <_realloc_r+0x500> + 1f5c: a8800017 ldw r2,0(r21) + 1f60: b0800215 stw r2,8(r22) + 1f64: a8800117 ldw r2,4(r21) + 1f68: b0800315 stw r2,12(r22) + 1f6c: 008006c4 movi r2,27 + 1f70: 11803f36 bltu r2,r6,2070 <_realloc_r+0x518> + 1f74: b0800404 addi r2,r22,16 + 1f78: ad400204 addi r21,r21,8 + 1f7c: a8c00017 ldw r3,0(r21) + 1f80: 10c00015 stw r3,0(r2) + 1f84: a8c00117 ldw r3,4(r21) + 1f88: 10c00115 stw r3,4(r2) + 1f8c: a8c00217 ldw r3,8(r21) + 1f90: 10c00215 stw r3,8(r2) + 1f94: b447883a add r3,r22,r17 + 1f98: bc45c83a sub r2,r23,r17 + 1f9c: e0c00215 stw r3,8(fp) + 1fa0: 10800054 ori r2,r2,1 + 1fa4: 18800115 stw r2,4(r3) + 1fa8: b0800117 ldw r2,4(r22) + 1fac: a009883a mov r4,r20 + 1fb0: 1080004c andi r2,r2,1 + 1fb4: 1462b03a or r17,r2,r17 + 1fb8: b4400115 stw r17,4(r22) + 1fbc: 00036380 call 3638 <__malloc_unlock> + 1fc0: 9005883a mov r2,r18 + 1fc4: 003f4006 br 1cc8 <__alt_data_end+0xfffe1cc8> + 1fc8: a8c00217 ldw r3,8(r21) + 1fcc: 90c00215 stw r3,8(r18) + 1fd0: a8c00317 ldw r3,12(r21) + 1fd4: 90c00315 stw r3,12(r18) + 1fd8: 30801126 beq r6,r2,2020 <_realloc_r+0x4c8> + 1fdc: 90800404 addi r2,r18,16 + 1fe0: a8c00404 addi r3,r21,16 + 1fe4: 003f1906 br 1c4c <__alt_data_end+0xfffe1c4c> + 1fe8: 90ffff17 ldw r3,-4(r18) + 1fec: 00bfff04 movi r2,-4 + 1ff0: a825883a mov r18,r21 + 1ff4: 1884703a and r2,r3,r2 + 1ff8: 80a1883a add r16,r16,r2 + 1ffc: 003f2406 br 1c90 <__alt_data_end+0xfffe1c90> + 2000: a8800217 ldw r2,8(r21) + 2004: b0800415 stw r2,16(r22) + 2008: a8800317 ldw r2,12(r21) + 200c: b0800515 stw r2,20(r22) + 2010: 31000a26 beq r6,r4,203c <_realloc_r+0x4e4> + 2014: b0800604 addi r2,r22,24 + 2018: ad400404 addi r21,r21,16 + 201c: 003fa906 br 1ec4 <__alt_data_end+0xfffe1ec4> + 2020: a9000417 ldw r4,16(r21) + 2024: 90800604 addi r2,r18,24 + 2028: a8c00604 addi r3,r21,24 + 202c: 91000415 stw r4,16(r18) + 2030: a9000517 ldw r4,20(r21) + 2034: 91000515 stw r4,20(r18) + 2038: 003f0406 br 1c4c <__alt_data_end+0xfffe1c4c> + 203c: a8c00417 ldw r3,16(r21) + 2040: ad400604 addi r21,r21,24 + 2044: b0800804 addi r2,r22,32 + 2048: b0c00615 stw r3,24(r22) + 204c: a8ffff17 ldw r3,-4(r21) + 2050: b0c00715 stw r3,28(r22) + 2054: 003f9b06 br 1ec4 <__alt_data_end+0xfffe1ec4> + 2058: 9005883a mov r2,r18 + 205c: 003fc706 br 1f7c <__alt_data_end+0xfffe1f7c> + 2060: a80b883a mov r5,r21 + 2064: 9009883a mov r4,r18 + 2068: 00018d40 call 18d4 + 206c: 003fc906 br 1f94 <__alt_data_end+0xfffe1f94> + 2070: a8800217 ldw r2,8(r21) + 2074: b0800415 stw r2,16(r22) + 2078: a8800317 ldw r2,12(r21) + 207c: b0800515 stw r2,20(r22) + 2080: 31000726 beq r6,r4,20a0 <_realloc_r+0x548> + 2084: b0800604 addi r2,r22,24 + 2088: ad400404 addi r21,r21,16 + 208c: 003fbb06 br 1f7c <__alt_data_end+0xfffe1f7c> + 2090: a009883a mov r4,r20 + 2094: 00036380 call 3638 <__malloc_unlock> + 2098: 0005883a mov r2,zero + 209c: 003f0a06 br 1cc8 <__alt_data_end+0xfffe1cc8> + 20a0: a8c00417 ldw r3,16(r21) + 20a4: ad400604 addi r21,r21,24 + 20a8: b0800804 addi r2,r22,32 + 20ac: b0c00615 stw r3,24(r22) + 20b0: a8ffff17 ldw r3,-4(r21) + 20b4: b0c00715 stw r3,28(r22) + 20b8: 003fb006 br 1f7c <__alt_data_end+0xfffe1f7c> + +000020bc <_sbrk_r>: + 20bc: defffd04 addi sp,sp,-12 + 20c0: dc000015 stw r16,0(sp) + 20c4: 04000034 movhi r16,0 + 20c8: dc400115 stw r17,4(sp) + 20cc: 841ca704 addi r16,r16,29340 + 20d0: 2023883a mov r17,r4 + 20d4: 2809883a mov r4,r5 + 20d8: dfc00215 stw ra,8(sp) + 20dc: 80000015 stw zero,0(r16) + 20e0: 00038200 call 3820 + 20e4: 00ffffc4 movi r3,-1 + 20e8: 10c00526 beq r2,r3,2100 <_sbrk_r+0x44> + 20ec: dfc00217 ldw ra,8(sp) + 20f0: dc400117 ldw r17,4(sp) + 20f4: dc000017 ldw r16,0(sp) + 20f8: dec00304 addi sp,sp,12 + 20fc: f800283a ret + 2100: 80c00017 ldw r3,0(r16) + 2104: 183ff926 beq r3,zero,20ec <__alt_data_end+0xfffe20ec> + 2108: 88c00015 stw r3,0(r17) + 210c: 003ff706 br 20ec <__alt_data_end+0xfffe20ec> + +00002110 <__sread>: + 2110: defffe04 addi sp,sp,-8 + 2114: dc000015 stw r16,0(sp) + 2118: 2821883a mov r16,r5 + 211c: 2940038f ldh r5,14(r5) + 2120: dfc00115 stw ra,4(sp) + 2124: 0002e500 call 2e50 <_read_r> + 2128: 10000716 blt r2,zero,2148 <__sread+0x38> + 212c: 80c01417 ldw r3,80(r16) + 2130: 1887883a add r3,r3,r2 + 2134: 80c01415 stw r3,80(r16) + 2138: dfc00117 ldw ra,4(sp) + 213c: dc000017 ldw r16,0(sp) + 2140: dec00204 addi sp,sp,8 + 2144: f800283a ret + 2148: 80c0030b ldhu r3,12(r16) + 214c: 18fbffcc andi r3,r3,61439 + 2150: 80c0030d sth r3,12(r16) + 2154: dfc00117 ldw ra,4(sp) + 2158: dc000017 ldw r16,0(sp) + 215c: dec00204 addi sp,sp,8 + 2160: f800283a ret + +00002164 <__seofread>: + 2164: 0005883a mov r2,zero + 2168: f800283a ret + +0000216c <__swrite>: + 216c: 2880030b ldhu r2,12(r5) + 2170: defffb04 addi sp,sp,-20 + 2174: dcc00315 stw r19,12(sp) + 2178: dc800215 stw r18,8(sp) + 217c: dc400115 stw r17,4(sp) + 2180: dc000015 stw r16,0(sp) + 2184: dfc00415 stw ra,16(sp) + 2188: 10c0400c andi r3,r2,256 + 218c: 2821883a mov r16,r5 + 2190: 2023883a mov r17,r4 + 2194: 3025883a mov r18,r6 + 2198: 3827883a mov r19,r7 + 219c: 18000526 beq r3,zero,21b4 <__swrite+0x48> + 21a0: 2940038f ldh r5,14(r5) + 21a4: 01c00084 movi r7,2 + 21a8: 000d883a mov r6,zero + 21ac: 0002c340 call 2c34 <_lseek_r> + 21b0: 8080030b ldhu r2,12(r16) + 21b4: 8140038f ldh r5,14(r16) + 21b8: 10bbffcc andi r2,r2,61439 + 21bc: 980f883a mov r7,r19 + 21c0: 900d883a mov r6,r18 + 21c4: 8809883a mov r4,r17 + 21c8: 8080030d sth r2,12(r16) + 21cc: dfc00417 ldw ra,16(sp) + 21d0: dcc00317 ldw r19,12(sp) + 21d4: dc800217 ldw r18,8(sp) + 21d8: dc400117 ldw r17,4(sp) + 21dc: dc000017 ldw r16,0(sp) + 21e0: dec00504 addi sp,sp,20 + 21e4: 000224c1 jmpi 224c <_write_r> + +000021e8 <__sseek>: + 21e8: defffe04 addi sp,sp,-8 + 21ec: dc000015 stw r16,0(sp) + 21f0: 2821883a mov r16,r5 + 21f4: 2940038f ldh r5,14(r5) + 21f8: dfc00115 stw ra,4(sp) + 21fc: 0002c340 call 2c34 <_lseek_r> + 2200: 00ffffc4 movi r3,-1 + 2204: 10c00826 beq r2,r3,2228 <__sseek+0x40> + 2208: 80c0030b ldhu r3,12(r16) + 220c: 80801415 stw r2,80(r16) + 2210: 18c40014 ori r3,r3,4096 + 2214: 80c0030d sth r3,12(r16) + 2218: dfc00117 ldw ra,4(sp) + 221c: dc000017 ldw r16,0(sp) + 2220: dec00204 addi sp,sp,8 + 2224: f800283a ret + 2228: 80c0030b ldhu r3,12(r16) + 222c: 18fbffcc andi r3,r3,61439 + 2230: 80c0030d sth r3,12(r16) + 2234: dfc00117 ldw ra,4(sp) + 2238: dc000017 ldw r16,0(sp) + 223c: dec00204 addi sp,sp,8 + 2240: f800283a ret + +00002244 <__sclose>: + 2244: 2940038f ldh r5,14(r5) + 2248: 00024001 jmpi 2400 <_close_r> + +0000224c <_write_r>: + 224c: defffd04 addi sp,sp,-12 + 2250: 2805883a mov r2,r5 + 2254: dc000015 stw r16,0(sp) + 2258: 04000034 movhi r16,0 + 225c: dc400115 stw r17,4(sp) + 2260: 300b883a mov r5,r6 + 2264: 841ca704 addi r16,r16,29340 + 2268: 2023883a mov r17,r4 + 226c: 380d883a mov r6,r7 + 2270: 1009883a mov r4,r2 + 2274: dfc00215 stw ra,8(sp) + 2278: 80000015 stw zero,0(r16) + 227c: 000390c0 call 390c + 2280: 00ffffc4 movi r3,-1 + 2284: 10c00526 beq r2,r3,229c <_write_r+0x50> + 2288: dfc00217 ldw ra,8(sp) + 228c: dc400117 ldw r17,4(sp) + 2290: dc000017 ldw r16,0(sp) + 2294: dec00304 addi sp,sp,12 + 2298: f800283a ret + 229c: 80c00017 ldw r3,0(r16) + 22a0: 183ff926 beq r3,zero,2288 <__alt_data_end+0xfffe2288> + 22a4: 88c00015 stw r3,0(r17) + 22a8: 003ff706 br 2288 <__alt_data_end+0xfffe2288> + +000022ac <__swsetup_r>: + 22ac: 00800034 movhi r2,0 + 22b0: defffd04 addi sp,sp,-12 + 22b4: 109c9704 addi r2,r2,29276 + 22b8: dc400115 stw r17,4(sp) + 22bc: 2023883a mov r17,r4 + 22c0: 11000017 ldw r4,0(r2) + 22c4: dc000015 stw r16,0(sp) + 22c8: dfc00215 stw ra,8(sp) + 22cc: 2821883a mov r16,r5 + 22d0: 20000226 beq r4,zero,22dc <__swsetup_r+0x30> + 22d4: 20800e17 ldw r2,56(r4) + 22d8: 10003126 beq r2,zero,23a0 <__swsetup_r+0xf4> + 22dc: 8080030b ldhu r2,12(r16) + 22e0: 10c0020c andi r3,r2,8 + 22e4: 1009883a mov r4,r2 + 22e8: 18000f26 beq r3,zero,2328 <__swsetup_r+0x7c> + 22ec: 80c00417 ldw r3,16(r16) + 22f0: 18001526 beq r3,zero,2348 <__swsetup_r+0x9c> + 22f4: 1100004c andi r4,r2,1 + 22f8: 20001c1e bne r4,zero,236c <__swsetup_r+0xc0> + 22fc: 1080008c andi r2,r2,2 + 2300: 1000291e bne r2,zero,23a8 <__swsetup_r+0xfc> + 2304: 80800517 ldw r2,20(r16) + 2308: 80800215 stw r2,8(r16) + 230c: 18001c26 beq r3,zero,2380 <__swsetup_r+0xd4> + 2310: 0005883a mov r2,zero + 2314: dfc00217 ldw ra,8(sp) + 2318: dc400117 ldw r17,4(sp) + 231c: dc000017 ldw r16,0(sp) + 2320: dec00304 addi sp,sp,12 + 2324: f800283a ret + 2328: 2080040c andi r2,r4,16 + 232c: 10002e26 beq r2,zero,23e8 <__swsetup_r+0x13c> + 2330: 2080010c andi r2,r4,4 + 2334: 10001e1e bne r2,zero,23b0 <__swsetup_r+0x104> + 2338: 80c00417 ldw r3,16(r16) + 233c: 20800214 ori r2,r4,8 + 2340: 8080030d sth r2,12(r16) + 2344: 183feb1e bne r3,zero,22f4 <__alt_data_end+0xfffe22f4> + 2348: 1100a00c andi r4,r2,640 + 234c: 01408004 movi r5,512 + 2350: 217fe826 beq r4,r5,22f4 <__alt_data_end+0xfffe22f4> + 2354: 800b883a mov r5,r16 + 2358: 8809883a mov r4,r17 + 235c: 0002c940 call 2c94 <__smakebuf_r> + 2360: 8080030b ldhu r2,12(r16) + 2364: 80c00417 ldw r3,16(r16) + 2368: 003fe206 br 22f4 <__alt_data_end+0xfffe22f4> + 236c: 80800517 ldw r2,20(r16) + 2370: 80000215 stw zero,8(r16) + 2374: 0085c83a sub r2,zero,r2 + 2378: 80800615 stw r2,24(r16) + 237c: 183fe41e bne r3,zero,2310 <__alt_data_end+0xfffe2310> + 2380: 80c0030b ldhu r3,12(r16) + 2384: 0005883a mov r2,zero + 2388: 1900200c andi r4,r3,128 + 238c: 203fe126 beq r4,zero,2314 <__alt_data_end+0xfffe2314> + 2390: 18c01014 ori r3,r3,64 + 2394: 80c0030d sth r3,12(r16) + 2398: 00bfffc4 movi r2,-1 + 239c: 003fdd06 br 2314 <__alt_data_end+0xfffe2314> + 23a0: 00007fc0 call 7fc <__sinit> + 23a4: 003fcd06 br 22dc <__alt_data_end+0xfffe22dc> + 23a8: 0005883a mov r2,zero + 23ac: 003fd606 br 2308 <__alt_data_end+0xfffe2308> + 23b0: 81400c17 ldw r5,48(r16) + 23b4: 28000626 beq r5,zero,23d0 <__swsetup_r+0x124> + 23b8: 80801004 addi r2,r16,64 + 23bc: 28800326 beq r5,r2,23cc <__swsetup_r+0x120> + 23c0: 8809883a mov r4,r17 + 23c4: 00029240 call 2924 <_free_r> + 23c8: 8100030b ldhu r4,12(r16) + 23cc: 80000c15 stw zero,48(r16) + 23d0: 80c00417 ldw r3,16(r16) + 23d4: 00bff6c4 movi r2,-37 + 23d8: 1108703a and r4,r2,r4 + 23dc: 80000115 stw zero,4(r16) + 23e0: 80c00015 stw r3,0(r16) + 23e4: 003fd506 br 233c <__alt_data_end+0xfffe233c> + 23e8: 00800244 movi r2,9 + 23ec: 88800015 stw r2,0(r17) + 23f0: 20801014 ori r2,r4,64 + 23f4: 8080030d sth r2,12(r16) + 23f8: 00bfffc4 movi r2,-1 + 23fc: 003fc506 br 2314 <__alt_data_end+0xfffe2314> + +00002400 <_close_r>: + 2400: defffd04 addi sp,sp,-12 + 2404: dc000015 stw r16,0(sp) + 2408: 04000034 movhi r16,0 + 240c: dc400115 stw r17,4(sp) + 2410: 841ca704 addi r16,r16,29340 + 2414: 2023883a mov r17,r4 + 2418: 2809883a mov r4,r5 + 241c: dfc00215 stw ra,8(sp) + 2420: 80000015 stw zero,0(r16) + 2424: 00031780 call 3178 + 2428: 00ffffc4 movi r3,-1 + 242c: 10c00526 beq r2,r3,2444 <_close_r+0x44> + 2430: dfc00217 ldw ra,8(sp) + 2434: dc400117 ldw r17,4(sp) + 2438: dc000017 ldw r16,0(sp) + 243c: dec00304 addi sp,sp,12 + 2440: f800283a ret + 2444: 80c00017 ldw r3,0(r16) + 2448: 183ff926 beq r3,zero,2430 <__alt_data_end+0xfffe2430> + 244c: 88c00015 stw r3,0(r17) + 2450: 003ff706 br 2430 <__alt_data_end+0xfffe2430> + +00002454 <_fclose_r>: + 2454: 28003926 beq r5,zero,253c <_fclose_r+0xe8> + 2458: defffc04 addi sp,sp,-16 + 245c: dc400115 stw r17,4(sp) + 2460: dc000015 stw r16,0(sp) + 2464: dfc00315 stw ra,12(sp) + 2468: dc800215 stw r18,8(sp) + 246c: 2023883a mov r17,r4 + 2470: 2821883a mov r16,r5 + 2474: 20000226 beq r4,zero,2480 <_fclose_r+0x2c> + 2478: 20800e17 ldw r2,56(r4) + 247c: 10002726 beq r2,zero,251c <_fclose_r+0xc8> + 2480: 8080030f ldh r2,12(r16) + 2484: 1000071e bne r2,zero,24a4 <_fclose_r+0x50> + 2488: 0005883a mov r2,zero + 248c: dfc00317 ldw ra,12(sp) + 2490: dc800217 ldw r18,8(sp) + 2494: dc400117 ldw r17,4(sp) + 2498: dc000017 ldw r16,0(sp) + 249c: dec00404 addi sp,sp,16 + 24a0: f800283a ret + 24a4: 800b883a mov r5,r16 + 24a8: 8809883a mov r4,r17 + 24ac: 00025580 call 2558 <__sflush_r> + 24b0: 1025883a mov r18,r2 + 24b4: 80800b17 ldw r2,44(r16) + 24b8: 10000426 beq r2,zero,24cc <_fclose_r+0x78> + 24bc: 81400717 ldw r5,28(r16) + 24c0: 8809883a mov r4,r17 + 24c4: 103ee83a callr r2 + 24c8: 10001616 blt r2,zero,2524 <_fclose_r+0xd0> + 24cc: 8080030b ldhu r2,12(r16) + 24d0: 1080200c andi r2,r2,128 + 24d4: 1000151e bne r2,zero,252c <_fclose_r+0xd8> + 24d8: 81400c17 ldw r5,48(r16) + 24dc: 28000526 beq r5,zero,24f4 <_fclose_r+0xa0> + 24e0: 80801004 addi r2,r16,64 + 24e4: 28800226 beq r5,r2,24f0 <_fclose_r+0x9c> + 24e8: 8809883a mov r4,r17 + 24ec: 00029240 call 2924 <_free_r> + 24f0: 80000c15 stw zero,48(r16) + 24f4: 81401117 ldw r5,68(r16) + 24f8: 28000326 beq r5,zero,2508 <_fclose_r+0xb4> + 24fc: 8809883a mov r4,r17 + 2500: 00029240 call 2924 <_free_r> + 2504: 80001115 stw zero,68(r16) + 2508: 000080c0 call 80c <__sfp_lock_acquire> + 250c: 8000030d sth zero,12(r16) + 2510: 00008100 call 810 <__sfp_lock_release> + 2514: 9005883a mov r2,r18 + 2518: 003fdc06 br 248c <__alt_data_end+0xfffe248c> + 251c: 00007fc0 call 7fc <__sinit> + 2520: 003fd706 br 2480 <__alt_data_end+0xfffe2480> + 2524: 04bfffc4 movi r18,-1 + 2528: 003fe806 br 24cc <__alt_data_end+0xfffe24cc> + 252c: 81400417 ldw r5,16(r16) + 2530: 8809883a mov r4,r17 + 2534: 00029240 call 2924 <_free_r> + 2538: 003fe706 br 24d8 <__alt_data_end+0xfffe24d8> + 253c: 0005883a mov r2,zero + 2540: f800283a ret + +00002544 : + 2544: 00800034 movhi r2,0 + 2548: 109c9704 addi r2,r2,29276 + 254c: 200b883a mov r5,r4 + 2550: 11000017 ldw r4,0(r2) + 2554: 00024541 jmpi 2454 <_fclose_r> + +00002558 <__sflush_r>: + 2558: 2880030b ldhu r2,12(r5) + 255c: defffb04 addi sp,sp,-20 + 2560: dcc00315 stw r19,12(sp) + 2564: dc400115 stw r17,4(sp) + 2568: dfc00415 stw ra,16(sp) + 256c: dc800215 stw r18,8(sp) + 2570: dc000015 stw r16,0(sp) + 2574: 10c0020c andi r3,r2,8 + 2578: 2823883a mov r17,r5 + 257c: 2027883a mov r19,r4 + 2580: 1800311e bne r3,zero,2648 <__sflush_r+0xf0> + 2584: 28c00117 ldw r3,4(r5) + 2588: 10820014 ori r2,r2,2048 + 258c: 2880030d sth r2,12(r5) + 2590: 00c04b0e bge zero,r3,26c0 <__sflush_r+0x168> + 2594: 8a000a17 ldw r8,40(r17) + 2598: 40002326 beq r8,zero,2628 <__sflush_r+0xd0> + 259c: 9c000017 ldw r16,0(r19) + 25a0: 10c4000c andi r3,r2,4096 + 25a4: 98000015 stw zero,0(r19) + 25a8: 18004826 beq r3,zero,26cc <__sflush_r+0x174> + 25ac: 89801417 ldw r6,80(r17) + 25b0: 10c0010c andi r3,r2,4 + 25b4: 18000626 beq r3,zero,25d0 <__sflush_r+0x78> + 25b8: 88c00117 ldw r3,4(r17) + 25bc: 88800c17 ldw r2,48(r17) + 25c0: 30cdc83a sub r6,r6,r3 + 25c4: 10000226 beq r2,zero,25d0 <__sflush_r+0x78> + 25c8: 88800f17 ldw r2,60(r17) + 25cc: 308dc83a sub r6,r6,r2 + 25d0: 89400717 ldw r5,28(r17) + 25d4: 000f883a mov r7,zero + 25d8: 9809883a mov r4,r19 + 25dc: 403ee83a callr r8 + 25e0: 00ffffc4 movi r3,-1 + 25e4: 10c04426 beq r2,r3,26f8 <__sflush_r+0x1a0> + 25e8: 88c0030b ldhu r3,12(r17) + 25ec: 89000417 ldw r4,16(r17) + 25f0: 88000115 stw zero,4(r17) + 25f4: 197dffcc andi r5,r3,63487 + 25f8: 8940030d sth r5,12(r17) + 25fc: 89000015 stw r4,0(r17) + 2600: 18c4000c andi r3,r3,4096 + 2604: 18002c1e bne r3,zero,26b8 <__sflush_r+0x160> + 2608: 89400c17 ldw r5,48(r17) + 260c: 9c000015 stw r16,0(r19) + 2610: 28000526 beq r5,zero,2628 <__sflush_r+0xd0> + 2614: 88801004 addi r2,r17,64 + 2618: 28800226 beq r5,r2,2624 <__sflush_r+0xcc> + 261c: 9809883a mov r4,r19 + 2620: 00029240 call 2924 <_free_r> + 2624: 88000c15 stw zero,48(r17) + 2628: 0005883a mov r2,zero + 262c: dfc00417 ldw ra,16(sp) + 2630: dcc00317 ldw r19,12(sp) + 2634: dc800217 ldw r18,8(sp) + 2638: dc400117 ldw r17,4(sp) + 263c: dc000017 ldw r16,0(sp) + 2640: dec00504 addi sp,sp,20 + 2644: f800283a ret + 2648: 2c800417 ldw r18,16(r5) + 264c: 903ff626 beq r18,zero,2628 <__alt_data_end+0xfffe2628> + 2650: 2c000017 ldw r16,0(r5) + 2654: 108000cc andi r2,r2,3 + 2658: 2c800015 stw r18,0(r5) + 265c: 84a1c83a sub r16,r16,r18 + 2660: 1000131e bne r2,zero,26b0 <__sflush_r+0x158> + 2664: 28800517 ldw r2,20(r5) + 2668: 88800215 stw r2,8(r17) + 266c: 04000316 blt zero,r16,267c <__sflush_r+0x124> + 2670: 003fed06 br 2628 <__alt_data_end+0xfffe2628> + 2674: 90a5883a add r18,r18,r2 + 2678: 043feb0e bge zero,r16,2628 <__alt_data_end+0xfffe2628> + 267c: 88800917 ldw r2,36(r17) + 2680: 89400717 ldw r5,28(r17) + 2684: 800f883a mov r7,r16 + 2688: 900d883a mov r6,r18 + 268c: 9809883a mov r4,r19 + 2690: 103ee83a callr r2 + 2694: 80a1c83a sub r16,r16,r2 + 2698: 00bff616 blt zero,r2,2674 <__alt_data_end+0xfffe2674> + 269c: 88c0030b ldhu r3,12(r17) + 26a0: 00bfffc4 movi r2,-1 + 26a4: 18c01014 ori r3,r3,64 + 26a8: 88c0030d sth r3,12(r17) + 26ac: 003fdf06 br 262c <__alt_data_end+0xfffe262c> + 26b0: 0005883a mov r2,zero + 26b4: 003fec06 br 2668 <__alt_data_end+0xfffe2668> + 26b8: 88801415 stw r2,80(r17) + 26bc: 003fd206 br 2608 <__alt_data_end+0xfffe2608> + 26c0: 28c00f17 ldw r3,60(r5) + 26c4: 00ffb316 blt zero,r3,2594 <__alt_data_end+0xfffe2594> + 26c8: 003fd706 br 2628 <__alt_data_end+0xfffe2628> + 26cc: 89400717 ldw r5,28(r17) + 26d0: 000d883a mov r6,zero + 26d4: 01c00044 movi r7,1 + 26d8: 9809883a mov r4,r19 + 26dc: 403ee83a callr r8 + 26e0: 100d883a mov r6,r2 + 26e4: 00bfffc4 movi r2,-1 + 26e8: 30801426 beq r6,r2,273c <__sflush_r+0x1e4> + 26ec: 8880030b ldhu r2,12(r17) + 26f0: 8a000a17 ldw r8,40(r17) + 26f4: 003fae06 br 25b0 <__alt_data_end+0xfffe25b0> + 26f8: 98c00017 ldw r3,0(r19) + 26fc: 183fba26 beq r3,zero,25e8 <__alt_data_end+0xfffe25e8> + 2700: 01000744 movi r4,29 + 2704: 19000626 beq r3,r4,2720 <__sflush_r+0x1c8> + 2708: 01000584 movi r4,22 + 270c: 19000426 beq r3,r4,2720 <__sflush_r+0x1c8> + 2710: 88c0030b ldhu r3,12(r17) + 2714: 18c01014 ori r3,r3,64 + 2718: 88c0030d sth r3,12(r17) + 271c: 003fc306 br 262c <__alt_data_end+0xfffe262c> + 2720: 8880030b ldhu r2,12(r17) + 2724: 88c00417 ldw r3,16(r17) + 2728: 88000115 stw zero,4(r17) + 272c: 10bdffcc andi r2,r2,63487 + 2730: 8880030d sth r2,12(r17) + 2734: 88c00015 stw r3,0(r17) + 2738: 003fb306 br 2608 <__alt_data_end+0xfffe2608> + 273c: 98800017 ldw r2,0(r19) + 2740: 103fea26 beq r2,zero,26ec <__alt_data_end+0xfffe26ec> + 2744: 00c00744 movi r3,29 + 2748: 10c00226 beq r2,r3,2754 <__sflush_r+0x1fc> + 274c: 00c00584 movi r3,22 + 2750: 10c0031e bne r2,r3,2760 <__sflush_r+0x208> + 2754: 9c000015 stw r16,0(r19) + 2758: 0005883a mov r2,zero + 275c: 003fb306 br 262c <__alt_data_end+0xfffe262c> + 2760: 88c0030b ldhu r3,12(r17) + 2764: 3005883a mov r2,r6 + 2768: 18c01014 ori r3,r3,64 + 276c: 88c0030d sth r3,12(r17) + 2770: 003fae06 br 262c <__alt_data_end+0xfffe262c> + +00002774 <_fflush_r>: + 2774: defffd04 addi sp,sp,-12 + 2778: dc000115 stw r16,4(sp) + 277c: dfc00215 stw ra,8(sp) + 2780: 2021883a mov r16,r4 + 2784: 20000226 beq r4,zero,2790 <_fflush_r+0x1c> + 2788: 20800e17 ldw r2,56(r4) + 278c: 10000c26 beq r2,zero,27c0 <_fflush_r+0x4c> + 2790: 2880030f ldh r2,12(r5) + 2794: 1000051e bne r2,zero,27ac <_fflush_r+0x38> + 2798: 0005883a mov r2,zero + 279c: dfc00217 ldw ra,8(sp) + 27a0: dc000117 ldw r16,4(sp) + 27a4: dec00304 addi sp,sp,12 + 27a8: f800283a ret + 27ac: 8009883a mov r4,r16 + 27b0: dfc00217 ldw ra,8(sp) + 27b4: dc000117 ldw r16,4(sp) + 27b8: dec00304 addi sp,sp,12 + 27bc: 00025581 jmpi 2558 <__sflush_r> + 27c0: d9400015 stw r5,0(sp) + 27c4: 00007fc0 call 7fc <__sinit> + 27c8: d9400017 ldw r5,0(sp) + 27cc: 003ff006 br 2790 <__alt_data_end+0xfffe2790> + +000027d0 : + 27d0: 20000526 beq r4,zero,27e8 + 27d4: 00800034 movhi r2,0 + 27d8: 109c9704 addi r2,r2,29276 + 27dc: 200b883a mov r5,r4 + 27e0: 11000017 ldw r4,0(r2) + 27e4: 00027741 jmpi 2774 <_fflush_r> + 27e8: 00800034 movhi r2,0 + 27ec: 109c9604 addi r2,r2,29272 + 27f0: 11000017 ldw r4,0(r2) + 27f4: 01400034 movhi r5,0 + 27f8: 2949dd04 addi r5,r5,10100 + 27fc: 0000dd81 jmpi dd8 <_fwalk_reent> + +00002800 <_malloc_trim_r>: + 2800: defffb04 addi sp,sp,-20 + 2804: dcc00315 stw r19,12(sp) + 2808: 04c00034 movhi r19,0 + 280c: dc800215 stw r18,8(sp) + 2810: dc400115 stw r17,4(sp) + 2814: dc000015 stw r16,0(sp) + 2818: dfc00415 stw ra,16(sp) + 281c: 2821883a mov r16,r5 + 2820: 9cd71204 addi r19,r19,23624 + 2824: 2025883a mov r18,r4 + 2828: 00036140 call 3614 <__malloc_lock> + 282c: 98800217 ldw r2,8(r19) + 2830: 14400117 ldw r17,4(r2) + 2834: 00bfff04 movi r2,-4 + 2838: 88a2703a and r17,r17,r2 + 283c: 8c21c83a sub r16,r17,r16 + 2840: 8403fbc4 addi r16,r16,4079 + 2844: 8020d33a srli r16,r16,12 + 2848: 0083ffc4 movi r2,4095 + 284c: 843fffc4 addi r16,r16,-1 + 2850: 8020933a slli r16,r16,12 + 2854: 1400060e bge r2,r16,2870 <_malloc_trim_r+0x70> + 2858: 000b883a mov r5,zero + 285c: 9009883a mov r4,r18 + 2860: 00020bc0 call 20bc <_sbrk_r> + 2864: 98c00217 ldw r3,8(r19) + 2868: 1c47883a add r3,r3,r17 + 286c: 10c00a26 beq r2,r3,2898 <_malloc_trim_r+0x98> + 2870: 9009883a mov r4,r18 + 2874: 00036380 call 3638 <__malloc_unlock> + 2878: 0005883a mov r2,zero + 287c: dfc00417 ldw ra,16(sp) + 2880: dcc00317 ldw r19,12(sp) + 2884: dc800217 ldw r18,8(sp) + 2888: dc400117 ldw r17,4(sp) + 288c: dc000017 ldw r16,0(sp) + 2890: dec00504 addi sp,sp,20 + 2894: f800283a ret + 2898: 040bc83a sub r5,zero,r16 + 289c: 9009883a mov r4,r18 + 28a0: 00020bc0 call 20bc <_sbrk_r> + 28a4: 00ffffc4 movi r3,-1 + 28a8: 10c00d26 beq r2,r3,28e0 <_malloc_trim_r+0xe0> + 28ac: 00c00034 movhi r3,0 + 28b0: 18dcaf04 addi r3,r3,29372 + 28b4: 18800017 ldw r2,0(r3) + 28b8: 99000217 ldw r4,8(r19) + 28bc: 8c23c83a sub r17,r17,r16 + 28c0: 8c400054 ori r17,r17,1 + 28c4: 1421c83a sub r16,r2,r16 + 28c8: 24400115 stw r17,4(r4) + 28cc: 9009883a mov r4,r18 + 28d0: 1c000015 stw r16,0(r3) + 28d4: 00036380 call 3638 <__malloc_unlock> + 28d8: 00800044 movi r2,1 + 28dc: 003fe706 br 287c <__alt_data_end+0xfffe287c> + 28e0: 000b883a mov r5,zero + 28e4: 9009883a mov r4,r18 + 28e8: 00020bc0 call 20bc <_sbrk_r> + 28ec: 99000217 ldw r4,8(r19) + 28f0: 014003c4 movi r5,15 + 28f4: 1107c83a sub r3,r2,r4 + 28f8: 28ffdd0e bge r5,r3,2870 <__alt_data_end+0xfffe2870> + 28fc: 01400034 movhi r5,0 + 2900: 295c9804 addi r5,r5,29280 + 2904: 29400017 ldw r5,0(r5) + 2908: 18c00054 ori r3,r3,1 + 290c: 20c00115 stw r3,4(r4) + 2910: 00c00034 movhi r3,0 + 2914: 1145c83a sub r2,r2,r5 + 2918: 18dcaf04 addi r3,r3,29372 + 291c: 18800015 stw r2,0(r3) + 2920: 003fd306 br 2870 <__alt_data_end+0xfffe2870> + +00002924 <_free_r>: + 2924: 28004126 beq r5,zero,2a2c <_free_r+0x108> + 2928: defffd04 addi sp,sp,-12 + 292c: dc400115 stw r17,4(sp) + 2930: dc000015 stw r16,0(sp) + 2934: 2023883a mov r17,r4 + 2938: 2821883a mov r16,r5 + 293c: dfc00215 stw ra,8(sp) + 2940: 00036140 call 3614 <__malloc_lock> + 2944: 81ffff17 ldw r7,-4(r16) + 2948: 00bfff84 movi r2,-2 + 294c: 01000034 movhi r4,0 + 2950: 81bffe04 addi r6,r16,-8 + 2954: 3884703a and r2,r7,r2 + 2958: 21171204 addi r4,r4,23624 + 295c: 308b883a add r5,r6,r2 + 2960: 2a400117 ldw r9,4(r5) + 2964: 22000217 ldw r8,8(r4) + 2968: 00ffff04 movi r3,-4 + 296c: 48c6703a and r3,r9,r3 + 2970: 2a005726 beq r5,r8,2ad0 <_free_r+0x1ac> + 2974: 28c00115 stw r3,4(r5) + 2978: 39c0004c andi r7,r7,1 + 297c: 3800091e bne r7,zero,29a4 <_free_r+0x80> + 2980: 823ffe17 ldw r8,-8(r16) + 2984: 22400204 addi r9,r4,8 + 2988: 320dc83a sub r6,r6,r8 + 298c: 31c00217 ldw r7,8(r6) + 2990: 1205883a add r2,r2,r8 + 2994: 3a406526 beq r7,r9,2b2c <_free_r+0x208> + 2998: 32000317 ldw r8,12(r6) + 299c: 3a000315 stw r8,12(r7) + 29a0: 41c00215 stw r7,8(r8) + 29a4: 28cf883a add r7,r5,r3 + 29a8: 39c00117 ldw r7,4(r7) + 29ac: 39c0004c andi r7,r7,1 + 29b0: 38003a26 beq r7,zero,2a9c <_free_r+0x178> + 29b4: 10c00054 ori r3,r2,1 + 29b8: 30c00115 stw r3,4(r6) + 29bc: 3087883a add r3,r6,r2 + 29c0: 18800015 stw r2,0(r3) + 29c4: 00c07fc4 movi r3,511 + 29c8: 18801936 bltu r3,r2,2a30 <_free_r+0x10c> + 29cc: 1004d0fa srli r2,r2,3 + 29d0: 01c00044 movi r7,1 + 29d4: 21400117 ldw r5,4(r4) + 29d8: 10c00044 addi r3,r2,1 + 29dc: 18c7883a add r3,r3,r3 + 29e0: 1005d0ba srai r2,r2,2 + 29e4: 18c7883a add r3,r3,r3 + 29e8: 18c7883a add r3,r3,r3 + 29ec: 1907883a add r3,r3,r4 + 29f0: 3884983a sll r2,r7,r2 + 29f4: 19c00017 ldw r7,0(r3) + 29f8: 1a3ffe04 addi r8,r3,-8 + 29fc: 1144b03a or r2,r2,r5 + 2a00: 32000315 stw r8,12(r6) + 2a04: 31c00215 stw r7,8(r6) + 2a08: 20800115 stw r2,4(r4) + 2a0c: 19800015 stw r6,0(r3) + 2a10: 39800315 stw r6,12(r7) + 2a14: 8809883a mov r4,r17 + 2a18: dfc00217 ldw ra,8(sp) + 2a1c: dc400117 ldw r17,4(sp) + 2a20: dc000017 ldw r16,0(sp) + 2a24: dec00304 addi sp,sp,12 + 2a28: 00036381 jmpi 3638 <__malloc_unlock> + 2a2c: f800283a ret + 2a30: 100ad27a srli r5,r2,9 + 2a34: 00c00104 movi r3,4 + 2a38: 19404a36 bltu r3,r5,2b64 <_free_r+0x240> + 2a3c: 100ad1ba srli r5,r2,6 + 2a40: 28c00e44 addi r3,r5,57 + 2a44: 18c7883a add r3,r3,r3 + 2a48: 29400e04 addi r5,r5,56 + 2a4c: 18c7883a add r3,r3,r3 + 2a50: 18c7883a add r3,r3,r3 + 2a54: 1909883a add r4,r3,r4 + 2a58: 20c00017 ldw r3,0(r4) + 2a5c: 01c00034 movhi r7,0 + 2a60: 213ffe04 addi r4,r4,-8 + 2a64: 39d71204 addi r7,r7,23624 + 2a68: 20c04426 beq r4,r3,2b7c <_free_r+0x258> + 2a6c: 01ffff04 movi r7,-4 + 2a70: 19400117 ldw r5,4(r3) + 2a74: 29ca703a and r5,r5,r7 + 2a78: 1140022e bgeu r2,r5,2a84 <_free_r+0x160> + 2a7c: 18c00217 ldw r3,8(r3) + 2a80: 20fffb1e bne r4,r3,2a70 <__alt_data_end+0xfffe2a70> + 2a84: 19000317 ldw r4,12(r3) + 2a88: 31000315 stw r4,12(r6) + 2a8c: 30c00215 stw r3,8(r6) + 2a90: 21800215 stw r6,8(r4) + 2a94: 19800315 stw r6,12(r3) + 2a98: 003fde06 br 2a14 <__alt_data_end+0xfffe2a14> + 2a9c: 29c00217 ldw r7,8(r5) + 2aa0: 10c5883a add r2,r2,r3 + 2aa4: 00c00034 movhi r3,0 + 2aa8: 18d71404 addi r3,r3,23632 + 2aac: 38c03b26 beq r7,r3,2b9c <_free_r+0x278> + 2ab0: 2a000317 ldw r8,12(r5) + 2ab4: 11400054 ori r5,r2,1 + 2ab8: 3087883a add r3,r6,r2 + 2abc: 3a000315 stw r8,12(r7) + 2ac0: 41c00215 stw r7,8(r8) + 2ac4: 31400115 stw r5,4(r6) + 2ac8: 18800015 stw r2,0(r3) + 2acc: 003fbd06 br 29c4 <__alt_data_end+0xfffe29c4> + 2ad0: 39c0004c andi r7,r7,1 + 2ad4: 10c5883a add r2,r2,r3 + 2ad8: 3800071e bne r7,zero,2af8 <_free_r+0x1d4> + 2adc: 81fffe17 ldw r7,-8(r16) + 2ae0: 31cdc83a sub r6,r6,r7 + 2ae4: 30c00317 ldw r3,12(r6) + 2ae8: 31400217 ldw r5,8(r6) + 2aec: 11c5883a add r2,r2,r7 + 2af0: 28c00315 stw r3,12(r5) + 2af4: 19400215 stw r5,8(r3) + 2af8: 10c00054 ori r3,r2,1 + 2afc: 30c00115 stw r3,4(r6) + 2b00: 00c00034 movhi r3,0 + 2b04: 18dc9904 addi r3,r3,29284 + 2b08: 18c00017 ldw r3,0(r3) + 2b0c: 21800215 stw r6,8(r4) + 2b10: 10ffc036 bltu r2,r3,2a14 <__alt_data_end+0xfffe2a14> + 2b14: 00800034 movhi r2,0 + 2b18: 109ca604 addi r2,r2,29336 + 2b1c: 11400017 ldw r5,0(r2) + 2b20: 8809883a mov r4,r17 + 2b24: 00028000 call 2800 <_malloc_trim_r> + 2b28: 003fba06 br 2a14 <__alt_data_end+0xfffe2a14> + 2b2c: 28c9883a add r4,r5,r3 + 2b30: 21000117 ldw r4,4(r4) + 2b34: 2100004c andi r4,r4,1 + 2b38: 2000391e bne r4,zero,2c20 <_free_r+0x2fc> + 2b3c: 29c00217 ldw r7,8(r5) + 2b40: 29000317 ldw r4,12(r5) + 2b44: 1885883a add r2,r3,r2 + 2b48: 10c00054 ori r3,r2,1 + 2b4c: 39000315 stw r4,12(r7) + 2b50: 21c00215 stw r7,8(r4) + 2b54: 30c00115 stw r3,4(r6) + 2b58: 308d883a add r6,r6,r2 + 2b5c: 30800015 stw r2,0(r6) + 2b60: 003fac06 br 2a14 <__alt_data_end+0xfffe2a14> + 2b64: 00c00504 movi r3,20 + 2b68: 19401536 bltu r3,r5,2bc0 <_free_r+0x29c> + 2b6c: 28c01704 addi r3,r5,92 + 2b70: 18c7883a add r3,r3,r3 + 2b74: 294016c4 addi r5,r5,91 + 2b78: 003fb406 br 2a4c <__alt_data_end+0xfffe2a4c> + 2b7c: 280bd0ba srai r5,r5,2 + 2b80: 00c00044 movi r3,1 + 2b84: 38800117 ldw r2,4(r7) + 2b88: 194a983a sll r5,r3,r5 + 2b8c: 2007883a mov r3,r4 + 2b90: 2884b03a or r2,r5,r2 + 2b94: 38800115 stw r2,4(r7) + 2b98: 003fbb06 br 2a88 <__alt_data_end+0xfffe2a88> + 2b9c: 21800515 stw r6,20(r4) + 2ba0: 21800415 stw r6,16(r4) + 2ba4: 10c00054 ori r3,r2,1 + 2ba8: 31c00315 stw r7,12(r6) + 2bac: 31c00215 stw r7,8(r6) + 2bb0: 30c00115 stw r3,4(r6) + 2bb4: 308d883a add r6,r6,r2 + 2bb8: 30800015 stw r2,0(r6) + 2bbc: 003f9506 br 2a14 <__alt_data_end+0xfffe2a14> + 2bc0: 00c01504 movi r3,84 + 2bc4: 19400536 bltu r3,r5,2bdc <_free_r+0x2b8> + 2bc8: 100ad33a srli r5,r2,12 + 2bcc: 28c01bc4 addi r3,r5,111 + 2bd0: 18c7883a add r3,r3,r3 + 2bd4: 29401b84 addi r5,r5,110 + 2bd8: 003f9c06 br 2a4c <__alt_data_end+0xfffe2a4c> + 2bdc: 00c05504 movi r3,340 + 2be0: 19400536 bltu r3,r5,2bf8 <_free_r+0x2d4> + 2be4: 100ad3fa srli r5,r2,15 + 2be8: 28c01e04 addi r3,r5,120 + 2bec: 18c7883a add r3,r3,r3 + 2bf0: 29401dc4 addi r5,r5,119 + 2bf4: 003f9506 br 2a4c <__alt_data_end+0xfffe2a4c> + 2bf8: 00c15504 movi r3,1364 + 2bfc: 19400536 bltu r3,r5,2c14 <_free_r+0x2f0> + 2c00: 100ad4ba srli r5,r2,18 + 2c04: 28c01f44 addi r3,r5,125 + 2c08: 18c7883a add r3,r3,r3 + 2c0c: 29401f04 addi r5,r5,124 + 2c10: 003f8e06 br 2a4c <__alt_data_end+0xfffe2a4c> + 2c14: 00c03f84 movi r3,254 + 2c18: 01401f84 movi r5,126 + 2c1c: 003f8b06 br 2a4c <__alt_data_end+0xfffe2a4c> + 2c20: 10c00054 ori r3,r2,1 + 2c24: 30c00115 stw r3,4(r6) + 2c28: 308d883a add r6,r6,r2 + 2c2c: 30800015 stw r2,0(r6) + 2c30: 003f7806 br 2a14 <__alt_data_end+0xfffe2a14> + +00002c34 <_lseek_r>: + 2c34: defffd04 addi sp,sp,-12 + 2c38: 2805883a mov r2,r5 + 2c3c: dc000015 stw r16,0(sp) + 2c40: 04000034 movhi r16,0 + 2c44: dc400115 stw r17,4(sp) + 2c48: 300b883a mov r5,r6 + 2c4c: 841ca704 addi r16,r16,29340 + 2c50: 2023883a mov r17,r4 + 2c54: 380d883a mov r6,r7 + 2c58: 1009883a mov r4,r2 + 2c5c: dfc00215 stw ra,8(sp) + 2c60: 80000015 stw zero,0(r16) + 2c64: 00034bc0 call 34bc + 2c68: 00ffffc4 movi r3,-1 + 2c6c: 10c00526 beq r2,r3,2c84 <_lseek_r+0x50> + 2c70: dfc00217 ldw ra,8(sp) + 2c74: dc400117 ldw r17,4(sp) + 2c78: dc000017 ldw r16,0(sp) + 2c7c: dec00304 addi sp,sp,12 + 2c80: f800283a ret + 2c84: 80c00017 ldw r3,0(r16) + 2c88: 183ff926 beq r3,zero,2c70 <__alt_data_end+0xfffe2c70> + 2c8c: 88c00015 stw r3,0(r17) + 2c90: 003ff706 br 2c70 <__alt_data_end+0xfffe2c70> + +00002c94 <__smakebuf_r>: + 2c94: 2880030b ldhu r2,12(r5) + 2c98: 10c0008c andi r3,r2,2 + 2c9c: 1800411e bne r3,zero,2da4 <__smakebuf_r+0x110> + 2ca0: deffec04 addi sp,sp,-80 + 2ca4: dc000f15 stw r16,60(sp) + 2ca8: 2821883a mov r16,r5 + 2cac: 2940038f ldh r5,14(r5) + 2cb0: dc401015 stw r17,64(sp) + 2cb4: dfc01315 stw ra,76(sp) + 2cb8: dcc01215 stw r19,72(sp) + 2cbc: dc801115 stw r18,68(sp) + 2cc0: 2023883a mov r17,r4 + 2cc4: 28001c16 blt r5,zero,2d38 <__smakebuf_r+0xa4> + 2cc8: d80d883a mov r6,sp + 2ccc: 0002eb00 call 2eb0 <_fstat_r> + 2cd0: 10001816 blt r2,zero,2d34 <__smakebuf_r+0xa0> + 2cd4: d8800117 ldw r2,4(sp) + 2cd8: 00e00014 movui r3,32768 + 2cdc: 10bc000c andi r2,r2,61440 + 2ce0: 14c80020 cmpeqi r19,r2,8192 + 2ce4: 10c03726 beq r2,r3,2dc4 <__smakebuf_r+0x130> + 2ce8: 80c0030b ldhu r3,12(r16) + 2cec: 18c20014 ori r3,r3,2048 + 2cf0: 80c0030d sth r3,12(r16) + 2cf4: 00c80004 movi r3,8192 + 2cf8: 10c0521e bne r2,r3,2e44 <__smakebuf_r+0x1b0> + 2cfc: 8140038f ldh r5,14(r16) + 2d00: 8809883a mov r4,r17 + 2d04: 0002f0c0 call 2f0c <_isatty_r> + 2d08: 10004c26 beq r2,zero,2e3c <__smakebuf_r+0x1a8> + 2d0c: 8080030b ldhu r2,12(r16) + 2d10: 80c010c4 addi r3,r16,67 + 2d14: 80c00015 stw r3,0(r16) + 2d18: 10800054 ori r2,r2,1 + 2d1c: 8080030d sth r2,12(r16) + 2d20: 00800044 movi r2,1 + 2d24: 80c00415 stw r3,16(r16) + 2d28: 80800515 stw r2,20(r16) + 2d2c: 04810004 movi r18,1024 + 2d30: 00000706 br 2d50 <__smakebuf_r+0xbc> + 2d34: 8080030b ldhu r2,12(r16) + 2d38: 10c0200c andi r3,r2,128 + 2d3c: 18001f1e bne r3,zero,2dbc <__smakebuf_r+0x128> + 2d40: 04810004 movi r18,1024 + 2d44: 10820014 ori r2,r2,2048 + 2d48: 8080030d sth r2,12(r16) + 2d4c: 0027883a mov r19,zero + 2d50: 900b883a mov r5,r18 + 2d54: 8809883a mov r4,r17 + 2d58: 0000e9c0 call e9c <_malloc_r> + 2d5c: 10002c26 beq r2,zero,2e10 <__smakebuf_r+0x17c> + 2d60: 80c0030b ldhu r3,12(r16) + 2d64: 01000034 movhi r4,0 + 2d68: 21012904 addi r4,r4,1188 + 2d6c: 89000f15 stw r4,60(r17) + 2d70: 18c02014 ori r3,r3,128 + 2d74: 80c0030d sth r3,12(r16) + 2d78: 80800015 stw r2,0(r16) + 2d7c: 80800415 stw r2,16(r16) + 2d80: 84800515 stw r18,20(r16) + 2d84: 98001a1e bne r19,zero,2df0 <__smakebuf_r+0x15c> + 2d88: dfc01317 ldw ra,76(sp) + 2d8c: dcc01217 ldw r19,72(sp) + 2d90: dc801117 ldw r18,68(sp) + 2d94: dc401017 ldw r17,64(sp) + 2d98: dc000f17 ldw r16,60(sp) + 2d9c: dec01404 addi sp,sp,80 + 2da0: f800283a ret + 2da4: 288010c4 addi r2,r5,67 + 2da8: 28800015 stw r2,0(r5) + 2dac: 28800415 stw r2,16(r5) + 2db0: 00800044 movi r2,1 + 2db4: 28800515 stw r2,20(r5) + 2db8: f800283a ret + 2dbc: 04801004 movi r18,64 + 2dc0: 003fe006 br 2d44 <__alt_data_end+0xfffe2d44> + 2dc4: 81000a17 ldw r4,40(r16) + 2dc8: 00c00034 movhi r3,0 + 2dcc: 18c87a04 addi r3,r3,8680 + 2dd0: 20ffc51e bne r4,r3,2ce8 <__alt_data_end+0xfffe2ce8> + 2dd4: 8080030b ldhu r2,12(r16) + 2dd8: 04810004 movi r18,1024 + 2ddc: 84801315 stw r18,76(r16) + 2de0: 1484b03a or r2,r2,r18 + 2de4: 8080030d sth r2,12(r16) + 2de8: 0027883a mov r19,zero + 2dec: 003fd806 br 2d50 <__alt_data_end+0xfffe2d50> + 2df0: 8140038f ldh r5,14(r16) + 2df4: 8809883a mov r4,r17 + 2df8: 0002f0c0 call 2f0c <_isatty_r> + 2dfc: 103fe226 beq r2,zero,2d88 <__alt_data_end+0xfffe2d88> + 2e00: 8080030b ldhu r2,12(r16) + 2e04: 10800054 ori r2,r2,1 + 2e08: 8080030d sth r2,12(r16) + 2e0c: 003fde06 br 2d88 <__alt_data_end+0xfffe2d88> + 2e10: 8080030b ldhu r2,12(r16) + 2e14: 10c0800c andi r3,r2,512 + 2e18: 183fdb1e bne r3,zero,2d88 <__alt_data_end+0xfffe2d88> + 2e1c: 10800094 ori r2,r2,2 + 2e20: 80c010c4 addi r3,r16,67 + 2e24: 8080030d sth r2,12(r16) + 2e28: 00800044 movi r2,1 + 2e2c: 80c00015 stw r3,0(r16) + 2e30: 80c00415 stw r3,16(r16) + 2e34: 80800515 stw r2,20(r16) + 2e38: 003fd306 br 2d88 <__alt_data_end+0xfffe2d88> + 2e3c: 04810004 movi r18,1024 + 2e40: 003fc306 br 2d50 <__alt_data_end+0xfffe2d50> + 2e44: 0027883a mov r19,zero + 2e48: 04810004 movi r18,1024 + 2e4c: 003fc006 br 2d50 <__alt_data_end+0xfffe2d50> + +00002e50 <_read_r>: + 2e50: defffd04 addi sp,sp,-12 + 2e54: 2805883a mov r2,r5 + 2e58: dc000015 stw r16,0(sp) + 2e5c: 04000034 movhi r16,0 + 2e60: dc400115 stw r17,4(sp) + 2e64: 300b883a mov r5,r6 + 2e68: 841ca704 addi r16,r16,29340 + 2e6c: 2023883a mov r17,r4 + 2e70: 380d883a mov r6,r7 + 2e74: 1009883a mov r4,r2 + 2e78: dfc00215 stw ra,8(sp) + 2e7c: 80000015 stw zero,0(r16) + 2e80: 00036980 call 3698 + 2e84: 00ffffc4 movi r3,-1 + 2e88: 10c00526 beq r2,r3,2ea0 <_read_r+0x50> + 2e8c: dfc00217 ldw ra,8(sp) + 2e90: dc400117 ldw r17,4(sp) + 2e94: dc000017 ldw r16,0(sp) + 2e98: dec00304 addi sp,sp,12 + 2e9c: f800283a ret + 2ea0: 80c00017 ldw r3,0(r16) + 2ea4: 183ff926 beq r3,zero,2e8c <__alt_data_end+0xfffe2e8c> + 2ea8: 88c00015 stw r3,0(r17) + 2eac: 003ff706 br 2e8c <__alt_data_end+0xfffe2e8c> + +00002eb0 <_fstat_r>: + 2eb0: defffd04 addi sp,sp,-12 + 2eb4: 2805883a mov r2,r5 + 2eb8: dc000015 stw r16,0(sp) + 2ebc: 04000034 movhi r16,0 + 2ec0: dc400115 stw r17,4(sp) + 2ec4: 841ca704 addi r16,r16,29340 + 2ec8: 2023883a mov r17,r4 + 2ecc: 300b883a mov r5,r6 + 2ed0: 1009883a mov r4,r2 + 2ed4: dfc00215 stw ra,8(sp) + 2ed8: 80000015 stw zero,0(r16) + 2edc: 00032e00 call 32e0 + 2ee0: 00ffffc4 movi r3,-1 + 2ee4: 10c00526 beq r2,r3,2efc <_fstat_r+0x4c> + 2ee8: dfc00217 ldw ra,8(sp) + 2eec: dc400117 ldw r17,4(sp) + 2ef0: dc000017 ldw r16,0(sp) + 2ef4: dec00304 addi sp,sp,12 + 2ef8: f800283a ret + 2efc: 80c00017 ldw r3,0(r16) + 2f00: 183ff926 beq r3,zero,2ee8 <__alt_data_end+0xfffe2ee8> + 2f04: 88c00015 stw r3,0(r17) + 2f08: 003ff706 br 2ee8 <__alt_data_end+0xfffe2ee8> + +00002f0c <_isatty_r>: + 2f0c: defffd04 addi sp,sp,-12 + 2f10: dc000015 stw r16,0(sp) + 2f14: 04000034 movhi r16,0 + 2f18: dc400115 stw r17,4(sp) + 2f1c: 841ca704 addi r16,r16,29340 + 2f20: 2023883a mov r17,r4 + 2f24: 2809883a mov r4,r5 + 2f28: dfc00215 stw ra,8(sp) + 2f2c: 80000015 stw zero,0(r16) + 2f30: 00033d40 call 33d4 + 2f34: 00ffffc4 movi r3,-1 + 2f38: 10c00526 beq r2,r3,2f50 <_isatty_r+0x44> + 2f3c: dfc00217 ldw ra,8(sp) + 2f40: dc400117 ldw r17,4(sp) + 2f44: dc000017 ldw r16,0(sp) + 2f48: dec00304 addi sp,sp,12 + 2f4c: f800283a ret + 2f50: 80c00017 ldw r3,0(r16) + 2f54: 183ff926 beq r3,zero,2f3c <__alt_data_end+0xfffe2f3c> + 2f58: 88c00015 stw r3,0(r17) + 2f5c: 003ff706 br 2f3c <__alt_data_end+0xfffe2f3c> + +00002f60 <__divsi3>: + 2f60: 20001b16 blt r4,zero,2fd0 <__divsi3+0x70> + 2f64: 000f883a mov r7,zero + 2f68: 28001616 blt r5,zero,2fc4 <__divsi3+0x64> + 2f6c: 200d883a mov r6,r4 + 2f70: 29001a2e bgeu r5,r4,2fdc <__divsi3+0x7c> + 2f74: 00800804 movi r2,32 + 2f78: 00c00044 movi r3,1 + 2f7c: 00000106 br 2f84 <__divsi3+0x24> + 2f80: 10000d26 beq r2,zero,2fb8 <__divsi3+0x58> + 2f84: 294b883a add r5,r5,r5 + 2f88: 10bfffc4 addi r2,r2,-1 + 2f8c: 18c7883a add r3,r3,r3 + 2f90: 293ffb36 bltu r5,r4,2f80 <__alt_data_end+0xfffe2f80> + 2f94: 0005883a mov r2,zero + 2f98: 18000726 beq r3,zero,2fb8 <__divsi3+0x58> + 2f9c: 0005883a mov r2,zero + 2fa0: 31400236 bltu r6,r5,2fac <__divsi3+0x4c> + 2fa4: 314dc83a sub r6,r6,r5 + 2fa8: 10c4b03a or r2,r2,r3 + 2fac: 1806d07a srli r3,r3,1 + 2fb0: 280ad07a srli r5,r5,1 + 2fb4: 183ffa1e bne r3,zero,2fa0 <__alt_data_end+0xfffe2fa0> + 2fb8: 38000126 beq r7,zero,2fc0 <__divsi3+0x60> + 2fbc: 0085c83a sub r2,zero,r2 + 2fc0: f800283a ret + 2fc4: 014bc83a sub r5,zero,r5 + 2fc8: 39c0005c xori r7,r7,1 + 2fcc: 003fe706 br 2f6c <__alt_data_end+0xfffe2f6c> + 2fd0: 0109c83a sub r4,zero,r4 + 2fd4: 01c00044 movi r7,1 + 2fd8: 003fe306 br 2f68 <__alt_data_end+0xfffe2f68> + 2fdc: 00c00044 movi r3,1 + 2fe0: 003fee06 br 2f9c <__alt_data_end+0xfffe2f9c> + +00002fe4 <__modsi3>: + 2fe4: 20001716 blt r4,zero,3044 <__modsi3+0x60> + 2fe8: 000f883a mov r7,zero + 2fec: 2005883a mov r2,r4 + 2ff0: 28001216 blt r5,zero,303c <__modsi3+0x58> + 2ff4: 2900162e bgeu r5,r4,3050 <__modsi3+0x6c> + 2ff8: 01800804 movi r6,32 + 2ffc: 00c00044 movi r3,1 + 3000: 00000106 br 3008 <__modsi3+0x24> + 3004: 30000a26 beq r6,zero,3030 <__modsi3+0x4c> + 3008: 294b883a add r5,r5,r5 + 300c: 31bfffc4 addi r6,r6,-1 + 3010: 18c7883a add r3,r3,r3 + 3014: 293ffb36 bltu r5,r4,3004 <__alt_data_end+0xfffe3004> + 3018: 18000526 beq r3,zero,3030 <__modsi3+0x4c> + 301c: 1806d07a srli r3,r3,1 + 3020: 11400136 bltu r2,r5,3028 <__modsi3+0x44> + 3024: 1145c83a sub r2,r2,r5 + 3028: 280ad07a srli r5,r5,1 + 302c: 183ffb1e bne r3,zero,301c <__alt_data_end+0xfffe301c> + 3030: 38000126 beq r7,zero,3038 <__modsi3+0x54> + 3034: 0085c83a sub r2,zero,r2 + 3038: f800283a ret + 303c: 014bc83a sub r5,zero,r5 + 3040: 003fec06 br 2ff4 <__alt_data_end+0xfffe2ff4> + 3044: 0109c83a sub r4,zero,r4 + 3048: 01c00044 movi r7,1 + 304c: 003fe706 br 2fec <__alt_data_end+0xfffe2fec> + 3050: 00c00044 movi r3,1 + 3054: 003ff106 br 301c <__alt_data_end+0xfffe301c> + +00003058 <__udivsi3>: + 3058: 200d883a mov r6,r4 + 305c: 2900152e bgeu r5,r4,30b4 <__udivsi3+0x5c> + 3060: 28001416 blt r5,zero,30b4 <__udivsi3+0x5c> + 3064: 00800804 movi r2,32 + 3068: 00c00044 movi r3,1 + 306c: 00000206 br 3078 <__udivsi3+0x20> + 3070: 10000e26 beq r2,zero,30ac <__udivsi3+0x54> + 3074: 28000516 blt r5,zero,308c <__udivsi3+0x34> + 3078: 294b883a add r5,r5,r5 + 307c: 10bfffc4 addi r2,r2,-1 + 3080: 18c7883a add r3,r3,r3 + 3084: 293ffa36 bltu r5,r4,3070 <__alt_data_end+0xfffe3070> + 3088: 18000826 beq r3,zero,30ac <__udivsi3+0x54> + 308c: 0005883a mov r2,zero + 3090: 31400236 bltu r6,r5,309c <__udivsi3+0x44> + 3094: 314dc83a sub r6,r6,r5 + 3098: 10c4b03a or r2,r2,r3 + 309c: 1806d07a srli r3,r3,1 + 30a0: 280ad07a srli r5,r5,1 + 30a4: 183ffa1e bne r3,zero,3090 <__alt_data_end+0xfffe3090> + 30a8: f800283a ret + 30ac: 0005883a mov r2,zero + 30b0: f800283a ret + 30b4: 00c00044 movi r3,1 + 30b8: 003ff406 br 308c <__alt_data_end+0xfffe308c> + +000030bc <__umodsi3>: + 30bc: 2005883a mov r2,r4 + 30c0: 2900122e bgeu r5,r4,310c <__umodsi3+0x50> + 30c4: 28001116 blt r5,zero,310c <__umodsi3+0x50> + 30c8: 01800804 movi r6,32 + 30cc: 00c00044 movi r3,1 + 30d0: 00000206 br 30dc <__umodsi3+0x20> + 30d4: 30000c26 beq r6,zero,3108 <__umodsi3+0x4c> + 30d8: 28000516 blt r5,zero,30f0 <__umodsi3+0x34> + 30dc: 294b883a add r5,r5,r5 + 30e0: 31bfffc4 addi r6,r6,-1 + 30e4: 18c7883a add r3,r3,r3 + 30e8: 293ffa36 bltu r5,r4,30d4 <__alt_data_end+0xfffe30d4> + 30ec: 18000626 beq r3,zero,3108 <__umodsi3+0x4c> + 30f0: 1806d07a srli r3,r3,1 + 30f4: 11400136 bltu r2,r5,30fc <__umodsi3+0x40> + 30f8: 1145c83a sub r2,r2,r5 + 30fc: 280ad07a srli r5,r5,1 + 3100: 183ffb1e bne r3,zero,30f0 <__alt_data_end+0xfffe30f0> + 3104: f800283a ret + 3108: f800283a ret + 310c: 00c00044 movi r3,1 + 3110: 003ff706 br 30f0 <__alt_data_end+0xfffe30f0> + +00003114 <__mulsi3>: + 3114: 0005883a mov r2,zero + 3118: 20000726 beq r4,zero,3138 <__mulsi3+0x24> + 311c: 20c0004c andi r3,r4,1 + 3120: 2008d07a srli r4,r4,1 + 3124: 18000126 beq r3,zero,312c <__mulsi3+0x18> + 3128: 1145883a add r2,r2,r5 + 312c: 294b883a add r5,r5,r5 + 3130: 203ffa1e bne r4,zero,311c <__alt_data_end+0xfffe311c> + 3134: f800283a ret + 3138: f800283a ret + +0000313c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 313c: defffe04 addi sp,sp,-8 + 3140: dfc00115 stw ra,4(sp) + 3144: df000015 stw fp,0(sp) + 3148: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 314c: d0a00917 ldw r2,-32732(gp) + 3150: 10000326 beq r2,zero,3160 + 3154: d0a00917 ldw r2,-32732(gp) + 3158: 103ee83a callr r2 + 315c: 00000106 br 3164 + 3160: d0a01104 addi r2,gp,-32700 +} + 3164: e037883a mov sp,fp + 3168: dfc00117 ldw ra,4(sp) + 316c: df000017 ldw fp,0(sp) + 3170: dec00204 addi sp,sp,8 + 3174: f800283a ret + +00003178 : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + 3178: defffb04 addi sp,sp,-20 + 317c: dfc00415 stw ra,16(sp) + 3180: df000315 stw fp,12(sp) + 3184: df000304 addi fp,sp,12 + 3188: e13fff15 stw r4,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + 318c: e0bfff17 ldw r2,-4(fp) + 3190: 10000816 blt r2,zero,31b4 + 3194: 01400304 movi r5,12 + 3198: e13fff17 ldw r4,-4(fp) + 319c: 00031140 call 3114 <__mulsi3> + 31a0: 1007883a mov r3,r2 + 31a4: 00800034 movhi r2,0 + 31a8: 10981e04 addi r2,r2,24696 + 31ac: 1885883a add r2,r3,r2 + 31b0: 00000106 br 31b8 + 31b4: 0005883a mov r2,zero + 31b8: e0bffd15 stw r2,-12(fp) + + if (fd) + 31bc: e0bffd17 ldw r2,-12(fp) + 31c0: 10001926 beq r2,zero,3228 + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + 31c4: e0bffd17 ldw r2,-12(fp) + 31c8: 10800017 ldw r2,0(r2) + 31cc: 10800417 ldw r2,16(r2) + 31d0: 10000626 beq r2,zero,31ec + 31d4: e0bffd17 ldw r2,-12(fp) + 31d8: 10800017 ldw r2,0(r2) + 31dc: 10800417 ldw r2,16(r2) + 31e0: e13ffd17 ldw r4,-12(fp) + 31e4: 103ee83a callr r2 + 31e8: 00000106 br 31f0 + 31ec: 0005883a mov r2,zero + 31f0: e0bffe15 stw r2,-8(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + 31f4: e13fff17 ldw r4,-4(fp) + 31f8: 000379c0 call 379c + if (rval < 0) + 31fc: e0bffe17 ldw r2,-8(fp) + 3200: 1000070e bge r2,zero,3220 + { + ALT_ERRNO = -rval; + 3204: 000313c0 call 313c + 3208: 1007883a mov r3,r2 + 320c: e0bffe17 ldw r2,-8(fp) + 3210: 0085c83a sub r2,zero,r2 + 3214: 18800015 stw r2,0(r3) + return -1; + 3218: 00bfffc4 movi r2,-1 + 321c: 00000706 br 323c + } + return 0; + 3220: 0005883a mov r2,zero + 3224: 00000506 br 323c + } + else + { + ALT_ERRNO = EBADFD; + 3228: 000313c0 call 313c + 322c: 1007883a mov r3,r2 + 3230: 00801444 movi r2,81 + 3234: 18800015 stw r2,0(r3) + return -1; + 3238: 00bfffc4 movi r2,-1 + } +} + 323c: e037883a mov sp,fp + 3240: dfc00117 ldw ra,4(sp) + 3244: df000017 ldw fp,0(sp) + 3248: dec00204 addi sp,sp,8 + 324c: f800283a ret + +00003250 : + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ + 3250: defffd04 addi sp,sp,-12 + 3254: df000215 stw fp,8(sp) + 3258: df000204 addi fp,sp,8 + 325c: e13ffe15 stw r4,-8(fp) + 3260: e17fff15 stw r5,-4(fp) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + 3264: 0001883a nop + 3268: e037883a mov sp,fp + 326c: df000017 ldw fp,0(sp) + 3270: dec00104 addi sp,sp,4 + 3274: f800283a ret + +00003278 : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + 3278: defffc04 addi sp,sp,-16 + 327c: df000315 stw fp,12(sp) + 3280: df000304 addi fp,sp,12 + 3284: e13ffd15 stw r4,-12(fp) + 3288: e17ffe15 stw r5,-8(fp) + 328c: e1bfff15 stw r6,-4(fp) + return len; + 3290: e0bfff17 ldw r2,-4(fp) +} + 3294: e037883a mov sp,fp + 3298: df000017 ldw fp,0(sp) + 329c: dec00104 addi sp,sp,4 + 32a0: f800283a ret + +000032a4 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 32a4: defffe04 addi sp,sp,-8 + 32a8: dfc00115 stw ra,4(sp) + 32ac: df000015 stw fp,0(sp) + 32b0: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 32b4: d0a00917 ldw r2,-32732(gp) + 32b8: 10000326 beq r2,zero,32c8 + 32bc: d0a00917 ldw r2,-32732(gp) + 32c0: 103ee83a callr r2 + 32c4: 00000106 br 32cc + 32c8: d0a01104 addi r2,gp,-32700 +} + 32cc: e037883a mov sp,fp + 32d0: dfc00117 ldw ra,4(sp) + 32d4: df000017 ldw fp,0(sp) + 32d8: dec00204 addi sp,sp,8 + 32dc: f800283a ret + +000032e0 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + 32e0: defffb04 addi sp,sp,-20 + 32e4: dfc00415 stw ra,16(sp) + 32e8: df000315 stw fp,12(sp) + 32ec: df000304 addi fp,sp,12 + 32f0: e13ffe15 stw r4,-8(fp) + 32f4: e17fff15 stw r5,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 32f8: e0bffe17 ldw r2,-8(fp) + 32fc: 10000816 blt r2,zero,3320 + 3300: 01400304 movi r5,12 + 3304: e13ffe17 ldw r4,-8(fp) + 3308: 00031140 call 3114 <__mulsi3> + 330c: 1007883a mov r3,r2 + 3310: 00800034 movhi r2,0 + 3314: 10981e04 addi r2,r2,24696 + 3318: 1885883a add r2,r3,r2 + 331c: 00000106 br 3324 + 3320: 0005883a mov r2,zero + 3324: e0bffd15 stw r2,-12(fp) + + if (fd) + 3328: e0bffd17 ldw r2,-12(fp) + 332c: 10001026 beq r2,zero,3370 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + 3330: e0bffd17 ldw r2,-12(fp) + 3334: 10800017 ldw r2,0(r2) + 3338: 10800817 ldw r2,32(r2) + 333c: 10000726 beq r2,zero,335c + { + return fd->dev->fstat(fd, st); + 3340: e0bffd17 ldw r2,-12(fp) + 3344: 10800017 ldw r2,0(r2) + 3348: 10800817 ldw r2,32(r2) + 334c: e17fff17 ldw r5,-4(fp) + 3350: e13ffd17 ldw r4,-12(fp) + 3354: 103ee83a callr r2 + 3358: 00000a06 br 3384 + * device. + */ + + else + { + st->st_mode = _IFCHR; + 335c: e0bfff17 ldw r2,-4(fp) + 3360: 00c80004 movi r3,8192 + 3364: 10c00115 stw r3,4(r2) + return 0; + 3368: 0005883a mov r2,zero + 336c: 00000506 br 3384 + } + } + else + { + ALT_ERRNO = EBADFD; + 3370: 00032a40 call 32a4 + 3374: 1007883a mov r3,r2 + 3378: 00801444 movi r2,81 + 337c: 18800015 stw r2,0(r3) + return -1; + 3380: 00bfffc4 movi r2,-1 + } +} + 3384: e037883a mov sp,fp + 3388: dfc00117 ldw ra,4(sp) + 338c: df000017 ldw fp,0(sp) + 3390: dec00204 addi sp,sp,8 + 3394: f800283a ret + +00003398 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 3398: defffe04 addi sp,sp,-8 + 339c: dfc00115 stw ra,4(sp) + 33a0: df000015 stw fp,0(sp) + 33a4: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 33a8: d0a00917 ldw r2,-32732(gp) + 33ac: 10000326 beq r2,zero,33bc + 33b0: d0a00917 ldw r2,-32732(gp) + 33b4: 103ee83a callr r2 + 33b8: 00000106 br 33c0 + 33bc: d0a01104 addi r2,gp,-32700 +} + 33c0: e037883a mov sp,fp + 33c4: dfc00117 ldw ra,4(sp) + 33c8: df000017 ldw fp,0(sp) + 33cc: dec00204 addi sp,sp,8 + 33d0: f800283a ret + +000033d4 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + 33d4: deffed04 addi sp,sp,-76 + 33d8: dfc01215 stw ra,72(sp) + 33dc: df001115 stw fp,68(sp) + 33e0: df001104 addi fp,sp,68 + 33e4: e13fff15 stw r4,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 33e8: e0bfff17 ldw r2,-4(fp) + 33ec: 10000816 blt r2,zero,3410 + 33f0: 01400304 movi r5,12 + 33f4: e13fff17 ldw r4,-4(fp) + 33f8: 00031140 call 3114 <__mulsi3> + 33fc: 1007883a mov r3,r2 + 3400: 00800034 movhi r2,0 + 3404: 10981e04 addi r2,r2,24696 + 3408: 1885883a add r2,r3,r2 + 340c: 00000106 br 3414 + 3410: 0005883a mov r2,zero + 3414: e0bfef15 stw r2,-68(fp) + + if (fd) + 3418: e0bfef17 ldw r2,-68(fp) + 341c: 10000e26 beq r2,zero,3458 + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + 3420: e0bfef17 ldw r2,-68(fp) + 3424: 10800017 ldw r2,0(r2) + 3428: 10800817 ldw r2,32(r2) + 342c: 1000021e bne r2,zero,3438 + { + return 1; + 3430: 00800044 movi r2,1 + 3434: 00000d06 br 346c + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + 3438: e0bff004 addi r2,fp,-64 + 343c: 100b883a mov r5,r2 + 3440: e13fff17 ldw r4,-4(fp) + 3444: 00032e00 call 32e0 + return (stat.st_mode == _IFCHR) ? 1 : 0; + 3448: e0bff117 ldw r2,-60(fp) + 344c: 10880020 cmpeqi r2,r2,8192 + 3450: 10803fcc andi r2,r2,255 + 3454: 00000506 br 346c + } + } + else + { + ALT_ERRNO = EBADFD; + 3458: 00033980 call 3398 + 345c: 1007883a mov r3,r2 + 3460: 00801444 movi r2,81 + 3464: 18800015 stw r2,0(r3) + return 0; + 3468: 0005883a mov r2,zero + } +} + 346c: e037883a mov sp,fp + 3470: dfc00117 ldw ra,4(sp) + 3474: df000017 ldw fp,0(sp) + 3478: dec00204 addi sp,sp,8 + 347c: f800283a ret + +00003480 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 3480: defffe04 addi sp,sp,-8 + 3484: dfc00115 stw ra,4(sp) + 3488: df000015 stw fp,0(sp) + 348c: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 3490: d0a00917 ldw r2,-32732(gp) + 3494: 10000326 beq r2,zero,34a4 + 3498: d0a00917 ldw r2,-32732(gp) + 349c: 103ee83a callr r2 + 34a0: 00000106 br 34a8 + 34a4: d0a01104 addi r2,gp,-32700 +} + 34a8: e037883a mov sp,fp + 34ac: dfc00117 ldw ra,4(sp) + 34b0: df000017 ldw fp,0(sp) + 34b4: dec00204 addi sp,sp,8 + 34b8: f800283a ret + +000034bc : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + 34bc: defff904 addi sp,sp,-28 + 34c0: dfc00615 stw ra,24(sp) + 34c4: df000515 stw fp,20(sp) + 34c8: df000504 addi fp,sp,20 + 34cc: e13ffd15 stw r4,-12(fp) + 34d0: e17ffe15 stw r5,-8(fp) + 34d4: e1bfff15 stw r6,-4(fp) + alt_fd* fd; + off_t rc = 0; + 34d8: e03ffb15 stw zero,-20(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 34dc: e0bffd17 ldw r2,-12(fp) + 34e0: 10000816 blt r2,zero,3504 + 34e4: 01400304 movi r5,12 + 34e8: e13ffd17 ldw r4,-12(fp) + 34ec: 00031140 call 3114 <__mulsi3> + 34f0: 1007883a mov r3,r2 + 34f4: 00800034 movhi r2,0 + 34f8: 10981e04 addi r2,r2,24696 + 34fc: 1885883a add r2,r3,r2 + 3500: 00000106 br 3508 + 3504: 0005883a mov r2,zero + 3508: e0bffc15 stw r2,-16(fp) + + if (fd) + 350c: e0bffc17 ldw r2,-16(fp) + 3510: 10001026 beq r2,zero,3554 + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + 3514: e0bffc17 ldw r2,-16(fp) + 3518: 10800017 ldw r2,0(r2) + 351c: 10800717 ldw r2,28(r2) + 3520: 10000926 beq r2,zero,3548 + { + rc = fd->dev->lseek(fd, ptr, dir); + 3524: e0bffc17 ldw r2,-16(fp) + 3528: 10800017 ldw r2,0(r2) + 352c: 10800717 ldw r2,28(r2) + 3530: e1bfff17 ldw r6,-4(fp) + 3534: e17ffe17 ldw r5,-8(fp) + 3538: e13ffc17 ldw r4,-16(fp) + 353c: 103ee83a callr r2 + 3540: e0bffb15 stw r2,-20(fp) + 3544: 00000506 br 355c + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + 3548: 00bfde84 movi r2,-134 + 354c: e0bffb15 stw r2,-20(fp) + 3550: 00000206 br 355c + } + } + else + { + rc = -EBADFD; + 3554: 00bfebc4 movi r2,-81 + 3558: e0bffb15 stw r2,-20(fp) + } + + if (rc < 0) + 355c: e0bffb17 ldw r2,-20(fp) + 3560: 1000070e bge r2,zero,3580 + { + ALT_ERRNO = -rc; + 3564: 00034800 call 3480 + 3568: 1007883a mov r3,r2 + 356c: e0bffb17 ldw r2,-20(fp) + 3570: 0085c83a sub r2,zero,r2 + 3574: 18800015 stw r2,0(r3) + rc = -1; + 3578: 00bfffc4 movi r2,-1 + 357c: e0bffb15 stw r2,-20(fp) + } + + return rc; + 3580: e0bffb17 ldw r2,-20(fp) +} + 3584: e037883a mov sp,fp + 3588: dfc00117 ldw ra,4(sp) + 358c: df000017 ldw fp,0(sp) + 3590: dec00204 addi sp,sp,8 + 3594: f800283a ret + +00003598 : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + 3598: defffd04 addi sp,sp,-12 + 359c: dfc00215 stw ra,8(sp) + 35a0: df000115 stw fp,4(sp) + 35a4: df000104 addi fp,sp,4 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + 35a8: 0009883a mov r4,zero + 35ac: 0003a400 call 3a40 + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + 35b0: 0001883a nop + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + 35b4: 0003a780 call 3a78 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + 35b8: 01800034 movhi r6,0 + 35bc: 31960104 addi r6,r6,22532 + 35c0: 01400034 movhi r5,0 + 35c4: 29560104 addi r5,r5,22532 + 35c8: 01000034 movhi r4,0 + 35cc: 21160104 addi r4,r4,22532 + 35d0: 0004c840 call 4c84 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + 35d4: 00048400 call 4840 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + 35d8: 01000034 movhi r4,0 + 35dc: 21122804 addi r4,r4,18592 + 35e0: 00054440 call 5444 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + 35e4: d0a01217 ldw r2,-32696(gp) + 35e8: d0e01317 ldw r3,-32692(gp) + 35ec: d1201417 ldw r4,-32688(gp) + 35f0: 200d883a mov r6,r4 + 35f4: 180b883a mov r5,r3 + 35f8: 1009883a mov r4,r2 + 35fc: 00002480 call 248
+ 3600: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + 3604: 01000044 movi r4,1 + 3608: 00031780 call 3178 + exit (result); + 360c: e13fff17 ldw r4,-4(fp) + 3610: 00054580 call 5458 + +00003614 <__malloc_lock>: + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that malloc is never called by an interrupt service routine. + */ + +void __malloc_lock ( struct _reent *_r ) +{ + 3614: defffe04 addi sp,sp,-8 + 3618: df000115 stw fp,4(sp) + 361c: df000104 addi fp,sp,4 + 3620: e13fff15 stw r4,-4(fp) +} + 3624: 0001883a nop + 3628: e037883a mov sp,fp + 362c: df000017 ldw fp,0(sp) + 3630: dec00104 addi sp,sp,4 + 3634: f800283a ret + +00003638 <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + 3638: defffe04 addi sp,sp,-8 + 363c: df000115 stw fp,4(sp) + 3640: df000104 addi fp,sp,4 + 3644: e13fff15 stw r4,-4(fp) +} + 3648: 0001883a nop + 364c: e037883a mov sp,fp + 3650: df000017 ldw fp,0(sp) + 3654: dec00104 addi sp,sp,4 + 3658: f800283a ret + +0000365c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 365c: defffe04 addi sp,sp,-8 + 3660: dfc00115 stw ra,4(sp) + 3664: df000015 stw fp,0(sp) + 3668: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 366c: d0a00917 ldw r2,-32732(gp) + 3670: 10000326 beq r2,zero,3680 + 3674: d0a00917 ldw r2,-32732(gp) + 3678: 103ee83a callr r2 + 367c: 00000106 br 3684 + 3680: d0a01104 addi r2,gp,-32700 +} + 3684: e037883a mov sp,fp + 3688: dfc00117 ldw ra,4(sp) + 368c: df000017 ldw fp,0(sp) + 3690: dec00204 addi sp,sp,8 + 3694: f800283a ret + +00003698 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + 3698: defff904 addi sp,sp,-28 + 369c: dfc00615 stw ra,24(sp) + 36a0: df000515 stw fp,20(sp) + 36a4: df000504 addi fp,sp,20 + 36a8: e13ffd15 stw r4,-12(fp) + 36ac: e17ffe15 stw r5,-8(fp) + 36b0: e1bfff15 stw r6,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 36b4: e0bffd17 ldw r2,-12(fp) + 36b8: 10000816 blt r2,zero,36dc + 36bc: 01400304 movi r5,12 + 36c0: e13ffd17 ldw r4,-12(fp) + 36c4: 00031140 call 3114 <__mulsi3> + 36c8: 1007883a mov r3,r2 + 36cc: 00800034 movhi r2,0 + 36d0: 10981e04 addi r2,r2,24696 + 36d4: 1885883a add r2,r3,r2 + 36d8: 00000106 br 36e0 + 36dc: 0005883a mov r2,zero + 36e0: e0bffb15 stw r2,-20(fp) + + if (fd) + 36e4: e0bffb17 ldw r2,-20(fp) + 36e8: 10002226 beq r2,zero,3774 + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 36ec: e0bffb17 ldw r2,-20(fp) + 36f0: 10800217 ldw r2,8(r2) + 36f4: 108000cc andi r2,r2,3 + 36f8: 10800060 cmpeqi r2,r2,1 + 36fc: 1000181e bne r2,zero,3760 + (fd->dev->read)) + 3700: e0bffb17 ldw r2,-20(fp) + 3704: 10800017 ldw r2,0(r2) + 3708: 10800517 ldw r2,20(r2) + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 370c: 10001426 beq r2,zero,3760 + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + 3710: e0bffb17 ldw r2,-20(fp) + 3714: 10800017 ldw r2,0(r2) + 3718: 10800517 ldw r2,20(r2) + 371c: e0ffff17 ldw r3,-4(fp) + 3720: 180d883a mov r6,r3 + 3724: e17ffe17 ldw r5,-8(fp) + 3728: e13ffb17 ldw r4,-20(fp) + 372c: 103ee83a callr r2 + 3730: e0bffc15 stw r2,-16(fp) + 3734: e0bffc17 ldw r2,-16(fp) + 3738: 1000070e bge r2,zero,3758 + { + ALT_ERRNO = -rval; + 373c: 000365c0 call 365c + 3740: 1007883a mov r3,r2 + 3744: e0bffc17 ldw r2,-16(fp) + 3748: 0085c83a sub r2,zero,r2 + 374c: 18800015 stw r2,0(r3) + return -1; + 3750: 00bfffc4 movi r2,-1 + 3754: 00000c06 br 3788 + } + return rval; + 3758: e0bffc17 ldw r2,-16(fp) + 375c: 00000a06 br 3788 + } + else + { + ALT_ERRNO = EACCES; + 3760: 000365c0 call 365c + 3764: 1007883a mov r3,r2 + 3768: 00800344 movi r2,13 + 376c: 18800015 stw r2,0(r3) + 3770: 00000406 br 3784 + } + } + else + { + ALT_ERRNO = EBADFD; + 3774: 000365c0 call 365c + 3778: 1007883a mov r3,r2 + 377c: 00801444 movi r2,81 + 3780: 18800015 stw r2,0(r3) + } + return -1; + 3784: 00bfffc4 movi r2,-1 +} + 3788: e037883a mov sp,fp + 378c: dfc00117 ldw ra,4(sp) + 3790: df000017 ldw fp,0(sp) + 3794: dec00204 addi sp,sp,8 + 3798: f800283a ret + +0000379c : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + 379c: defffc04 addi sp,sp,-16 + 37a0: dfc00315 stw ra,12(sp) + 37a4: df000215 stw fp,8(sp) + 37a8: dc000115 stw r16,4(sp) + 37ac: df000204 addi fp,sp,8 + 37b0: e13ffe15 stw r4,-8(fp) + if (fd > 2) + 37b4: e0bffe17 ldw r2,-8(fp) + 37b8: 108000d0 cmplti r2,r2,3 + 37bc: 1000111e bne r2,zero,3804 + { + alt_fd_list[fd].fd_flags = 0; + 37c0: 04000034 movhi r16,0 + 37c4: 84181e04 addi r16,r16,24696 + 37c8: e0bffe17 ldw r2,-8(fp) + 37cc: 01400304 movi r5,12 + 37d0: 1009883a mov r4,r2 + 37d4: 00031140 call 3114 <__mulsi3> + 37d8: 8085883a add r2,r16,r2 + 37dc: 10800204 addi r2,r2,8 + 37e0: 10000015 stw zero,0(r2) + alt_fd_list[fd].dev = 0; + 37e4: 04000034 movhi r16,0 + 37e8: 84181e04 addi r16,r16,24696 + 37ec: e0bffe17 ldw r2,-8(fp) + 37f0: 01400304 movi r5,12 + 37f4: 1009883a mov r4,r2 + 37f8: 00031140 call 3114 <__mulsi3> + 37fc: 8085883a add r2,r16,r2 + 3800: 10000015 stw zero,0(r2) + } +} + 3804: 0001883a nop + 3808: e6ffff04 addi sp,fp,-4 + 380c: dfc00217 ldw ra,8(sp) + 3810: df000117 ldw fp,4(sp) + 3814: dc000017 ldw r16,0(sp) + 3818: dec00304 addi sp,sp,12 + 381c: f800283a ret + +00003820 : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + 3820: defff904 addi sp,sp,-28 + 3824: df000615 stw fp,24(sp) + 3828: df000604 addi fp,sp,24 + 382c: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 3830: 0005303a rdctl r2,status + 3834: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 3838: e0fffe17 ldw r3,-8(fp) + 383c: 00bfff84 movi r2,-2 + 3840: 1884703a and r2,r3,r2 + 3844: 1001703a wrctl status,r2 + + return context; + 3848: e0bffe17 ldw r2,-8(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + 384c: e0bffb15 stw r2,-20(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + 3850: d0a00a17 ldw r2,-32728(gp) + 3854: 10c000c4 addi r3,r2,3 + 3858: 00bfff04 movi r2,-4 + 385c: 1884703a and r2,r3,r2 + 3860: d0a00a15 stw r2,-32728(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + 3864: d0e00a17 ldw r3,-32728(gp) + 3868: e0bfff17 ldw r2,-4(fp) + 386c: 1887883a add r3,r3,r2 + 3870: 008000b4 movhi r2,2 + 3874: 10800004 addi r2,r2,0 + 3878: 10c0062e bgeu r2,r3,3894 + 387c: e0bffb17 ldw r2,-20(fp) + 3880: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 3884: e0bffa17 ldw r2,-24(fp) + 3888: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + 388c: 00bfffc4 movi r2,-1 + 3890: 00000b06 br 38c0 + } +#endif + + prev_heap_end = heap_end; + 3894: d0a00a17 ldw r2,-32728(gp) + 3898: e0bffd15 stw r2,-12(fp) + heap_end += incr; + 389c: d0e00a17 ldw r3,-32728(gp) + 38a0: e0bfff17 ldw r2,-4(fp) + 38a4: 1885883a add r2,r3,r2 + 38a8: d0a00a15 stw r2,-32728(gp) + 38ac: e0bffb17 ldw r2,-20(fp) + 38b0: e0bffc15 stw r2,-16(fp) + 38b4: e0bffc17 ldw r2,-16(fp) + 38b8: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + 38bc: e0bffd17 ldw r2,-12(fp) +} + 38c0: e037883a mov sp,fp + 38c4: df000017 ldw fp,0(sp) + 38c8: dec00104 addi sp,sp,4 + 38cc: f800283a ret + +000038d0 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 38d0: defffe04 addi sp,sp,-8 + 38d4: dfc00115 stw ra,4(sp) + 38d8: df000015 stw fp,0(sp) + 38dc: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 38e0: d0a00917 ldw r2,-32732(gp) + 38e4: 10000326 beq r2,zero,38f4 + 38e8: d0a00917 ldw r2,-32732(gp) + 38ec: 103ee83a callr r2 + 38f0: 00000106 br 38f8 + 38f4: d0a01104 addi r2,gp,-32700 +} + 38f8: e037883a mov sp,fp + 38fc: dfc00117 ldw ra,4(sp) + 3900: df000017 ldw fp,0(sp) + 3904: dec00204 addi sp,sp,8 + 3908: f800283a ret + +0000390c : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + 390c: defff904 addi sp,sp,-28 + 3910: dfc00615 stw ra,24(sp) + 3914: df000515 stw fp,20(sp) + 3918: df000504 addi fp,sp,20 + 391c: e13ffd15 stw r4,-12(fp) + 3920: e17ffe15 stw r5,-8(fp) + 3924: e1bfff15 stw r6,-4(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 3928: e0bffd17 ldw r2,-12(fp) + 392c: 10000816 blt r2,zero,3950 + 3930: 01400304 movi r5,12 + 3934: e13ffd17 ldw r4,-12(fp) + 3938: 00031140 call 3114 <__mulsi3> + 393c: 1007883a mov r3,r2 + 3940: 00800034 movhi r2,0 + 3944: 10981e04 addi r2,r2,24696 + 3948: 1885883a add r2,r3,r2 + 394c: 00000106 br 3954 + 3950: 0005883a mov r2,zero + 3954: e0bffb15 stw r2,-20(fp) + + if (fd) + 3958: e0bffb17 ldw r2,-20(fp) + 395c: 10002126 beq r2,zero,39e4 + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + 3960: e0bffb17 ldw r2,-20(fp) + 3964: 10800217 ldw r2,8(r2) + 3968: 108000cc andi r2,r2,3 + 396c: 10001826 beq r2,zero,39d0 + 3970: e0bffb17 ldw r2,-20(fp) + 3974: 10800017 ldw r2,0(r2) + 3978: 10800617 ldw r2,24(r2) + 397c: 10001426 beq r2,zero,39d0 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + 3980: e0bffb17 ldw r2,-20(fp) + 3984: 10800017 ldw r2,0(r2) + 3988: 10800617 ldw r2,24(r2) + 398c: e0ffff17 ldw r3,-4(fp) + 3990: 180d883a mov r6,r3 + 3994: e17ffe17 ldw r5,-8(fp) + 3998: e13ffb17 ldw r4,-20(fp) + 399c: 103ee83a callr r2 + 39a0: e0bffc15 stw r2,-16(fp) + 39a4: e0bffc17 ldw r2,-16(fp) + 39a8: 1000070e bge r2,zero,39c8 + { + ALT_ERRNO = -rval; + 39ac: 00038d00 call 38d0 + 39b0: 1007883a mov r3,r2 + 39b4: e0bffc17 ldw r2,-16(fp) + 39b8: 0085c83a sub r2,zero,r2 + 39bc: 18800015 stw r2,0(r3) + return -1; + 39c0: 00bfffc4 movi r2,-1 + 39c4: 00000c06 br 39f8 + } + return rval; + 39c8: e0bffc17 ldw r2,-16(fp) + 39cc: 00000a06 br 39f8 + } + else + { + ALT_ERRNO = EACCES; + 39d0: 00038d00 call 38d0 + 39d4: 1007883a mov r3,r2 + 39d8: 00800344 movi r2,13 + 39dc: 18800015 stw r2,0(r3) + 39e0: 00000406 br 39f4 + } + } + else + { + ALT_ERRNO = EBADFD; + 39e4: 00038d00 call 38d0 + 39e8: 1007883a mov r3,r2 + 39ec: 00801444 movi r2,81 + 39f0: 18800015 stw r2,0(r3) + } + return -1; + 39f4: 00bfffc4 movi r2,-1 +} + 39f8: e037883a mov sp,fp + 39fc: dfc00117 ldw ra,4(sp) + 3a00: df000017 ldw fp,0(sp) + 3a04: dec00204 addi sp,sp,8 + 3a08: f800283a ret + +00003a0c : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + 3a0c: defffd04 addi sp,sp,-12 + 3a10: dfc00215 stw ra,8(sp) + 3a14: df000115 stw fp,4(sp) + 3a18: df000104 addi fp,sp,4 + 3a1c: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + 3a20: d1600604 addi r5,gp,-32744 + 3a24: e13fff17 ldw r4,-4(fp) + 3a28: 000479c0 call 479c +} + 3a2c: e037883a mov sp,fp + 3a30: dfc00117 ldw ra,4(sp) + 3a34: df000017 ldw fp,0(sp) + 3a38: dec00204 addi sp,sp,8 + 3a3c: f800283a ret + +00003a40 : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + 3a40: defffd04 addi sp,sp,-12 + 3a44: dfc00215 stw ra,8(sp) + 3a48: df000115 stw fp,4(sp) + 3a4c: df000104 addi fp,sp,4 + 3a50: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu); + 3a54: 00051280 call 5128 + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts (void) +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + 3a58: 00800044 movi r2,1 + 3a5c: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + 3a60: 0001883a nop + 3a64: e037883a mov sp,fp + 3a68: dfc00117 ldw ra,4(sp) + 3a6c: df000017 ldw fp,0(sp) + 3a70: dec00204 addi sp,sp,8 + 3a74: f800283a ret + +00003a78 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + 3a78: defffe04 addi sp,sp,-8 + 3a7c: dfc00115 stw ra,4(sp) + 3a80: df000015 stw fp,0(sp) + 3a84: d839883a mov fp,sp + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + 3a88: 01c0fa04 movi r7,1000 + 3a8c: 000d883a mov r6,zero + 3a90: 000b883a mov r5,zero + 3a94: 010000b4 movhi r4,2 + 3a98: 21040004 addi r4,r4,4096 + 3a9c: 00045b80 call 45b8 + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart); + 3aa0: 01800044 movi r6,1 + 3aa4: 000b883a mov r5,zero + 3aa8: 01000034 movhi r4,0 + 3aac: 21188804 addi r4,r4,25120 + 3ab0: 0003c3c0 call 3c3c + 3ab4: 01000034 movhi r4,0 + 3ab8: 21187e04 addi r4,r4,25080 + 3abc: 0003a0c0 call 3a0c +} + 3ac0: 0001883a nop + 3ac4: e037883a mov sp,fp + 3ac8: dfc00117 ldw ra,4(sp) + 3acc: df000017 ldw fp,0(sp) + 3ad0: dec00204 addi sp,sp,8 + 3ad4: f800283a ret + +00003ad8 : + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 3ad8: defffa04 addi sp,sp,-24 + 3adc: dfc00515 stw ra,20(sp) + 3ae0: df000415 stw fp,16(sp) + 3ae4: df000404 addi fp,sp,16 + 3ae8: e13ffd15 stw r4,-12(fp) + 3aec: e17ffe15 stw r5,-8(fp) + 3af0: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 3af4: e0bffd17 ldw r2,-12(fp) + 3af8: 10800017 ldw r2,0(r2) + 3afc: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + 3b00: e0bffc17 ldw r2,-16(fp) + 3b04: 10c00a04 addi r3,r2,40 + 3b08: e0bffd17 ldw r2,-12(fp) + 3b0c: 10800217 ldw r2,8(r2) + 3b10: 100f883a mov r7,r2 + 3b14: e1bfff17 ldw r6,-4(fp) + 3b18: e17ffe17 ldw r5,-8(fp) + 3b1c: 1809883a mov r4,r3 + 3b20: 00041000 call 4100 + fd->fd_flags); +} + 3b24: e037883a mov sp,fp + 3b28: dfc00117 ldw ra,4(sp) + 3b2c: df000017 ldw fp,0(sp) + 3b30: dec00204 addi sp,sp,8 + 3b34: f800283a ret + +00003b38 : + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 3b38: defffa04 addi sp,sp,-24 + 3b3c: dfc00515 stw ra,20(sp) + 3b40: df000415 stw fp,16(sp) + 3b44: df000404 addi fp,sp,16 + 3b48: e13ffd15 stw r4,-12(fp) + 3b4c: e17ffe15 stw r5,-8(fp) + 3b50: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 3b54: e0bffd17 ldw r2,-12(fp) + 3b58: 10800017 ldw r2,0(r2) + 3b5c: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + 3b60: e0bffc17 ldw r2,-16(fp) + 3b64: 10c00a04 addi r3,r2,40 + 3b68: e0bffd17 ldw r2,-12(fp) + 3b6c: 10800217 ldw r2,8(r2) + 3b70: 100f883a mov r7,r2 + 3b74: e1bfff17 ldw r6,-4(fp) + 3b78: e17ffe17 ldw r5,-8(fp) + 3b7c: 1809883a mov r4,r3 + 3b80: 000431c0 call 431c + fd->fd_flags); +} + 3b84: e037883a mov sp,fp + 3b88: dfc00117 ldw ra,4(sp) + 3b8c: df000017 ldw fp,0(sp) + 3b90: dec00204 addi sp,sp,8 + 3b94: f800283a ret + +00003b98 : + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + 3b98: defffc04 addi sp,sp,-16 + 3b9c: dfc00315 stw ra,12(sp) + 3ba0: df000215 stw fp,8(sp) + 3ba4: df000204 addi fp,sp,8 + 3ba8: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 3bac: e0bfff17 ldw r2,-4(fp) + 3bb0: 10800017 ldw r2,0(r2) + 3bb4: e0bffe15 stw r2,-8(fp) + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); + 3bb8: e0bffe17 ldw r2,-8(fp) + 3bbc: 10c00a04 addi r3,r2,40 + 3bc0: e0bfff17 ldw r2,-4(fp) + 3bc4: 10800217 ldw r2,8(r2) + 3bc8: 100b883a mov r5,r2 + 3bcc: 1809883a mov r4,r3 + 3bd0: 0003fa80 call 3fa8 +} + 3bd4: e037883a mov sp,fp + 3bd8: dfc00117 ldw ra,4(sp) + 3bdc: df000017 ldw fp,0(sp) + 3be0: dec00204 addi sp,sp,8 + 3be4: f800283a ret + +00003be8 : + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + 3be8: defffa04 addi sp,sp,-24 + 3bec: dfc00515 stw ra,20(sp) + 3bf0: df000415 stw fp,16(sp) + 3bf4: df000404 addi fp,sp,16 + 3bf8: e13ffd15 stw r4,-12(fp) + 3bfc: e17ffe15 stw r5,-8(fp) + 3c00: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 3c04: e0bffd17 ldw r2,-12(fp) + 3c08: 10800017 ldw r2,0(r2) + 3c0c: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); + 3c10: e0bffc17 ldw r2,-16(fp) + 3c14: 10800a04 addi r2,r2,40 + 3c18: e1bfff17 ldw r6,-4(fp) + 3c1c: e17ffe17 ldw r5,-8(fp) + 3c20: 1009883a mov r4,r2 + 3c24: 00040100 call 4010 +} + 3c28: e037883a mov sp,fp + 3c2c: dfc00117 ldw ra,4(sp) + 3c30: df000017 ldw fp,0(sp) + 3c34: dec00204 addi sp,sp,8 + 3c38: f800283a ret + +00003c3c : + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + 3c3c: defffa04 addi sp,sp,-24 + 3c40: dfc00515 stw ra,20(sp) + 3c44: df000415 stw fp,16(sp) + 3c48: df000404 addi fp,sp,16 + 3c4c: e13ffd15 stw r4,-12(fp) + 3c50: e17ffe15 stw r5,-8(fp) + 3c54: e1bfff15 stw r6,-4(fp) + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 3c58: e0bffd17 ldw r2,-12(fp) + 3c5c: 00c00044 movi r3,1 + 3c60: 10c00815 stw r3,32(r2) + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 3c64: e0bffd17 ldw r2,-12(fp) + 3c68: 10800017 ldw r2,0(r2) + 3c6c: 10800104 addi r2,r2,4 + 3c70: 1007883a mov r3,r2 + 3c74: e0bffd17 ldw r2,-12(fp) + 3c78: 10800817 ldw r2,32(r2) + 3c7c: 18800035 stwio r2,0(r3) + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + 3c80: e0bffe17 ldw r2,-8(fp) + 3c84: e0ffff17 ldw r3,-4(fp) + 3c88: d8000015 stw zero,0(sp) + 3c8c: e1fffd17 ldw r7,-12(fp) + 3c90: 01800034 movhi r6,0 + 3c94: 318f3f04 addi r6,r6,15612 + 3c98: 180b883a mov r5,r3 + 3c9c: 1009883a mov r4,r2 + 3ca0: 00049000 call 4900 +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + 3ca4: e0bffd17 ldw r2,-12(fp) + 3ca8: 10000915 stw zero,36(r2) + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + 3cac: e0bffd17 ldw r2,-12(fp) + 3cb0: 10800204 addi r2,r2,8 + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 3cb4: d0e01617 ldw r3,-32680(gp) + 3cb8: e1fffd17 ldw r7,-12(fp) + 3cbc: 01800034 movhi r6,0 + 3cc0: 318fc204 addi r6,r6,16136 + 3cc4: 180b883a mov r5,r3 + 3cc8: 1009883a mov r4,r2 + 3ccc: 00046340 call 4634 + 3cd0: 1000040e bge r2,zero,3ce4 + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + 3cd4: e0fffd17 ldw r3,-12(fp) + 3cd8: 00a00034 movhi r2,32768 + 3cdc: 10bfffc4 addi r2,r2,-1 + 3ce0: 18800115 stw r2,4(r3) + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + 3ce4: 0001883a nop + 3ce8: e037883a mov sp,fp + 3cec: dfc00117 ldw ra,4(sp) + 3cf0: df000017 ldw fp,0(sp) + 3cf4: dec00204 addi sp,sp,8 + 3cf8: f800283a ret + +00003cfc : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + 3cfc: defff804 addi sp,sp,-32 + 3d00: df000715 stw fp,28(sp) + 3d04: df000704 addi fp,sp,28 + 3d08: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + 3d0c: e0bfff17 ldw r2,-4(fp) + 3d10: e0bffb15 stw r2,-20(fp) + unsigned int base = sp->base; + 3d14: e0bffb17 ldw r2,-20(fp) + 3d18: 10800017 ldw r2,0(r2) + 3d1c: e0bffc15 stw r2,-16(fp) + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 3d20: e0bffc17 ldw r2,-16(fp) + 3d24: 10800104 addi r2,r2,4 + 3d28: 10800037 ldwio r2,0(r2) + 3d2c: e0bffd15 stw r2,-12(fp) + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + 3d30: e0bffd17 ldw r2,-12(fp) + 3d34: 1080c00c andi r2,r2,768 + 3d38: 10006d26 beq r2,zero,3ef0 + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + 3d3c: e0bffd17 ldw r2,-12(fp) + 3d40: 1080400c andi r2,r2,256 + 3d44: 10003526 beq r2,zero,3e1c + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + 3d48: 00800074 movhi r2,1 + 3d4c: e0bff915 stw r2,-28(fp) + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 3d50: e0bffb17 ldw r2,-20(fp) + 3d54: 10800a17 ldw r2,40(r2) + 3d58: 10800044 addi r2,r2,1 + 3d5c: 1081ffcc andi r2,r2,2047 + 3d60: e0bffe15 stw r2,-8(fp) + if (next == sp->rx_out) + 3d64: e0bffb17 ldw r2,-20(fp) + 3d68: 10c00b17 ldw r3,44(r2) + 3d6c: e0bffe17 ldw r2,-8(fp) + 3d70: 18801526 beq r3,r2,3dc8 + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + 3d74: e0bffc17 ldw r2,-16(fp) + 3d78: 10800037 ldwio r2,0(r2) + 3d7c: e0bff915 stw r2,-28(fp) + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + 3d80: e0bff917 ldw r2,-28(fp) + 3d84: 10a0000c andi r2,r2,32768 + 3d88: 10001126 beq r2,zero,3dd0 + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + 3d8c: e0bffb17 ldw r2,-20(fp) + 3d90: 10800a17 ldw r2,40(r2) + 3d94: e0fff917 ldw r3,-28(fp) + 3d98: 1809883a mov r4,r3 + 3d9c: e0fffb17 ldw r3,-20(fp) + 3da0: 1885883a add r2,r3,r2 + 3da4: 10800e04 addi r2,r2,56 + 3da8: 11000005 stb r4,0(r2) + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 3dac: e0bffb17 ldw r2,-20(fp) + 3db0: 10800a17 ldw r2,40(r2) + 3db4: 10800044 addi r2,r2,1 + 3db8: 10c1ffcc andi r3,r2,2047 + 3dbc: e0bffb17 ldw r2,-20(fp) + 3dc0: 10c00a15 stw r3,40(r2) + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + 3dc4: 003fe206 br 3d50 <__alt_data_end+0xfffe3d50> + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + if (next == sp->rx_out) + break; + 3dc8: 0001883a nop + 3dcc: 00000106 br 3dd4 + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + break; + 3dd0: 0001883a nop + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + 3dd4: e0bff917 ldw r2,-28(fp) + 3dd8: 10bfffec andhi r2,r2,65535 + 3ddc: 10000f26 beq r2,zero,3e1c + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 3de0: e0bffb17 ldw r2,-20(fp) + 3de4: 10c00817 ldw r3,32(r2) + 3de8: 00bfff84 movi r2,-2 + 3dec: 1886703a and r3,r3,r2 + 3df0: e0bffb17 ldw r2,-20(fp) + 3df4: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + 3df8: e0bffc17 ldw r2,-16(fp) + 3dfc: 10800104 addi r2,r2,4 + 3e00: 1007883a mov r3,r2 + 3e04: e0bffb17 ldw r2,-20(fp) + 3e08: 10800817 ldw r2,32(r2) + 3e0c: 18800035 stwio r2,0(r3) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 3e10: e0bffc17 ldw r2,-16(fp) + 3e14: 10800104 addi r2,r2,4 + 3e18: 10800037 ldwio r2,0(r2) + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + 3e1c: e0bffd17 ldw r2,-12(fp) + 3e20: 1080800c andi r2,r2,512 + 3e24: 103fbe26 beq r2,zero,3d20 <__alt_data_end+0xfffe3d20> + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + 3e28: e0bffd17 ldw r2,-12(fp) + 3e2c: 1004d43a srli r2,r2,16 + 3e30: e0bffa15 stw r2,-24(fp) + + while (space > 0 && sp->tx_out != sp->tx_in) + 3e34: 00001406 br 3e88 + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + 3e38: e0bffc17 ldw r2,-16(fp) + 3e3c: e0fffb17 ldw r3,-20(fp) + 3e40: 18c00d17 ldw r3,52(r3) + 3e44: e13ffb17 ldw r4,-20(fp) + 3e48: 20c7883a add r3,r4,r3 + 3e4c: 18c20e04 addi r3,r3,2104 + 3e50: 18c00003 ldbu r3,0(r3) + 3e54: 18c03fcc andi r3,r3,255 + 3e58: 18c0201c xori r3,r3,128 + 3e5c: 18ffe004 addi r3,r3,-128 + 3e60: 10c00035 stwio r3,0(r2) + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 3e64: e0bffb17 ldw r2,-20(fp) + 3e68: 10800d17 ldw r2,52(r2) + 3e6c: 10800044 addi r2,r2,1 + 3e70: 10c1ffcc andi r3,r2,2047 + 3e74: e0bffb17 ldw r2,-20(fp) + 3e78: 10c00d15 stw r3,52(r2) + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + 3e7c: e0bffa17 ldw r2,-24(fp) + 3e80: 10bfffc4 addi r2,r2,-1 + 3e84: e0bffa15 stw r2,-24(fp) + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + 3e88: e0bffa17 ldw r2,-24(fp) + 3e8c: 10000526 beq r2,zero,3ea4 + 3e90: e0bffb17 ldw r2,-20(fp) + 3e94: 10c00d17 ldw r3,52(r2) + 3e98: e0bffb17 ldw r2,-20(fp) + 3e9c: 10800c17 ldw r2,48(r2) + 3ea0: 18bfe51e bne r3,r2,3e38 <__alt_data_end+0xfffe3e38> + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + 3ea4: e0bffa17 ldw r2,-24(fp) + 3ea8: 103f9d26 beq r2,zero,3d20 <__alt_data_end+0xfffe3d20> + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 3eac: e0bffb17 ldw r2,-20(fp) + 3eb0: 10c00817 ldw r3,32(r2) + 3eb4: 00bfff44 movi r2,-3 + 3eb8: 1886703a and r3,r3,r2 + 3ebc: e0bffb17 ldw r2,-20(fp) + 3ec0: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 3ec4: e0bffb17 ldw r2,-20(fp) + 3ec8: 10800017 ldw r2,0(r2) + 3ecc: 10800104 addi r2,r2,4 + 3ed0: 1007883a mov r3,r2 + 3ed4: e0bffb17 ldw r2,-20(fp) + 3ed8: 10800817 ldw r2,32(r2) + 3edc: 18800035 stwio r2,0(r3) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 3ee0: e0bffc17 ldw r2,-16(fp) + 3ee4: 10800104 addi r2,r2,4 + 3ee8: 10800037 ldwio r2,0(r2) + } + } + } + 3eec: 003f8c06 br 3d20 <__alt_data_end+0xfffe3d20> + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + break; + 3ef0: 0001883a nop + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + } +} + 3ef4: 0001883a nop + 3ef8: e037883a mov sp,fp + 3efc: df000017 ldw fp,0(sp) + 3f00: dec00104 addi sp,sp,4 + 3f04: f800283a ret + +00003f08 : + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + 3f08: defff804 addi sp,sp,-32 + 3f0c: df000715 stw fp,28(sp) + 3f10: df000704 addi fp,sp,28 + 3f14: e13ffb15 stw r4,-20(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + 3f18: e0bffb17 ldw r2,-20(fp) + 3f1c: e0bff915 stw r2,-28(fp) + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + 3f20: e0bff917 ldw r2,-28(fp) + 3f24: 10800017 ldw r2,0(r2) + 3f28: 10800104 addi r2,r2,4 + 3f2c: 10800037 ldwio r2,0(r2) + 3f30: e0bffa15 stw r2,-24(fp) + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + 3f34: e0bffa17 ldw r2,-24(fp) + 3f38: 1081000c andi r2,r2,1024 + 3f3c: 10000b26 beq r2,zero,3f6c + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + 3f40: e0bff917 ldw r2,-28(fp) + 3f44: 10800017 ldw r2,0(r2) + 3f48: 10800104 addi r2,r2,4 + 3f4c: 1007883a mov r3,r2 + 3f50: e0bff917 ldw r2,-28(fp) + 3f54: 10800817 ldw r2,32(r2) + 3f58: 10810014 ori r2,r2,1024 + 3f5c: 18800035 stwio r2,0(r3) + sp->host_inactive = 0; + 3f60: e0bff917 ldw r2,-28(fp) + 3f64: 10000915 stw zero,36(r2) + 3f68: 00000a06 br 3f94 + } + else if (sp->host_inactive < INT_MAX - 2) { + 3f6c: e0bff917 ldw r2,-28(fp) + 3f70: 10c00917 ldw r3,36(r2) + 3f74: 00a00034 movhi r2,32768 + 3f78: 10bfff04 addi r2,r2,-4 + 3f7c: 10c00536 bltu r2,r3,3f94 + sp->host_inactive++; + 3f80: e0bff917 ldw r2,-28(fp) + 3f84: 10800917 ldw r2,36(r2) + 3f88: 10c00044 addi r3,r2,1 + 3f8c: e0bff917 ldw r2,-28(fp) + 3f90: 10c00915 stw r3,36(r2) + 3f94: d0a01617 ldw r2,-32680(gp) + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + 3f98: e037883a mov sp,fp + 3f9c: df000017 ldw fp,0(sp) + 3fa0: dec00104 addi sp,sp,4 + 3fa4: f800283a ret + +00003fa8 : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + 3fa8: defffd04 addi sp,sp,-12 + 3fac: df000215 stw fp,8(sp) + 3fb0: df000204 addi fp,sp,8 + 3fb4: e13ffe15 stw r4,-8(fp) + 3fb8: e17fff15 stw r5,-4(fp) + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 3fbc: 00000506 br 3fd4 + if (flags & O_NONBLOCK) { + 3fc0: e0bfff17 ldw r2,-4(fp) + 3fc4: 1090000c andi r2,r2,16384 + 3fc8: 10000226 beq r2,zero,3fd4 + return -EWOULDBLOCK; + 3fcc: 00bffd44 movi r2,-11 + 3fd0: 00000b06 br 4000 +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 3fd4: e0bffe17 ldw r2,-8(fp) + 3fd8: 10c00d17 ldw r3,52(r2) + 3fdc: e0bffe17 ldw r2,-8(fp) + 3fe0: 10800c17 ldw r2,48(r2) + 3fe4: 18800526 beq r3,r2,3ffc + 3fe8: e0bffe17 ldw r2,-8(fp) + 3fec: 10c00917 ldw r3,36(r2) + 3ff0: e0bffe17 ldw r2,-8(fp) + 3ff4: 10800117 ldw r2,4(r2) + 3ff8: 18bff136 bltu r3,r2,3fc0 <__alt_data_end+0xfffe3fc0> + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 3ffc: 0005883a mov r2,zero +} + 4000: e037883a mov sp,fp + 4004: df000017 ldw fp,0(sp) + 4008: dec00104 addi sp,sp,4 + 400c: f800283a ret + +00004010 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + 4010: defffa04 addi sp,sp,-24 + 4014: df000515 stw fp,20(sp) + 4018: df000504 addi fp,sp,20 + 401c: e13ffd15 stw r4,-12(fp) + 4020: e17ffe15 stw r5,-8(fp) + 4024: e1bfff15 stw r6,-4(fp) + int rc = -ENOTTY; + 4028: 00bff9c4 movi r2,-25 + 402c: e0bffb15 stw r2,-20(fp) + + switch (req) + 4030: e0bffe17 ldw r2,-8(fp) + 4034: 10da8060 cmpeqi r3,r2,27137 + 4038: 1800031e bne r3,zero,4048 + 403c: 109a80a0 cmpeqi r2,r2,27138 + 4040: 1000181e bne r2,zero,40a4 + rc = 0; + } + break; + + default: + break; + 4044: 00002906 br 40ec + + switch (req) + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + 4048: e0bffd17 ldw r2,-12(fp) + 404c: 10c00117 ldw r3,4(r2) + 4050: 00a00034 movhi r2,32768 + 4054: 10bfffc4 addi r2,r2,-1 + 4058: 18802126 beq r3,r2,40e0 + { + int timeout = *((int *)arg); + 405c: e0bfff17 ldw r2,-4(fp) + 4060: 10800017 ldw r2,0(r2) + 4064: e0bffc15 stw r2,-16(fp) + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + 4068: e0bffc17 ldw r2,-16(fp) + 406c: 10800090 cmplti r2,r2,2 + 4070: 1000061e bne r2,zero,408c + 4074: e0fffc17 ldw r3,-16(fp) + 4078: 00a00034 movhi r2,32768 + 407c: 10bfffc4 addi r2,r2,-1 + 4080: 18800226 beq r3,r2,408c + 4084: e0bffc17 ldw r2,-16(fp) + 4088: 00000206 br 4094 + 408c: 00a00034 movhi r2,32768 + 4090: 10bfff84 addi r2,r2,-2 + 4094: e0fffd17 ldw r3,-12(fp) + 4098: 18800115 stw r2,4(r3) + rc = 0; + 409c: e03ffb15 stw zero,-20(fp) + } + break; + 40a0: 00000f06 br 40e0 + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + 40a4: e0bffd17 ldw r2,-12(fp) + 40a8: 10c00117 ldw r3,4(r2) + 40ac: 00a00034 movhi r2,32768 + 40b0: 10bfffc4 addi r2,r2,-1 + 40b4: 18800c26 beq r3,r2,40e8 + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + 40b8: e0bffd17 ldw r2,-12(fp) + 40bc: 10c00917 ldw r3,36(r2) + 40c0: e0bffd17 ldw r2,-12(fp) + 40c4: 10800117 ldw r2,4(r2) + 40c8: 1885803a cmpltu r2,r3,r2 + 40cc: 10c03fcc andi r3,r2,255 + 40d0: e0bfff17 ldw r2,-4(fp) + 40d4: 10c00015 stw r3,0(r2) + rc = 0; + 40d8: e03ffb15 stw zero,-20(fp) + } + break; + 40dc: 00000206 br 40e8 + { + int timeout = *((int *)arg); + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + rc = 0; + } + break; + 40e0: 0001883a nop + 40e4: 00000106 br 40ec + if (sp->timeout != INT_MAX) + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + rc = 0; + } + break; + 40e8: 0001883a nop + + default: + break; + } + + return rc; + 40ec: e0bffb17 ldw r2,-20(fp) +} + 40f0: e037883a mov sp,fp + 40f4: df000017 ldw fp,0(sp) + 40f8: dec00104 addi sp,sp,4 + 40fc: f800283a ret + +00004100 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + 4100: defff304 addi sp,sp,-52 + 4104: dfc00c15 stw ra,48(sp) + 4108: df000b15 stw fp,44(sp) + 410c: df000b04 addi fp,sp,44 + 4110: e13ffc15 stw r4,-16(fp) + 4114: e17ffd15 stw r5,-12(fp) + 4118: e1bffe15 stw r6,-8(fp) + 411c: e1ffff15 stw r7,-4(fp) + char * ptr = buffer; + 4120: e0bffd17 ldw r2,-12(fp) + 4124: e0bff515 stw r2,-44(fp) + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + 4128: 00004706 br 4248 + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + 412c: e0bffc17 ldw r2,-16(fp) + 4130: 10800a17 ldw r2,40(r2) + 4134: e0bff715 stw r2,-36(fp) + out = sp->rx_out; + 4138: e0bffc17 ldw r2,-16(fp) + 413c: 10800b17 ldw r2,44(r2) + 4140: e0bff815 stw r2,-32(fp) + + if (in >= out) + 4144: e0fff717 ldw r3,-36(fp) + 4148: e0bff817 ldw r2,-32(fp) + 414c: 18800536 bltu r3,r2,4164 + n = in - out; + 4150: e0fff717 ldw r3,-36(fp) + 4154: e0bff817 ldw r2,-32(fp) + 4158: 1885c83a sub r2,r3,r2 + 415c: e0bff615 stw r2,-40(fp) + 4160: 00000406 br 4174 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + 4164: 00c20004 movi r3,2048 + 4168: e0bff817 ldw r2,-32(fp) + 416c: 1885c83a sub r2,r3,r2 + 4170: e0bff615 stw r2,-40(fp) + + if (n == 0) + 4174: e0bff617 ldw r2,-40(fp) + 4178: 10001e26 beq r2,zero,41f4 + break; /* No more data available */ + + if (n > space) + 417c: e0fffe17 ldw r3,-8(fp) + 4180: e0bff617 ldw r2,-40(fp) + 4184: 1880022e bgeu r3,r2,4190 + n = space; + 4188: e0bffe17 ldw r2,-8(fp) + 418c: e0bff615 stw r2,-40(fp) + + memcpy(ptr, sp->rx_buf + out, n); + 4190: e0bffc17 ldw r2,-16(fp) + 4194: 10c00e04 addi r3,r2,56 + 4198: e0bff817 ldw r2,-32(fp) + 419c: 1885883a add r2,r3,r2 + 41a0: e1bff617 ldw r6,-40(fp) + 41a4: 100b883a mov r5,r2 + 41a8: e13ff517 ldw r4,-44(fp) + 41ac: 000178c0 call 178c + ptr += n; + 41b0: e0fff517 ldw r3,-44(fp) + 41b4: e0bff617 ldw r2,-40(fp) + 41b8: 1885883a add r2,r3,r2 + 41bc: e0bff515 stw r2,-44(fp) + space -= n; + 41c0: e0fffe17 ldw r3,-8(fp) + 41c4: e0bff617 ldw r2,-40(fp) + 41c8: 1885c83a sub r2,r3,r2 + 41cc: e0bffe15 stw r2,-8(fp) + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 41d0: e0fff817 ldw r3,-32(fp) + 41d4: e0bff617 ldw r2,-40(fp) + 41d8: 1885883a add r2,r3,r2 + 41dc: 10c1ffcc andi r3,r2,2047 + 41e0: e0bffc17 ldw r2,-16(fp) + 41e4: 10c00b15 stw r3,44(r2) + } + while (space > 0); + 41e8: e0bffe17 ldw r2,-8(fp) + 41ec: 00bfcf16 blt zero,r2,412c <__alt_data_end+0xfffe412c> + 41f0: 00000106 br 41f8 + n = in - out; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + + if (n == 0) + break; /* No more data available */ + 41f4: 0001883a nop + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + 41f8: e0fff517 ldw r3,-44(fp) + 41fc: e0bffd17 ldw r2,-12(fp) + 4200: 1880141e bne r3,r2,4254 + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + 4204: e0bfff17 ldw r2,-4(fp) + 4208: 1090000c andi r2,r2,16384 + 420c: 1000131e bne r2,zero,425c + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + 4210: 0001883a nop + 4214: e0bffc17 ldw r2,-16(fp) + 4218: 10c00a17 ldw r3,40(r2) + 421c: e0bff717 ldw r2,-36(fp) + 4220: 1880051e bne r3,r2,4238 + 4224: e0bffc17 ldw r2,-16(fp) + 4228: 10c00917 ldw r3,36(r2) + 422c: e0bffc17 ldw r2,-16(fp) + 4230: 10800117 ldw r2,4(r2) + 4234: 18bff736 bltu r3,r2,4214 <__alt_data_end+0xfffe4214> + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + 4238: e0bffc17 ldw r2,-16(fp) + 423c: 10c00a17 ldw r3,40(r2) + 4240: e0bff717 ldw r2,-36(fp) + 4244: 18800726 beq r3,r2,4264 + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + 4248: e0bffe17 ldw r2,-8(fp) + 424c: 00bfb716 blt zero,r2,412c <__alt_data_end+0xfffe412c> + 4250: 00000506 br 4268 + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + break; + 4254: 0001883a nop + 4258: 00000306 br 4268 + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + break; + 425c: 0001883a nop + 4260: 00000106 br 4268 + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + break; + 4264: 0001883a nop + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + 4268: e0fff517 ldw r3,-44(fp) + 426c: e0bffd17 ldw r2,-12(fp) + 4270: 18801826 beq r3,r2,42d4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 4274: 0005303a rdctl r2,status + 4278: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 427c: e0fffb17 ldw r3,-20(fp) + 4280: 00bfff84 movi r2,-2 + 4284: 1884703a and r2,r3,r2 + 4288: 1001703a wrctl status,r2 + + return context; + 428c: e0bffb17 ldw r2,-20(fp) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + 4290: e0bffa15 stw r2,-24(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 4294: e0bffc17 ldw r2,-16(fp) + 4298: 10800817 ldw r2,32(r2) + 429c: 10c00054 ori r3,r2,1 + 42a0: e0bffc17 ldw r2,-16(fp) + 42a4: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 42a8: e0bffc17 ldw r2,-16(fp) + 42ac: 10800017 ldw r2,0(r2) + 42b0: 10800104 addi r2,r2,4 + 42b4: 1007883a mov r3,r2 + 42b8: e0bffc17 ldw r2,-16(fp) + 42bc: 10800817 ldw r2,32(r2) + 42c0: 18800035 stwio r2,0(r3) + 42c4: e0bffa17 ldw r2,-24(fp) + 42c8: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 42cc: e0bff917 ldw r2,-28(fp) + 42d0: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + if (ptr != buffer) + 42d4: e0fff517 ldw r3,-44(fp) + 42d8: e0bffd17 ldw r2,-12(fp) + 42dc: 18800426 beq r3,r2,42f0 + return ptr - buffer; + 42e0: e0fff517 ldw r3,-44(fp) + 42e4: e0bffd17 ldw r2,-12(fp) + 42e8: 1885c83a sub r2,r3,r2 + 42ec: 00000606 br 4308 + else if (flags & O_NONBLOCK) + 42f0: e0bfff17 ldw r2,-4(fp) + 42f4: 1090000c andi r2,r2,16384 + 42f8: 10000226 beq r2,zero,4304 + return -EWOULDBLOCK; + 42fc: 00bffd44 movi r2,-11 + 4300: 00000106 br 4308 + else + return -EIO; + 4304: 00bffec4 movi r2,-5 +} + 4308: e037883a mov sp,fp + 430c: dfc00117 ldw ra,4(sp) + 4310: df000017 ldw fp,0(sp) + 4314: dec00204 addi sp,sp,8 + 4318: f800283a ret + +0000431c : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + 431c: defff304 addi sp,sp,-52 + 4320: dfc00c15 stw ra,48(sp) + 4324: df000b15 stw fp,44(sp) + 4328: df000b04 addi fp,sp,44 + 432c: e13ffc15 stw r4,-16(fp) + 4330: e17ffd15 stw r5,-12(fp) + 4334: e1bffe15 stw r6,-8(fp) + 4338: e1ffff15 stw r7,-4(fp) + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + 433c: e03ff515 stw zero,-44(fp) + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + 4340: e0bffd17 ldw r2,-12(fp) + 4344: e0bff715 stw r2,-36(fp) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 4348: 00003706 br 4428 + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + 434c: e0bffc17 ldw r2,-16(fp) + 4350: 10800c17 ldw r2,48(r2) + 4354: e0bff915 stw r2,-28(fp) + out = sp->tx_out; + 4358: e0bffc17 ldw r2,-16(fp) + 435c: 10800d17 ldw r2,52(r2) + 4360: e0bff515 stw r2,-44(fp) + + if (in < out) + 4364: e0fff917 ldw r3,-28(fp) + 4368: e0bff517 ldw r2,-44(fp) + 436c: 1880062e bgeu r3,r2,4388 + n = out - 1 - in; + 4370: e0fff517 ldw r3,-44(fp) + 4374: e0bff917 ldw r2,-28(fp) + 4378: 1885c83a sub r2,r3,r2 + 437c: 10bfffc4 addi r2,r2,-1 + 4380: e0bff615 stw r2,-40(fp) + 4384: 00000b06 br 43b4 + else if (out > 0) + 4388: e0bff517 ldw r2,-44(fp) + 438c: 10000526 beq r2,zero,43a4 + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + 4390: 00c20004 movi r3,2048 + 4394: e0bff917 ldw r2,-28(fp) + 4398: 1885c83a sub r2,r3,r2 + 439c: e0bff615 stw r2,-40(fp) + 43a0: 00000406 br 43b4 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + 43a4: 00c1ffc4 movi r3,2047 + 43a8: e0bff917 ldw r2,-28(fp) + 43ac: 1885c83a sub r2,r3,r2 + 43b0: e0bff615 stw r2,-40(fp) + + if (n == 0) + 43b4: e0bff617 ldw r2,-40(fp) + 43b8: 10001e26 beq r2,zero,4434 + break; + + if (n > count) + 43bc: e0fffe17 ldw r3,-8(fp) + 43c0: e0bff617 ldw r2,-40(fp) + 43c4: 1880022e bgeu r3,r2,43d0 + n = count; + 43c8: e0bffe17 ldw r2,-8(fp) + 43cc: e0bff615 stw r2,-40(fp) + + memcpy(sp->tx_buf + in, ptr, n); + 43d0: e0bffc17 ldw r2,-16(fp) + 43d4: 10c20e04 addi r3,r2,2104 + 43d8: e0bff917 ldw r2,-28(fp) + 43dc: 1885883a add r2,r3,r2 + 43e0: e1bff617 ldw r6,-40(fp) + 43e4: e17ffd17 ldw r5,-12(fp) + 43e8: 1009883a mov r4,r2 + 43ec: 000178c0 call 178c + ptr += n; + 43f0: e0fffd17 ldw r3,-12(fp) + 43f4: e0bff617 ldw r2,-40(fp) + 43f8: 1885883a add r2,r3,r2 + 43fc: e0bffd15 stw r2,-12(fp) + count -= n; + 4400: e0fffe17 ldw r3,-8(fp) + 4404: e0bff617 ldw r2,-40(fp) + 4408: 1885c83a sub r2,r3,r2 + 440c: e0bffe15 stw r2,-8(fp) + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 4410: e0fff917 ldw r3,-28(fp) + 4414: e0bff617 ldw r2,-40(fp) + 4418: 1885883a add r2,r3,r2 + 441c: 10c1ffcc andi r3,r2,2047 + 4420: e0bffc17 ldw r2,-16(fp) + 4424: 10c00c15 stw r3,48(r2) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 4428: e0bffe17 ldw r2,-8(fp) + 442c: 00bfc716 blt zero,r2,434c <__alt_data_end+0xfffe434c> + 4430: 00000106 br 4438 + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + + if (n == 0) + break; + 4434: 0001883a nop +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 4438: 0005303a rdctl r2,status + 443c: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4440: e0fffb17 ldw r3,-20(fp) + 4444: 00bfff84 movi r2,-2 + 4448: 1884703a and r2,r3,r2 + 444c: 1001703a wrctl status,r2 + + return context; + 4450: e0bffb17 ldw r2,-20(fp) + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + 4454: e0bffa15 stw r2,-24(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 4458: e0bffc17 ldw r2,-16(fp) + 445c: 10800817 ldw r2,32(r2) + 4460: 10c00094 ori r3,r2,2 + 4464: e0bffc17 ldw r2,-16(fp) + 4468: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 446c: e0bffc17 ldw r2,-16(fp) + 4470: 10800017 ldw r2,0(r2) + 4474: 10800104 addi r2,r2,4 + 4478: 1007883a mov r3,r2 + 447c: e0bffc17 ldw r2,-16(fp) + 4480: 10800817 ldw r2,32(r2) + 4484: 18800035 stwio r2,0(r3) + 4488: e0bffa17 ldw r2,-24(fp) + 448c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 4490: e0bff817 ldw r2,-32(fp) + 4494: 1001703a wrctl status,r2 + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + 4498: e0bffe17 ldw r2,-8(fp) + 449c: 0080100e bge zero,r2,44e0 + { + if (flags & O_NONBLOCK) + 44a0: e0bfff17 ldw r2,-4(fp) + 44a4: 1090000c andi r2,r2,16384 + 44a8: 1000101e bne r2,zero,44ec + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + 44ac: 0001883a nop + 44b0: e0bffc17 ldw r2,-16(fp) + 44b4: 10c00d17 ldw r3,52(r2) + 44b8: e0bff517 ldw r2,-44(fp) + 44bc: 1880051e bne r3,r2,44d4 + 44c0: e0bffc17 ldw r2,-16(fp) + 44c4: 10c00917 ldw r3,36(r2) + 44c8: e0bffc17 ldw r2,-16(fp) + 44cc: 10800117 ldw r2,4(r2) + 44d0: 18bff736 bltu r3,r2,44b0 <__alt_data_end+0xfffe44b0> + ; +#endif /* __ucosii__ */ + + if (sp->host_inactive) + 44d4: e0bffc17 ldw r2,-16(fp) + 44d8: 10800917 ldw r2,36(r2) + 44dc: 1000051e bne r2,zero,44f4 + break; + } + } + while (count > 0); + 44e0: e0bffe17 ldw r2,-8(fp) + 44e4: 00bfd016 blt zero,r2,4428 <__alt_data_end+0xfffe4428> + 44e8: 00000306 br 44f8 + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + { + if (flags & O_NONBLOCK) + break; + 44ec: 0001883a nop + 44f0: 00000106 br 44f8 + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (sp->host_inactive) + break; + 44f4: 0001883a nop + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + 44f8: e0fffd17 ldw r3,-12(fp) + 44fc: e0bff717 ldw r2,-36(fp) + 4500: 18800426 beq r3,r2,4514 + return ptr - start; + 4504: e0fffd17 ldw r3,-12(fp) + 4508: e0bff717 ldw r2,-36(fp) + 450c: 1885c83a sub r2,r3,r2 + 4510: 00000606 br 452c + else if (flags & O_NONBLOCK) + 4514: e0bfff17 ldw r2,-4(fp) + 4518: 1090000c andi r2,r2,16384 + 451c: 10000226 beq r2,zero,4528 + return -EWOULDBLOCK; + 4520: 00bffd44 movi r2,-11 + 4524: 00000106 br 452c + sp->tx_out = sp->tx_in = 0; + return ptr - start + count; + } +#endif + else + return -EIO; /* Host not connected */ + 4528: 00bffec4 movi r2,-5 +} + 452c: e037883a mov sp,fp + 4530: dfc00117 ldw ra,4(sp) + 4534: df000017 ldw fp,0(sp) + 4538: dec00204 addi sp,sp,8 + 453c: f800283a ret + +00004540 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + 4540: defffa04 addi sp,sp,-24 + 4544: dfc00515 stw ra,20(sp) + 4548: df000415 stw fp,16(sp) + 454c: df000404 addi fp,sp,16 + 4550: e13fff15 stw r4,-4(fp) + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + 4554: 0007883a mov r3,zero + 4558: e0bfff17 ldw r2,-4(fp) + 455c: 10c00035 stwio r3,0(r2) + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + 4560: e0bfff17 ldw r2,-4(fp) + 4564: 10800104 addi r2,r2,4 + 4568: 10800037 ldwio r2,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 456c: 0005303a rdctl r2,status + 4570: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4574: e0fffd17 ldw r3,-12(fp) + 4578: 00bfff84 movi r2,-2 + 457c: 1884703a and r2,r3,r2 + 4580: 1001703a wrctl status,r2 + + return context; + 4584: e0bffd17 ldw r2,-12(fp) + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + 4588: e0bffc15 stw r2,-16(fp) + alt_tick (); + 458c: 00050200 call 5020 + 4590: e0bffc17 ldw r2,-16(fp) + 4594: e0bffe15 stw r2,-8(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 4598: e0bffe17 ldw r2,-8(fp) + 459c: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); +} + 45a0: 0001883a nop + 45a4: e037883a mov sp,fp + 45a8: dfc00117 ldw ra,4(sp) + 45ac: df000017 ldw fp,0(sp) + 45b0: dec00204 addi sp,sp,8 + 45b4: f800283a ret + +000045b8 : + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + 45b8: defff804 addi sp,sp,-32 + 45bc: dfc00715 stw ra,28(sp) + 45c0: df000615 stw fp,24(sp) + 45c4: df000604 addi fp,sp,24 + 45c8: e13ffc15 stw r4,-16(fp) + 45cc: e17ffd15 stw r5,-12(fp) + 45d0: e1bffe15 stw r6,-8(fp) + 45d4: e1ffff15 stw r7,-4(fp) + 45d8: e0bfff17 ldw r2,-4(fp) + 45dc: e0bffb15 stw r2,-20(fp) + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + 45e0: d0a01617 ldw r2,-32680(gp) + 45e4: 1000021e bne r2,zero,45f0 + { + _alt_tick_rate = nticks; + 45e8: e0bffb17 ldw r2,-20(fp) + 45ec: d0a01615 stw r2,-32680(gp) + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + 45f0: e0bffc17 ldw r2,-16(fp) + 45f4: 10800104 addi r2,r2,4 + 45f8: 00c001c4 movi r3,7 + 45fc: 10c00035 stwio r3,0(r2) + ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | + ALTERA_AVALON_TIMER_CONTROL_START_MSK); + + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + 4600: d8000015 stw zero,0(sp) + 4604: e1fffc17 ldw r7,-16(fp) + 4608: 01800034 movhi r6,0 + 460c: 31915004 addi r6,r6,17728 + 4610: e17ffe17 ldw r5,-8(fp) + 4614: e13ffd17 ldw r4,-12(fp) + 4618: 00049000 call 4900 + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); +#endif +} + 461c: 0001883a nop + 4620: e037883a mov sp,fp + 4624: dfc00117 ldw ra,4(sp) + 4628: df000017 ldw fp,0(sp) + 462c: dec00204 addi sp,sp,8 + 4630: f800283a ret + +00004634 : + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + 4634: defff504 addi sp,sp,-44 + 4638: df000a15 stw fp,40(sp) + 463c: df000a04 addi fp,sp,40 + 4640: e13ffc15 stw r4,-16(fp) + 4644: e17ffd15 stw r5,-12(fp) + 4648: e1bffe15 stw r6,-8(fp) + 464c: e1ffff15 stw r7,-4(fp) + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + 4650: e03ff615 stw zero,-40(fp) + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 4654: d0a01617 ldw r2,-32680(gp) + + if (alt_ticks_per_second ()) + 4658: 10003c26 beq r2,zero,474c + { + if (alarm) + 465c: e0bffc17 ldw r2,-16(fp) + 4660: 10003826 beq r2,zero,4744 + { + alarm->callback = callback; + 4664: e0bffc17 ldw r2,-16(fp) + 4668: e0fffe17 ldw r3,-8(fp) + 466c: 10c00315 stw r3,12(r2) + alarm->context = context; + 4670: e0bffc17 ldw r2,-16(fp) + 4674: e0ffff17 ldw r3,-4(fp) + 4678: 10c00515 stw r3,20(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 467c: 0005303a rdctl r2,status + 4680: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4684: e0fff917 ldw r3,-28(fp) + 4688: 00bfff84 movi r2,-2 + 468c: 1884703a and r2,r3,r2 + 4690: 1001703a wrctl status,r2 + + return context; + 4694: e0bff917 ldw r2,-28(fp) + + irq_context = alt_irq_disable_all (); + 4698: e0bff815 stw r2,-32(fp) + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; + 469c: d0a01717 ldw r2,-32676(gp) + + current_nticks = alt_nticks(); + 46a0: e0bff615 stw r2,-40(fp) + + alarm->time = nticks + current_nticks + 1; + 46a4: e0fffd17 ldw r3,-12(fp) + 46a8: e0bff617 ldw r2,-40(fp) + 46ac: 1885883a add r2,r3,r2 + 46b0: 10c00044 addi r3,r2,1 + 46b4: e0bffc17 ldw r2,-16(fp) + 46b8: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + 46bc: e0bffc17 ldw r2,-16(fp) + 46c0: 10c00217 ldw r3,8(r2) + 46c4: e0bff617 ldw r2,-40(fp) + 46c8: 1880042e bgeu r3,r2,46dc + { + alarm->rollover = 1; + 46cc: e0bffc17 ldw r2,-16(fp) + 46d0: 00c00044 movi r3,1 + 46d4: 10c00405 stb r3,16(r2) + 46d8: 00000206 br 46e4 + } + else + { + alarm->rollover = 0; + 46dc: e0bffc17 ldw r2,-16(fp) + 46e0: 10000405 stb zero,16(r2) + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + 46e4: e0bffc17 ldw r2,-16(fp) + 46e8: d0e00c04 addi r3,gp,-32720 + 46ec: e0fffa15 stw r3,-24(fp) + 46f0: e0bffb15 stw r2,-20(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 46f4: e0bffb17 ldw r2,-20(fp) + 46f8: e0fffa17 ldw r3,-24(fp) + 46fc: 10c00115 stw r3,4(r2) + entry->next = list->next; + 4700: e0bffa17 ldw r2,-24(fp) + 4704: 10c00017 ldw r3,0(r2) + 4708: e0bffb17 ldw r2,-20(fp) + 470c: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 4710: e0bffa17 ldw r2,-24(fp) + 4714: 10800017 ldw r2,0(r2) + 4718: e0fffb17 ldw r3,-20(fp) + 471c: 10c00115 stw r3,4(r2) + list->next = entry; + 4720: e0bffa17 ldw r2,-24(fp) + 4724: e0fffb17 ldw r3,-20(fp) + 4728: 10c00015 stw r3,0(r2) + 472c: e0bff817 ldw r2,-32(fp) + 4730: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 4734: e0bff717 ldw r2,-36(fp) + 4738: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); + + return 0; + 473c: 0005883a mov r2,zero + 4740: 00000306 br 4750 + } + else + { + return -EINVAL; + 4744: 00bffa84 movi r2,-22 + 4748: 00000106 br 4750 + } + } + else + { + return -ENOTSUP; + 474c: 00bfde84 movi r2,-134 + } +} + 4750: e037883a mov sp,fp + 4754: df000017 ldw fp,0(sp) + 4758: dec00104 addi sp,sp,4 + 475c: f800283a ret + +00004760 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 4760: defffe04 addi sp,sp,-8 + 4764: dfc00115 stw ra,4(sp) + 4768: df000015 stw fp,0(sp) + 476c: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 4770: d0a00917 ldw r2,-32732(gp) + 4774: 10000326 beq r2,zero,4784 + 4778: d0a00917 ldw r2,-32732(gp) + 477c: 103ee83a callr r2 + 4780: 00000106 br 4788 + 4784: d0a01104 addi r2,gp,-32700 +} + 4788: e037883a mov sp,fp + 478c: dfc00117 ldw ra,4(sp) + 4790: df000017 ldw fp,0(sp) + 4794: dec00204 addi sp,sp,8 + 4798: f800283a ret + +0000479c : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + 479c: defffa04 addi sp,sp,-24 + 47a0: dfc00515 stw ra,20(sp) + 47a4: df000415 stw fp,16(sp) + 47a8: df000404 addi fp,sp,16 + 47ac: e13ffe15 stw r4,-8(fp) + 47b0: e17fff15 stw r5,-4(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + 47b4: e0bffe17 ldw r2,-8(fp) + 47b8: 10000326 beq r2,zero,47c8 + 47bc: e0bffe17 ldw r2,-8(fp) + 47c0: 10800217 ldw r2,8(r2) + 47c4: 1000061e bne r2,zero,47e0 + { + ALT_ERRNO = EINVAL; + 47c8: 00047600 call 4760 + 47cc: 1007883a mov r3,r2 + 47d0: 00800584 movi r2,22 + 47d4: 18800015 stw r2,0(r3) + return -EINVAL; + 47d8: 00bffa84 movi r2,-22 + 47dc: 00001306 br 482c + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + 47e0: e0bffe17 ldw r2,-8(fp) + 47e4: e0ffff17 ldw r3,-4(fp) + 47e8: e0fffc15 stw r3,-16(fp) + 47ec: e0bffd15 stw r2,-12(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 47f0: e0bffd17 ldw r2,-12(fp) + 47f4: e0fffc17 ldw r3,-16(fp) + 47f8: 10c00115 stw r3,4(r2) + entry->next = list->next; + 47fc: e0bffc17 ldw r2,-16(fp) + 4800: 10c00017 ldw r3,0(r2) + 4804: e0bffd17 ldw r2,-12(fp) + 4808: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 480c: e0bffc17 ldw r2,-16(fp) + 4810: 10800017 ldw r2,0(r2) + 4814: e0fffd17 ldw r3,-12(fp) + 4818: 10c00115 stw r3,4(r2) + list->next = entry; + 481c: e0bffc17 ldw r2,-16(fp) + 4820: e0fffd17 ldw r3,-12(fp) + 4824: 10c00015 stw r3,0(r2) + + return 0; + 4828: 0005883a mov r2,zero +} + 482c: e037883a mov sp,fp + 4830: dfc00117 ldw ra,4(sp) + 4834: df000017 ldw fp,0(sp) + 4838: dec00204 addi sp,sp,8 + 483c: f800283a ret + +00004840 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + 4840: defffd04 addi sp,sp,-12 + 4844: dfc00215 stw ra,8(sp) + 4848: df000115 stw fp,4(sp) + 484c: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 4850: 00800034 movhi r2,0 + 4854: 1095f504 addi r2,r2,22484 + 4858: e0bfff15 stw r2,-4(fp) + 485c: 00000606 br 4878 <_do_ctors+0x38> + (*ctor) (); + 4860: e0bfff17 ldw r2,-4(fp) + 4864: 10800017 ldw r2,0(r2) + 4868: 103ee83a callr r2 + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 486c: e0bfff17 ldw r2,-4(fp) + 4870: 10bfff04 addi r2,r2,-4 + 4874: e0bfff15 stw r2,-4(fp) + 4878: e0ffff17 ldw r3,-4(fp) + 487c: 00800034 movhi r2,0 + 4880: 1095f604 addi r2,r2,22488 + 4884: 18bff62e bgeu r3,r2,4860 <__alt_data_end+0xfffe4860> + (*ctor) (); +} + 4888: 0001883a nop + 488c: e037883a mov sp,fp + 4890: dfc00117 ldw ra,4(sp) + 4894: df000017 ldw fp,0(sp) + 4898: dec00204 addi sp,sp,8 + 489c: f800283a ret + +000048a0 <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + 48a0: defffd04 addi sp,sp,-12 + 48a4: dfc00215 stw ra,8(sp) + 48a8: df000115 stw fp,4(sp) + 48ac: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 48b0: 00800034 movhi r2,0 + 48b4: 1095f504 addi r2,r2,22484 + 48b8: e0bfff15 stw r2,-4(fp) + 48bc: 00000606 br 48d8 <_do_dtors+0x38> + (*dtor) (); + 48c0: e0bfff17 ldw r2,-4(fp) + 48c4: 10800017 ldw r2,0(r2) + 48c8: 103ee83a callr r2 + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 48cc: e0bfff17 ldw r2,-4(fp) + 48d0: 10bfff04 addi r2,r2,-4 + 48d4: e0bfff15 stw r2,-4(fp) + 48d8: e0ffff17 ldw r3,-4(fp) + 48dc: 00800034 movhi r2,0 + 48e0: 1095f604 addi r2,r2,22488 + 48e4: 18bff62e bgeu r3,r2,48c0 <__alt_data_end+0xfffe48c0> + (*dtor) (); +} + 48e8: 0001883a nop + 48ec: e037883a mov sp,fp + 48f0: dfc00117 ldw ra,4(sp) + 48f4: df000017 ldw fp,0(sp) + 48f8: dec00204 addi sp,sp,8 + 48fc: f800283a ret + +00004900 : + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + 4900: defff904 addi sp,sp,-28 + 4904: dfc00615 stw ra,24(sp) + 4908: df000515 stw fp,20(sp) + 490c: df000504 addi fp,sp,20 + 4910: e13ffc15 stw r4,-16(fp) + 4914: e17ffd15 stw r5,-12(fp) + 4918: e1bffe15 stw r6,-8(fp) + 491c: e1ffff15 stw r7,-4(fp) + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); + 4920: e0800217 ldw r2,8(fp) + 4924: d8800015 stw r2,0(sp) + 4928: e1ffff17 ldw r7,-4(fp) + 492c: e1bffe17 ldw r6,-8(fp) + 4930: e17ffd17 ldw r5,-12(fp) + 4934: e13ffc17 ldw r4,-16(fp) + 4938: 0004ab00 call 4ab0 +} + 493c: e037883a mov sp,fp + 4940: dfc00117 ldw ra,4(sp) + 4944: df000017 ldw fp,0(sp) + 4948: dec00204 addi sp,sp,8 + 494c: f800283a ret + +00004950 : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + 4950: defff904 addi sp,sp,-28 + 4954: df000615 stw fp,24(sp) + 4958: df000604 addi fp,sp,24 + 495c: e13ffe15 stw r4,-8(fp) + 4960: e17fff15 stw r5,-4(fp) + 4964: e0bfff17 ldw r2,-4(fp) + 4968: e0bffa15 stw r2,-24(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 496c: 0005303a rdctl r2,status + 4970: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4974: e0fffb17 ldw r3,-20(fp) + 4978: 00bfff84 movi r2,-2 + 497c: 1884703a and r2,r3,r2 + 4980: 1001703a wrctl status,r2 + + return context; + 4984: e0bffb17 ldw r2,-20(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 4988: e0bffc15 stw r2,-16(fp) + + alt_irq_active |= (1 << id); + 498c: 00c00044 movi r3,1 + 4990: e0bffa17 ldw r2,-24(fp) + 4994: 1884983a sll r2,r3,r2 + 4998: 1007883a mov r3,r2 + 499c: d0a01517 ldw r2,-32684(gp) + 49a0: 1884b03a or r2,r3,r2 + 49a4: d0a01515 stw r2,-32684(gp) + NIOS2_WRITE_IENABLE (alt_irq_active); + 49a8: d0a01517 ldw r2,-32684(gp) + 49ac: 100170fa wrctl ienable,r2 + 49b0: e0bffc17 ldw r2,-16(fp) + 49b4: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 49b8: e0bffd17 ldw r2,-12(fp) + 49bc: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 49c0: 0005883a mov r2,zero + return alt_irq_enable(irq); + 49c4: 0001883a nop +} + 49c8: e037883a mov sp,fp + 49cc: df000017 ldw fp,0(sp) + 49d0: dec00104 addi sp,sp,4 + 49d4: f800283a ret + +000049d8 : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + 49d8: defff904 addi sp,sp,-28 + 49dc: df000615 stw fp,24(sp) + 49e0: df000604 addi fp,sp,24 + 49e4: e13ffe15 stw r4,-8(fp) + 49e8: e17fff15 stw r5,-4(fp) + 49ec: e0bfff17 ldw r2,-4(fp) + 49f0: e0bffa15 stw r2,-24(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 49f4: 0005303a rdctl r2,status + 49f8: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 49fc: e0fffb17 ldw r3,-20(fp) + 4a00: 00bfff84 movi r2,-2 + 4a04: 1884703a and r2,r3,r2 + 4a08: 1001703a wrctl status,r2 + + return context; + 4a0c: e0bffb17 ldw r2,-20(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 4a10: e0bffc15 stw r2,-16(fp) + + alt_irq_active &= ~(1 << id); + 4a14: 00c00044 movi r3,1 + 4a18: e0bffa17 ldw r2,-24(fp) + 4a1c: 1884983a sll r2,r3,r2 + 4a20: 0084303a nor r2,zero,r2 + 4a24: 1007883a mov r3,r2 + 4a28: d0a01517 ldw r2,-32684(gp) + 4a2c: 1884703a and r2,r3,r2 + 4a30: d0a01515 stw r2,-32684(gp) + NIOS2_WRITE_IENABLE (alt_irq_active); + 4a34: d0a01517 ldw r2,-32684(gp) + 4a38: 100170fa wrctl ienable,r2 + 4a3c: e0bffc17 ldw r2,-16(fp) + 4a40: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 4a44: e0bffd17 ldw r2,-12(fp) + 4a48: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 4a4c: 0005883a mov r2,zero + return alt_irq_disable(irq); + 4a50: 0001883a nop +} + 4a54: e037883a mov sp,fp + 4a58: df000017 ldw fp,0(sp) + 4a5c: dec00104 addi sp,sp,4 + 4a60: f800283a ret + +00004a64 : + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + 4a64: defffc04 addi sp,sp,-16 + 4a68: df000315 stw fp,12(sp) + 4a6c: df000304 addi fp,sp,12 + 4a70: e13ffe15 stw r4,-8(fp) + 4a74: e17fff15 stw r5,-4(fp) + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + 4a78: 000530fa rdctl r2,ienable + 4a7c: e0bffd15 stw r2,-12(fp) + + return (irq_enabled & (1 << irq)) ? 1: 0; + 4a80: 00c00044 movi r3,1 + 4a84: e0bfff17 ldw r2,-4(fp) + 4a88: 1884983a sll r2,r3,r2 + 4a8c: 1007883a mov r3,r2 + 4a90: e0bffd17 ldw r2,-12(fp) + 4a94: 1884703a and r2,r3,r2 + 4a98: 1004c03a cmpne r2,r2,zero + 4a9c: 10803fcc andi r2,r2,255 +} + 4aa0: e037883a mov sp,fp + 4aa4: df000017 ldw fp,0(sp) + 4aa8: dec00104 addi sp,sp,4 + 4aac: f800283a ret + +00004ab0 : + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + 4ab0: defff504 addi sp,sp,-44 + 4ab4: dfc00a15 stw ra,40(sp) + 4ab8: df000915 stw fp,36(sp) + 4abc: df000904 addi fp,sp,36 + 4ac0: e13ffc15 stw r4,-16(fp) + 4ac4: e17ffd15 stw r5,-12(fp) + 4ac8: e1bffe15 stw r6,-8(fp) + 4acc: e1ffff15 stw r7,-4(fp) + int rc = -EINVAL; + 4ad0: 00bffa84 movi r2,-22 + 4ad4: e0bff715 stw r2,-36(fp) + int id = irq; /* IRQ interpreted as the interrupt ID. */ + 4ad8: e0bffd17 ldw r2,-12(fp) + 4adc: e0bff815 stw r2,-32(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + 4ae0: e0bff817 ldw r2,-32(fp) + 4ae4: 10800808 cmpgei r2,r2,32 + 4ae8: 1000271e bne r2,zero,4b88 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 4aec: 0005303a rdctl r2,status + 4af0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4af4: e0fffb17 ldw r3,-20(fp) + 4af8: 00bfff84 movi r2,-2 + 4afc: 1884703a and r2,r3,r2 + 4b00: 1001703a wrctl status,r2 + + return context; + 4b04: e0bffb17 ldw r2,-20(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + 4b08: e0bffa15 stw r2,-24(fp) + + alt_irq[id].handler = isr; + 4b0c: 00800034 movhi r2,0 + 4b10: 109cb904 addi r2,r2,29412 + 4b14: e0fff817 ldw r3,-32(fp) + 4b18: 180690fa slli r3,r3,3 + 4b1c: 10c5883a add r2,r2,r3 + 4b20: e0fffe17 ldw r3,-8(fp) + 4b24: 10c00015 stw r3,0(r2) + alt_irq[id].context = isr_context; + 4b28: 00800034 movhi r2,0 + 4b2c: 109cb904 addi r2,r2,29412 + 4b30: e0fff817 ldw r3,-32(fp) + 4b34: 180690fa slli r3,r3,3 + 4b38: 10c5883a add r2,r2,r3 + 4b3c: 10800104 addi r2,r2,4 + 4b40: e0ffff17 ldw r3,-4(fp) + 4b44: 10c00015 stw r3,0(r2) + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + 4b48: e0bffe17 ldw r2,-8(fp) + 4b4c: 10000526 beq r2,zero,4b64 + 4b50: e0bff817 ldw r2,-32(fp) + 4b54: 100b883a mov r5,r2 + 4b58: e13ffc17 ldw r4,-16(fp) + 4b5c: 00049500 call 4950 + 4b60: 00000406 br 4b74 + 4b64: e0bff817 ldw r2,-32(fp) + 4b68: 100b883a mov r5,r2 + 4b6c: e13ffc17 ldw r4,-16(fp) + 4b70: 00049d80 call 49d8 + 4b74: e0bff715 stw r2,-36(fp) + 4b78: e0bffa17 ldw r2,-24(fp) + 4b7c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 4b80: e0bff917 ldw r2,-28(fp) + 4b84: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + + return rc; + 4b88: e0bff717 ldw r2,-36(fp) +} + 4b8c: e037883a mov sp,fp + 4b90: dfc00117 ldw ra,4(sp) + 4b94: df000017 ldw fp,0(sp) + 4b98: dec00204 addi sp,sp,8 + 4b9c: f800283a ret + +00004ba0 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + 4ba0: defff804 addi sp,sp,-32 + 4ba4: dfc00715 stw ra,28(sp) + 4ba8: df000615 stw fp,24(sp) + 4bac: dc000515 stw r16,20(sp) + 4bb0: df000604 addi fp,sp,24 + 4bb4: e13ffb15 stw r4,-20(fp) + 4bb8: e17ffc15 stw r5,-16(fp) + 4bbc: e1bffd15 stw r6,-12(fp) + 4bc0: e1fffe15 stw r7,-8(fp) + int old; + + old = open (name, flags, mode); + 4bc4: e1bffe17 ldw r6,-8(fp) + 4bc8: e17ffd17 ldw r5,-12(fp) + 4bcc: e13ffc17 ldw r4,-16(fp) + 4bd0: 0004e280 call 4e28 + 4bd4: e0bffa15 stw r2,-24(fp) + + if (old >= 0) + 4bd8: e0bffa17 ldw r2,-24(fp) + 4bdc: 10002216 blt r2,zero,4c68 + { + fd->dev = alt_fd_list[old].dev; + 4be0: 04000034 movhi r16,0 + 4be4: 84181e04 addi r16,r16,24696 + 4be8: e0bffa17 ldw r2,-24(fp) + 4bec: 01400304 movi r5,12 + 4bf0: 1009883a mov r4,r2 + 4bf4: 00031140 call 3114 <__mulsi3> + 4bf8: 8085883a add r2,r16,r2 + 4bfc: 10c00017 ldw r3,0(r2) + 4c00: e0bffb17 ldw r2,-20(fp) + 4c04: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + 4c08: 04000034 movhi r16,0 + 4c0c: 84181e04 addi r16,r16,24696 + 4c10: e0bffa17 ldw r2,-24(fp) + 4c14: 01400304 movi r5,12 + 4c18: 1009883a mov r4,r2 + 4c1c: 00031140 call 3114 <__mulsi3> + 4c20: 8085883a add r2,r16,r2 + 4c24: 10800104 addi r2,r2,4 + 4c28: 10c00017 ldw r3,0(r2) + 4c2c: e0bffb17 ldw r2,-20(fp) + 4c30: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + 4c34: 04000034 movhi r16,0 + 4c38: 84181e04 addi r16,r16,24696 + 4c3c: e0bffa17 ldw r2,-24(fp) + 4c40: 01400304 movi r5,12 + 4c44: 1009883a mov r4,r2 + 4c48: 00031140 call 3114 <__mulsi3> + 4c4c: 8085883a add r2,r16,r2 + 4c50: 10800204 addi r2,r2,8 + 4c54: 10c00017 ldw r3,0(r2) + 4c58: e0bffb17 ldw r2,-20(fp) + 4c5c: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + 4c60: e13ffa17 ldw r4,-24(fp) + 4c64: 000379c0 call 379c + } +} + 4c68: 0001883a nop + 4c6c: e6ffff04 addi sp,fp,-4 + 4c70: dfc00217 ldw ra,8(sp) + 4c74: df000117 ldw fp,4(sp) + 4c78: dc000017 ldw r16,0(sp) + 4c7c: dec00304 addi sp,sp,12 + 4c80: f800283a ret + +00004c84 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + 4c84: defffb04 addi sp,sp,-20 + 4c88: dfc00415 stw ra,16(sp) + 4c8c: df000315 stw fp,12(sp) + 4c90: df000304 addi fp,sp,12 + 4c94: e13ffd15 stw r4,-12(fp) + 4c98: e17ffe15 stw r5,-8(fp) + 4c9c: e1bfff15 stw r6,-4(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + 4ca0: 01c07fc4 movi r7,511 + 4ca4: 01800044 movi r6,1 + 4ca8: e17ffd17 ldw r5,-12(fp) + 4cac: 01000034 movhi r4,0 + 4cb0: 21182104 addi r4,r4,24708 + 4cb4: 0004ba00 call 4ba0 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + 4cb8: 01c07fc4 movi r7,511 + 4cbc: 000d883a mov r6,zero + 4cc0: e17ffe17 ldw r5,-8(fp) + 4cc4: 01000034 movhi r4,0 + 4cc8: 21181e04 addi r4,r4,24696 + 4ccc: 0004ba00 call 4ba0 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + 4cd0: 01c07fc4 movi r7,511 + 4cd4: 01800044 movi r6,1 + 4cd8: e17fff17 ldw r5,-4(fp) + 4cdc: 01000034 movhi r4,0 + 4ce0: 21182404 addi r4,r4,24720 + 4ce4: 0004ba00 call 4ba0 +} + 4ce8: 0001883a nop + 4cec: e037883a mov sp,fp + 4cf0: dfc00117 ldw ra,4(sp) + 4cf4: df000017 ldw fp,0(sp) + 4cf8: dec00204 addi sp,sp,8 + 4cfc: f800283a ret + +00004d00 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 4d00: defffe04 addi sp,sp,-8 + 4d04: dfc00115 stw ra,4(sp) + 4d08: df000015 stw fp,0(sp) + 4d0c: d839883a mov fp,sp + return ((alt_errno) ? alt_errno() : &errno); + 4d10: d0a00917 ldw r2,-32732(gp) + 4d14: 10000326 beq r2,zero,4d24 + 4d18: d0a00917 ldw r2,-32732(gp) + 4d1c: 103ee83a callr r2 + 4d20: 00000106 br 4d28 + 4d24: d0a01104 addi r2,gp,-32700 +} + 4d28: e037883a mov sp,fp + 4d2c: dfc00117 ldw ra,4(sp) + 4d30: df000017 ldw fp,0(sp) + 4d34: dec00204 addi sp,sp,8 + 4d38: f800283a ret + +00004d3c : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + 4d3c: defffb04 addi sp,sp,-20 + 4d40: dfc00415 stw ra,16(sp) + 4d44: df000315 stw fp,12(sp) + 4d48: dc000215 stw r16,8(sp) + 4d4c: df000304 addi fp,sp,12 + 4d50: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + 4d54: e0bffe17 ldw r2,-8(fp) + 4d58: 10800217 ldw r2,8(r2) + 4d5c: 10d00034 orhi r3,r2,16384 + 4d60: e0bffe17 ldw r2,-8(fp) + 4d64: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 4d68: e03ffd15 stw zero,-12(fp) + 4d6c: 00002306 br 4dfc + { + if ((alt_fd_list[i].dev == fd->dev) && + 4d70: 04000034 movhi r16,0 + 4d74: 84181e04 addi r16,r16,24696 + 4d78: e0bffd17 ldw r2,-12(fp) + 4d7c: 01400304 movi r5,12 + 4d80: 1009883a mov r4,r2 + 4d84: 00031140 call 3114 <__mulsi3> + 4d88: 8085883a add r2,r16,r2 + 4d8c: 10c00017 ldw r3,0(r2) + 4d90: e0bffe17 ldw r2,-8(fp) + 4d94: 10800017 ldw r2,0(r2) + 4d98: 1880151e bne r3,r2,4df0 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + 4d9c: 04000034 movhi r16,0 + 4da0: 84181e04 addi r16,r16,24696 + 4da4: e0bffd17 ldw r2,-12(fp) + 4da8: 01400304 movi r5,12 + 4dac: 1009883a mov r4,r2 + 4db0: 00031140 call 3114 <__mulsi3> + 4db4: 8085883a add r2,r16,r2 + 4db8: 10800204 addi r2,r2,8 + 4dbc: 10800017 ldw r2,0(r2) + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + 4dc0: 10000b0e bge r2,zero,4df0 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + 4dc4: 01400304 movi r5,12 + 4dc8: e13ffd17 ldw r4,-12(fp) + 4dcc: 00031140 call 3114 <__mulsi3> + 4dd0: 1007883a mov r3,r2 + 4dd4: 00800034 movhi r2,0 + 4dd8: 10981e04 addi r2,r2,24696 + 4ddc: 1887883a add r3,r3,r2 + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + 4de0: e0bffe17 ldw r2,-8(fp) + 4de4: 18800226 beq r3,r2,4df0 + (&alt_fd_list[i] != fd)) + { + return -EACCES; + 4de8: 00bffcc4 movi r2,-13 + 4dec: 00000806 br 4e10 + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 4df0: e0bffd17 ldw r2,-12(fp) + 4df4: 10800044 addi r2,r2,1 + 4df8: e0bffd15 stw r2,-12(fp) + 4dfc: d0a00817 ldw r2,-32736(gp) + 4e00: 1007883a mov r3,r2 + 4e04: e0bffd17 ldw r2,-12(fp) + 4e08: 18bfd92e bgeu r3,r2,4d70 <__alt_data_end+0xfffe4d70> + } + } + + /* The device is not locked */ + + return 0; + 4e0c: 0005883a mov r2,zero +} + 4e10: e6ffff04 addi sp,fp,-4 + 4e14: dfc00217 ldw ra,8(sp) + 4e18: df000117 ldw fp,4(sp) + 4e1c: dc000017 ldw r16,0(sp) + 4e20: dec00304 addi sp,sp,12 + 4e24: f800283a ret + +00004e28 : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + 4e28: defff604 addi sp,sp,-40 + 4e2c: dfc00915 stw ra,36(sp) + 4e30: df000815 stw fp,32(sp) + 4e34: df000804 addi fp,sp,32 + 4e38: e13ffd15 stw r4,-12(fp) + 4e3c: e17ffe15 stw r5,-8(fp) + 4e40: e1bfff15 stw r6,-4(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + 4e44: 00bfffc4 movi r2,-1 + 4e48: e0bff915 stw r2,-28(fp) + int status = -ENODEV; + 4e4c: 00bffb44 movi r2,-19 + 4e50: e0bffa15 stw r2,-24(fp) + int isafs = 0; + 4e54: e03ffb15 stw zero,-20(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + 4e58: d1600604 addi r5,gp,-32744 + 4e5c: e13ffd17 ldw r4,-12(fp) + 4e60: 000514c0 call 514c + 4e64: e0bff815 stw r2,-32(fp) + 4e68: e0bff817 ldw r2,-32(fp) + 4e6c: 1000051e bne r2,zero,4e84 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + 4e70: e13ffd17 ldw r4,-12(fp) + 4e74: 00051dc0 call 51dc + 4e78: e0bff815 stw r2,-32(fp) + isafs = 1; + 4e7c: 00800044 movi r2,1 + 4e80: e0bffb15 stw r2,-20(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + 4e84: e0bff817 ldw r2,-32(fp) + 4e88: 10002b26 beq r2,zero,4f38 + { + if ((index = alt_get_fd (dev)) < 0) + 4e8c: e13ff817 ldw r4,-32(fp) + 4e90: 00052e40 call 52e4 + 4e94: e0bff915 stw r2,-28(fp) + 4e98: e0bff917 ldw r2,-28(fp) + 4e9c: 1000030e bge r2,zero,4eac + { + status = index; + 4ea0: e0bff917 ldw r2,-28(fp) + 4ea4: e0bffa15 stw r2,-24(fp) + 4ea8: 00002506 br 4f40 + } + else + { + fd = &alt_fd_list[index]; + 4eac: 01400304 movi r5,12 + 4eb0: e13ff917 ldw r4,-28(fp) + 4eb4: 00031140 call 3114 <__mulsi3> + 4eb8: 1007883a mov r3,r2 + 4ebc: 00800034 movhi r2,0 + 4ec0: 10981e04 addi r2,r2,24696 + 4ec4: 1885883a add r2,r3,r2 + 4ec8: e0bffc15 stw r2,-16(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + 4ecc: e0fffe17 ldw r3,-8(fp) + 4ed0: 00900034 movhi r2,16384 + 4ed4: 10bfffc4 addi r2,r2,-1 + 4ed8: 1886703a and r3,r3,r2 + 4edc: e0bffc17 ldw r2,-16(fp) + 4ee0: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + 4ee4: e0bffb17 ldw r2,-20(fp) + 4ee8: 1000051e bne r2,zero,4f00 + 4eec: e13ffc17 ldw r4,-16(fp) + 4ef0: 0004d3c0 call 4d3c + 4ef4: e0bffa15 stw r2,-24(fp) + 4ef8: e0bffa17 ldw r2,-24(fp) + 4efc: 10001016 blt r2,zero,4f40 + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + 4f00: e0bff817 ldw r2,-32(fp) + 4f04: 10800317 ldw r2,12(r2) + 4f08: 10000826 beq r2,zero,4f2c + 4f0c: e0bff817 ldw r2,-32(fp) + 4f10: 10800317 ldw r2,12(r2) + 4f14: e1ffff17 ldw r7,-4(fp) + 4f18: e1bffe17 ldw r6,-8(fp) + 4f1c: e17ffd17 ldw r5,-12(fp) + 4f20: e13ffc17 ldw r4,-16(fp) + 4f24: 103ee83a callr r2 + 4f28: 00000106 br 4f30 + 4f2c: 0005883a mov r2,zero + 4f30: e0bffa15 stw r2,-24(fp) + 4f34: 00000206 br 4f40 + } + } + } + else + { + status = -ENODEV; + 4f38: 00bffb44 movi r2,-19 + 4f3c: e0bffa15 stw r2,-24(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + 4f40: e0bffa17 ldw r2,-24(fp) + 4f44: 1000090e bge r2,zero,4f6c + { + alt_release_fd (index); + 4f48: e13ff917 ldw r4,-28(fp) + 4f4c: 000379c0 call 379c + ALT_ERRNO = -status; + 4f50: 0004d000 call 4d00 + 4f54: 1007883a mov r3,r2 + 4f58: e0bffa17 ldw r2,-24(fp) + 4f5c: 0085c83a sub r2,zero,r2 + 4f60: 18800015 stw r2,0(r3) + return -1; + 4f64: 00bfffc4 movi r2,-1 + 4f68: 00000106 br 4f70 + } + + /* return the reference upon success */ + + return index; + 4f6c: e0bff917 ldw r2,-28(fp) +} + 4f70: e037883a mov sp,fp + 4f74: dfc00117 ldw ra,4(sp) + 4f78: df000017 ldw fp,0(sp) + 4f7c: dec00204 addi sp,sp,8 + 4f80: f800283a ret + +00004f84 : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + 4f84: defffa04 addi sp,sp,-24 + 4f88: df000515 stw fp,20(sp) + 4f8c: df000504 addi fp,sp,20 + 4f90: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 4f94: 0005303a rdctl r2,status + 4f98: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 4f9c: e0fffc17 ldw r3,-16(fp) + 4fa0: 00bfff84 movi r2,-2 + 4fa4: 1884703a and r2,r3,r2 + 4fa8: 1001703a wrctl status,r2 + + return context; + 4fac: e0bffc17 ldw r2,-16(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + 4fb0: e0bffb15 stw r2,-20(fp) + alt_llist_remove (&alarm->llist); + 4fb4: e0bfff17 ldw r2,-4(fp) + 4fb8: e0bffd15 stw r2,-12(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + 4fbc: e0bffd17 ldw r2,-12(fp) + 4fc0: 10800017 ldw r2,0(r2) + 4fc4: e0fffd17 ldw r3,-12(fp) + 4fc8: 18c00117 ldw r3,4(r3) + 4fcc: 10c00115 stw r3,4(r2) + entry->previous->next = entry->next; + 4fd0: e0bffd17 ldw r2,-12(fp) + 4fd4: 10800117 ldw r2,4(r2) + 4fd8: e0fffd17 ldw r3,-12(fp) + 4fdc: 18c00017 ldw r3,0(r3) + 4fe0: 10c00015 stw r3,0(r2) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + 4fe4: e0bffd17 ldw r2,-12(fp) + 4fe8: e0fffd17 ldw r3,-12(fp) + 4fec: 10c00115 stw r3,4(r2) + entry->next = entry; + 4ff0: e0bffd17 ldw r2,-12(fp) + 4ff4: e0fffd17 ldw r3,-12(fp) + 4ff8: 10c00015 stw r3,0(r2) + 4ffc: e0bffb17 ldw r2,-20(fp) + 5000: e0bffe15 stw r2,-8(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 5004: e0bffe17 ldw r2,-8(fp) + 5008: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + 500c: 0001883a nop + 5010: e037883a mov sp,fp + 5014: df000017 ldw fp,0(sp) + 5018: dec00104 addi sp,sp,4 + 501c: f800283a ret + +00005020 : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + 5020: defffb04 addi sp,sp,-20 + 5024: dfc00415 stw ra,16(sp) + 5028: df000315 stw fp,12(sp) + 502c: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + 5030: d0a00c17 ldw r2,-32720(gp) + 5034: e0bffd15 stw r2,-12(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + 5038: d0a01717 ldw r2,-32676(gp) + 503c: 10800044 addi r2,r2,1 + 5040: d0a01715 stw r2,-32676(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 5044: 00002e06 br 5100 + { + next = (alt_alarm*) alarm->llist.next; + 5048: e0bffd17 ldw r2,-12(fp) + 504c: 10800017 ldw r2,0(r2) + 5050: e0bffe15 stw r2,-8(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + 5054: e0bffd17 ldw r2,-12(fp) + 5058: 10800403 ldbu r2,16(r2) + 505c: 10803fcc andi r2,r2,255 + 5060: 10000426 beq r2,zero,5074 + 5064: d0a01717 ldw r2,-32676(gp) + 5068: 1000021e bne r2,zero,5074 + { + alarm->rollover = 0; + 506c: e0bffd17 ldw r2,-12(fp) + 5070: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + 5074: e0bffd17 ldw r2,-12(fp) + 5078: 10800217 ldw r2,8(r2) + 507c: d0e01717 ldw r3,-32676(gp) + 5080: 18801d36 bltu r3,r2,50f8 + 5084: e0bffd17 ldw r2,-12(fp) + 5088: 10800403 ldbu r2,16(r2) + 508c: 10803fcc andi r2,r2,255 + 5090: 1000191e bne r2,zero,50f8 + { + next_callback = alarm->callback (alarm->context); + 5094: e0bffd17 ldw r2,-12(fp) + 5098: 10800317 ldw r2,12(r2) + 509c: e0fffd17 ldw r3,-12(fp) + 50a0: 18c00517 ldw r3,20(r3) + 50a4: 1809883a mov r4,r3 + 50a8: 103ee83a callr r2 + 50ac: e0bfff15 stw r2,-4(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + 50b0: e0bfff17 ldw r2,-4(fp) + 50b4: 1000031e bne r2,zero,50c4 + { + alt_alarm_stop (alarm); + 50b8: e13ffd17 ldw r4,-12(fp) + 50bc: 0004f840 call 4f84 + 50c0: 00000d06 br 50f8 + } + else + { + alarm->time += next_callback; + 50c4: e0bffd17 ldw r2,-12(fp) + 50c8: 10c00217 ldw r3,8(r2) + 50cc: e0bfff17 ldw r2,-4(fp) + 50d0: 1887883a add r3,r3,r2 + 50d4: e0bffd17 ldw r2,-12(fp) + 50d8: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + 50dc: e0bffd17 ldw r2,-12(fp) + 50e0: 10c00217 ldw r3,8(r2) + 50e4: d0a01717 ldw r2,-32676(gp) + 50e8: 1880032e bgeu r3,r2,50f8 + { + alarm->rollover = 1; + 50ec: e0bffd17 ldw r2,-12(fp) + 50f0: 00c00044 movi r3,1 + 50f4: 10c00405 stb r3,16(r2) + } + } + } + alarm = next; + 50f8: e0bffe17 ldw r2,-8(fp) + 50fc: e0bffd15 stw r2,-12(fp) + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 5100: e0fffd17 ldw r3,-12(fp) + 5104: d0a00c04 addi r2,gp,-32720 + 5108: 18bfcf1e bne r3,r2,5048 <__alt_data_end+0xfffe5048> + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); + 510c: 0001883a nop +} + 5110: 0001883a nop + 5114: e037883a mov sp,fp + 5118: dfc00117 ldw ra,4(sp) + 511c: df000017 ldw fp,0(sp) + 5120: dec00204 addi sp,sp,8 + 5124: f800283a ret + +00005128 : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_gen2_irq_init(void) +{ + 5128: deffff04 addi sp,sp,-4 + 512c: df000015 stw fp,0(sp) + 5130: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + 5134: 000170fa wrctl ienable,zero +} + 5138: 0001883a nop + 513c: e037883a mov sp,fp + 5140: df000017 ldw fp,0(sp) + 5144: dec00104 addi sp,sp,4 + 5148: f800283a ret + +0000514c : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + 514c: defffa04 addi sp,sp,-24 + 5150: dfc00515 stw ra,20(sp) + 5154: df000415 stw fp,16(sp) + 5158: df000404 addi fp,sp,16 + 515c: e13ffe15 stw r4,-8(fp) + 5160: e17fff15 stw r5,-4(fp) + alt_dev* next = (alt_dev*) llist->next; + 5164: e0bfff17 ldw r2,-4(fp) + 5168: 10800017 ldw r2,0(r2) + 516c: e0bffc15 stw r2,-16(fp) + alt_32 len; + + len = strlen(name) + 1; + 5170: e13ffe17 ldw r4,-8(fp) + 5174: 00004040 call 404 + 5178: 10800044 addi r2,r2,1 + 517c: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 5180: 00000d06 br 51b8 + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + 5184: e0bffc17 ldw r2,-16(fp) + 5188: 10800217 ldw r2,8(r2) + 518c: e0fffd17 ldw r3,-12(fp) + 5190: 180d883a mov r6,r3 + 5194: e17ffe17 ldw r5,-8(fp) + 5198: 1009883a mov r4,r2 + 519c: 00054900 call 5490 + 51a0: 1000021e bne r2,zero,51ac + { + /* match found */ + + return next; + 51a4: e0bffc17 ldw r2,-16(fp) + 51a8: 00000706 br 51c8 + } + next = (alt_dev*) next->llist.next; + 51ac: e0bffc17 ldw r2,-16(fp) + 51b0: 10800017 ldw r2,0(r2) + 51b4: e0bffc15 stw r2,-16(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 51b8: e0fffc17 ldw r3,-16(fp) + 51bc: e0bfff17 ldw r2,-4(fp) + 51c0: 18bff01e bne r3,r2,5184 <__alt_data_end+0xfffe5184> + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 51c4: 0005883a mov r2,zero +} + 51c8: e037883a mov sp,fp + 51cc: dfc00117 ldw ra,4(sp) + 51d0: df000017 ldw fp,0(sp) + 51d4: dec00204 addi sp,sp,8 + 51d8: f800283a ret + +000051dc : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + 51dc: defffb04 addi sp,sp,-20 + 51e0: dfc00415 stw ra,16(sp) + 51e4: df000315 stw fp,12(sp) + 51e8: df000304 addi fp,sp,12 + 51ec: e13fff15 stw r4,-4(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + 51f0: d0a00417 ldw r2,-32752(gp) + 51f4: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 51f8: 00003106 br 52c0 + { + len = strlen(next->name); + 51fc: e0bffd17 ldw r2,-12(fp) + 5200: 10800217 ldw r2,8(r2) + 5204: 1009883a mov r4,r2 + 5208: 00004040 call 404 + 520c: e0bffe15 stw r2,-8(fp) + + if (next->name[len-1] == '/') + 5210: e0bffd17 ldw r2,-12(fp) + 5214: 10c00217 ldw r3,8(r2) + 5218: e0bffe17 ldw r2,-8(fp) + 521c: 10bfffc4 addi r2,r2,-1 + 5220: 1885883a add r2,r3,r2 + 5224: 10800003 ldbu r2,0(r2) + 5228: 10803fcc andi r2,r2,255 + 522c: 1080201c xori r2,r2,128 + 5230: 10bfe004 addi r2,r2,-128 + 5234: 10800bd8 cmpnei r2,r2,47 + 5238: 1000031e bne r2,zero,5248 + { + len -= 1; + 523c: e0bffe17 ldw r2,-8(fp) + 5240: 10bfffc4 addi r2,r2,-1 + 5244: e0bffe15 stw r2,-8(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 5248: e0bffe17 ldw r2,-8(fp) + 524c: e0ffff17 ldw r3,-4(fp) + 5250: 1885883a add r2,r3,r2 + 5254: 10800003 ldbu r2,0(r2) + 5258: 10803fcc andi r2,r2,255 + 525c: 1080201c xori r2,r2,128 + 5260: 10bfe004 addi r2,r2,-128 + 5264: 10800be0 cmpeqi r2,r2,47 + 5268: 1000081e bne r2,zero,528c + 526c: e0bffe17 ldw r2,-8(fp) + 5270: e0ffff17 ldw r3,-4(fp) + 5274: 1885883a add r2,r3,r2 + 5278: 10800003 ldbu r2,0(r2) + 527c: 10803fcc andi r2,r2,255 + 5280: 1080201c xori r2,r2,128 + 5284: 10bfe004 addi r2,r2,-128 + 5288: 10000a1e bne r2,zero,52b4 + !memcmp (next->name, name, len)) + 528c: e0bffd17 ldw r2,-12(fp) + 5290: 10800217 ldw r2,8(r2) + 5294: e0fffe17 ldw r3,-8(fp) + 5298: 180d883a mov r6,r3 + 529c: e17fff17 ldw r5,-4(fp) + 52a0: 1009883a mov r4,r2 + 52a4: 00054900 call 5490 + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 52a8: 1000021e bne r2,zero,52b4 + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + 52ac: e0bffd17 ldw r2,-12(fp) + 52b0: 00000706 br 52d0 + } + next = (alt_dev*) next->llist.next; + 52b4: e0bffd17 ldw r2,-12(fp) + 52b8: 10800017 ldw r2,0(r2) + 52bc: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 52c0: e0fffd17 ldw r3,-12(fp) + 52c4: d0a00404 addi r2,gp,-32752 + 52c8: 18bfcc1e bne r3,r2,51fc <__alt_data_end+0xfffe51fc> + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 52cc: 0005883a mov r2,zero +} + 52d0: e037883a mov sp,fp + 52d4: dfc00117 ldw ra,4(sp) + 52d8: df000017 ldw fp,0(sp) + 52dc: dec00204 addi sp,sp,8 + 52e0: f800283a ret + +000052e4 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + 52e4: defffa04 addi sp,sp,-24 + 52e8: dfc00515 stw ra,20(sp) + 52ec: df000415 stw fp,16(sp) + 52f0: dc000315 stw r16,12(sp) + 52f4: df000404 addi fp,sp,16 + 52f8: e13ffe15 stw r4,-8(fp) + alt_32 i; + int rc = -EMFILE; + 52fc: 00bffa04 movi r2,-24 + 5300: e0bffd15 stw r2,-12(fp) + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 5304: e03ffc15 stw zero,-16(fp) + 5308: 00001d06 br 5380 + { + if (!alt_fd_list[i].dev) + 530c: 04000034 movhi r16,0 + 5310: 84181e04 addi r16,r16,24696 + 5314: e0bffc17 ldw r2,-16(fp) + 5318: 01400304 movi r5,12 + 531c: 1009883a mov r4,r2 + 5320: 00031140 call 3114 <__mulsi3> + 5324: 8085883a add r2,r16,r2 + 5328: 10800017 ldw r2,0(r2) + 532c: 1000111e bne r2,zero,5374 + { + alt_fd_list[i].dev = dev; + 5330: 04000034 movhi r16,0 + 5334: 84181e04 addi r16,r16,24696 + 5338: e0bffc17 ldw r2,-16(fp) + 533c: 01400304 movi r5,12 + 5340: 1009883a mov r4,r2 + 5344: 00031140 call 3114 <__mulsi3> + 5348: 8085883a add r2,r16,r2 + 534c: e0fffe17 ldw r3,-8(fp) + 5350: 10c00015 stw r3,0(r2) + if (i > alt_max_fd) + 5354: d0e00817 ldw r3,-32736(gp) + 5358: e0bffc17 ldw r2,-16(fp) + 535c: 1880020e bge r3,r2,5368 + { + alt_max_fd = i; + 5360: e0bffc17 ldw r2,-16(fp) + 5364: d0a00815 stw r2,-32736(gp) + } + rc = i; + 5368: e0bffc17 ldw r2,-16(fp) + 536c: e0bffd15 stw r2,-12(fp) + goto alt_get_fd_exit; + 5370: 00000606 br 538c + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 5374: e0bffc17 ldw r2,-16(fp) + 5378: 10800044 addi r2,r2,1 + 537c: e0bffc15 stw r2,-16(fp) + 5380: e0bffc17 ldw r2,-16(fp) + 5384: 10800810 cmplti r2,r2,32 + 5388: 103fe01e bne r2,zero,530c <__alt_data_end+0xfffe530c> + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; + 538c: e0bffd17 ldw r2,-12(fp) +} + 5390: e6ffff04 addi sp,fp,-4 + 5394: dfc00217 ldw ra,8(sp) + 5398: df000117 ldw fp,4(sp) + 539c: dc000017 ldw r16,0(sp) + 53a0: dec00304 addi sp,sp,12 + 53a4: f800283a ret + +000053a8 : + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int +alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + 53a8: defffe04 addi sp,sp,-8 + 53ac: df000115 stw fp,4(sp) + 53b0: df000104 addi fp,sp,4 + 53b4: e13fff15 stw r4,-4(fp) + switch (cause) { + 53b8: e0bfff17 ldw r2,-4(fp) + 53bc: 10bffe84 addi r2,r2,-6 + 53c0: 10c00428 cmpgeui r3,r2,16 + 53c4: 18001a1e bne r3,zero,5430 + 53c8: 100690ba slli r3,r2,2 + 53cc: 00800034 movhi r2,0 + 53d0: 1094f804 addi r2,r2,21472 + 53d4: 1885883a add r2,r3,r2 + 53d8: 10800017 ldw r2,0(r2) + 53dc: 1000683a jmp r2 + 53e0: 00005420 cmpeqi zero,zero,336 + 53e4: 00005420 cmpeqi zero,zero,336 + 53e8: 00005430 cmpltui zero,zero,336 + 53ec: 00005430 cmpltui zero,zero,336 + 53f0: 00005430 cmpltui zero,zero,336 + 53f4: 00005420 cmpeqi zero,zero,336 + 53f8: 00005428 cmpgeui zero,zero,336 + 53fc: 00005430 cmpltui zero,zero,336 + 5400: 00005420 cmpeqi zero,zero,336 + 5404: 00005420 cmpeqi zero,zero,336 + 5408: 00005430 cmpltui zero,zero,336 + 540c: 00005420 cmpeqi zero,zero,336 + 5410: 00005428 cmpgeui zero,zero,336 + 5414: 00005430 cmpltui zero,zero,336 + 5418: 00005430 cmpltui zero,zero,336 + 541c: 00005420 cmpeqi zero,zero,336 + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + case NIOS2_EXCEPTION_ECC_DATA_ERR: + return 1; + 5420: 00800044 movi r2,1 + 5424: 00000306 br 5434 + + case NIOS2_EXCEPTION_TLB_MISS: + case NIOS2_EXCEPTION_ECC_TLB_ERR: + return 0; + 5428: 0005883a mov r2,zero + 542c: 00000106 br 5434 + + default: + return 0; + 5430: 0005883a mov r2,zero + } +} + 5434: e037883a mov sp,fp + 5438: df000017 ldw fp,0(sp) + 543c: dec00104 addi sp,sp,4 + 5440: f800283a ret + +00005444 : + 5444: 200b883a mov r5,r4 + 5448: 000f883a mov r7,zero + 544c: 000d883a mov r6,zero + 5450: 0009883a mov r4,zero + 5454: 000550c1 jmpi 550c <__register_exitproc> + +00005458 : + 5458: defffe04 addi sp,sp,-8 + 545c: 000b883a mov r5,zero + 5460: dc000015 stw r16,0(sp) + 5464: dfc00115 stw ra,4(sp) + 5468: 2021883a mov r16,r4 + 546c: 00056240 call 5624 <__call_exitprocs> + 5470: 00800034 movhi r2,0 + 5474: 109c9604 addi r2,r2,29272 + 5478: 11000017 ldw r4,0(r2) + 547c: 20800f17 ldw r2,60(r4) + 5480: 10000126 beq r2,zero,5488 + 5484: 103ee83a callr r2 + 5488: 8009883a mov r4,r16 + 548c: 00057a40 call 57a4 <_exit> + +00005490 : + 5490: 01c000c4 movi r7,3 + 5494: 3980192e bgeu r7,r6,54fc + 5498: 2144b03a or r2,r4,r5 + 549c: 11c4703a and r2,r2,r7 + 54a0: 10000f26 beq r2,zero,54e0 + 54a4: 20800003 ldbu r2,0(r4) + 54a8: 28c00003 ldbu r3,0(r5) + 54ac: 10c0151e bne r2,r3,5504 + 54b0: 31bfff84 addi r6,r6,-2 + 54b4: 01ffffc4 movi r7,-1 + 54b8: 00000406 br 54cc + 54bc: 20800003 ldbu r2,0(r4) + 54c0: 28c00003 ldbu r3,0(r5) + 54c4: 31bfffc4 addi r6,r6,-1 + 54c8: 10c00e1e bne r2,r3,5504 + 54cc: 21000044 addi r4,r4,1 + 54d0: 29400044 addi r5,r5,1 + 54d4: 31fff91e bne r6,r7,54bc <__alt_data_end+0xfffe54bc> + 54d8: 0005883a mov r2,zero + 54dc: f800283a ret + 54e0: 20c00017 ldw r3,0(r4) + 54e4: 28800017 ldw r2,0(r5) + 54e8: 18bfee1e bne r3,r2,54a4 <__alt_data_end+0xfffe54a4> + 54ec: 31bfff04 addi r6,r6,-4 + 54f0: 21000104 addi r4,r4,4 + 54f4: 29400104 addi r5,r5,4 + 54f8: 39bff936 bltu r7,r6,54e0 <__alt_data_end+0xfffe54e0> + 54fc: 303fe91e bne r6,zero,54a4 <__alt_data_end+0xfffe54a4> + 5500: 003ff506 br 54d8 <__alt_data_end+0xfffe54d8> + 5504: 10c5c83a sub r2,r2,r3 + 5508: f800283a ret + +0000550c <__register_exitproc>: + 550c: defffa04 addi sp,sp,-24 + 5510: dc000315 stw r16,12(sp) + 5514: 04000034 movhi r16,0 + 5518: 841c9604 addi r16,r16,29272 + 551c: 80c00017 ldw r3,0(r16) + 5520: dc400415 stw r17,16(sp) + 5524: dfc00515 stw ra,20(sp) + 5528: 18805217 ldw r2,328(r3) + 552c: 2023883a mov r17,r4 + 5530: 10003726 beq r2,zero,5610 <__register_exitproc+0x104> + 5534: 10c00117 ldw r3,4(r2) + 5538: 010007c4 movi r4,31 + 553c: 20c00e16 blt r4,r3,5578 <__register_exitproc+0x6c> + 5540: 1a000044 addi r8,r3,1 + 5544: 8800221e bne r17,zero,55d0 <__register_exitproc+0xc4> + 5548: 18c00084 addi r3,r3,2 + 554c: 18c7883a add r3,r3,r3 + 5550: 18c7883a add r3,r3,r3 + 5554: 12000115 stw r8,4(r2) + 5558: 10c7883a add r3,r2,r3 + 555c: 19400015 stw r5,0(r3) + 5560: 0005883a mov r2,zero + 5564: dfc00517 ldw ra,20(sp) + 5568: dc400417 ldw r17,16(sp) + 556c: dc000317 ldw r16,12(sp) + 5570: dec00604 addi sp,sp,24 + 5574: f800283a ret + 5578: 00800034 movhi r2,0 + 557c: 10800004 addi r2,r2,0 + 5580: 10002626 beq r2,zero,561c <__register_exitproc+0x110> + 5584: 01006404 movi r4,400 + 5588: d9400015 stw r5,0(sp) + 558c: d9800115 stw r6,4(sp) + 5590: d9c00215 stw r7,8(sp) + 5594: 00000000 call 0 <__reset> + 5598: d9400017 ldw r5,0(sp) + 559c: d9800117 ldw r6,4(sp) + 55a0: d9c00217 ldw r7,8(sp) + 55a4: 10001d26 beq r2,zero,561c <__register_exitproc+0x110> + 55a8: 81000017 ldw r4,0(r16) + 55ac: 10000115 stw zero,4(r2) + 55b0: 02000044 movi r8,1 + 55b4: 22405217 ldw r9,328(r4) + 55b8: 0007883a mov r3,zero + 55bc: 12400015 stw r9,0(r2) + 55c0: 20805215 stw r2,328(r4) + 55c4: 10006215 stw zero,392(r2) + 55c8: 10006315 stw zero,396(r2) + 55cc: 883fde26 beq r17,zero,5548 <__alt_data_end+0xfffe5548> + 55d0: 18c9883a add r4,r3,r3 + 55d4: 2109883a add r4,r4,r4 + 55d8: 1109883a add r4,r2,r4 + 55dc: 21802215 stw r6,136(r4) + 55e0: 01800044 movi r6,1 + 55e4: 12406217 ldw r9,392(r2) + 55e8: 30cc983a sll r6,r6,r3 + 55ec: 4992b03a or r9,r9,r6 + 55f0: 12406215 stw r9,392(r2) + 55f4: 21c04215 stw r7,264(r4) + 55f8: 01000084 movi r4,2 + 55fc: 893fd21e bne r17,r4,5548 <__alt_data_end+0xfffe5548> + 5600: 11006317 ldw r4,396(r2) + 5604: 218cb03a or r6,r4,r6 + 5608: 11806315 stw r6,396(r2) + 560c: 003fce06 br 5548 <__alt_data_end+0xfffe5548> + 5610: 18805304 addi r2,r3,332 + 5614: 18805215 stw r2,328(r3) + 5618: 003fc606 br 5534 <__alt_data_end+0xfffe5534> + 561c: 00bfffc4 movi r2,-1 + 5620: 003fd006 br 5564 <__alt_data_end+0xfffe5564> + +00005624 <__call_exitprocs>: + 5624: defff504 addi sp,sp,-44 + 5628: df000915 stw fp,36(sp) + 562c: dd400615 stw r21,24(sp) + 5630: dc800315 stw r18,12(sp) + 5634: dfc00a15 stw ra,40(sp) + 5638: ddc00815 stw r23,32(sp) + 563c: dd800715 stw r22,28(sp) + 5640: dd000515 stw r20,20(sp) + 5644: dcc00415 stw r19,16(sp) + 5648: dc400215 stw r17,8(sp) + 564c: dc000115 stw r16,4(sp) + 5650: d9000015 stw r4,0(sp) + 5654: 2839883a mov fp,r5 + 5658: 04800044 movi r18,1 + 565c: 057fffc4 movi r21,-1 + 5660: 00800034 movhi r2,0 + 5664: 109c9604 addi r2,r2,29272 + 5668: 12000017 ldw r8,0(r2) + 566c: 45005217 ldw r20,328(r8) + 5670: 44c05204 addi r19,r8,328 + 5674: a0001c26 beq r20,zero,56e8 <__call_exitprocs+0xc4> + 5678: a0800117 ldw r2,4(r20) + 567c: 15ffffc4 addi r23,r2,-1 + 5680: b8000d16 blt r23,zero,56b8 <__call_exitprocs+0x94> + 5684: 14000044 addi r16,r2,1 + 5688: 8421883a add r16,r16,r16 + 568c: 8421883a add r16,r16,r16 + 5690: 84402004 addi r17,r16,128 + 5694: a463883a add r17,r20,r17 + 5698: a421883a add r16,r20,r16 + 569c: e0001e26 beq fp,zero,5718 <__call_exitprocs+0xf4> + 56a0: 80804017 ldw r2,256(r16) + 56a4: e0801c26 beq fp,r2,5718 <__call_exitprocs+0xf4> + 56a8: bdffffc4 addi r23,r23,-1 + 56ac: 843fff04 addi r16,r16,-4 + 56b0: 8c7fff04 addi r17,r17,-4 + 56b4: bd7ff91e bne r23,r21,569c <__alt_data_end+0xfffe569c> + 56b8: 00800034 movhi r2,0 + 56bc: 10800004 addi r2,r2,0 + 56c0: 10000926 beq r2,zero,56e8 <__call_exitprocs+0xc4> + 56c4: a0800117 ldw r2,4(r20) + 56c8: 1000301e bne r2,zero,578c <__call_exitprocs+0x168> + 56cc: a0800017 ldw r2,0(r20) + 56d0: 10003226 beq r2,zero,579c <__call_exitprocs+0x178> + 56d4: a009883a mov r4,r20 + 56d8: 98800015 stw r2,0(r19) + 56dc: 00000000 call 0 <__reset> + 56e0: 9d000017 ldw r20,0(r19) + 56e4: a03fe41e bne r20,zero,5678 <__alt_data_end+0xfffe5678> + 56e8: dfc00a17 ldw ra,40(sp) + 56ec: df000917 ldw fp,36(sp) + 56f0: ddc00817 ldw r23,32(sp) + 56f4: dd800717 ldw r22,28(sp) + 56f8: dd400617 ldw r21,24(sp) + 56fc: dd000517 ldw r20,20(sp) + 5700: dcc00417 ldw r19,16(sp) + 5704: dc800317 ldw r18,12(sp) + 5708: dc400217 ldw r17,8(sp) + 570c: dc000117 ldw r16,4(sp) + 5710: dec00b04 addi sp,sp,44 + 5714: f800283a ret + 5718: a0800117 ldw r2,4(r20) + 571c: 80c00017 ldw r3,0(r16) + 5720: 10bfffc4 addi r2,r2,-1 + 5724: 15c01426 beq r2,r23,5778 <__call_exitprocs+0x154> + 5728: 80000015 stw zero,0(r16) + 572c: 183fde26 beq r3,zero,56a8 <__alt_data_end+0xfffe56a8> + 5730: 95c8983a sll r4,r18,r23 + 5734: a0806217 ldw r2,392(r20) + 5738: a5800117 ldw r22,4(r20) + 573c: 2084703a and r2,r4,r2 + 5740: 10000b26 beq r2,zero,5770 <__call_exitprocs+0x14c> + 5744: a0806317 ldw r2,396(r20) + 5748: 2088703a and r4,r4,r2 + 574c: 20000c1e bne r4,zero,5780 <__call_exitprocs+0x15c> + 5750: 89400017 ldw r5,0(r17) + 5754: d9000017 ldw r4,0(sp) + 5758: 183ee83a callr r3 + 575c: a0800117 ldw r2,4(r20) + 5760: 15bfbf1e bne r2,r22,5660 <__alt_data_end+0xfffe5660> + 5764: 98800017 ldw r2,0(r19) + 5768: 153fcf26 beq r2,r20,56a8 <__alt_data_end+0xfffe56a8> + 576c: 003fbc06 br 5660 <__alt_data_end+0xfffe5660> + 5770: 183ee83a callr r3 + 5774: 003ff906 br 575c <__alt_data_end+0xfffe575c> + 5778: a5c00115 stw r23,4(r20) + 577c: 003feb06 br 572c <__alt_data_end+0xfffe572c> + 5780: 89000017 ldw r4,0(r17) + 5784: 183ee83a callr r3 + 5788: 003ff406 br 575c <__alt_data_end+0xfffe575c> + 578c: a0800017 ldw r2,0(r20) + 5790: a027883a mov r19,r20 + 5794: 1029883a mov r20,r2 + 5798: 003fb606 br 5674 <__alt_data_end+0xfffe5674> + 579c: 0005883a mov r2,zero + 57a0: 003ffb06 br 5790 <__alt_data_end+0xfffe5790> + +000057a4 <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + 57a4: defffd04 addi sp,sp,-12 + 57a8: df000215 stw fp,8(sp) + 57ac: df000204 addi fp,sp,8 + 57b0: e13fff15 stw r4,-4(fp) + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + 57b4: 0001883a nop + 57b8: e0bfff17 ldw r2,-4(fp) + 57bc: e0bffe15 stw r2,-8(fp) +/* + * Routine called on exit. + */ +static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + register int r2 asm ("r2") = exit_code; + 57c0: e0bffe17 ldw r2,-8(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + 57c4: 10000226 beq r2,zero,57d0 <_exit+0x2c> + ALT_SIM_FAIL(); + 57c8: 002af070 cmpltui zero,zero,43969 + 57cc: 00000106 br 57d4 <_exit+0x30> + } else { + ALT_SIM_PASS(); + 57d0: 002af0b0 cmpltui zero,zero,43970 + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + 57d4: 003fff06 br 57d4 <__alt_data_end+0xfffe57d4> diff --git a/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat new file mode 100644 index 0000000..59ec0be --- /dev/null +++ b/Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat @@ -0,0 +1,7332 @@ +@0000 00400034 +@0001 08408C14 +@0002 0800683A +@0003 00000000 +@0004 00000000 +@0005 00000000 +@0006 00000000 +@0007 00000000 +@0008 DEFFED04 +@0009 DFC00015 +@000A D8400215 +@000B D8800315 +@000C D8C00415 +@000D D9000515 +@000E D9400615 +@000F D9800715 +@0010 D9C00815 +@0011 000B307A +@0012 DA000915 +@0013 DA400A15 +@0014 DA800B15 +@0015 DAC00C15 +@0016 DB000D15 +@0017 DB400E15 +@0018 DB800F15 +@0019 DBC01015 +@001A D9401115 +@001B EBFFFF04 +@001C DBC01215 +@001D 0009313A +@001E 2880004C +@001F 10000326 +@0020 20000226 +@0021 00000FC0 +@0022 00000706 +@0023 DF401215 +@0024 E8BFFF17 +@0025 E93FFF04 +@0026 00001D00 +@0027 1000021E +@0028 EBFFFF04 +@0029 DBC01215 +@002A D9401117 +@002B DF401217 +@002C DFC00017 +@002D 2801707A +@002E D8400217 +@002F D8800317 +@0030 D8C00417 +@0031 D9000517 +@0032 D9400617 +@0033 D9800717 +@0034 D9C00817 +@0035 DA000917 +@0036 DA400A17 +@0037 DA800B17 +@0038 DAC00C17 +@0039 DB000D17 +@003A DB400E17 +@003B DB800F17 +@003C DBC01017 +@003D DEC01304 +@003E EF80083A +@003F DEFFF904 +@0040 DFC00615 +@0041 DF000515 +@0042 DF000504 +@0043 0001883A +@0044 0005313A +@0045 E0BFFE15 +@0046 E0BFFE17 +@0047 E0BFFB15 +@0048 E03FFD15 +@0049 00800044 +@004A E0BFFC15 +@004B E0FFFB17 +@004C E0BFFC17 +@004D 1884703A +@004E 10001426 +@004F 00800034 +@0050 109CB904 +@0051 E0FFFD17 +@0052 180690FA +@0053 10C5883A +@0054 10C00017 +@0055 00800034 +@0056 109CB904 +@0057 E13FFD17 +@0058 200890FA +@0059 1105883A +@005A 10800104 +@005B 10800017 +@005C 1009883A +@005D 183EE83A +@005E 0001883A +@005F 0005313A +@0060 E0BFFF15 +@0061 E0BFFF17 +@0062 00000706 +@0063 E0BFFC17 +@0064 1085883A +@0065 E0BFFC15 +@0066 E0BFFD17 +@0067 10800044 +@0068 E0BFFD15 +@0069 003FE106 +@006A E0BFFB15 +@006B E0BFFB17 +@006C 103FDB1E +@006D 0001883A +@006E 0001883A +@006F E037883A +@0070 DFC00117 +@0071 DF000017 +@0072 DEC00204 +@0073 F800283A +@0074 DEFFFB04 +@0075 DFC00415 +@0076 DF000315 +@0077 DF000304 +@0078 E13FFF15 +@0079 00BFFFC4 +@007A E0BFFD15 +@007B E03FFE15 +@007C D0A01817 +@007D 10000726 +@007E D0A01817 +@007F E0FFFD17 +@0080 E1BFFE17 +@0081 E17FFF17 +@0082 1809883A +@0083 103EE83A +@0084 00000206 +@0085 003DA03A +@0086 0005883A +@0087 E037883A +@0088 DFC00117 +@0089 DF000017 +@008A DEC00204 +@008B F800283A +@008C 06C000B4 +@008D DEC00014 +@008E 06800034 +@008F D6BC9614 +@0090 00035980 +@0091 003FFF06 +@0092 DEFFFA04 +@0093 DFC00515 +@0094 DF000415 +@0095 DF000404 +@0096 008000B4 +@0097 10840804 +@0098 E0BFFE15 +@0099 E03FFC15 +@009A 00002106 +@009B E03FFF15 +@009C 00800104 +@009D E0BFFD15 +@009E 00001206 +@009F E0BFFF17 +@00A0 1008923A +@00A1 E0BFFD17 +@00A2 117FFFC4 +@00A3 00800034 +@00A4 1095F604 +@00A5 E0FFFC17 +@00A6 18C7883A +@00A7 18C7883A +@00A8 10C5883A +@00A9 1145883A +@00AA 10800003 +@00AB 10803FCC +@00AC 2084B03A +@00AD E0BFFF15 +@00AE E0BFFD17 +@00AF 10BFFFC4 +@00B0 E0BFFD15 +@00B1 E0BFFD17 +@00B2 00BFEC16 +@00B3 E0BFFE17 +@00B4 E0FFFF17 +@00B5 10C00015 +@00B6 E0BFFE17 +@00B7 10800104 +@00B8 E0BFFE15 +@00B9 E0BFFC17 +@00BA 10800044 +@00BB E0BFFC15 +@00BC E0BFFC17 +@00BD 10800110 +@00BE 103FDC1E +@00BF 00032500 +@00C0 0007883A +@00C1 008000B4 +@00C2 10840D04 +@00C3 10C00035 +@00C4 00C00044 +@00C5 008000B4 +@00C6 10840C04 +@00C7 10C00035 +@00C8 01000034 +@00C9 2115FA04 +@00CA 00003F00 +@00CB 003FFF06 +@00CC DEFFF604 +@00CD DC000715 +@00CE 2021883A +@00CF 2809883A +@00D0 DC400815 +@00D1 DFC00915 +@00D2 2823883A +@00D3 00004040 +@00D4 10C00044 +@00D5 D8800115 +@00D6 00800034 +@00D7 1095FC04 +@00D8 D8800215 +@00D9 00800044 +@00DA D8800315 +@00DB 00800084 +@00DC DC400015 +@00DD D8C00615 +@00DE DEC00415 +@00DF D8800515 +@00E0 80000226 +@00E1 80800E17 +@00E2 10001426 +@00E3 81400217 +@00E4 2880030B +@00E5 10C8000C +@00E6 1800061E +@00E7 29001917 +@00E8 00F7FFC4 +@00E9 10880014 +@00EA 20C6703A +@00EB 2880030D +@00EC 28C01915 +@00ED D9800404 +@00EE 8009883A +@00EF 000084C0 +@00F0 1000091E +@00F1 00800284 +@00F2 DFC00917 +@00F3 DC400817 +@00F4 DC000717 +@00F5 DEC00A04 +@00F6 F800283A +@00F7 8009883A +@00F8 00007FC0 +@00F9 003FE906 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b/Top/software/semafor/transcript @@ -0,0 +1 @@ +# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl diff --git a/Top/software/semafor_bsp/.settings/language.settings.xml b/Top/software/semafor_bsp/.settings/language.settings.xml index 1e74bad..2eb9a59 100644 --- a/Top/software/semafor_bsp/.settings/language.settings.xml +++ b/Top/software/semafor_bsp/.settings/language.settings.xml @@ -6,7 +6,7 @@ - + diff --git a/Top/software/semafor_bsp/libhal_bsp.a b/Top/software/semafor_bsp/libhal_bsp.a new file mode 100644 index 0000000..72049ac Binary files /dev/null and b/Top/software/semafor_bsp/libhal_bsp.a differ diff --git a/Top/software/semafor_bsp/linker.h b/Top/software/semafor_bsp/linker.h index 5b1b065..48634ed 100644 --- a/Top/software/semafor_bsp/linker.h +++ b/Top/software/semafor_bsp/linker.h @@ -4,7 +4,7 @@ * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * SOPC Builder design path: ../../niosII.sopcinfo * - * Generated: Wed Oct 19 15:19:38 MSK 2022 + * Generated: Wed Oct 19 16:14:31 MSK 2022 */ /* @@ -82,20 +82,4 @@ #define ALT_RWDATA_DEVICE MEM #define ALT_TEXT_DEVICE MEM - -/* - * Initialization code at the reset address is allowed (e.g. no external bootloader). - * - */ - -#define ALT_ALLOW_CODE_AT_RESET - - -/* - * The alt_load() facility is called from crt0 to copy sections into RAM. - * - */ - -#define ALT_LOAD_COPY_RWDATA - #endif /* __LINKER_H_ */ diff --git a/Top/software/semafor_bsp/linker.x b/Top/software/semafor_bsp/linker.x index f6f573c..51e815c 100644 --- a/Top/software/semafor_bsp/linker.x +++ b/Top/software/semafor_bsp/linker.x @@ -4,7 +4,7 @@ * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * SOPC Builder design path: ../../niosII.sopcinfo * - * Generated: Wed Oct 19 15:19:38 MSK 2022 + * Generated: Wed Oct 19 16:14:31 MSK 2022 */ /* @@ -64,12 +64,9 @@ OUTPUT_ARCH( nios2 ) ENTRY( _start ) /* - * The alt_load() facility is enabled. This typically happens when there isn't - * an external bootloader (e.g. flash bootloader). - * The LMA (aka physical address) of each loaded section is - * set to the .text memory device. - * The HAL alt_load() routine called from crt0 copies sections from - * the .text memory to RAM as needed. + * The alt_load() facility is disabled. This typically happens when an + * external bootloader is provided or the application runs in place. + * The LMA (aka physical address) of each section defaults to its VMA. */ SECTIONS @@ -221,18 +218,7 @@ SECTIONS PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - * .rwdata region equals the .text region, and is set to be loaded into .text region. - * This requires two copies of .rwdata in the .text region. One read writable at VMA. - * and one read-only at LMA. crt0 will copy from LMA to VMA on reset - * - */ - - .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + .rwdata : { PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); . = ALIGN(4); @@ -255,14 +241,7 @@ SECTIONS PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + .bss : { __bss_start = ABSOLUTE(.); PROVIDE (__sbss_start = ABSOLUTE(.)); @@ -293,21 +272,9 @@ SECTIONS * The output section used for the heap is treated in a special way, * i.e. the symbols "end" and "_end" are added to point to the heap start. * - * Because alt_load() is enabled, these sections have - * their LMA set to be loaded into the .text memory region. - * However, the alt_load() code will NOT automatically copy - * these sections into their mapped memory region. - * */ - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .mem LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + .mem : { PROVIDE (_alt_partition_mem_start = ABSOLUTE(.)); *(.mem .mem. mem.*) diff --git a/Top/software/semafor_bsp/mem_init.mk b/Top/software/semafor_bsp/mem_init.mk index 604682c..32d8d72 100644 --- a/Top/software/semafor_bsp/mem_init.mk +++ b/Top/software/semafor_bsp/mem_init.mk @@ -158,7 +158,7 @@ ACDS_VERSION := 18.1 # BUILD_NUMBER: 625 # Optimize for simulation -SIM_OPTIMIZE ?= 0 +SIM_OPTIMIZE ?= 1 # The CPU reset address as needed by elf2flash RESET_ADDRESS ?= 0x00000000 diff --git a/Top/software/semafor_bsp/public.mk b/Top/software/semafor_bsp/public.mk index d41c376..c72f769 100644 --- a/Top/software/semafor_bsp/public.mk +++ b/Top/software/semafor_bsp/public.mk @@ -221,7 +221,8 @@ ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION # loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When # this setting is true, the BSP shouldn't be used to build applications that # are expected to run real hardware. -# setting hal.enable_sim_optimize is false +# setting hal.enable_sim_optimize is true +ALT_CPPFLAGS += -DALT_SIM_OPTIMIZE # Causes the small newlib (C library) to be used. This reduces code and data # footprint at the expense of reduced functionality. Several newlib features diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp index 11946ee..bcaf256 100644 --- a/Top/software/semafor_bsp/settings.bsp +++ b/Top/software/semafor_bsp/settings.bsp @@ -2,8 +2,8 @@ hal default - 19.10.2022 15:24:36 - 1666178676551 + 24.10.2022 23:23:55 + 1666639435860 C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp settings.bsp ..\..\niosII.sopcinfo @@ -62,7 +62,7 @@ hal.linker.allow_code_at_reset ALT_ALLOW_CODE_AT_RESET Boolean - 1 + 0 0 none Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. @@ -74,7 +74,7 @@ hal.linker.enable_alt_load none Boolean - 1 + 0 0 none Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. @@ -98,7 +98,7 @@ hal.linker.enable_alt_load_copy_rwdata none Boolean - 1 + 0 0 none Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. @@ -830,7 +830,7 @@ hal.enable_sim_optimize ALT_SIM_OPTIMIZE Boolean - 0 + 1 0 public_mk_define The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html index b186d1d..870f281 100644 --- a/Top/software/semafor_bsp/summary.html +++ b/Top/software/semafor_bsp/summary.html @@ -22,10 +22,10 @@ BSP Version:default -BSP Generated On:19.10.2022 15:24:36 +BSP Generated On:24.10.2022 23:23:55 -BSP Generated Timestamp:1666178676551 +BSP Generated Timestamp:1666639435860 BSP Generated Location:C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp @@ -423,7 +423,7 @@ Default Value:0 -Value:0 +Value:1 Type:Boolean @@ -504,7 +504,7 @@ Default Value:0 -Value:1 +Value:0 Type:Boolean @@ -531,7 +531,7 @@ Default Value:0 -Value:1 +Value:0 Type:Boolean @@ -612,7 +612,7 @@ Default Value:0 -Value:1 +Value:0 Type:Boolean diff --git a/Top/software/semafor_bsp/system.h b/Top/software/semafor_bsp/system.h index 6d29be3..d09f74f 100644 --- a/Top/software/semafor_bsp/system.h +++ b/Top/software/semafor_bsp/system.h @@ -4,7 +4,7 @@ * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * SOPC Builder design path: ../../niosII.sopcinfo * - * Generated: Wed Oct 19 15:19:38 MSK 2022 + * Generated: Mon Oct 24 11:12:11 MSK 2022 */ /* @@ -137,7 +137,7 @@ #define __ALTERA_AVALON_ONCHIP_MEMORY2 #define __ALTERA_AVALON_TIMER #define __ALTERA_NIOS2_GEN2 -#define __SEMAFOR +#define __SEM /* @@ -239,13 +239,13 @@ * */ -#define ALT_MODULE_CLASS_sem_ctl_slave Semafor +#define ALT_MODULE_CLASS_sem_ctl_slave sem #define SEM_CTL_SLAVE_BASE 0x21030 #define SEM_CTL_SLAVE_IRQ -1 #define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave" #define SEM_CTL_SLAVE_SPAN 8 -#define SEM_CTL_SLAVE_TYPE "Semafor" +#define SEM_CTL_SLAVE_TYPE "sem" /* @@ -253,13 +253,13 @@ * */ -#define ALT_MODULE_CLASS_sem_ram_slave Semafor +#define ALT_MODULE_CLASS_sem_ram_slave sem #define SEM_RAM_SLAVE_BASE 0x21020 #define SEM_RAM_SLAVE_IRQ -1 #define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave" #define SEM_RAM_SLAVE_SPAN 16 -#define SEM_RAM_SLAVE_TYPE "Semafor" +#define SEM_RAM_SLAVE_TYPE "sem" /*