From f6e75a12d51cd00e56bb43866d6943c025c9cff2 Mon Sep 17 00:00:00 2001 From: "Ivan I. Ovchinnikov" Date: Thu, 22 Dec 2022 15:20:49 +0300 Subject: [PATCH] periodram x32 unchecked --- HDL/IP/periodram.v | 30 +-- Testbench/dec/dec.qws | Bin 0 -> 619 bytes Top/Semafor_hw.tcl | 4 +- Top/Semafor_hw.tcl~ | 4 +- Top/niosII.sopcinfo | 4 +- Top/niosII/niosII.bsf | 2 +- Top/niosII/niosII.html | 4 +- Top/niosII/niosII.xml | 192 +++++++++--------- Top/niosII/synthesis/niosII.debuginfo | 6 +- Top/niosII/synthesis/niosII.qip | 4 +- Top/niosII/synthesis/submodules/periodram.v | 30 +-- Top/niosII/testbench/mentor/msim_setup.tcl | 2 +- Top/niosII/testbench/niosII.html | 6 +- Top/niosII/testbench/niosII_tb.html | 6 +- .../niosII_tb/simulation/niosII_tb.v | 43 ++++ .../testbench/synopsys/vcs/vcs_setup.sh | 4 +- .../testbench/synopsys/vcsmx/vcsmx_setup.sh | 4 +- Top/niosII_tb.csv | 6 +- .../semafor/.settings/language.settings.xml | 2 +- .../.settings/language.settings.xml | 2 +- Top/software/semafor_bsp/settings.bsp | 4 +- Top/software/semafor_bsp/summary.html | 4 +- 22 files changed, 203 insertions(+), 160 deletions(-) create mode 100644 Testbench/dec/dec.qws create mode 100644 Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v diff --git a/HDL/IP/periodram.v b/HDL/IP/periodram.v index 2360633..b0a05bc 100644 --- a/HDL/IP/periodram.v +++ b/HDL/IP/periodram.v @@ -46,8 +46,8 @@ module periodram ( input clock; input [31:0] data; - input [1:0] rdaddress; - input [1:0] wraddress; + input [3:0] rdaddress; + input [3:0] wraddress; input wren; output [31:0] q; `ifndef ALTERA_RESERVED_QIS @@ -94,15 +94,15 @@ module periodram ( altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4, - altsyncram_component.numwords_b = 4, + altsyncram_component.numwords_a = 16, + altsyncram_component.numwords_b = 16, altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = 2, - altsyncram_component.widthad_b = 2, + altsyncram_component.widthad_a = 4, + altsyncram_component.widthad_b = 4, altsyncram_component.width_a = 32, altsyncram_component.width_b = 32, altsyncram_component.width_byteena_a = 1; @@ -143,7 +143,7 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" @@ -180,26 +180,26 @@ endmodule // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" -// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]" -// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" +// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" -// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0 -// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0 +// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0 +// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 diff --git a/Testbench/dec/dec.qws b/Testbench/dec/dec.qws new file mode 100644 index 0000000000000000000000000000000000000000..045a66f76c7eeafeba764a56b7a06f33d5350a32 GIT binary patch literal 619 zcmbV}F;2rk5JkUDkSKEi3JQcQB%>q*i4q|M4Hcpf!FC`rU=xfe5NDzwx1gcrEQG+D ziBkn3!LDZi{PE1r-|=3g`C8SL`npr4o*qi;9dLHpZN5EyvFz^PnZvzLV-}i0IG%*&esDx+D$#a}!U}~6 zm^$XJc?i2eLsi#@V~Wn?EgA=s^9C`q6|+fA09l(2UYDV;(wg>l4_coa*eO^rp>x!a zEY+@c!RE7?I;1p1f~6$Ne@Zf8W|2-bMC;{$I{7@fWZgxTze^==LFy7AQ?bb#i~5b% ef4^occz=7H|0`=FEgvz*mznQvrwnOoJk&RO+-Zvd literal 0 HcmV?d00001 diff --git a/Top/Semafor_hw.tcl b/Top/Semafor_hw.tcl index 0a26897..6f9fa28 100644 --- a/Top/Semafor_hw.tcl +++ b/Top/Semafor_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Mon Dec 19 20:23:41 MSK 2022 +# Wed Dec 21 21:00:10 MSK 2022 # DO NOT MODIFY # # sem "Semafor" v1.1 -# 2022.12.19.20:23:40 +# 2022.12.21.21:00:10 # # diff --git a/Top/Semafor_hw.tcl~ b/Top/Semafor_hw.tcl~ index 330d180..0a26897 100644 --- a/Top/Semafor_hw.tcl~ +++ b/Top/Semafor_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 18.1 -# Mon Dec 19 20:18:22 MSK 2022 +# Mon Dec 19 20:23:41 MSK 2022 # DO NOT MODIFY # # sem "Semafor" v1.1 -# 2022.12.19.20:18:22 +# 2022.12.19.20:23:40 # # diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo index 8d1a6df..ef8ac5d 100644 --- a/Top/niosII.sopcinfo +++ b/Top/niosII.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1671467059 + 1671642230 false true false diff --git a/Top/niosII/niosII.bsf b/Top/niosII/niosII.bsf index 3f01ac6..c61f1b7 100644 --- a/Top/niosII/niosII.bsf +++ b/Top/niosII/niosII.bsf @@ -75,7 +75,7 @@ refer to the applicable agreement for further details. (text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0))) (text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0))) (text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0))) - (text " system " (rect 253 216 554 442)(font "Arial" )) + (text " niosII " (rect 262 216 572 442)(font "Arial" )) (line (pt 112 32)(pt 176 32)(line_width 1)) (line (pt 176 32)(pt 176 216)(line_width 1)) (line (pt 112 216)(pt 176 216)(line_width 1)) diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html index 3db69d8..448fddf 100644 --- a/Top/niosII/niosII.html +++ b/Top/niosII/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.17.15:20:082022.12.21.21:02:26 Datasheet
@@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
generation took 0,00 secondsrendering took 0,11 secondsrendering took 0,05 seconds
diff --git a/Top/niosII/niosII.xml b/Top/niosII/niosII.xml index 9f0eb1b..11e36c1 100644 --- a/Top/niosII/niosII.xml +++ b/Top/niosII/niosII.xml @@ -1,6 +1,6 @@ - + @@ -607,36 +607,36 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.17 14:20:37 (*) Starting Nios II generation - # 2022.12.17 14:20:37 (*) Checking for plaintext license. - # 2022.12.17 14:20:38 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.17 14:20:38 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.17 14:20:38 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.17 14:20:38 (*) Plaintext license not found. - # 2022.12.17 14:20:38 (*) No license required to generate encrypted Nios II/e. - # 2022.12.17 14:20:38 (*) Elaborating CPU configuration settings - # 2022.12.17 14:20:38 (*) Creating all objects for CPU - # 2022.12.17 14:20:41 (*) Generating RTL from CPU objects - # 2022.12.17 14:20:41 (*) Creating plain-text RTL - # 2022.12.17 14:20:42 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.21 20:02:49 (*) Starting Nios II generation + # 2022.12.21 20:02:49 (*) Checking for plaintext license. + # 2022.12.21 20:02:50 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.21 20:02:50 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.21 20:02:50 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.21 20:02:50 (*) Plaintext license not found. + # 2022.12.21 20:02:50 (*) No license required to generate encrypted Nios II/e. + # 2022.12.21 20:02:50 (*) Elaborating CPU configuration settings + # 2022.12.21 20:02:50 (*) Creating all objects for CPU + # 2022.12.21 20:02:52 (*) Generating RTL from CPU objects + # 2022.12.21 20:02:52 (*) Creating plain-text RTL + # 2022.12.21 20:02:52 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0028_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0028_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0029_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0029_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> queue size: 5 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0031_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0031_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" @@ -881,57 +881,57 @@ Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.059s/0.091s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.052s/0.063s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.031s/0.041s + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.026s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.028s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.025s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.026s/0.033s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.016s - Timing: COM:3/0.024s/0.028s + Timing: ELA:1/0.000s + Timing: ELA:2/0.008s/0.016s + Timing: ELA:1/0.000s + Timing: COM:3/0.020s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.030s + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.025s/0.047s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.021s - Timing: COM:3/0.024s/0.033s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.031s 61 modules, 199 connections]]> @@ -1334,19 +1334,19 @@ niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.17 14:20:37 (*) Starting Nios II generation - # 2022.12.17 14:20:37 (*) Checking for plaintext license. - # 2022.12.17 14:20:38 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.17 14:20:38 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.17 14:20:38 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.17 14:20:38 (*) Plaintext license not found. - # 2022.12.17 14:20:38 (*) No license required to generate encrypted Nios II/e. - # 2022.12.17 14:20:38 (*) Elaborating CPU configuration settings - # 2022.12.17 14:20:38 (*) Creating all objects for CPU - # 2022.12.17 14:20:41 (*) Generating RTL from CPU objects - # 2022.12.17 14:20:41 (*) Creating plain-text RTL - # 2022.12.17 14:20:42 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.21 20:02:49 (*) Starting Nios II generation + # 2022.12.21 20:02:49 (*) Checking for plaintext license. + # 2022.12.21 20:02:50 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.21 20:02:50 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.21 20:02:50 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.21 20:02:50 (*) Plaintext license not found. + # 2022.12.21 20:02:50 (*) No license required to generate encrypted Nios II/e. + # 2022.12.21 20:02:50 (*) Elaborating CPU configuration settings + # 2022.12.21 20:02:50 (*) Creating all objects for CPU + # 2022.12.21 20:02:52 (*) Generating RTL from CPU objects + # 2022.12.21 20:02:52 (*) Creating plain-text RTL + # 2022.12.21 20:02:52 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> @@ -1390,7 +1390,7 @@ queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0028_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0028_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> @@ -1459,7 +1459,7 @@ queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' - Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0029_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0029_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> @@ -1533,7 +1533,7 @@ queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0031_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0031_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> @@ -2129,57 +2129,57 @@ Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.000s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.059s/0.091s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.052s/0.063s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.012s - Timing: COM:3/0.031s/0.041s + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.026s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.028s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.025s/0.031s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.009s - Timing: COM:3/0.026s/0.033s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.016s - Timing: COM:3/0.024s/0.028s + Timing: ELA:1/0.000s + Timing: ELA:2/0.008s/0.016s + Timing: ELA:1/0.000s + Timing: COM:3/0.020s/0.032s Inserting error_adapter: error_adapter_0 - Timing: ELA:1/0.001s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.010s - Timing: COM:3/0.023s/0.030s + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.015s + Timing: COM:3/0.025s/0.047s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s - Timing: ELA:2/0.001s/0.001s - Timing: ELA:1/0.021s - Timing: COM:3/0.024s/0.033s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.016s + Timing: COM:3/0.026s/0.031s 61 modules, 199 connections]]> @@ -2605,19 +2605,19 @@ queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' - Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9343_6886777904387685244.dir/0034_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] - # 2022.12.17 14:20:37 (*) Starting Nios II generation - # 2022.12.17 14:20:37 (*) Checking for plaintext license. - # 2022.12.17 14:20:38 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ - # 2022.12.17 14:20:38 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2022.12.17 14:20:38 (*) LM_LICENSE_FILE environment variable is empty - # 2022.12.17 14:20:38 (*) Plaintext license not found. - # 2022.12.17 14:20:38 (*) No license required to generate encrypted Nios II/e. - # 2022.12.17 14:20:38 (*) Elaborating CPU configuration settings - # 2022.12.17 14:20:38 (*) Creating all objects for CPU - # 2022.12.17 14:20:41 (*) Generating RTL from CPU objects - # 2022.12.17 14:20:41 (*) Creating plain-text RTL - # 2022.12.17 14:20:42 (*) Done Nios II generation + Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9347_6187306962785413670.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2022.12.21 20:02:49 (*) Starting Nios II generation + # 2022.12.21 20:02:49 (*) Checking for plaintext license. + # 2022.12.21 20:02:50 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ + # 2022.12.21 20:02:50 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2022.12.21 20:02:50 (*) LM_LICENSE_FILE environment variable is empty + # 2022.12.21 20:02:50 (*) Plaintext license not found. + # 2022.12.21 20:02:50 (*) No license required to generate encrypted Nios II/e. + # 2022.12.21 20:02:50 (*) Elaborating CPU configuration settings + # 2022.12.21 20:02:50 (*) Creating all objects for CPU + # 2022.12.21 20:02:52 (*) Generating RTL from CPU objects + # 2022.12.21 20:02:52 (*) Creating plain-text RTL + # 2022.12.21 20:02:52 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> diff --git a/Top/niosII/synthesis/niosII.debuginfo b/Top/niosII/synthesis/niosII.debuginfo index 5354989..1cad090 100644 --- a/Top/niosII/synthesis/niosII.debuginfo +++ b/Top/niosII/synthesis/niosII.debuginfo @@ -1,7 +1,7 @@ - + com.altera.sopcmodel.ensemble.EClockAdapter @@ -53,7 +53,7 @@ int - 1671276008 + 1671642146 false true true @@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. --> 18.1 18.1 625 - 7A31C1D08890000001851FD02AF4 + 7A31C1D088900000018535A2F788 diff --git a/Top/niosII/synthesis/niosII.qip b/Top/niosII/synthesis/niosII.qip index 3665102..55c67ab 100644 --- a/Top/niosII/synthesis/niosII.qip +++ b/Top/niosII/synthesis/niosII.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] -set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671276008" +set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671642146" set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] @@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTI3NjAwOA==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTY0MjE0Ng==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" diff --git a/Top/niosII/synthesis/submodules/periodram.v b/Top/niosII/synthesis/submodules/periodram.v index 2360633..b0a05bc 100644 --- a/Top/niosII/synthesis/submodules/periodram.v +++ b/Top/niosII/synthesis/submodules/periodram.v @@ -46,8 +46,8 @@ module periodram ( input clock; input [31:0] data; - input [1:0] rdaddress; - input [1:0] wraddress; + input [3:0] rdaddress; + input [3:0] wraddress; input wren; output [31:0] q; `ifndef ALTERA_RESERVED_QIS @@ -94,15 +94,15 @@ module periodram ( altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4, - altsyncram_component.numwords_b = 4, + altsyncram_component.numwords_a = 16, + altsyncram_component.numwords_b = 16, altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = 2, - altsyncram_component.widthad_b = 2, + altsyncram_component.widthad_a = 4, + altsyncram_component.widthad_b = 4, altsyncram_component.width_a = 32, altsyncram_component.width_b = 32, altsyncram_component.width_byteena_a = 1; @@ -143,7 +143,7 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" @@ -180,26 +180,26 @@ endmodule // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" -// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]" -// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" +// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" -// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0 -// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0 +// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0 +// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 diff --git a/Top/niosII/testbench/mentor/msim_setup.tcl b/Top/niosII/testbench/mentor/msim_setup.tcl index 17caddb..3ac8fe5 100644 --- a/Top/niosII/testbench/mentor/msim_setup.tcl +++ b/Top/niosII/testbench/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.19.20:25:08 +# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ---------------------------------------- # Initialize variables diff --git a/Top/niosII/testbench/niosII.html b/Top/niosII/testbench/niosII.html index 4246d4c..c8465d3 100644 --- a/Top/niosII/testbench/niosII.html +++ b/Top/niosII/testbench/niosII.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.19.20:24:192022.12.21.21:01:24 Datasheet
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - - + +
generation took 0,01 secondsrendering took 0,07 secondsgeneration took 0,00 secondsrendering took 0,08 seconds
diff --git a/Top/niosII/testbench/niosII_tb.html b/Top/niosII/testbench/niosII_tb.html index 1df88df..b53ebcd 100644 --- a/Top/niosII/testbench/niosII_tb.html +++ b/Top/niosII/testbench/niosII_tb.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.12.19.20:24:292022.12.21.21:01:33 Datasheet
@@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -2360,7 +2360,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
AUTO_GENERATION_ID16714670691671642093
AUTO_UNIQUE_ID
- +
generation took 0,00 secondsrendering took 0,04 secondsrendering took 0,06 seconds
diff --git a/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v new file mode 100644 index 0000000..b883521 --- /dev/null +++ b/Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v @@ -0,0 +1,43 @@ +`timescale 1 ps / 1 ps +module niosII_tb ( +); + + wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk] + wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n + + niosII niosii_inst ( + .clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk + .reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n + .sem_export_train (), // sem_export.train + .sem_export_red (), // .red + .sem_export_yellow (), // .yellow + .sem_export_green () // .green + ); + + altera_avalon_clock_source #( + .CLOCK_RATE (50000000), + .CLOCK_UNIT (1) + ) niosii_inst_clk_bfm ( + .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk + ); + + altera_avalon_reset_source #( + .ASSERT_HIGH_RESET (0), + .INITIAL_RESET_CYCLES (50) + ) niosii_inst_reset_bfm ( + .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n + .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk + ); + + initial begin + train = 0; + wait (niosii_inst_reset_bfm_reset_reset); + forever begin + repeat (29000) @(posedge niosII_inst_clk_bfm_clk_clk); + train = 1; + repeat (10) @(posedge niosII_inst_clk_bfm_clk_clk); + train = 0; + end + end + +endmodule diff --git a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh index c44ab83..2c5d711 100644 --- a/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh +++ b/Top/niosII/testbench/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.12.19.20:25:08 +# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.19.20:25:08 +# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh index 70994b3..1afa210 100644 --- a/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh +++ b/Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 18.1 625 win32 2022.12.19.20:25:08 +# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 18.1 625 win32 2022.12.19.20:25:08 +# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="niosII_tb" diff --git a/Top/niosII_tb.csv b/Top/niosII_tb.csv index 0da0a88..12b906e 100644 --- a/Top/niosII_tb.csv +++ b/Top/niosII_tb.csv @@ -1,12 +1,12 @@ -# system info niosII_tb on 2022.12.19.20:25:06 +# system info niosII_tb on 2022.12.21.21:02:06 system_info: name,value DEVICE,EP4CE115F29C7 DEVICE_FAMILY,Cyclone IV E -GENERATION_ID,1671467069 +GENERATION_ID,1671642093 # # -# Files generated for niosII_tb on 2022.12.19.20:25:06 +# Files generated for niosII_tb on 2022.12.21.21:02:06 files: filepath,kind,attributes,module,is_top niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true diff --git a/Top/software/semafor/.settings/language.settings.xml b/Top/software/semafor/.settings/language.settings.xml index 89c0e5a..f9a6a5e 100644 --- a/Top/software/semafor/.settings/language.settings.xml +++ b/Top/software/semafor/.settings/language.settings.xml @@ -2,7 +2,7 @@ - + diff --git a/Top/software/semafor_bsp/.settings/language.settings.xml b/Top/software/semafor_bsp/.settings/language.settings.xml index b4218df..8c49b53 100644 --- a/Top/software/semafor_bsp/.settings/language.settings.xml +++ b/Top/software/semafor_bsp/.settings/language.settings.xml @@ -2,7 +2,7 @@ - + diff --git a/Top/software/semafor_bsp/settings.bsp b/Top/software/semafor_bsp/settings.bsp index 5f0b7eb..9abac2b 100644 --- a/Top/software/semafor_bsp/settings.bsp +++ b/Top/software/semafor_bsp/settings.bsp @@ -2,8 +2,8 @@ hal default - 17.12.2022 15:27:50 - 1671276470966 + 21.12.2022 21:06:52 + 1671642412929 C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp settings.bsp ..\..\niosII.sopcinfo diff --git a/Top/software/semafor_bsp/summary.html b/Top/software/semafor_bsp/summary.html index 1e8fb1e..f4c0076 100644 --- a/Top/software/semafor_bsp/summary.html +++ b/Top/software/semafor_bsp/summary.html @@ -22,10 +22,10 @@ BSP Version:default -BSP Generated On:17.12.2022 15:27:50 +BSP Generated On:21.12.2022 21:06:52 -BSP Generated Timestamp:1671276470966 +BSP Generated Timestamp:1671642412929 BSP Generated Location:C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp