diff --git a/HDL/dec.sv b/HDL/dec.sv
index c80033a..e14fc41 100644
--- a/HDL/dec.sv
+++ b/HDL/dec.sv
@@ -83,6 +83,7 @@ module dec
colors <= 3'b001;
state <= GREEN;
end
+
if (train) begin
colors <= 3'b100;
state <= RED;
diff --git a/Testbench/dec/dec.qws b/Testbench/dec/dec.qws
deleted file mode 100644
index 045a66f..0000000
Binary files a/Testbench/dec/dec.qws and /dev/null differ
diff --git a/Testbench/sigdel/db/prev_cmp_sigdel.qmsg b/Testbench/sigdel/db/prev_cmp_sigdel.qmsg
new file mode 100644
index 0000000..1a6f05d
--- /dev/null
+++ b/Testbench/sigdel/db/prev_cmp_sigdel.qmsg
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}
diff --git a/Testbench/sigdel/db/sigdel.(0).cnf.cdb b/Testbench/sigdel/db/sigdel.(0).cnf.cdb
new file mode 100644
index 0000000..0f55ee1
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.(0).cnf.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.(0).cnf.hdb b/Testbench/sigdel/db/sigdel.(0).cnf.hdb
new file mode 100644
index 0000000..c9098ef
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.(0).cnf.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.cbx.xml b/Testbench/sigdel/db/sigdel.cbx.xml
new file mode 100644
index 0000000..4c9d94f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.cbx.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/Testbench/sigdel/db/sigdel.cmp.rdb b/Testbench/sigdel/db/sigdel.cmp.rdb
new file mode 100644
index 0000000..d161ef5
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.cmp.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.cmp_merge.kpt b/Testbench/sigdel/db/sigdel.cmp_merge.kpt
new file mode 100644
index 0000000..049df89
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.cmp_merge.kpt differ
diff --git a/Testbench/sigdel/db/sigdel.db_info b/Testbench/sigdel/db/sigdel.db_info
new file mode 100644
index 0000000..132a34a
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Mon Jan 16 21:47:58 2023
diff --git a/Testbench/sigdel/db/sigdel.hier_info b/Testbench/sigdel/db/sigdel.hier_info
new file mode 100644
index 0000000..388f4ea
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.hier_info
@@ -0,0 +1,47 @@
+|sigdel
+phinc[0] => Add0.IN14
+phinc[1] => Add0.IN13
+phinc[2] => Add0.IN12
+phinc[3] => Add0.IN11
+phinc[4] => Add0.IN10
+phinc[5] => Add0.IN9
+phinc[6] => Add0.IN8
+phinc[7] => Add0.IN7
+clk => acc[0].CLK
+clk => acc[1].CLK
+clk => acc[2].CLK
+clk => acc[3].CLK
+clk => acc[4].CLK
+clk => acc[5].CLK
+clk => acc[6].CLK
+clk => acc[7].CLK
+clk => acc[8].CLK
+clk => acc[9].CLK
+clk => acc[10].CLK
+clk => acc[11].CLK
+clk => acc[12].CLK
+clk => acc[13].CLK
+clr_n => acc[0].ACLR
+clr_n => acc[1].ACLR
+clr_n => acc[2].ACLR
+clr_n => acc[3].ACLR
+clr_n => acc[4].ACLR
+clr_n => acc[5].ACLR
+clr_n => acc[6].ACLR
+clr_n => acc[7].ACLR
+clr_n => acc[8].ACLR
+clr_n => acc[9].ACLR
+clr_n => acc[10].ACLR
+clr_n => acc[11].ACLR
+clr_n => acc[12].ACLR
+clr_n => acc[13].ACLR
+phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
+phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
+phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
+phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
+phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
+phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
+phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
+phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Testbench/sigdel/db/sigdel.hif b/Testbench/sigdel/db/sigdel.hif
new file mode 100644
index 0000000..c478932
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.hif differ
diff --git a/Testbench/sigdel/db/sigdel.lpc.html b/Testbench/sigdel/db/sigdel.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.lpc.html
@@ -0,0 +1,18 @@
+
+
+Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
diff --git a/Testbench/sigdel/db/sigdel.lpc.rdb b/Testbench/sigdel/db/sigdel.lpc.rdb
new file mode 100644
index 0000000..6da93af
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.lpc.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.lpc.txt b/Testbench/sigdel/db/sigdel.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Testbench/sigdel/db/sigdel.map.ammdb b/Testbench/sigdel/db/sigdel.map.ammdb
new file mode 100644
index 0000000..46055fc
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.ammdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.bpm b/Testbench/sigdel/db/sigdel.map.bpm
new file mode 100644
index 0000000..c0ec0ab
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.bpm differ
diff --git a/Testbench/sigdel/db/sigdel.map.cdb b/Testbench/sigdel/db/sigdel.map.cdb
new file mode 100644
index 0000000..4f7368c
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.hdb b/Testbench/sigdel/db/sigdel.map.hdb
new file mode 100644
index 0000000..33b95dd
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.map.kpt b/Testbench/sigdel/db/sigdel.map.kpt
new file mode 100644
index 0000000..3da6623
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.kpt differ
diff --git a/Testbench/sigdel/db/sigdel.map.logdb b/Testbench/sigdel/db/sigdel.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Testbench/sigdel/db/sigdel.map.qmsg b/Testbench/sigdel/db/sigdel.map.qmsg
new file mode 100644
index 0000000..94d2057
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}
diff --git a/Testbench/sigdel/db/sigdel.map.rdb b/Testbench/sigdel/db/sigdel.map.rdb
new file mode 100644
index 0000000..f833721
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map.rdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.cdb b/Testbench/sigdel/db/sigdel.map_bb.cdb
new file mode 100644
index 0000000..8caa875
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map_bb.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.hdb b/Testbench/sigdel/db/sigdel.map_bb.hdb
new file mode 100644
index 0000000..a750c1f
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.map_bb.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.map_bb.logdb b/Testbench/sigdel/db/sigdel.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Testbench/sigdel/db/sigdel.pre_map.hdb b/Testbench/sigdel/db/sigdel.pre_map.hdb
new file mode 100644
index 0000000..2016702
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.pre_map.hdb differ
diff --git a/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb b/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..24e9fc3
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.root_partition.map.reg_db.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.rtlv.hdb b/Testbench/sigdel/db/sigdel.rtlv.hdb
new file mode 100644
index 0000000..5597348
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diff --git a/Testbench/sigdel/db/sigdel.rtlv_sg.cdb b/Testbench/sigdel/db/sigdel.rtlv_sg.cdb
new file mode 100644
index 0000000..d586076
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.rtlv_sg.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb b/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..96b5aa3
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.rtlv_sg_swap.cdb differ
diff --git a/Testbench/sigdel/db/sigdel.sld_design_entry.sci b/Testbench/sigdel/db/sigdel.sld_design_entry.sci
new file mode 100644
index 0000000..6849b47
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.sld_design_entry.sci differ
diff --git a/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci b/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..6849b47
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.sld_design_entry_dsc.sci differ
diff --git a/Testbench/sigdel/db/sigdel.smart_action.txt b/Testbench/sigdel/db/sigdel.smart_action.txt
new file mode 100644
index 0000000..e04bbcf
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/Testbench/sigdel/db/sigdel.tis_db_list.ddb b/Testbench/sigdel/db/sigdel.tis_db_list.ddb
new file mode 100644
index 0000000..9b5e0bf
Binary files /dev/null and b/Testbench/sigdel/db/sigdel.tis_db_list.ddb differ
diff --git a/Testbench/sigdel/db/sigdel_partition_pins.json b/Testbench/sigdel/db/sigdel_partition_pins.json
new file mode 100644
index 0000000..42834f5
--- /dev/null
+++ b/Testbench/sigdel/db/sigdel_partition_pins.json
@@ -0,0 +1,81 @@
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "phase[0]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[1]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[2]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[3]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[4]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[5]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[6]",
+ "strict" : false
+ },
+ {
+ "name" : "phase[7]",
+ "strict" : false
+ },
+ {
+ "name" : "clk",
+ "strict" : false
+ },
+ {
+ "name" : "clr_n",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[6]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[7]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[5]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[4]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[3]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[2]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[1]",
+ "strict" : false
+ },
+ {
+ "name" : "phinc[0]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/Testbench/sigdel/incremental_db/README b/Testbench/sigdel/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info
new file mode 100644
index 0000000..faa6190
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Thu Jan 12 13:26:18 2023
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb
new file mode 100644
index 0000000..71d080d
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.cdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi
new file mode 100644
index 0000000..96aaa29
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.dpi differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..c88e3ee
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.cdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hb_info differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..d831a4a
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.hdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..af9b8e9
--- /dev/null
+++ b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb
new file mode 100644
index 0000000..5fd74e7
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hdb differ
diff --git a/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt
new file mode 100644
index 0000000..7c434b5
Binary files /dev/null and b/Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.kpt differ
diff --git a/Top/niosII.sopcinfo b/Top/niosII.sopcinfo
index 0f955c5..5862f65 100644
--- a/Top/niosII.sopcinfo
+++ b/Top/niosII.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1671833790
+ 1673967689
false
true
false
diff --git a/Top/niosII/niosII.html b/Top/niosII/niosII.html
index b1d525b..940f164 100644
--- a/Top/niosII/niosII.html
+++ b/Top/niosII/niosII.html
@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- 2022.12.24.02:16:30 |
+ 2023.01.17.19:00:54 |
Datasheet |
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- generation took 0,00 seconds |
- rendering took 0,03 seconds |
+ generation took 0.00 seconds |
+ rendering took 0.02 seconds |