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77e2cf25d3
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d2e26e53f7
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@ -83,7 +83,6 @@ module dec
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colors <= 3'b001;
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state <= GREEN;
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end
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if (train) begin
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colors <= 3'b100;
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state <= RED;
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@ -1,9 +0,0 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
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{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
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{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}
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@ -1,5 +0,0 @@
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<?xml version="1.0" ?>
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<LOG_ROOT>
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<PROJECT NAME="sigdel">
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</PROJECT>
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</LOG_ROOT>
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@ -1,3 +0,0 @@
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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Version_Index = 486699264
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Creation_Time = Mon Jan 16 21:47:58 2023
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@ -1,47 +0,0 @@
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|sigdel
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phinc[0] => Add0.IN14
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phinc[1] => Add0.IN13
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phinc[2] => Add0.IN12
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phinc[3] => Add0.IN11
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phinc[4] => Add0.IN10
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phinc[5] => Add0.IN9
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phinc[6] => Add0.IN8
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phinc[7] => Add0.IN7
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clk => acc[0].CLK
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clk => acc[1].CLK
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clk => acc[2].CLK
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clk => acc[3].CLK
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clk => acc[4].CLK
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clk => acc[5].CLK
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clk => acc[6].CLK
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clk => acc[7].CLK
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clk => acc[8].CLK
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clk => acc[9].CLK
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clk => acc[10].CLK
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clk => acc[11].CLK
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clk => acc[12].CLK
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clk => acc[13].CLK
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clr_n => acc[0].ACLR
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clr_n => acc[1].ACLR
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clr_n => acc[2].ACLR
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clr_n => acc[3].ACLR
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clr_n => acc[4].ACLR
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clr_n => acc[5].ACLR
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clr_n => acc[6].ACLR
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clr_n => acc[7].ACLR
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clr_n => acc[8].ACLR
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clr_n => acc[9].ACLR
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clr_n => acc[10].ACLR
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clr_n => acc[11].ACLR
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clr_n => acc[12].ACLR
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clr_n => acc[13].ACLR
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phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
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phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
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phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
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phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
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phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
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phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
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phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
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phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
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@ -1,18 +0,0 @@
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<TABLE>
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<TR bgcolor="#C0C0C0">
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<TH>Hierarchy</TH>
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<TH>Input</TH>
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<TH>Constant Input</TH>
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<TH>Unused Input</TH>
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<TH>Floating Input</TH>
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<TH>Output</TH>
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<TH>Constant Output</TH>
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<TH>Unused Output</TH>
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<TH>Floating Output</TH>
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<TH>Bidir</TH>
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<TH>Constant Bidir</TH>
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<TH>Unused Bidir</TH>
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<TH>Input only Bidir</TH>
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<TH>Output only Bidir</TH>
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</TR>
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</TABLE>
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@ -1,5 +0,0 @@
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Legal Partition Candidates ;
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+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
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+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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@ -1 +0,0 @@
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v1
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@ -1,12 +0,0 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
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||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
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||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
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||||
{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}
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@ -1 +0,0 @@
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v1
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@ -1 +0,0 @@
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FIT
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@ -1,81 +0,0 @@
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{
|
||||
"partitions" : [
|
||||
{
|
||||
"name" : "Top",
|
||||
"pins" : [
|
||||
{
|
||||
"name" : "phase[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "clk",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "clr_n",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[0]",
|
||||
"strict" : false
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
|
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
Version_Index = 486699264
|
||||
Creation_Time = Thu Jan 12 13:26:18 2023
|
||||
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
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</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:00:54</td>
|
||||
<td class="l">2022.12.24.02:16:30</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
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@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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</div>
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||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
<td class="l">generation took 0,00 seconds</td>
|
||||
<td class="r">rendering took 0,03 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
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@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2023.01.17.19:00:59 -->
|
||||
<!-- 2022.12.24.02:16:58 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="clockCrossingAdapter">
|
||||
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
</parameter>
|
||||
<parameter name="generationId">
|
||||
<type>int</type>
|
||||
<value>1673967654</value>
|
||||
<value>1671833790</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
|
|
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier>024262A031A800000185C03F5C6B</uniqueIdentifier>
|
||||
<uniqueIdentifier>7A31C1D0889000000185410F37E7</uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
|
|||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1673967654"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790"
|
||||
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
||||
|
|
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
|
|||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3Mzk2NzY1NA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
|
|
@ -1083,15 +1083,15 @@ set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(
|
|||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_sysclk.v"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_ociram_default_contents.mif"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
|
||||
set_global_assignment -library "niosII" -name SDC_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.sdc"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_sysclk.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_ociram_default_contents.mif"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_a.mif"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"]
|
||||
|
||||
set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_NAME "altera_reset_controller"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<?xml version="1.0"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>niosII</name>
|
||||
<peripherals>
|
||||
|
|
|
|||
|
|
@ -83,7 +83,6 @@ module dec
|
|||
colors <= 3'b001;
|
||||
state <= GREEN;
|
||||
end
|
||||
|
||||
if (train) begin
|
||||
colors <= 3'b100;
|
||||
state <= RED;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
# Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
# use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any
|
||||
# output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -7,261 +7,261 @@ DATA_RADIX=HEX;
|
|||
|
||||
CONTENT BEGIN
|
||||
|
||||
00 : 5870e850;
|
||||
01 : c7a32b0d;
|
||||
02 : 6f82d8fd;
|
||||
03 : 40bb3819;
|
||||
04 : 03c0b473;
|
||||
05 : 8f16cf30;
|
||||
06 : d708360b;
|
||||
07 : 880f36dc;
|
||||
08 : d1a275f0;
|
||||
09 : 5944e053;
|
||||
0a : c1313a53;
|
||||
0b : 4cb0c559;
|
||||
0c : 528cd209;
|
||||
0d : 1ed6d1c2;
|
||||
0e : 3fe378c9;
|
||||
0f : aa1b9ac8;
|
||||
10 : 31d374f0;
|
||||
11 : be61ec44;
|
||||
12 : 2c7a1043;
|
||||
13 : 2641125e;
|
||||
14 : 0c46e1e9;
|
||||
15 : 9860f4c3;
|
||||
16 : d9980c45;
|
||||
17 : 85005ae5;
|
||||
18 : b156d9cb;
|
||||
19 : 8a5321c3;
|
||||
1a : b603ed2b;
|
||||
1b : 2a1eb3a0;
|
||||
1c : f4b7b88b;
|
||||
1d : a1ce694f;
|
||||
1e : 469d3811;
|
||||
1f : 2185240b;
|
||||
20 : a745eb3e;
|
||||
21 : 3d2ce9c9;
|
||||
22 : e4f87c64;
|
||||
23 : 4e473b66;
|
||||
24 : f25af5e6;
|
||||
25 : 5bf0ba5c;
|
||||
26 : d9f793ee;
|
||||
27 : a5410324;
|
||||
28 : 298d0d25;
|
||||
29 : e60402c3;
|
||||
2a : 97132679;
|
||||
2b : bcd9897b;
|
||||
2c : 82a038f5;
|
||||
2d : 201cbf45;
|
||||
2e : fe6ce958;
|
||||
2f : c368dfdf;
|
||||
30 : 6a3f8ef7;
|
||||
31 : 83368a01;
|
||||
32 : 65976a6a;
|
||||
33 : 821cfabf;
|
||||
34 : 20bdc8df;
|
||||
35 : 60d97952;
|
||||
36 : 73819628;
|
||||
37 : 674070d1;
|
||||
38 : fc155d79;
|
||||
39 : d3a408b1;
|
||||
3a : bfdf2c88;
|
||||
3b : 22a2fce0;
|
||||
3c : 01e7c505;
|
||||
3d : e3e78ba0;
|
||||
3e : a049e343;
|
||||
3f : c0f1b055;
|
||||
40 : 877e1ef1;
|
||||
41 : ca871fa5;
|
||||
42 : 25ab3e85;
|
||||
43 : f9f4b822;
|
||||
44 : 90aad39a;
|
||||
45 : 08f5e44c;
|
||||
46 : 39d12cce;
|
||||
47 : 80f2ed6f;
|
||||
48 : 6a29b7d6;
|
||||
49 : 8b913cf5;
|
||||
4a : 63815e88;
|
||||
4b : 3b598e73;
|
||||
4c : 73bfa5d4;
|
||||
4d : 77c09ce3;
|
||||
4e : 839a407b;
|
||||
4f : 6433730b;
|
||||
50 : 44284f24;
|
||||
51 : f5d5762e;
|
||||
52 : b65d636d;
|
||||
53 : d1c786b8;
|
||||
54 : f3c8d2f5;
|
||||
55 : 356dc558;
|
||||
56 : 591772eb;
|
||||
57 : 79e0fdb4;
|
||||
58 : e8932f59;
|
||||
59 : 259d108a;
|
||||
5a : bb57a7f8;
|
||||
5b : 4825e3bc;
|
||||
5c : 52cf4522;
|
||||
5d : 79e4316b;
|
||||
5e : 8c0d6004;
|
||||
5f : a754e118;
|
||||
60 : 4e281ca2;
|
||||
61 : fbbc819a;
|
||||
62 : 4aee7640;
|
||||
63 : 7d333e63;
|
||||
64 : b15aaa9c;
|
||||
65 : 4f43ec26;
|
||||
66 : 1ec71c75;
|
||||
67 : 8836d7ff;
|
||||
68 : 03bf3159;
|
||||
69 : 64fe92e3;
|
||||
6a : 967a0361;
|
||||
6b : 52d392c1;
|
||||
6c : ed91cb89;
|
||||
6d : 576cc97b;
|
||||
6e : 6b3ffb6a;
|
||||
6f : 35d248a1;
|
||||
70 : f9045e40;
|
||||
71 : 67ec2a14;
|
||||
72 : c6a8d3b4;
|
||||
73 : 215bfb86;
|
||||
74 : c69c1f66;
|
||||
75 : 4244d56d;
|
||||
76 : 1b3928f3;
|
||||
77 : 731a2236;
|
||||
78 : 38d78b27;
|
||||
79 : 059c9248;
|
||||
7a : 5f87a44a;
|
||||
7b : aba5ed2e;
|
||||
7c : c0524059;
|
||||
7d : 980abb72;
|
||||
7e : 7437c9f5;
|
||||
7f : 7eceac74;
|
||||
80 : e459de2d;
|
||||
81 : 70371382;
|
||||
82 : 9e5c9169;
|
||||
83 : e019ec71;
|
||||
84 : 8a8a254a;
|
||||
85 : 5d6b1e75;
|
||||
86 : b69a1826;
|
||||
87 : 1895f4fa;
|
||||
88 : f357cacf;
|
||||
89 : d52486ab;
|
||||
8a : 1e598442;
|
||||
8b : d8d4c72d;
|
||||
8c : f8973f5f;
|
||||
8d : 7df07844;
|
||||
8e : 603c0386;
|
||||
8f : 5fa48cd0;
|
||||
90 : 7dad0b4e;
|
||||
91 : d8063146;
|
||||
92 : dd06b1d5;
|
||||
93 : a42cea93;
|
||||
94 : 937d88ca;
|
||||
95 : 0c6e9a23;
|
||||
96 : b81bdfa3;
|
||||
97 : 28077cf0;
|
||||
98 : 9aab97aa;
|
||||
99 : b6597e34;
|
||||
9a : 436fcd2b;
|
||||
9b : be8fe3e1;
|
||||
9c : dae80c2f;
|
||||
9d : e95b81e6;
|
||||
9e : 767f7b1b;
|
||||
9f : 23d2190d;
|
||||
a0 : dbd13b92;
|
||||
a1 : ba04bced;
|
||||
a2 : c59ab4a9;
|
||||
a3 : d18cd97a;
|
||||
a4 : fdc9eef9;
|
||||
a5 : e5d3431b;
|
||||
a6 : 36145dba;
|
||||
a7 : 381901fd;
|
||||
a8 : 2b84a31d;
|
||||
a9 : 56d3b835;
|
||||
aa : 82d83a4f;
|
||||
ab : 521d2b9a;
|
||||
ac : 0224591a;
|
||||
ad : 80d7ea50;
|
||||
ae : 49815eac;
|
||||
af : 9c8177e2;
|
||||
b0 : d83c171d;
|
||||
b1 : 82d4e894;
|
||||
b2 : 2da7a2cf;
|
||||
b3 : ae082f05;
|
||||
b4 : ea847ea7;
|
||||
b5 : c53a36ee;
|
||||
b6 : 9044fe8d;
|
||||
b7 : dadb18f9;
|
||||
b8 : 3631522b;
|
||||
b9 : 2bae3746;
|
||||
ba : 02d78d99;
|
||||
bb : 8e0e2771;
|
||||
bc : 2ed189db;
|
||||
bd : 63aa82eb;
|
||||
be : 754229af;
|
||||
bf : a11062b5;
|
||||
c0 : e28618e1;
|
||||
c1 : fcaf3400;
|
||||
c2 : c8a7faac;
|
||||
c3 : be56d9b0;
|
||||
c4 : 7c3f3063;
|
||||
c5 : 4d331f3f;
|
||||
c6 : 8cceb16d;
|
||||
c7 : 2d352b5d;
|
||||
c8 : 0db6cd22;
|
||||
c9 : 745ff58e;
|
||||
ca : e450c6d2;
|
||||
cb : 5567ae51;
|
||||
cc : ec2ac609;
|
||||
cd : fcced128;
|
||||
ce : 193f8e92;
|
||||
cf : 5719a6cc;
|
||||
d0 : 065cddb6;
|
||||
d1 : 04f4e1f9;
|
||||
d2 : a95d8a1e;
|
||||
d3 : d516bf8e;
|
||||
d4 : e30d671e;
|
||||
d5 : ebeeb2fe;
|
||||
d6 : b48fdd0f;
|
||||
d7 : f4b75c46;
|
||||
d8 : 4d9c9650;
|
||||
d9 : f2df58d8;
|
||||
da : 67ace373;
|
||||
db : 7ccace3c;
|
||||
dc : f4f3f5d5;
|
||||
dd : 2be9f598;
|
||||
de : f7889908;
|
||||
df : f67c2f07;
|
||||
e0 : 880a8491;
|
||||
e1 : 9c3967d0;
|
||||
e2 : d89b44d2;
|
||||
e3 : 7c21987c;
|
||||
e4 : 495e0377;
|
||||
e5 : 1c88706d;
|
||||
e6 : bf0b4325;
|
||||
e7 : 79fcc944;
|
||||
e8 : fd8c1d81;
|
||||
e9 : f4f168ae;
|
||||
ea : cf67e751;
|
||||
eb : 75907b16;
|
||||
ec : d859c7c1;
|
||||
ed : 05ef2e02;
|
||||
ee : 1f5802c9;
|
||||
ef : 8cb4928b;
|
||||
f0 : 19e65b5f;
|
||||
f1 : 9c3b7bab;
|
||||
f2 : 22bc8d7d;
|
||||
f3 : 03aa0e5f;
|
||||
f4 : 7d35f4ff;
|
||||
f5 : e5208a6e;
|
||||
f6 : 44fdd477;
|
||||
f7 : 74a81f1c;
|
||||
f8 : 6936d4f1;
|
||||
f9 : 375fc2a2;
|
||||
fa : 22a07f26;
|
||||
fb : 701c1a4d;
|
||||
fc : af4d2557;
|
||||
fd : bac85a82;
|
||||
fe : 29cff602;
|
||||
ff : 3e17ccab;
|
||||
00 : 88997af9;
|
||||
01 : abaae595;
|
||||
02 : 32fd14d1;
|
||||
03 : b66193c4;
|
||||
04 : c6a6aa09;
|
||||
05 : 0b43de5b;
|
||||
06 : d1d93028;
|
||||
07 : bcd08e2a;
|
||||
08 : 1c8bae85;
|
||||
09 : b11dad63;
|
||||
0a : 864ddf62;
|
||||
0b : 68301486;
|
||||
0c : 51a3d8d0;
|
||||
0d : 7af7d39e;
|
||||
0e : 4761b503;
|
||||
0f : 2a976e14;
|
||||
10 : 98141041;
|
||||
11 : 4c1f6471;
|
||||
12 : 41dc0a35;
|
||||
13 : 7d484ae3;
|
||||
14 : 2a1329f3;
|
||||
15 : 44ecf499;
|
||||
16 : dccdd125;
|
||||
17 : 240142e9;
|
||||
18 : 3b7e4b05;
|
||||
19 : bb92e762;
|
||||
1a : 4594a3c5;
|
||||
1b : ea0d940f;
|
||||
1c : 66525d7c;
|
||||
1d : 0f552242;
|
||||
1e : 452bd52d;
|
||||
1f : d1f4ed11;
|
||||
20 : 5d590422;
|
||||
21 : c8016b5f;
|
||||
22 : 9ab94f07;
|
||||
23 : 16bac9b4;
|
||||
24 : fe569ae3;
|
||||
25 : c6e1e6e7;
|
||||
26 : 2ff19932;
|
||||
27 : feb058ad;
|
||||
28 : 1dcce651;
|
||||
29 : e18b9bfb;
|
||||
2a : e2f4fc64;
|
||||
2b : 05d34847;
|
||||
2c : 077a8143;
|
||||
2d : 2ce4207f;
|
||||
2e : 3f3e5113;
|
||||
2f : c24d2803;
|
||||
30 : e289b503;
|
||||
31 : d16bcd4e;
|
||||
32 : 57a841cf;
|
||||
33 : 1194f754;
|
||||
34 : 5c925a31;
|
||||
35 : 40fd6946;
|
||||
36 : e397e5d7;
|
||||
37 : eada7553;
|
||||
38 : eba8ec01;
|
||||
39 : f5b39d0b;
|
||||
3a : 88af39a3;
|
||||
3b : 5b7f243e;
|
||||
3c : 4f2bb4ba;
|
||||
3d : 9451a234;
|
||||
3e : 10fd984d;
|
||||
3f : ad4ef4f7;
|
||||
40 : 7fe97f8b;
|
||||
41 : 08ea614d;
|
||||
42 : 9f2c5cf4;
|
||||
43 : 3f90b7a2;
|
||||
44 : 8c2bc774;
|
||||
45 : 45dd63a5;
|
||||
46 : 3204329c;
|
||||
47 : 9909be0d;
|
||||
48 : be65c97b;
|
||||
49 : 78f3d4a4;
|
||||
4a : 3ee8b71c;
|
||||
4b : 9e9a0de4;
|
||||
4c : 56db426b;
|
||||
4d : e6869d81;
|
||||
4e : 20ab0652;
|
||||
4f : 05d247ed;
|
||||
50 : 1edccf12;
|
||||
51 : 1e483b5a;
|
||||
52 : 8e48ef1e;
|
||||
53 : f19aefbf;
|
||||
54 : 98335d23;
|
||||
55 : 954ac923;
|
||||
56 : 4679ced6;
|
||||
57 : ae18d9b8;
|
||||
58 : be57db48;
|
||||
59 : 2af933e3;
|
||||
5a : 3f04e244;
|
||||
5b : 5d11c958;
|
||||
5c : 65bda8cb;
|
||||
5d : c53fe664;
|
||||
5e : 797ceac8;
|
||||
5f : aaa406e5;
|
||||
60 : f785e24e;
|
||||
61 : 95510077;
|
||||
62 : 5b6f55a3;
|
||||
63 : 2a3c749a;
|
||||
64 : a92e6ae6;
|
||||
65 : b2117fb0;
|
||||
66 : 262a254e;
|
||||
67 : b8c4da74;
|
||||
68 : f69070ee;
|
||||
69 : 9e7f80b8;
|
||||
6a : 834528b4;
|
||||
6b : 4aaf6d98;
|
||||
6c : 96023372;
|
||||
6d : d11663ed;
|
||||
6e : 33a3c007;
|
||||
6f : 0e7f06ee;
|
||||
70 : 34385787;
|
||||
71 : 2edfd7b0;
|
||||
72 : 00d60e4b;
|
||||
73 : 49535c30;
|
||||
74 : e83f5c14;
|
||||
75 : 5e0c4c59;
|
||||
76 : 1d7b944a;
|
||||
77 : 6ae69731;
|
||||
78 : bf8414e4;
|
||||
79 : 7451c212;
|
||||
7a : 74ede6d2;
|
||||
7b : 080eafa5;
|
||||
7c : f21052d8;
|
||||
7d : cc0819fb;
|
||||
7e : 8993e5b6;
|
||||
7f : e20f2df6;
|
||||
80 : 0f267a65;
|
||||
81 : 7a8e8407;
|
||||
82 : e7be656d;
|
||||
83 : 01ba4ca3;
|
||||
84 : 7f998e44;
|
||||
85 : 29d83420;
|
||||
86 : 149f9a73;
|
||||
87 : 643ae51e;
|
||||
88 : 125714d3;
|
||||
89 : 6e49dc21;
|
||||
8a : 0b227946;
|
||||
8b : 360a837d;
|
||||
8c : b2187074;
|
||||
8d : 17b0bdbd;
|
||||
8e : 938fc73d;
|
||||
8f : e73f501e;
|
||||
90 : 70b5b87e;
|
||||
91 : 2a2aed8a;
|
||||
92 : f96cc881;
|
||||
93 : 021b49e1;
|
||||
94 : 8691600d;
|
||||
95 : b45e1d12;
|
||||
96 : 64d9644e;
|
||||
97 : 486cbaf9;
|
||||
98 : 386acf20;
|
||||
99 : 0d1384d4;
|
||||
9a : 62455f77;
|
||||
9b : 866fde20;
|
||||
9c : 006fecec;
|
||||
9d : 94e84514;
|
||||
9e : 7babc333;
|
||||
9f : afaa8445;
|
||||
a0 : b1175e3a;
|
||||
a1 : e08de629;
|
||||
a2 : 7f12a52d;
|
||||
a3 : 0e322909;
|
||||
a4 : 18784dc6;
|
||||
a5 : b23bcc20;
|
||||
a6 : 266c9e34;
|
||||
a7 : c857eaf3;
|
||||
a8 : 2ae3b164;
|
||||
a9 : 038acf2a;
|
||||
aa : c1abc60d;
|
||||
ab : 8af787bd;
|
||||
ac : 043723a9;
|
||||
ad : c37c952d;
|
||||
ae : 693a361f;
|
||||
af : da4b8e99;
|
||||
b0 : fb8fdb10;
|
||||
b1 : 4d6365f2;
|
||||
b2 : 712358e9;
|
||||
b3 : 85dae0fa;
|
||||
b4 : 7e82a418;
|
||||
b5 : d3493768;
|
||||
b6 : 739c65ec;
|
||||
b7 : 73b66b19;
|
||||
b8 : 22142816;
|
||||
b9 : ff498322;
|
||||
ba : 3266495e;
|
||||
bb : e26e8214;
|
||||
bc : c8c47131;
|
||||
bd : 660793d8;
|
||||
be : 689f8d69;
|
||||
bf : faae340b;
|
||||
c0 : 37518ba7;
|
||||
c1 : f2865fe5;
|
||||
c2 : 1bb44f3d;
|
||||
c3 : 3bce44c5;
|
||||
c4 : aff2d188;
|
||||
c5 : 985442da;
|
||||
c6 : 85bb58bd;
|
||||
c7 : 0c53135d;
|
||||
c8 : 495f80bc;
|
||||
c9 : 853c95dc;
|
||||
ca : dde937f1;
|
||||
cb : 418f9452;
|
||||
cc : 7669641c;
|
||||
cd : 0e752434;
|
||||
ce : b0fe17a7;
|
||||
cf : d1be9b88;
|
||||
d0 : cfbfeb76;
|
||||
d1 : 80b48a11;
|
||||
d2 : 9327c69e;
|
||||
d3 : beca5a88;
|
||||
d4 : e71d428f;
|
||||
d5 : b318d275;
|
||||
d6 : 56fea35e;
|
||||
d7 : 140cd6bd;
|
||||
d8 : b8c937ce;
|
||||
d9 : 540eea36;
|
||||
da : ee58fc7f;
|
||||
db : 5615c389;
|
||||
dc : 46692ad0;
|
||||
dd : 5c713e51;
|
||||
de : 6ba95f60;
|
||||
df : 0e166732;
|
||||
e0 : ac0e49f5;
|
||||
e1 : c9a5ea76;
|
||||
e2 : 05b04d86;
|
||||
e3 : b29ac712;
|
||||
e4 : 4e344493;
|
||||
e5 : d45ede48;
|
||||
e6 : 3da7e426;
|
||||
e7 : 4d6a8937;
|
||||
e8 : 99b59bd4;
|
||||
e9 : 1f8a5751;
|
||||
ea : 8b07e64e;
|
||||
eb : b4dcd496;
|
||||
ec : 42f84fe6;
|
||||
ed : f1d5952f;
|
||||
ee : a2e5a42d;
|
||||
ef : 15b1af16;
|
||||
f0 : 168012bc;
|
||||
f1 : 2e276612;
|
||||
f2 : 89913eaa;
|
||||
f3 : c607a1a2;
|
||||
f4 : fd8b544d;
|
||||
f5 : aec31a53;
|
||||
f6 : 25f958ad;
|
||||
f7 : 365903ec;
|
||||
f8 : 14761865;
|
||||
f9 : 568cc23b;
|
||||
fa : b0386305;
|
||||
fb : fb9ebd8a;
|
||||
fc : a25911d4;
|
||||
fd : 806e3fbb;
|
||||
fe : 9df35264;
|
||||
ff : d62b3814;
|
||||
|
||||
END;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# (C) 2001-2023 Altera Corporation. All rights reserved.
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
|
|
@ -94,7 +94,7 @@
|
|||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 18.1 625 linux 2023.01.17.19:01:36
|
||||
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
|
|
@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
|
|||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
|
||||
set QUARTUS_INSTALL_DIR "C:/software/intelfpga_lite/18.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
|
|
@ -142,14 +142,14 @@ if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
|||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
|
||||
}
|
||||
|
||||
|
|
@ -280,9 +280,9 @@ alias com {
|
|||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
|
||||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
|
||||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:01:29</td>
|
||||
<td class="l">2022.12.24.02:15:37</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
<td class="l">generation took 0,01 seconds</td>
|
||||
<td class="r">rendering took 0,07 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:01:31</td>
|
||||
<td class="l">2022.12.24.02:15:47</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<table>
|
||||
<tr>
|
||||
<td class="parametername">AUTO_GENERATION_ID</td>
|
||||
<td class="parametervalue">1673967691</td>
|
||||
<td class="parametervalue">1671833747</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">AUTO_UNIQUE_ID</td>
|
||||
|
|
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
<td class="l">generation took 0,01 seconds</td>
|
||||
<td class="r">rendering took 0,06 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
|
|
@ -1,55 +1,64 @@
|
|||
// niosII_tb.v
|
||||
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module niosII_tb (
|
||||
);
|
||||
);
|
||||
|
||||
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
|
||||
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
|
||||
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
|
||||
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
|
||||
reg train;
|
||||
wire red, yellow, green;
|
||||
|
||||
niosII niosii_inst (
|
||||
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
||||
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.sem_export_train (train), // sem_export.train
|
||||
.sem_export_red (red), // .red
|
||||
.sem_export_yellow (yellow), // .yellow
|
||||
.sem_export_green (green) // .green
|
||||
);
|
||||
niosII niosii_inst
|
||||
(
|
||||
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
||||
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.sem_export_train (train), // sem_export.train
|
||||
.sem_export_red (red), // .red
|
||||
.sem_export_yellow (yellow), // .yellow
|
||||
.sem_export_green (green) // .green
|
||||
);
|
||||
|
||||
altera_avalon_clock_source #(
|
||||
.CLOCK_RATE (50000000),
|
||||
.CLOCK_UNIT (1)
|
||||
) niosii_inst_clk_bfm (
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
altera_avalon_clock_source
|
||||
#(
|
||||
.CLOCK_RATE (50000000),
|
||||
.CLOCK_UNIT (1)
|
||||
)
|
||||
niosii_inst_clk_bfm
|
||||
(
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
|
||||
altera_avalon_reset_source
|
||||
#(
|
||||
.ASSERT_HIGH_RESET (0),
|
||||
.INITIAL_RESET_CYCLES (50)
|
||||
)
|
||||
niosii_inst_reset_bfm
|
||||
(
|
||||
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
|
||||
altera_avalon_reset_source #(
|
||||
.ASSERT_HIGH_RESET (0),
|
||||
.INITIAL_RESET_CYCLES (50)
|
||||
) niosii_inst_reset_bfm (
|
||||
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
initial begin
|
||||
train = 0;
|
||||
wait (niosii_inst_reset_bfm_reset_reset);
|
||||
forever begin
|
||||
wait ({red,yellow,green}==3'b001);
|
||||
repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
repeat(8) begin
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
wait ({red,yellow,green}==3'b001);
|
||||
repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
end
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# (C) 2001-2023 Altera Corporation. All rights reserved.
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 18.1 625 linux 2023.01.17.19:01:36
|
||||
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||
|
||||
# ----------------------------------------
|
||||
# vcs - auto-generated simulation script
|
||||
|
|
@ -94,12 +94,12 @@
|
|||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 18.1 625 linux 2023.01.17.19:01:36
|
||||
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="niosII_tb"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
|
||||
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
|
|
@ -131,14 +131,14 @@ fi
|
|||
# copy RAM/ROM files to simulation directory
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
|
||||
fi
|
||||
|
||||
|
|
@ -171,9 +171,9 @@ vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPT
|
|||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
|
||||
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# (C) 2001-2023 Altera Corporation. All rights reserved.
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 18.1 625 linux 2023.01.17.19:01:36
|
||||
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
|
@ -107,12 +107,12 @@
|
|||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 18.1 625 linux 2023.01.17.19:01:36
|
||||
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="niosII_tb"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
|
||||
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
|
|
@ -189,14 +189,14 @@ mkdir -p ./libraries/cycloneive_ver/
|
|||
# copy RAM/ROM files to simulation directory
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
|
||||
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
|
||||
fi
|
||||
|
||||
|
|
@ -239,9 +239,9 @@ if [ $SKIP_COM -eq 0 ]; then
|
|||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -work cpu_data_master_agent
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -work jtag_uart_avalon_jtag_slave_translator
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -work cpu_data_master_translator
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
# system info niosII_tb on 2023.01.17.19:01:35
|
||||
# system info niosII_tb on 2022.12.24.02:16:19
|
||||
system_info:
|
||||
name,value
|
||||
DEVICE,EP4CE115F29C7
|
||||
DEVICE_FAMILY,Cyclone IV E
|
||||
GENERATION_ID,1673967691
|
||||
GENERATION_ID,1671833747
|
||||
#
|
||||
#
|
||||
# Files generated for niosII_tb on 2023.01.17.19:01:35
|
||||
# Files generated for niosII_tb on 2022.12.24.02:16:19
|
||||
files:
|
||||
filepath,kind,attributes,module,is_top
|
||||
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
||||
|
|
@ -27,22 +27,22 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VER
|
|||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
|
||||
|
|
|
|||
|
|
|
@ -102,69 +102,69 @@
|
|||
type="SYSTEM_VERILOG"
|
||||
library="cpu_data_master_translator" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
|
||||
type="OTHER"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
|
||||
type="VERILOG"
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
|
||||
type="SDC"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
|
||||
type="MIF"
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
|
||||
type="SDC"
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
|
||||
type="OTHER"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
|
||||
type="VERILOG"
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
|
||||
type="VERILOG"
|
||||
|
|
|
|||
|
|
@ -6,6 +6,9 @@
|
|||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
|
|
|
|||
Loading…
Reference in New Issue