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f331b13121
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13a80845a9
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@ -1,5 +0,0 @@
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
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set_global_assignment -name IP_TOOL_VERSION "14.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]
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@ -1,214 +0,0 @@
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// megafunction wizard: %RAM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: periodram.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 14.0.2 Build 209 09/17/2014 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus II License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module periodram (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [31:0] data;
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input [3:0] rdaddress;
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input [1:0] wraddress;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({8{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 4,
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altsyncram_component.numwords_b = 16,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 2,
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altsyncram_component.widthad_b = 4,
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altsyncram_component.width_a = 32,
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altsyncram_component.width_b = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren NUMERIC "1"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
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// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
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// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
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// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -1,8 +0,0 @@
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periodram periodram_inst (
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.clock ( clock_sig ),
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||||||
.data ( data_sig ),
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||||||
.rdaddress ( rdaddress_sig ),
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||||||
.wraddress ( wraddress_sig ),
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||||||
.wren ( wren_sig ),
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.q ( q_sig )
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);
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132
HDL/dec.sv
132
HDL/dec.sv
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@ -1,132 +0,0 @@
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||||||
module dec
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#(m = 8)
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||||||
(
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|
||||||
//clock and reset
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|
||||||
input logic clk, clrn,
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|
||||||
//control slave
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|
||||||
input logic ctl_wr, ctl_rd,
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|
||||||
input logic ctl_addr,
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|
||||||
input logic [31:0] ctl_wrdata,
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|
||||||
output logic [31:0] ctl_rddata,
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|
||||||
//memory slave
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|
||||||
input logic ram_wr,
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|
||||||
input logic [1:0] ram_addr,
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|
||||||
input logic [31:0] ram_wrdata,
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|
||||||
//external ports
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|
||||||
input logic train,
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|
||||||
output logic red, yellow, green
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|
||||||
);
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|
||||||
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|
||||||
logic run;
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|
||||||
logic [1:0] divider;
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|
||||||
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|
||||||
logic [m-1:0] divisor;
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|
||||||
logic [1:0] contr;
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|
||||||
logic [2:0] colors;
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|
||||||
logic [m-1:0] cntdiv;
|
|
||||||
logic enacnt;
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|
||||||
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|
||||||
//control slave logic
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|
||||||
always_ff @ (posedge clk or negedge clrn)
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|
||||||
begin
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|
||||||
if (!clrn)
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|
||||||
begin
|
|
||||||
run <= 0;
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|
||||||
divider <= 0;
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|
||||||
end
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|
||||||
else
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|
||||||
begin
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|
||||||
if (ctl_wr)
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|
||||||
begin
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|
||||||
case (ctl_addr)
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|
||||||
1'b0: run <= ctl_wrdata[0];
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|
||||||
1'b1: divider <= ctl_wrdata[1:0];
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|
||||||
endcase
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|
||||||
end
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|
||||||
end
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|
||||||
end
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|
||||||
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|
||||||
always_comb
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|
||||||
begin
|
|
||||||
case (ctl_addr)
|
|
||||||
1'b0: ctl_rddata = {31'b0,run};
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|
||||||
1'b1: ctl_rddata = {30'b0,divider};
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|
||||||
default: ctl_rddata = 'bx;
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|
||||||
endcase
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|
||||||
end
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|
||||||
|
|
||||||
//semaphore logic
|
|
||||||
|
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
|
||||||
begin
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|
||||||
if (!clrn) cntdiv<=0;
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|
||||||
else
|
|
||||||
begin
|
|
||||||
if (train | ~run) cntdiv<=0;
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt) cntdiv<=0;
|
|
||||||
else cntdiv<=cntdiv+1;
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|
||||||
end
|
|
||||||
end
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|
||||||
end
|
|
||||||
|
|
||||||
always_comb
|
|
||||||
begin
|
|
||||||
enacnt=(cntdiv==divisor);
|
|
||||||
end
|
|
||||||
|
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
|
||||||
begin
|
|
||||||
if (!clrn)
|
|
||||||
begin
|
|
||||||
colors <= 3'b100;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (train | ~run)
|
|
||||||
begin
|
|
||||||
colors <= 3'b100;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt)
|
|
||||||
begin
|
|
||||||
case (colors)
|
|
||||||
3'b100: colors <= 3'b010;
|
|
||||||
3'b010: colors <= 3'b011;
|
|
||||||
3'b011: colors <= 3'b001;
|
|
||||||
3'b001: colors <= 3'b001;
|
|
||||||
default: colors <= 3'b100;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always_comb
|
|
||||||
begin
|
|
||||||
case (colors)
|
|
||||||
3'b100: contr = 2'b00;
|
|
||||||
3'b010: contr = 2'b01;
|
|
||||||
3'b011: contr = 2'b10;
|
|
||||||
3'b001: contr = 2'b11;
|
|
||||||
default : contr = 2'b00;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
assign red = colors[2];
|
|
||||||
assign yellow = colors[1];
|
|
||||||
assign green = colors[0];
|
|
||||||
|
|
||||||
periodram b2v_inst3(
|
|
||||||
.clock(clk),
|
|
||||||
.data (ram_wrdata),
|
|
||||||
.wraddress (ram_addr),
|
|
||||||
.wren (ram_wr),
|
|
||||||
.rdaddress({divider,contr}),
|
|
||||||
.q(divisor)
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
*.pdf
|
|
||||||
*.rpt
|
|
||||||
*.bak
|
|
||||||
.#*
|
|
||||||
|
|
||||||
/db
|
|
||||||
/incremental_db
|
|
||||||
/output_files
|
|
||||||
/simulation
|
|
||||||
/.qsys*
|
|
||||||
# /atom_netlists
|
|
||||||
|
|
||||||
|
|
||||||
/testbenches/*.bak
|
|
||||||
/common_uart/*.bak
|
|
||||||
|
|
||||||
/build/*
|
|
||||||
!/build/*.pdf
|
|
||||||
!/build/tikz*.sty
|
|
||||||
|
|
@ -1,67 +0,0 @@
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
||||||
# Your use of Intel Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Intel Program License
|
|
||||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
# the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
# agreement, including, without limitation, that your use is for
|
|
||||||
# the sole purpose of programming logic devices manufactured by
|
|
||||||
# Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
# refer to the applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus Prime
|
|
||||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
|
||||||
# Date created = 16:14:06 October 18, 2022
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Notes:
|
|
||||||
#
|
|
||||||
# 1) The default values for assignments are stored in the file:
|
|
||||||
# dec_assignment_defaults.qdf
|
|
||||||
# If this file doesn't exist, see file:
|
|
||||||
# assignment_defaults.qdf
|
|
||||||
#
|
|
||||||
# 2) Altera recommends that you do not modify this file. This
|
|
||||||
# file is updated automatically by the Quartus Prime software
|
|
||||||
# and any changes you make may be lost or overwritten.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
|
|
||||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
|
||||||
set_global_assignment -name DEVICE EP4CE6E22A7
|
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY dec
|
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06 OCTOBER 18, 2022"
|
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
|
||||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
||||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
|
||||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
|
|
||||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
|
||||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
|
||||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
|
|
||||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
|
||||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
|
|
||||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
|
|
||||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
|
||||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
|
||||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
||||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
||||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
||||||
set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
|
|
||||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
|
|
||||||
set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
|
|
||||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
|
||||||
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
|
|
||||||
set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
|
|
||||||
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
|
|
||||||
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
|
|
||||||
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
|
|
||||||
Binary file not shown.
|
|
@ -1,128 +0,0 @@
|
||||||
`timescale 1 ns/1 ns
|
|
||||||
|
|
||||||
module dec_tb();
|
|
||||||
|
|
||||||
// Wires and variables to connect to UUT (unit under test)
|
|
||||||
logic clk, clrn, train;
|
|
||||||
logic r, y, g;
|
|
||||||
logic [1:0] div;
|
|
||||||
logic ctl_wr, ctl_rd;
|
|
||||||
logic ctl_addr;
|
|
||||||
logic [31:0] ctl_wrdata;
|
|
||||||
logic [31:0] ctl_rddata;
|
|
||||||
logic ram_wr;
|
|
||||||
logic [1:0] ram_addr;
|
|
||||||
logic [31:0] ram_wrdata;
|
|
||||||
|
|
||||||
logic [31:0] divisor[3:0] = {
|
|
||||||
{8'd10, 8'd70, 8'd50, 8'd20},
|
|
||||||
{8'd10, 8'd30, 8'd40, 8'd30},
|
|
||||||
{8'd10, 8'd30, 8'd10, 8'd100},
|
|
||||||
{8'd10, 8'd60, 8'd80, 8'd50}
|
|
||||||
};
|
|
||||||
|
|
||||||
// Instantiate UUT
|
|
||||||
dec my_sem(
|
|
||||||
.clk(clk), .clrn(clrn),
|
|
||||||
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
|
|
||||||
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
|
|
||||||
.ram_wr(ram_wr),
|
|
||||||
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
|
|
||||||
.train(train), .red(r), .yellow(y), .green(g)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Clock definition
|
|
||||||
initial begin
|
|
||||||
clk = 0;
|
|
||||||
forever #10 clk = ~clk;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Divisor and train definition
|
|
||||||
initial begin
|
|
||||||
//initial reset
|
|
||||||
clrn = 0;
|
|
||||||
div = 0;
|
|
||||||
train = 0;
|
|
||||||
//take reset off
|
|
||||||
@(negedge clk) clrn = 1;
|
|
||||||
//configure semaphore
|
|
||||||
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
|
|
||||||
write_reg_transaction(1,div); //write initial divisor
|
|
||||||
write_reg_transaction(0,1); //enable semaphore
|
|
||||||
//run trains
|
|
||||||
repeat (4)
|
|
||||||
begin
|
|
||||||
repeat (10) @(posedge clk);
|
|
||||||
train=1;
|
|
||||||
repeat (4) @(posedge clk);
|
|
||||||
train=0;
|
|
||||||
wait ({r,y,g}==3'b001);
|
|
||||||
repeat (10) @(posedge clk);
|
|
||||||
write_reg_transaction(1,div);
|
|
||||||
div=div+1;
|
|
||||||
end
|
|
||||||
//wait a little
|
|
||||||
repeat (10) @(posedge clk);
|
|
||||||
$stop;
|
|
||||||
end
|
|
||||||
|
|
||||||
//Single register write transaction task
|
|
||||||
task write_reg_transaction;
|
|
||||||
//input signals
|
|
||||||
input [1:0] offs;
|
|
||||||
input [31:0] val;
|
|
||||||
//transaction implementation
|
|
||||||
begin
|
|
||||||
@(posedge clk);
|
|
||||||
//assert signals for one clock cycle
|
|
||||||
ctl_wr = 1;
|
|
||||||
ctl_addr = offs;
|
|
||||||
ctl_wrdata = val;
|
|
||||||
@(posedge clk);
|
|
||||||
//deassert signals
|
|
||||||
ctl_wr = 0;
|
|
||||||
ctl_addr = 'bx;
|
|
||||||
ctl_wrdata = 'bx;
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
//Single register read transaction task
|
|
||||||
task read_reg_transaction;
|
|
||||||
//input signals
|
|
||||||
input [1:0] offs;
|
|
||||||
output [31:0] val;
|
|
||||||
//transaction implementation
|
|
||||||
begin
|
|
||||||
@(posedge clk);
|
|
||||||
//assert signals for one clock cycle
|
|
||||||
ctl_rd = 1;
|
|
||||||
ctl_addr = offs;
|
|
||||||
@(posedge clk);
|
|
||||||
val = ctl_rddata;
|
|
||||||
//deassert signals
|
|
||||||
ctl_rd = 0;
|
|
||||||
ctl_addr = 'bx;
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
//RAM write transaction task
|
|
||||||
task write_ram_transaction;
|
|
||||||
//input signals
|
|
||||||
input [1:0] offs;
|
|
||||||
input [31:0] val;
|
|
||||||
//transaction implementation
|
|
||||||
begin
|
|
||||||
@(posedge clk);
|
|
||||||
//assert signals for one clock cycle
|
|
||||||
ram_wr = 1;
|
|
||||||
ram_addr = offs;
|
|
||||||
ram_wrdata = val;
|
|
||||||
@(posedge clk);
|
|
||||||
//deassert signals
|
|
||||||
ram_wr = 0;
|
|
||||||
ram_addr = 'bx;
|
|
||||||
ram_wrdata = 'bx;
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
@ -1,30 +0,0 @@
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
||||||
# Your use of Intel Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Intel Program License
|
|
||||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
# the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
# agreement, including, without limitation, that your use is for
|
|
||||||
# the sole purpose of programming logic devices manufactured by
|
|
||||||
# Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
# refer to the applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus Prime
|
|
||||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
|
||||||
# Date created = 16:14:06 October 18, 2022
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
QUARTUS_VERSION = "18.1"
|
|
||||||
DATE = "16:14:06 October 18, 2022"
|
|
||||||
|
|
||||||
# Revisions
|
|
||||||
|
|
||||||
PROJECT_REVISION = "dec"
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
onerror {resume}
|
|
||||||
quietly WaveActivateNextPane {} 0
|
|
||||||
add wave -noupdate /dec_tb/clk
|
|
||||||
add wave -noupdate /dec_tb/clrn
|
|
||||||
add wave -noupdate /dec_tb/train
|
|
||||||
add wave -noupdate /dec_tb/r
|
|
||||||
add wave -noupdate /dec_tb/y
|
|
||||||
add wave -noupdate /dec_tb/g
|
|
||||||
add wave -noupdate /dec_tb/div
|
|
||||||
add wave -noupdate /dec_tb/ctl_wr
|
|
||||||
add wave -noupdate /dec_tb/ctl_rd
|
|
||||||
add wave -noupdate /dec_tb/ctl_addr
|
|
||||||
add wave -noupdate /dec_tb/ctl_wrdata
|
|
||||||
add wave -noupdate /dec_tb/ctl_rddata
|
|
||||||
add wave -noupdate /dec_tb/ram_wr
|
|
||||||
add wave -noupdate /dec_tb/ram_addr
|
|
||||||
add wave -noupdate /dec_tb/ram_wrdata
|
|
||||||
TreeUpdate [SetDefaultTree]
|
|
||||||
WaveRestoreCursors {{Cursor 1} {3346003 ps} 0}
|
|
||||||
quietly wave cursor active 1
|
|
||||||
configure wave -namecolwidth 150
|
|
||||||
configure wave -valuecolwidth 100
|
|
||||||
configure wave -justifyvalue left
|
|
||||||
configure wave -signalnamewidth 0
|
|
||||||
configure wave -snapdistance 10
|
|
||||||
configure wave -datasetprefix 0
|
|
||||||
configure wave -rowmargin 4
|
|
||||||
configure wave -childrowmargin 2
|
|
||||||
configure wave -gridoffset 0
|
|
||||||
configure wave -gridperiod 1
|
|
||||||
configure wave -griddelta 40
|
|
||||||
configure wave -timeline 0
|
|
||||||
configure wave -timelineunits ns
|
|
||||||
update
|
|
||||||
WaveRestoreZoom {0 ps} {15928500 ps}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
*.pdf
|
|
||||||
*.rpt
|
|
||||||
*.bak
|
|
||||||
.#*
|
|
||||||
|
|
||||||
/db
|
|
||||||
/incremental_db
|
|
||||||
/output_files
|
|
||||||
/simulation
|
|
||||||
/.qsys*
|
|
||||||
# /atom_netlists
|
|
||||||
|
|
||||||
|
|
||||||
/testbenches/*.bak
|
|
||||||
/common_uart/*.bak
|
|
||||||
|
|
||||||
/build/*
|
|
||||||
!/build/*.pdf
|
|
||||||
!/build/tikz*.sty
|
|
||||||
388
Top/niosII.qsys
388
Top/niosII.qsys
File diff suppressed because one or more lines are too long
|
|
@ -1,59 +0,0 @@
|
||||||
/*
|
|
||||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
|
||||||
editor if you plan to continue editing the block that represents it in
|
|
||||||
the Block Editor! File corruption is VERY likely to occur.
|
|
||||||
*/
|
|
||||||
/*
|
|
||||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
||||||
Your use of Intel Corporation's design tools, logic functions
|
|
||||||
and other software and tools, and its AMPP partner logic
|
|
||||||
functions, and any output files from any of the foregoing
|
|
||||||
(including device programming or simulation files), and any
|
|
||||||
associated documentation or information are expressly subject
|
|
||||||
to the terms and conditions of the Intel Program License
|
|
||||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
agreement, including, without limitation, that your use is for
|
|
||||||
the sole purpose of programming logic devices manufactured by
|
|
||||||
Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
refer to the applicable agreement for further details.
|
|
||||||
*/
|
|
||||||
(header "symbol" (version "1.1"))
|
|
||||||
(symbol
|
|
||||||
(rect 0 0 224 144)
|
|
||||||
(text "niosII" (rect 98 -1 118 11)(font "Arial" (font_size 10)))
|
|
||||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
|
||||||
(port
|
|
||||||
(pt 0 72)
|
|
||||||
(input)
|
|
||||||
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
|
|
||||||
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
|
|
||||||
(line (pt 0 72)(pt 80 72)(line_width 1))
|
|
||||||
)
|
|
||||||
(port
|
|
||||||
(pt 0 112)
|
|
||||||
(input)
|
|
||||||
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
|
|
||||||
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
|
|
||||||
(line (pt 0 112)(pt 80 112)(line_width 1))
|
|
||||||
)
|
|
||||||
(drawing
|
|
||||||
(text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
|
||||||
(text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0)))
|
|
||||||
(text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
|
||||||
(text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0)))
|
|
||||||
(text " system " (rect 189 128 426 266)(font "Arial" ))
|
|
||||||
(line (pt 80 32)(pt 144 32)(line_width 1))
|
|
||||||
(line (pt 144 32)(pt 144 128)(line_width 1))
|
|
||||||
(line (pt 80 128)(pt 144 128)(line_width 1))
|
|
||||||
(line (pt 80 32)(pt 80 128)(line_width 1))
|
|
||||||
(line (pt 81 52)(pt 81 76)(line_width 1))
|
|
||||||
(line (pt 82 52)(pt 82 76)(line_width 1))
|
|
||||||
(line (pt 81 92)(pt 81 116)(line_width 1))
|
|
||||||
(line (pt 82 92)(pt 82 116)(line_width 1))
|
|
||||||
(line (pt 0 0)(pt 224 0)(line_width 1))
|
|
||||||
(line (pt 224 0)(pt 224 144)(line_width 1))
|
|
||||||
(line (pt 0 144)(pt 224 144)(line_width 1))
|
|
||||||
(line (pt 0 0)(pt 0 144)(line_width 1))
|
|
||||||
)
|
|
||||||
)
|
|
||||||
|
|
@ -1,7 +0,0 @@
|
||||||
component niosII is
|
|
||||||
port (
|
|
||||||
clk_clk : in std_logic := 'X'; -- clk
|
|
||||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
|
||||||
);
|
|
||||||
end component niosII;
|
|
||||||
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
|
|
||||||
module niosII (
|
|
||||||
clk_clk,
|
|
||||||
reset_reset_n);
|
|
||||||
|
|
||||||
input clk_clk;
|
|
||||||
input reset_reset_n;
|
|
||||||
endmodule
|
|
||||||
|
|
@ -1,5 +0,0 @@
|
||||||
niosII u0 (
|
|
||||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
|
||||||
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
@ -1,13 +0,0 @@
|
||||||
component niosII is
|
|
||||||
port (
|
|
||||||
clk_clk : in std_logic := 'X'; -- clk
|
|
||||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
|
||||||
);
|
|
||||||
end component niosII;
|
|
||||||
|
|
||||||
u0 : component niosII
|
|
||||||
port map (
|
|
||||||
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
|
||||||
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
@ -1,30 +0,0 @@
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
||||||
# Your use of Intel Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Intel Program License
|
|
||||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
# the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
# agreement, including, without limitation, that your use is for
|
|
||||||
# the sole purpose of programming logic devices manufactured by
|
|
||||||
# Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
# refer to the applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus Prime
|
|
||||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
|
||||||
# Date created = 16:34:55 October 18, 2022
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
QUARTUS_VERSION = "18.1"
|
|
||||||
DATE = "16:34:55 October 18, 2022"
|
|
||||||
|
|
||||||
# Revisions
|
|
||||||
|
|
||||||
PROJECT_REVISION = "semafor"
|
|
||||||
|
|
@ -1,52 +0,0 @@
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
||||||
# Your use of Intel Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Intel Program License
|
|
||||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
# the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
# agreement, including, without limitation, that your use is for
|
|
||||||
# the sole purpose of programming logic devices manufactured by
|
|
||||||
# Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
# refer to the applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus Prime
|
|
||||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
|
||||||
# Date created = 16:34:55 October 18, 2022
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Notes:
|
|
||||||
#
|
|
||||||
# 1) The default values for assignments are stored in the file:
|
|
||||||
# semafor_assignment_defaults.qdf
|
|
||||||
# If this file doesn't exist, see file:
|
|
||||||
# assignment_defaults.qdf
|
|
||||||
#
|
|
||||||
# 2) Altera recommends that you do not modify this file. This
|
|
||||||
# file is updated automatically by the Quartus Prime software
|
|
||||||
# and any changes you make may be lost or overwritten.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
|
|
||||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
|
||||||
set_global_assignment -name DEVICE EP4CE115F29C7
|
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY semafor
|
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022"
|
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
|
||||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
||||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
||||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
||||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
|
||||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
|
||||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
|
|
||||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
|
||||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
|
|
||||||
Loading…
Reference in New Issue