| tmr_enabled |
false |
| setting_disable_tmr_inj |
false |
| setting_showUnpublishedSettings |
false |
| setting_showInternalSettings |
false |
| setting_preciseIllegalMemAccessException |
false |
| setting_exportPCB |
false |
| setting_exportdebuginfo |
false |
| setting_clearXBitsLDNonBypass |
true |
| setting_bigEndian |
false |
| setting_export_large_RAMs |
false |
| setting_asic_enabled |
false |
| register_file_por |
false |
| setting_asic_synopsys_translate_on_off |
false |
| setting_asic_third_party_synthesis |
false |
| setting_asic_add_scan_mode_input |
false |
| setting_oci_version |
1 |
| setting_fast_register_read |
false |
| setting_exportHostDebugPort |
false |
| setting_oci_export_jtag_signals |
false |
| setting_avalonDebugPortPresent |
false |
| setting_alwaysEncrypt |
true |
| io_regionbase |
0 |
| io_regionsize |
0 |
| setting_support31bitdcachebypass |
true |
| setting_activateTrace |
false |
| setting_allow_break_inst |
false |
| setting_activateTestEndChecker |
false |
| setting_ecc_sim_test_ports |
false |
| setting_disableocitrace |
false |
| setting_activateMonitors |
true |
| setting_HDLSimCachesCleared |
true |
| setting_HBreakTest |
false |
| setting_breakslaveoveride |
false |
| mpu_useLimit |
false |
| mpu_enabled |
false |
| mmu_enabled |
false |
| mmu_autoAssignTlbPtrSz |
true |
| cpuReset |
false |
| resetrequest_enabled |
true |
| setting_removeRAMinit |
false |
| setting_tmr_output_disable |
false |
| setting_shadowRegisterSets |
0 |
| mpu_numOfInstRegion |
8 |
| mpu_numOfDataRegion |
8 |
| mmu_TLBMissExcOffset |
0 |
| resetOffset |
0 |
| exceptionOffset |
32 |
| cpuID |
0 |
| breakOffset |
32 |
| userDefinedSettings |
|
| tracefilename |
|
| resetSlave |
mem.s1 |
| mmu_TLBMissExcSlave |
None |
| exceptionSlave |
mem.s1 |
| breakSlave |
None |
| setting_interruptControllerType |
Internal |
| setting_branchpredictiontype |
Dynamic |
| setting_bhtPtrSz |
8 |
| cpuArchRev |
1 |
| stratix_dspblock_shift_mul |
false |
| shifterType |
medium_le_shift |
| multiplierType |
no_mul |
| mul_shift_choice |
0 |
| mul_32_impl |
2 |
| mul_64_impl |
0 |
| shift_rot_impl |
1 |
| dividerType |
no_div |
| mpu_minInstRegionSize |
12 |
| mpu_minDataRegionSize |
12 |
| mmu_uitlbNumEntries |
4 |
| mmu_udtlbNumEntries |
6 |
| mmu_tlbPtrSz |
7 |
| mmu_tlbNumWays |
16 |
| mmu_processIDNumBits |
8 |
| impl |
Tiny |
| icache_size |
4096 |
| fa_cache_line |
2 |
| fa_cache_linesize |
0 |
| icache_tagramBlockType |
Automatic |
| icache_ramBlockType |
Automatic |
| icache_numTCIM |
0 |
| icache_burstType |
None |
| dcache_bursts |
false |
| dcache_victim_buf_impl |
ram |
| dcache_size |
2048 |
| dcache_tagramBlockType |
Automatic |
| dcache_ramBlockType |
Automatic |
| dcache_numTCDM |
0 |
| setting_exportvectors |
false |
| setting_usedesignware |
false |
| setting_ecc_present |
false |
| setting_ic_ecc_present |
true |
| setting_rf_ecc_present |
true |
| setting_mmu_ecc_present |
true |
| setting_dc_ecc_present |
true |
| setting_itcm_ecc_present |
true |
| setting_dtcm_ecc_present |
true |
| regfile_ramBlockType |
Automatic |
| ocimem_ramBlockType |
Automatic |
| ocimem_ramInit |
false |
| mmu_ramBlockType |
Automatic |
| bht_ramBlockType |
Automatic |
| cdx_enabled |
false |
| mpx_enabled |
false |
| debug_enabled |
true |
| debug_triggerArming |
true |
| debug_debugReqSignals |
false |
| debug_assignJtagInstanceID |
false |
| debug_jtagInstanceID |
0 |
| debug_OCIOnchipTrace |
_128 |
| debug_hwbreakpoint |
0 |
| debug_datatrigger |
0 |
| debug_traceType |
none |
| debug_traceStorage |
onchip_trace |
| master_addr_map |
false |
| instruction_master_paddr_base |
0 |
| instruction_master_paddr_size |
0 |
| flash_instruction_master_paddr_base |
0 |
| flash_instruction_master_paddr_size |
0 |
| data_master_paddr_base |
0 |
| data_master_paddr_size |
0 |
| tightly_coupled_instruction_master_0_paddr_base |
0 |
| tightly_coupled_instruction_master_0_paddr_size |
0 |
| tightly_coupled_instruction_master_1_paddr_base |
0 |
| tightly_coupled_instruction_master_1_paddr_size |
0 |
| tightly_coupled_instruction_master_2_paddr_base |
0 |
| tightly_coupled_instruction_master_2_paddr_size |
0 |
| tightly_coupled_instruction_master_3_paddr_base |
0 |
| tightly_coupled_instruction_master_3_paddr_size |
0 |
| tightly_coupled_data_master_0_paddr_base |
0 |
| tightly_coupled_data_master_0_paddr_size |
0 |
| tightly_coupled_data_master_1_paddr_base |
0 |
| tightly_coupled_data_master_1_paddr_size |
0 |
| tightly_coupled_data_master_2_paddr_base |
0 |
| tightly_coupled_data_master_2_paddr_size |
0 |
| tightly_coupled_data_master_3_paddr_base |
0 |
| tightly_coupled_data_master_3_paddr_size |
0 |
| instruction_master_high_performance_paddr_base |
0 |
| instruction_master_high_performance_paddr_size |
0 |
| data_master_high_performance_paddr_base |
0 |
| data_master_high_performance_paddr_size |
0 |
| resetAbsoluteAddr |
0 |
| exceptionAbsoluteAddr |
32 |
| breakAbsoluteAddr |
133152 |
| mmu_TLBMissExcAbsAddr |
0 |
| dcache_bursts_derived |
false |
| dcache_size_derived |
2048 |
| breakSlave_derived |
cpu.debug_mem_slave |
| dcache_lineSize_derived |
32 |
| setting_ioregionBypassDCache |
false |
| setting_bit31BypassDCache |
false |
| translate_on |
"synthesis translate_on" |
| translate_off |
"synthesis translate_off" |
| debug_onchiptrace |
false |
| debug_offchiptrace |
false |
| debug_insttrace |
false |
| debug_datatrace |
false |
| instAddrWidth |
18 |
| faAddrWidth |
1 |
| dataAddrWidth |
18 |
| tightlyCoupledDataMaster0AddrWidth |
1 |
| tightlyCoupledDataMaster1AddrWidth |
1 |
| tightlyCoupledDataMaster2AddrWidth |
1 |
| tightlyCoupledDataMaster3AddrWidth |
1 |
| tightlyCoupledInstructionMaster0AddrWidth |
1 |
| tightlyCoupledInstructionMaster1AddrWidth |
1 |
| tightlyCoupledInstructionMaster2AddrWidth |
1 |
| tightlyCoupledInstructionMaster3AddrWidth |
1 |
| dataMasterHighPerformanceAddrWidth |
1 |
| instructionMasterHighPerformanceAddrWidth |
1 |
| instSlaveMapParam |
<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map> |
| faSlaveMapParam |
|
| dataSlaveMapParam |
<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> |
| tightlyCoupledDataMaster0MapParam |
|
| tightlyCoupledDataMaster1MapParam |
|
| tightlyCoupledDataMaster2MapParam |
|
| tightlyCoupledDataMaster3MapParam |
|
| tightlyCoupledInstructionMaster0MapParam |
|
| tightlyCoupledInstructionMaster1MapParam |
|
| tightlyCoupledInstructionMaster2MapParam |
|
| tightlyCoupledInstructionMaster3MapParam |
|
| dataMasterHighPerformanceMapParam |
|
| instructionMasterHighPerformanceMapParam |
|
| clockFrequency |
50000000 |
| deviceFamilyName |
CYCLONEIVE |
| internalIrqMaskSystemInfo |
3 |
| customInstSlavesSystemInfo |
<info/> |
| customInstSlavesSystemInfo_nios_a |
<info/> |
| customInstSlavesSystemInfo_nios_b |
<info/> |
| customInstSlavesSystemInfo_nios_c |
<info/> |
| deviceFeaturesSystemInfo |
ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 |
| AUTO_DEVICE |
EP4CE115F29C7 |
| AUTO_DEVICE_SPEEDGRADE |
7 |
| AUTO_CLK_CLOCK_DOMAIN |
1 |
| AUTO_CLK_RESET_DOMAIN |
1 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |