//top-level module
module sigdel
#(
    PHACC_WIDTH = 14
) (
	//clock and reset
	input logic clk, clr_n,
	//control slave
	input logic [31:0] wr_data,
	input logic wr_n,
	output logic fout
);

	phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
	defparam phacc_inst.WIDTH = PHACC_WIDTH;
	
	sinelut	sinelut_inst (
       .address (phase), .clock (clk), .q(sine)
	);

endmodule