niosII niosII_sys_clk_timer_s1_altera_avalon_timer0x00000000 0x0 16 registers status Status The status register has two defined bits. TO (timeout), RUN 0x0 16 read-write 0x0 0xffff TO The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit. 0x0 1 read-only clear RUN The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by a write operation to the status register. 1 1 read-only Reserved Reserved 2 14 read-write Reserved true control The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP 0x1 16 read-write 0x0 ITO If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs. 0 1 read-write CONT The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit. 1 1 read-write START Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect. 2 1 write-only STOP Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect. 3 1 write-only Reserved Reserved 4 12 read-write Reserved true ${period_name_0} The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time. 0x2 16 read-write ${period_name_0_reset_value} 0xffff ${period_name_1} 0x3 16 read-write ${period_name_1_reset_value} 0xffff ${period_snap_0} 0x4 16 read-write ${period_snap_0_reset_value} 0xffff ${period_snap_1} 0x5 16 read-write ${period_snap_1_reset_value} 0xffff ${snap_0} A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation. 0x6 16 read-write 0x0 0xffff ${snap_1} 0x7 16 read-write 0x0 0xffff ${snap_2} 0x8 16 read-write 0x0 0xffff ${snap_3} 0x9 16 read-write 0x0 0xffff niosII_jtag_uart_avalon_jtag_slave_altera_avalon_jtag_uart0x00000000 0x0 8 registers DATA Data Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost. 0x0 32 read-write 0x0 0xffffffff data The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO. 0x0 8 read-write rvalid Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined. 0xf 1 read-only ravail The number of characters remaining in the read FIFO (after the current read). 0x10 16 read-only CONTROL Control Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit. 0x4 32 read-write 0x0 0xffffffff re Interrupt-enable bit for read interrupts. 0x0 1 read-write we Interrupt-enable bit for write interrupts 0x1 1 read-write ri Indicates that the read interrupt is pending. 0x8 1 read-only wi Indicates that the write interrupt is pending. 0x9 1 read-only ac Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0. 0xa 1 read-write wspace The number of spaces available in the write FIFO 0x10 16 read-only