# system info niosII_tb on 2022.12.22.22:39:13
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1671734322
#
#
# Files generated for niosII_tb on 2022.12.22.22:39:13
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sem,dec
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source