`timescale 1 ns/1 ns

module inc_lut_tb();

	// Parameters
	localparam CLK_PRD = 20;
	localparam PHACC_WIDTH = 14;
	
	logic clk, clr_n, wr_n;
	logic [7:0] phinc_val, phase, sine;
		
	// Instantiate UUT and connect used ports
	phacc phacc(.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
	defparam phacc.WIDTH = PHACC_WIDTH;
	
	sinelut	sinelut_inst (
       .address (phase), .clock (clk), .q(sine)
	);


	// Clock definition
	initial begin
		clk = 0;
		forever #(CLK_PRD/2) clk = ~clk;
	end

	// Reset and initial values definition
	initial begin
		clr_n = 0;
		#(CLK_PRD*5) clr_n = 1;
	end
	
	// Bus write transaction simulation
	initial begin
		// Wait until system is out of reset
		@(posedge clr_n);
		
		phinc_val=(2**(PHACC_WIDTH - 8));
		if ((phinc_val <= 255) && (phinc_val != 0)) begin
          #(CLK_PRD * 256 * 5) $stop;
		end else begin
			$display("Error: value of phase increment is out of range! Stopped simulation.");
			#1 $stop;
		end
	end
endmodule