queue size: 0 starting:niosII "niosII" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 6 modules, 25 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 6 modules, 23 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 15 modules, 59 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave Transform merlin_domain_transform not run on matched interfaces sem_ctl_slave_translator.avalon_anti_slave_0 and sem.ctl_slave Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave Transform merlin_domain_transform not run on matched interfaces sem_ram_slave_translator.avalon_anti_slave_0 and sem.ram_slave Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1 Transform merlin_domain_transform not run on matched interfaces mem_s2_translator.avalon_anti_slave_0 and mem.s2 Transform merlin_domain_transform not run on matched interfaces mem_s1_translator.avalon_anti_slave_0 and mem.s1 32 modules, 174 connections]]> Transform: RouterTransform 41 modules, 210 connections]]> Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform 58 modules, 253 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform 60 modules, 312 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 7 modules, 29 connections]]> 7 modules, 29 connections]]> Transform: InterruptMapperTransform 8 modules, 33 connections]]> Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation 10 modules, 35 connections]]> niosII" reuses altera_nios2_gen2 "submodules/niosII_cpu"]]> niosII" reuses altera_avalon_jtag_uart "submodules/niosII_jtag_uart"]]> niosII" reuses altera_avalon_onchip_memory2 "submodules/niosII_mem"]]> niosII" reuses sem "submodules/dec"]]> niosII" reuses altera_avalon_timer "submodules/niosII_sys_clk_timer"]]> niosII" reuses altera_mm_interconnect "submodules/niosII_mm_interconnect_0"]]> niosII" reuses altera_irq_mapper "submodules/niosII_irq_mapper"]]> niosII" reuses altera_reset_controller "submodules/altera_reset_controller"]]> queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"]]> niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2022.12.24 01:16:53 (*) Starting Nios II generation # 2022.12.24 01:16:53 (*) Checking for plaintext license. # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty # 2022.12.24 01:16:54 (*) Plaintext license not found. # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings # 2022.12.24 01:16:54 (*) Creating all objects for CPU # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects # 2022.12.24 01:16:55 (*) Creating plain-text RTL # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> queue size: 5 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 54 modules, 178 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.027s Timing: COM:3/0.052s/0.076s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.002s Timing: ELA:1/0.011s Timing: COM:3/0.021s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.009s Timing: COM:3/0.019s/0.025s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.002s Timing: ELA:1/0.011s Timing: COM:3/0.021s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s Timing: COM:3/0.024s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.008s Timing: COM:3/0.019s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.011s Timing: COM:3/0.022s/0.028s 61 modules, 199 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> niosII" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper" niosII" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller" niosII" instantiated altera_reset_controller "rst_controller"]]> queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"]]> niosII" instantiated altera_nios2_gen2 "cpu"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2022.12.24 01:16:53 (*) Starting Nios II generation # 2022.12.24 01:16:53 (*) Checking for plaintext license. # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty # 2022.12.24 01:16:54 (*) Plaintext license not found. # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings # 2022.12.24 01:16:54 (*) Creating all objects for CPU # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects # 2022.12.24 01:16:55 (*) Creating plain-text RTL # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart" Starting RTL generation for module 'niosII_jtag_uart' Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_jtag_uart' niosII" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem" Starting RTL generation for module 'niosII_mem' Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_mem' niosII" instantiated altera_avalon_onchip_memory2 "mem"]]> queue size: 5 starting:sem "submodules/dec" niosII" instantiated sem "sem"]]> queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer" Starting RTL generation for module 'niosII_sys_clk_timer' Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'niosII_sys_clk_timer' niosII" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 54 modules, 178 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 54 modules, 178 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.027s Timing: COM:3/0.052s/0.076s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.002s Timing: ELA:1/0.011s Timing: COM:3/0.021s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.009s Timing: COM:3/0.019s/0.025s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.002s Timing: ELA:1/0.011s Timing: COM:3/0.021s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.010s Timing: COM:3/0.024s/0.032s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.008s Timing: COM:3/0.019s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.011s Timing: COM:3/0.022s/0.028s 61 modules, 199 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"]]> niosII" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper" niosII" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller" niosII" instantiated altera_reset_controller "rst_controller"]]> queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu" Starting RTL generation for module 'niosII_cpu_cpu' Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2022.12.24 01:16:53 (*) Starting Nios II generation # 2022.12.24 01:16:53 (*) Checking for plaintext license. # 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/ # 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty # 2022.12.24 01:16:54 (*) Plaintext license not found. # 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e. # 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings # 2022.12.24 01:16:54 (*) Creating all objects for CPU # 2022.12.24 01:16:55 (*) Generating RTL from CPU objects # 2022.12.24 01:16:55 (*) Creating plain-text RTL # 2022.12.24 01:16:56 (*) Done Nios II generation Done RTL generation for module 'niosII_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "cpu_data_master_translator"]]> queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004" mm_interconnect_0" instantiated altera_merlin_router "router_004"]]> queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008" mm_interconnect_0" instantiated altera_merlin_router "router_008"]]> queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]>