module phacc
  #(
    parameter unsigned WIDTH = 14
    ) (
	   input logic [7:0] phinc,
	   input             clk,
	   input             reset,
	   output [7:0]      phase
       );

    logic [WIDTH - 1 : 0] sum;

    always_ff @(posedge clk, negedge reset) begin
	    if (~reset) begin
		    sum <= 0;
	    end else begin
		    sum <= sum + phinc;
	    end
    end

    assign phase = sum[WIDTH - 1 : WIDTH - 8];

endmodule