# system info niosII_tb on 2023.01.27.19:00:20
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1674831618
#
#
# Files generated for niosII_tb on 2023.01.27.19:00:20
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sigdel_0,niosII_sigdel_0
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source