# TCL File Generated by Component Editor 18.1 # Tue Feb 07 16:48:35 MSK 2023 # DO NOT MODIFY # # sigdel "Sigma-Delta Modulator" v1.0 # 2023.02.07.16:48:35 # # # # request TCL package from ACDS 16.1 # package require -exact qsys 16.1 # # module sigdel # set_module_property DESCRIPTION "" set_module_property NAME sigdel set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP "User Logic" set_module_property AUTHOR "" set_module_property DISPLAY_NAME "Sigma-Delta Modulator" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif # # parameters # add_parameter PHACC_WIDTH INTEGER 14 set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14 set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH set_parameter_property PHACC_WIDTH TYPE INTEGER set_parameter_property PHACC_WIDTH UNITS None set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647 set_parameter_property PHACC_WIDTH HDL_PARAMETER true # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset_sink # add_interface reset_sink reset end set_interface_property reset_sink associatedClock clock set_interface_property reset_sink synchronousEdges DEASSERT set_interface_property reset_sink ENABLED true set_interface_property reset_sink EXPORT_OF "" set_interface_property reset_sink PORT_NAME_MAP "" set_interface_property reset_sink CMSIS_SVD_VARIABLES "" set_interface_property reset_sink SVD_ADDRESS_GROUP "" add_interface_port reset_sink clr_n reset_n Input 1 # # connection point conduit_end # add_interface conduit_end conduit end set_interface_property conduit_end associatedClock "" set_interface_property conduit_end associatedReset "" set_interface_property conduit_end ENABLED true set_interface_property conduit_end EXPORT_OF "" set_interface_property conduit_end PORT_NAME_MAP "" set_interface_property conduit_end CMSIS_SVD_VARIABLES "" set_interface_property conduit_end SVD_ADDRESS_GROUP "" add_interface_port conduit_end fout writeresponsevalid_n Output 1 # # connection point avalon_slave # add_interface avalon_slave avalon end set_interface_property avalon_slave addressUnits WORDS set_interface_property avalon_slave associatedClock clock set_interface_property avalon_slave associatedReset reset_sink set_interface_property avalon_slave bitsPerSymbol 8 set_interface_property avalon_slave burstOnBurstBoundariesOnly false set_interface_property avalon_slave burstcountUnits WORDS set_interface_property avalon_slave explicitAddressSpan 0 set_interface_property avalon_slave holdTime 0 set_interface_property avalon_slave linewrapBursts false set_interface_property avalon_slave maximumPendingReadTransactions 0 set_interface_property avalon_slave maximumPendingWriteTransactions 0 set_interface_property avalon_slave readLatency 0 set_interface_property avalon_slave readWaitTime 1 set_interface_property avalon_slave setupTime 0 set_interface_property avalon_slave timingUnits Cycles set_interface_property avalon_slave writeWaitTime 0 set_interface_property avalon_slave ENABLED true set_interface_property avalon_slave EXPORT_OF "" set_interface_property avalon_slave PORT_NAME_MAP "" set_interface_property avalon_slave CMSIS_SVD_VARIABLES "" set_interface_property avalon_slave SVD_ADDRESS_GROUP "" add_interface_port avalon_slave wr_n write_n Input 1 add_interface_port avalon_slave wr_data writedata Input 32 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0