24 lines
448 B
Systemverilog
24 lines
448 B
Systemverilog
module sdmod (
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input signed [7:0] val,
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input clk,
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input reset,
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output daco
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);
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logic out;
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logic signed [7:0] eps;
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logic signed [8:0] un;
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always_ff @(posedge clk, negedge reset) begin
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if (~reset) begin
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un <= 9'd0;
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end else begin
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un <= val - eps;
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end
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end
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assign out = (un >= $signed(9'd0)) ? 1'd1 : 1'd0;
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assign eps = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
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assign daco = out;
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endmodule
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