16 lines
659 B
VHDL
16 lines
659 B
VHDL
component niosII is
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port (
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clk_clk : in std_logic := 'X'; -- clk
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conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
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reset_reset_n : in std_logic := 'X' -- reset_n
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);
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end component niosII;
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u0 : component niosII
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port map (
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clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
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conduit_end_writeresponsevalid_n => CONNECTED_TO_conduit_end_writeresponsevalid_n, -- conduit_end.writeresponsevalid_n
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reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
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);
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