133 lines
2.1 KiB
Systemverilog
133 lines
2.1 KiB
Systemverilog
module dec
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#(m = 8)
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(
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//clock and reset
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input logic clk, clrn,
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//control slave
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input logic ctl_wr, ctl_rd,
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input logic ctl_addr,
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input logic [31:0] ctl_wrdata,
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output logic [31:0] ctl_rddata,
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//memory slave
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input logic ram_wr,
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input logic [1:0] ram_addr,
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input logic [31:0] ram_wrdata,
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//external ports
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input logic train,
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output logic red, yellow, green
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);
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logic run;
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logic [1:0] divider;
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logic [m-1:0] divisor;
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logic [1:0] contr;
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logic [2:0] colors;
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logic [m-1:0] cntdiv;
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logic enacnt;
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//control slave logic
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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run <= 0;
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divider <= 0;
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end
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else
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begin
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if (ctl_wr)
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begin
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case (ctl_addr)
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1'b0: run <= ctl_wrdata[0];
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1'b1: divider <= ctl_wrdata[1:0];
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endcase
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end
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end
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end
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always_comb
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begin
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case (ctl_addr)
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1'b0: ctl_rddata = {31'b0,run};
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1'b1: ctl_rddata = {30'b0,divider};
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default: ctl_rddata = 'bx;
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endcase
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end
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//semaphore logic
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn) cntdiv<=0;
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else
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begin
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if (train | ~run) cntdiv<=0;
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else
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begin
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if (enacnt) cntdiv<=0;
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else cntdiv<=cntdiv+1;
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end
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end
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end
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always_comb
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begin
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enacnt=(cntdiv==divisor);
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end
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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colors <= 3'b100;
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end
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else
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begin
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if (train | ~run)
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begin
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colors <= 3'b100;
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end
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else
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begin
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if (enacnt)
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begin
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case (colors)
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3'b100: colors <= 3'b010;
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3'b010: colors <= 3'b011;
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3'b011: colors <= 3'b001;
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3'b001: colors <= 3'b001;
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default: colors <= 3'b100;
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endcase
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end
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end
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end
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end
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always_comb
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begin
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case (colors)
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3'b100: contr = 2'b00;
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3'b010: contr = 2'b01;
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3'b011: contr = 2'b10;
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3'b001: contr = 2'b11;
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default : contr = 2'b00;
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endcase
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end
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assign red = colors[2];
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assign yellow = colors[1];
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assign green = colors[0];
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periodram b2v_inst3(
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.clock(clk),
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.data (ram_wrdata),
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.wraddress (ram_addr),
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.wren (ram_wr),
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.rdaddress({divider,contr}),
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.q(divisor)
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);
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endmodule
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