ivan-igorevich
/
fpga-lab-2
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
23 Commits 3 Branches 0 Tags 2.3 MiB
Verilog 67.2%
SystemVerilog 23%
HTML 8.8%
Tcl 0.7%
Stata 0.1%
Go to file
Ivan I. Ovchinnikov 22f16bc090 wip lab4, tested module 2023-01-27 17:06:29 +03:00
HDL wip lab4, tested module 2023-01-27 17:06:29 +03:00
Testbench wip lab4, tested module 2023-01-27 17:06:29 +03:00
Top wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
.gitignore wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00