fpga-lab-2/HDL/IP
Ivan I. Ovchinnikov 3b13bb1166 wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
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periodram.qip done in hardware 2023-01-24 12:46:22 +03:00
periodram.v done in hardware 2023-01-24 12:46:22 +03:00
periodram_inst.v done in hardware 2023-01-24 12:46:22 +03:00
sine256.mif wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sinelut.qip wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sinelut.v wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sinelut_bb.v wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sinelut_inst.v wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00