300 lines
28 KiB
Verilog
300 lines
28 KiB
Verilog
// niosII.v
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module niosII (
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input wire clk_clk, // clk.clk
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input wire reset_reset_n, // reset.reset_n
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input wire sem_export_train, // sem_export.train
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output wire sem_export_red, // .red
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output wire sem_export_yellow, // .yellow
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output wire sem_export_green // .green
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);
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wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
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wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
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wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
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wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
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wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
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wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
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wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
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wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
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wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
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wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
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wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
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wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
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wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
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wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
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wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
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wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
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wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
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wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
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wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
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wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
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wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
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wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
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wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
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wire [8:0] mm_interconnect_0_cpu_debug_mem_slave_address; // mm_interconnect_0:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address
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wire mm_interconnect_0_cpu_debug_mem_slave_read; // mm_interconnect_0:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read
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wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
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wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
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wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
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wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
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wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
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wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
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wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
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wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
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wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
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wire mm_interconnect_0_sys_clk_timer_s1_write; // mm_interconnect_0:sys_clk_timer_s1_write -> sys_clk_timer:write_n
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wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
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wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
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wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
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wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
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wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
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wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2
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wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
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wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2
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wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
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wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata
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wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
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wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
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wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write
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wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata
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wire mm_interconnect_0_mem_s1_clken; // mm_interconnect_0:mem_s1_clken -> mem:clken
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wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
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wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
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wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
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wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
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wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
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niosII_cpu cpu (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
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.reset_req (rst_controller_reset_out_reset_req), // .reset_req
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.d_address (cpu_data_master_address), // data_master.address
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.d_byteenable (cpu_data_master_byteenable), // .byteenable
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.d_read (cpu_data_master_read), // .read
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.d_readdata (cpu_data_master_readdata), // .readdata
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.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
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.d_write (cpu_data_master_write), // .write
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.d_writedata (cpu_data_master_writedata), // .writedata
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.debug_mem_slave_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
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.i_address (cpu_instruction_master_address), // instruction_master.address
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.i_read (cpu_instruction_master_read), // .read
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.i_readdata (cpu_instruction_master_readdata), // .readdata
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.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
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.irq (cpu_irq_irq), // irq.irq
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.debug_reset_request (cpu_debug_reset_request_reset), // debug_reset_request.reset
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.debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // debug_mem_slave.address
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.debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable
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.debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess
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.debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read
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.debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata
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.debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest
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.debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write
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.debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata
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.dummy_ci_port () // custom_instruction_master.readra
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);
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niosII_jtag_uart jtag_uart (
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.clk (clk_clk), // clk.clk
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.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
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.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
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.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
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.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
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.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
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.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
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.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
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.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
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.av_irq (irq_mapper_receiver1_irq) // irq.irq
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);
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niosII_mem mem (
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.address (mm_interconnect_0_mem_s1_address), // s1.address
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.clken (mm_interconnect_0_mem_s1_clken), // .clken
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.chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect
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.write (mm_interconnect_0_mem_s1_write), // .write
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.readdata (mm_interconnect_0_mem_s1_readdata), // .readdata
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.writedata (mm_interconnect_0_mem_s1_writedata), // .writedata
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.byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable
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.address2 (mm_interconnect_0_mem_s2_address), // s2.address
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.chipselect2 (mm_interconnect_0_mem_s2_chipselect), // .chipselect
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.clken2 (mm_interconnect_0_mem_s2_clken), // .clken
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.write2 (mm_interconnect_0_mem_s2_write), // .write
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.readdata2 (mm_interconnect_0_mem_s2_readdata), // .readdata
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.writedata2 (mm_interconnect_0_mem_s2_writedata), // .writedata
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.byteenable2 (mm_interconnect_0_mem_s2_byteenable), // .byteenable
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.clk (clk_clk), // clk1.clk
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.reset (rst_controller_reset_out_reset), // reset1.reset
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.reset_req (rst_controller_reset_out_reset_req), // .reset_req
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.freeze (1'b0) // (terminated)
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);
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dec #(
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.m (32)
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) sem (
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.clk (clk_clk), // clock.clk
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.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write
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.ctl_rd (mm_interconnect_0_sem_ctl_slave_read), // .read
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.ctl_addr (mm_interconnect_0_sem_ctl_slave_address), // .address
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.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
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.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
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.clrn (~rst_controller_reset_out_reset), // reset_n.reset_n
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.ram_wr (mm_interconnect_0_sem_ram_slave_write), // ram_slave.write
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.ram_addr (mm_interconnect_0_sem_ram_slave_address), // .address
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.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
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.train (sem_export_train), // sem.train
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.red (sem_export_red), // .red
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.yellow (sem_export_yellow), // .yellow
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.green (sem_export_green) // .green
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);
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niosII_sys_clk_timer sys_clk_timer (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
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.address (mm_interconnect_0_sys_clk_timer_s1_address), // s1.address
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.writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata
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.readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata
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.chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect), // .chipselect
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.write_n (~mm_interconnect_0_sys_clk_timer_s1_write), // .write_n
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.irq (irq_mapper_receiver0_irq) // irq.irq
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);
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niosII_mm_interconnect_0 mm_interconnect_0 (
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.clk_clk_clk (clk_clk), // clk_clk.clk
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.cpu_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_reset_reset_bridge_in_reset.reset
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.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
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.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
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.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
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.cpu_data_master_read (cpu_data_master_read), // .read
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.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
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.cpu_data_master_write (cpu_data_master_write), // .write
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.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
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.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
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.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
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.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
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.cpu_instruction_master_read (cpu_instruction_master_read), // .read
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.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
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.cpu_debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // cpu_debug_mem_slave.address
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.cpu_debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write
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.cpu_debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read
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.cpu_debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata
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.cpu_debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata
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.cpu_debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable
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.cpu_debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest
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.cpu_debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess
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.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
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.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
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.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
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.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
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.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
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.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
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.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
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.mem_s1_address (mm_interconnect_0_mem_s1_address), // mem_s1.address
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.mem_s1_write (mm_interconnect_0_mem_s1_write), // .write
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.mem_s1_readdata (mm_interconnect_0_mem_s1_readdata), // .readdata
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.mem_s1_writedata (mm_interconnect_0_mem_s1_writedata), // .writedata
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.mem_s1_byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable
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.mem_s1_chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect
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.mem_s1_clken (mm_interconnect_0_mem_s1_clken), // .clken
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.mem_s2_address (mm_interconnect_0_mem_s2_address), // mem_s2.address
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.mem_s2_write (mm_interconnect_0_mem_s2_write), // .write
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.mem_s2_readdata (mm_interconnect_0_mem_s2_readdata), // .readdata
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.mem_s2_writedata (mm_interconnect_0_mem_s2_writedata), // .writedata
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.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
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.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
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.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
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.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
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.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
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.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
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.sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
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.sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
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.sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address
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.sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write
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.sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
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.sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address
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.sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write
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.sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata
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.sys_clk_timer_s1_writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata
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.sys_clk_timer_s1_chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect) // .chipselect
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);
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niosII_irq_mapper irq_mapper (
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.clk (clk_clk), // clk.clk
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.reset (rst_controller_reset_out_reset), // clk_reset.reset
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.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
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.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
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.sender_irq (cpu_irq_irq) // sender.irq
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);
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altera_reset_controller #(
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.NUM_RESET_INPUTS (2),
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.OUTPUT_RESET_SYNC_EDGES ("deassert"),
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.SYNC_DEPTH (2),
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.RESET_REQUEST_PRESENT (1),
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.RESET_REQ_WAIT_TIME (1),
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.MIN_RST_ASSERTION_TIME (3),
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.RESET_REQ_EARLY_DSRT_TIME (1),
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.USE_RESET_REQUEST_IN0 (0),
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.USE_RESET_REQUEST_IN1 (0),
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.USE_RESET_REQUEST_IN2 (0),
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.USE_RESET_REQUEST_IN3 (0),
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.USE_RESET_REQUEST_IN4 (0),
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.USE_RESET_REQUEST_IN5 (0),
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.USE_RESET_REQUEST_IN6 (0),
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.USE_RESET_REQUEST_IN7 (0),
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.USE_RESET_REQUEST_IN8 (0),
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.USE_RESET_REQUEST_IN9 (0),
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.USE_RESET_REQUEST_IN10 (0),
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.USE_RESET_REQUEST_IN11 (0),
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.USE_RESET_REQUEST_IN12 (0),
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.USE_RESET_REQUEST_IN13 (0),
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.USE_RESET_REQUEST_IN14 (0),
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.USE_RESET_REQUEST_IN15 (0),
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.ADAPT_RESET_REQUEST (0)
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) rst_controller (
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.reset_in0 (~reset_reset_n), // reset_in0.reset
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.reset_in1 (cpu_debug_reset_request_reset), // reset_in1.reset
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.clk (clk_clk), // clk.clk
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.reset_out (rst_controller_reset_out_reset), // reset_out.reset
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.reset_req (rst_controller_reset_out_reset_req), // .reset_req
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.reset_req_in0 (1'b0), // (terminated)
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.reset_req_in1 (1'b0), // (terminated)
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.reset_in2 (1'b0), // (terminated)
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|
.reset_req_in2 (1'b0), // (terminated)
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|
.reset_in3 (1'b0), // (terminated)
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|
.reset_req_in3 (1'b0), // (terminated)
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|
.reset_in4 (1'b0), // (terminated)
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|
.reset_req_in4 (1'b0), // (terminated)
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|
.reset_in5 (1'b0), // (terminated)
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|
.reset_req_in5 (1'b0), // (terminated)
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|
.reset_in6 (1'b0), // (terminated)
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|
.reset_req_in6 (1'b0), // (terminated)
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|
.reset_in7 (1'b0), // (terminated)
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|
.reset_req_in7 (1'b0), // (terminated)
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|
.reset_in8 (1'b0), // (terminated)
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|
.reset_req_in8 (1'b0), // (terminated)
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|
.reset_in9 (1'b0), // (terminated)
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|
.reset_req_in9 (1'b0), // (terminated)
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|
.reset_in10 (1'b0), // (terminated)
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|
.reset_req_in10 (1'b0), // (terminated)
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|
.reset_in11 (1'b0), // (terminated)
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|
.reset_req_in11 (1'b0), // (terminated)
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|
.reset_in12 (1'b0), // (terminated)
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|
.reset_req_in12 (1'b0), // (terminated)
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|
.reset_in13 (1'b0), // (terminated)
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|
.reset_req_in13 (1'b0), // (terminated)
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|
.reset_in14 (1'b0), // (terminated)
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|
.reset_req_in14 (1'b0), // (terminated)
|
|
.reset_in15 (1'b0), // (terminated)
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|
.reset_req_in15 (1'b0) // (terminated)
|
|
);
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|
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|
endmodule
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