129 lines
2.8 KiB
Systemverilog
129 lines
2.8 KiB
Systemverilog
`timescale 1 ns/1 ns
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module dec_tb();
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// Wires and variables to connect to UUT (unit under test)
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logic clk, clrn, train;
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logic r, y, g;
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logic [1:0] div;
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logic ctl_wr, ctl_rd;
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logic ctl_addr;
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logic [31:0] ctl_wrdata;
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logic [31:0] ctl_rddata;
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logic ram_wr;
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logic [1:0] ram_addr;
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logic [31:0] ram_wrdata;
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logic [31:0] divisor[3:0] = {
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{8'd10, 8'd70, 8'd50, 8'd20},
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{8'd10, 8'd30, 8'd40, 8'd30},
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{8'd10, 8'd30, 8'd10, 8'd100},
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{8'd10, 8'd60, 8'd80, 8'd50}
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};
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// Instantiate UUT
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dec my_sem(
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.clk(clk), .clrn(clrn),
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.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
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.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
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.ram_wr(ram_wr),
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.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
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.train(train), .red(r), .yellow(y), .green(g)
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);
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// Clock definition
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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// Divisor and train definition
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initial begin
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//initial reset
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clrn = 0;
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div = 0;
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train = 0;
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//take reset off
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@(negedge clk) clrn = 1;
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//configure semaphore
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for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
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write_reg_transaction(1,div); //write initial divisor
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write_reg_transaction(0,1); //enable semaphore
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//run trains
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repeat (4)
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begin
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repeat (10) @(posedge clk);
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train=1;
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repeat (4) @(posedge clk);
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train=0;
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wait ({r,y,g}==3'b001);
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repeat (10) @(posedge clk);
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write_reg_transaction(1,div);
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div=div+1;
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end
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//wait a little
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repeat (10) @(posedge clk);
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$stop;
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end
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//Single register write transaction task
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task write_reg_transaction;
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//input signals
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input [1:0] offs;
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input [31:0] val;
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//transaction implementation
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begin
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@(posedge clk);
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//assert signals for one clock cycle
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ctl_wr = 1;
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ctl_addr = offs;
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ctl_wrdata = val;
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@(posedge clk);
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//deassert signals
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ctl_wr = 0;
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ctl_addr = 'bx;
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ctl_wrdata = 'bx;
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end
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endtask
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//Single register read transaction task
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task read_reg_transaction;
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//input signals
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input [1:0] offs;
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output [31:0] val;
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//transaction implementation
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begin
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@(posedge clk);
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//assert signals for one clock cycle
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ctl_rd = 1;
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ctl_addr = offs;
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@(posedge clk);
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val = ctl_rddata;
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//deassert signals
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ctl_rd = 0;
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ctl_addr = 'bx;
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end
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endtask
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//RAM write transaction task
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task write_ram_transaction;
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//input signals
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input [1:0] offs;
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input [31:0] val;
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//transaction implementation
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begin
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@(posedge clk);
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//assert signals for one clock cycle
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ram_wr = 1;
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ram_addr = offs;
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ram_wrdata = val;
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@(posedge clk);
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//deassert signals
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ram_wr = 0;
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ram_addr = 'bx;
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ram_wrdata = 'bx;
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end
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endtask
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endmodule
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