191 lines
6.6 KiB
Tcl
191 lines
6.6 KiB
Tcl
# TCL File Generated by Component Editor 18.1
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# Wed Dec 21 21:00:10 MSK 2022
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# DO NOT MODIFY
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#
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# sem "Semafor" v1.1
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# 2022.12.21.21:00:10
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module sem
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME sem
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set_module_property VERSION 1.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "User Logic"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME Semafor
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL dec
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
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add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG TOP_LEVEL dec
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
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add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
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#
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# parameters
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#
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add_parameter m INTEGER 32 ""
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set_parameter_property m DEFAULT_VALUE 32
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set_parameter_property m DISPLAY_NAME m
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set_parameter_property m TYPE INTEGER
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set_parameter_property m UNITS None
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set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
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set_parameter_property m DESCRIPTION ""
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set_parameter_property m HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point ctl_slave
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#
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add_interface ctl_slave avalon end
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set_interface_property ctl_slave addressUnits WORDS
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set_interface_property ctl_slave associatedClock clock
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set_interface_property ctl_slave associatedReset reset_n
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set_interface_property ctl_slave bitsPerSymbol 8
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set_interface_property ctl_slave burstOnBurstBoundariesOnly false
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set_interface_property ctl_slave burstcountUnits WORDS
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set_interface_property ctl_slave explicitAddressSpan 0
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set_interface_property ctl_slave holdTime 0
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set_interface_property ctl_slave linewrapBursts false
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set_interface_property ctl_slave maximumPendingReadTransactions 0
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set_interface_property ctl_slave maximumPendingWriteTransactions 0
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set_interface_property ctl_slave readLatency 0
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set_interface_property ctl_slave readWaitStates 0
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set_interface_property ctl_slave readWaitTime 0
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set_interface_property ctl_slave setupTime 0
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set_interface_property ctl_slave timingUnits Cycles
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set_interface_property ctl_slave writeWaitTime 0
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set_interface_property ctl_slave ENABLED true
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set_interface_property ctl_slave EXPORT_OF ""
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set_interface_property ctl_slave PORT_NAME_MAP ""
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set_interface_property ctl_slave CMSIS_SVD_VARIABLES ""
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set_interface_property ctl_slave SVD_ADDRESS_GROUP ""
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add_interface_port ctl_slave ctl_wr write Input 1
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add_interface_port ctl_slave ctl_rd read Input 1
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add_interface_port ctl_slave ctl_addr address Input 1
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add_interface_port ctl_slave ctl_wrdata writedata Input 32
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add_interface_port ctl_slave ctl_rddata readdata Output 32
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set_interface_assignment ctl_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment ctl_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ctl_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment ctl_slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point reset_n
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#
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add_interface reset_n reset end
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set_interface_property reset_n associatedClock clock
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set_interface_property reset_n synchronousEdges DEASSERT
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set_interface_property reset_n ENABLED true
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set_interface_property reset_n EXPORT_OF ""
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set_interface_property reset_n PORT_NAME_MAP ""
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set_interface_property reset_n CMSIS_SVD_VARIABLES ""
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set_interface_property reset_n SVD_ADDRESS_GROUP ""
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add_interface_port reset_n clrn reset_n Input 1
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#
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# connection point ram_slave
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#
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add_interface ram_slave avalon end
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set_interface_property ram_slave addressUnits WORDS
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set_interface_property ram_slave associatedClock clock
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set_interface_property ram_slave associatedReset reset_n
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set_interface_property ram_slave bitsPerSymbol 8
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set_interface_property ram_slave burstOnBurstBoundariesOnly false
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set_interface_property ram_slave burstcountUnits WORDS
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set_interface_property ram_slave explicitAddressSpan 0
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set_interface_property ram_slave holdTime 0
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set_interface_property ram_slave linewrapBursts false
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set_interface_property ram_slave maximumPendingReadTransactions 0
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set_interface_property ram_slave maximumPendingWriteTransactions 0
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set_interface_property ram_slave readLatency 0
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set_interface_property ram_slave readWaitTime 1
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set_interface_property ram_slave setupTime 0
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set_interface_property ram_slave timingUnits Cycles
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set_interface_property ram_slave writeWaitTime 0
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set_interface_property ram_slave ENABLED true
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set_interface_property ram_slave EXPORT_OF ""
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set_interface_property ram_slave PORT_NAME_MAP ""
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set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
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set_interface_property ram_slave SVD_ADDRESS_GROUP ""
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add_interface_port ram_slave ram_wr write Input 1
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add_interface_port ram_slave ram_addr address Input 2
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add_interface_port ram_slave ram_wrdata writedata Input 32
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set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ram_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment ram_slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point sem
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#
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add_interface sem conduit end
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set_interface_property sem associatedClock ""
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set_interface_property sem associatedReset reset_n
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set_interface_property sem ENABLED true
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set_interface_property sem EXPORT_OF ""
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set_interface_property sem PORT_NAME_MAP ""
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set_interface_property sem CMSIS_SVD_VARIABLES ""
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set_interface_property sem SVD_ADDRESS_GROUP ""
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add_interface_port sem train train Input 1
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add_interface_port sem red red Output 1
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add_interface_port sem yellow yellow Output 1
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add_interface_port sem green green Output 1
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