fpga-lab-2/Testbench/dec
Ivan I. Ovchinnikov 77e2cf25d3 Merge remote-tracking branch 'my/simulation' into simulation preferring their
# Conflicts:
#	Top/niosII.sopcinfo
#	Top/semafor.qws
#	Top/software/semafor/.settings/language.settings.xml
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
#	Top/software/semafor/mem_init/niosII_mem.hex
#	Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
#	Top/software/semafor/sem.c
#	Top/software/semafor_bsp/.settings/language.settings.xml
#	Top/software/semafor_bsp/libhal_bsp.a
#	Top/software/semafor_bsp/settings.bsp
#	Top/software/semafor_bsp/summary.html
2023-01-24 15:05:03 +03:00
..
#dec_tb.sv# simulated individual, looks ok 2022-12-24 02:08:20 +03:00
.gitignore done in hardware 2023-01-24 12:46:22 +03:00
dec.qsf done in hardware 2023-01-24 12:46:22 +03:00
dec.qws trailing files 2023-01-18 16:51:49 +03:00
dec_tb.sv done in hardware 2023-01-24 12:46:22 +03:00
periodram.hex done in hardware 2023-01-24 12:46:22 +03:00
semafor.qpf done in hardware 2023-01-24 12:46:22 +03:00
wave.do done in hardware 2023-01-24 12:46:22 +03:00