22 lines
884 B
VHDL
22 lines
884 B
VHDL
component niosII is
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port (
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clk_clk : in std_logic := 'X'; -- clk
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reset_reset_n : in std_logic := 'X'; -- reset_n
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sem_export_train : in std_logic := 'X'; -- train
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sem_export_red : out std_logic; -- red
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sem_export_yellow : out std_logic; -- yellow
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sem_export_green : out std_logic -- green
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);
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end component niosII;
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u0 : component niosII
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port map (
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clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
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reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
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sem_export_train => CONNECTED_TO_sem_export_train, -- sem_export.train
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sem_export_red => CONNECTED_TO_sem_export_red, -- .red
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sem_export_yellow => CONNECTED_TO_sem_export_yellow, -- .yellow
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sem_export_green => CONNECTED_TO_sem_export_green -- .green
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);
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