fpga-lab-2/Top/niosII_tb.spd

<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
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   type="SYSTEM_VERILOG"
   library="altera_common_sv_packages"
   systemVerilogPackageName="avalon_vip_verbosity_pkg" />
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   type="SYSTEM_VERILOG"
   library="error_adapter_0" />
 <file
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   type="VERILOG"
   library="avalon_st_adapter" />
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   type="SYSTEM_VERILOG"
   library="rsp_mux_001" />
 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
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 <file
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   type="SYSTEM_VERILOG"
   library="rsp_demux" />
 <file
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 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
   type="SYSTEM_VERILOG"
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 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
   type="SYSTEM_VERILOG"
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   library="cpu" />
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   library="cpu" />
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   library="cpu" />
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   library="rst_controller" />
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   type="VERILOG"
   library="rst_controller" />
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   library="rst_controller" />
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   type="SYSTEM_VERILOG"
   library="irq_mapper" />
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   type="VERILOG"
   library="mm_interconnect_0" />
 <file
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   type="VERILOG"
   library="sys_clk_timer" />
 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/dec.sv"
   type="SYSTEM_VERILOG"
   library="sem" />
 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/periodram.v"
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   library="sem" />
 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
   type="HEX"
   library="mem" />
 <file
   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
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   library="mem" />
 <file
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   library="jtag_uart" />
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   library="cpu" />
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   type="SYSTEM_VERILOG"
   library="niosII_inst_reset_bfm" />
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   library="niosII_inst_clk_bfm" />
 <file
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   type="VERILOG"
   library="niosII_inst" />
 <file
   path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
   type="VERILOG" />
 <topLevel name="niosII_tb" />
 <deviceFamily name="cycloneive" />
 <modelMap
   controllerPath="niosII_tb.niosII_inst.mem"
   modelPath="niosII_tb.niosII_inst.mem" />
</simPackage>