53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
module top
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//(
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// input logic clk,
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// input logic train,
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// output logic green,
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// output logic red,
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// output logic yellow
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//);
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//
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// niosII u0 (
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// .clk_clk (clk), // clk.clk
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// .reset_reset_n (1'b1), // reset.reset_n
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// .sem_export_train (~train), // sem_export.train
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// .sem_export_red (red), // .red
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// .sem_export_yellow (yellow), // .yellow
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// .sem_export_green (green) // .green
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// );
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(
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//////////// CLOCK //////////
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CLOCK_50,
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CLOCK2_50,
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CLOCK3_50,
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//////////// LED //////////
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LEDG,
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LEDR,
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FOUTA
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);
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output FOUTA;
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//////////// CLOCK //////////
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input CLOCK_50;
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input CLOCK2_50;
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input CLOCK3_50;
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//////////// LED //////////
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output [8:0] LEDG;
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output [17:0] LEDR;
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niosII u0 (
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.clk_clk (CLOCK_50), // clk.clk
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.conduit_end_writeresponsevalid_n (LEDG[0]), // conduit_end.writeresponsevalid_n
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.reset_reset_n (1'b1) // reset.reset_n
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);
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assign LEDG[7:1] = 1'b0;
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assign LEDR[17:0] = 1'b0;
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assign FOUTA = LEDG[0];
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endmodule
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