fpga-lab-2/Top/niosII/testbench/synopsys/vcsmx/synopsys_sim.setup

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WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_common_sv_packages: ./libraries/altera_common_sv_packages/
error_adapter_0: ./libraries/error_adapter_0/
avalon_st_adapter: ./libraries/avalon_st_adapter/
rsp_mux_001: ./libraries/rsp_mux_001/
rsp_mux: ./libraries/rsp_mux/
rsp_demux: ./libraries/rsp_demux/
cmd_mux_002: ./libraries/cmd_mux_002/
cmd_mux: ./libraries/cmd_mux/
cmd_demux_001: ./libraries/cmd_demux_001/
cmd_demux: ./libraries/cmd_demux/
router_008: ./libraries/router_008/
router_004: ./libraries/router_004/
router_002: ./libraries/router_002/
router_001: ./libraries/router_001/
router: ./libraries/router/
jtag_uart_avalon_jtag_slave_agent_rsp_fifo: ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
jtag_uart_avalon_jtag_slave_agent: ./libraries/jtag_uart_avalon_jtag_slave_agent/
cpu_data_master_agent: ./libraries/cpu_data_master_agent/
jtag_uart_avalon_jtag_slave_translator: ./libraries/jtag_uart_avalon_jtag_slave_translator/
cpu_data_master_translator: ./libraries/cpu_data_master_translator/
cpu: ./libraries/cpu/
rst_controller: ./libraries/rst_controller/
irq_mapper: ./libraries/irq_mapper/
mm_interconnect_0: ./libraries/mm_interconnect_0/
sys_clk_timer: ./libraries/sys_clk_timer/
sem: ./libraries/sem/
mem: ./libraries/mem/
jtag_uart: ./libraries/jtag_uart/
niosII_inst_reset_bfm: ./libraries/niosII_inst_reset_bfm/
niosII_inst_clk_bfm: ./libraries/niosII_inst_clk_bfm/
niosII_inst: ./libraries/niosII_inst/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cycloneive_ver: ./libraries/cycloneive_ver/