39 lines
706 B
Plaintext
39 lines
706 B
Plaintext
# -*- mode: snippet -*-
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# name: testbench
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# key: tb
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# --
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`timescale 1 ns/1 ns
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// `timescale 10 ps/10 ps
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module $1_tb();
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logic clk, clr;
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// Instantiate UUT
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$1 UUT (.clk(clk), .reset(clr),
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//add more custom signals here
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);
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// Clock definition
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initial begin
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clk = 0;
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forever #25 clk = ~clk; // 20MHz
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end
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// reset signal definition
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initial begin
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clr = 0;
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repeat(100)@(posedge clk); // wait 100 clock periods
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clr = 1;
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end
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initial begin
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repeat(120)@(posedge clk); // wait 120 clock periods (reset + a bit more)
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// do useful things here
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repeat(10)@(posedge clk);
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$stop;
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end
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endmodule
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