fpga-lab-2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v

// niosII_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module niosII_mm_interconnect_0 (
		input  wire        clk_clk_clk,                              //                         clk_clk.clk
		input  wire        cpu_reset_reset_bridge_in_reset_reset,    // cpu_reset_reset_bridge_in_reset.reset
		input  wire [17:0] cpu_data_master_address,                  //                 cpu_data_master.address
		output wire        cpu_data_master_waitrequest,              //                                .waitrequest
		input  wire [3:0]  cpu_data_master_byteenable,               //                                .byteenable
		input  wire        cpu_data_master_read,                     //                                .read
		output wire [31:0] cpu_data_master_readdata,                 //                                .readdata
		input  wire        cpu_data_master_write,                    //                                .write
		input  wire [31:0] cpu_data_master_writedata,                //                                .writedata
		input  wire        cpu_data_master_debugaccess,              //                                .debugaccess
		input  wire [17:0] cpu_instruction_master_address,           //          cpu_instruction_master.address
		output wire        cpu_instruction_master_waitrequest,       //                                .waitrequest
		input  wire        cpu_instruction_master_read,              //                                .read
		output wire [31:0] cpu_instruction_master_readdata,          //                                .readdata
		output wire [8:0]  cpu_debug_mem_slave_address,              //             cpu_debug_mem_slave.address
		output wire        cpu_debug_mem_slave_write,                //                                .write
		output wire        cpu_debug_mem_slave_read,                 //                                .read
		input  wire [31:0] cpu_debug_mem_slave_readdata,             //                                .readdata
		output wire [31:0] cpu_debug_mem_slave_writedata,            //                                .writedata
		output wire [3:0]  cpu_debug_mem_slave_byteenable,           //                                .byteenable
		input  wire        cpu_debug_mem_slave_waitrequest,          //                                .waitrequest
		output wire        cpu_debug_mem_slave_debugaccess,          //                                .debugaccess
		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,      //     jtag_uart_avalon_jtag_slave.address
		output wire        jtag_uart_avalon_jtag_slave_write,        //                                .write
		output wire        jtag_uart_avalon_jtag_slave_read,         //                                .read
		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,     //                                .readdata
		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,    //                                .writedata
		input  wire        jtag_uart_avalon_jtag_slave_waitrequest,  //                                .waitrequest
		output wire        jtag_uart_avalon_jtag_slave_chipselect,   //                                .chipselect
		output wire [14:0] mem_s1_address,                           //                          mem_s1.address
		output wire        mem_s1_write,                             //                                .write
		input  wire [31:0] mem_s1_readdata,                          //                                .readdata
		output wire [31:0] mem_s1_writedata,                         //                                .writedata
		output wire [3:0]  mem_s1_byteenable,                        //                                .byteenable
		output wire        mem_s1_chipselect,                        //                                .chipselect
		output wire        mem_s1_clken,                             //                                .clken
		output wire [14:0] mem_s2_address,                           //                          mem_s2.address
		output wire        mem_s2_write,                             //                                .write
		input  wire [31:0] mem_s2_readdata,                          //                                .readdata
		output wire [31:0] mem_s2_writedata,                         //                                .writedata
		output wire [3:0]  mem_s2_byteenable,                        //                                .byteenable
		output wire        mem_s2_chipselect,                        //                                .chipselect
		output wire        mem_s2_clken,                             //                                .clken
		output wire [3:0]  perf_counter_control_slave_address,       //      perf_counter_control_slave.address
		output wire        perf_counter_control_slave_write,         //                                .write
		input  wire [31:0] perf_counter_control_slave_readdata,      //                                .readdata
		output wire [31:0] perf_counter_control_slave_writedata,     //                                .writedata
		output wire        perf_counter_control_slave_begintransfer, //                                .begintransfer
		output wire [0:0]  sem_ctl_slave_address,                    //                   sem_ctl_slave.address
		output wire        sem_ctl_slave_write,                      //                                .write
		output wire        sem_ctl_slave_read,                       //                                .read
		input  wire [31:0] sem_ctl_slave_readdata,                   //                                .readdata
		output wire [31:0] sem_ctl_slave_writedata,                  //                                .writedata
		output wire [3:0]  sem_ram_slave_address,                    //                   sem_ram_slave.address
		output wire        sem_ram_slave_write,                      //                                .write
		output wire [31:0] sem_ram_slave_writedata,                  //                                .writedata
		output wire [2:0]  sys_clk_timer_s1_address,                 //                sys_clk_timer_s1.address
		output wire        sys_clk_timer_s1_write,                   //                                .write
		input  wire [15:0] sys_clk_timer_s1_readdata,                //                                .readdata
		output wire [15:0] sys_clk_timer_s1_writedata,               //                                .writedata
		output wire        sys_clk_timer_s1_chipselect               //                                .chipselect
	);

	wire         cpu_data_master_translator_avalon_universal_master_0_waitrequest;          // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
	wire  [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata;             // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
	wire         cpu_data_master_translator_avalon_universal_master_0_debugaccess;          // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
	wire  [17:0] cpu_data_master_translator_avalon_universal_master_0_address;              // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
	wire         cpu_data_master_translator_avalon_universal_master_0_read;                 // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
	wire   [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable;           // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
	wire         cpu_data_master_translator_avalon_universal_master_0_readdatavalid;        // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
	wire         cpu_data_master_translator_avalon_universal_master_0_lock;                 // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
	wire         cpu_data_master_translator_avalon_universal_master_0_write;                // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
	wire  [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata;            // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
	wire   [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount;           // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
	wire         rsp_mux_src_valid;                                                         // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
	wire  [93:0] rsp_mux_src_data;                                                          // rsp_mux:src_data -> cpu_data_master_agent:rp_data
	wire         rsp_mux_src_ready;                                                         // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
	wire   [7:0] rsp_mux_src_channel;                                                       // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
	wire         rsp_mux_src_startofpacket;                                                 // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
	wire         rsp_mux_src_endofpacket;                                                   // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
	wire         cpu_instruction_master_translator_avalon_universal_master_0_waitrequest;   // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
	wire  [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata;      // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
	wire         cpu_instruction_master_translator_avalon_universal_master_0_debugaccess;   // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
	wire  [17:0] cpu_instruction_master_translator_avalon_universal_master_0_address;       // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
	wire         cpu_instruction_master_translator_avalon_universal_master_0_read;          // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
	wire   [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable;    // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
	wire         cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
	wire         cpu_instruction_master_translator_avalon_universal_master_0_lock;          // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
	wire         cpu_instruction_master_translator_avalon_universal_master_0_write;         // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
	wire  [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata;     // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
	wire   [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount;    // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
	wire         rsp_mux_001_src_valid;                                                     // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
	wire  [93:0] rsp_mux_001_src_data;                                                      // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
	wire         rsp_mux_001_src_ready;                                                     // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
	wire   [7:0] rsp_mux_001_src_channel;                                                   // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
	wire         rsp_mux_001_src_startofpacket;                                             // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
	wire         rsp_mux_001_src_endofpacket;                                               // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
	wire  [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                             // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
	wire         jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                          // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
	wire         jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                          // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire  [17:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                              // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire   [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                           // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire         jtag_uart_avalon_jtag_slave_agent_m0_read;                                 // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire         jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                        // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
	wire         jtag_uart_avalon_jtag_slave_agent_m0_lock;                                 // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire  [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                            // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire         jtag_uart_avalon_jtag_slave_agent_m0_write;                                // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire   [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                           // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                         // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [94:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                          // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                         // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;                 // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;                   // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                      // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
	wire  [94:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                       // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                      // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;              // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire         cmd_mux_src_valid;                                                         // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
	wire  [93:0] cmd_mux_src_data;                                                          // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
	wire         cmd_mux_src_ready;                                                         // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
	wire   [7:0] cmd_mux_src_channel;                                                       // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
	wire         cmd_mux_src_startofpacket;                                                 // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
	wire         cmd_mux_src_endofpacket;                                                   // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
	wire  [31:0] perf_counter_control_slave_agent_m0_readdata;                              // perf_counter_control_slave_translator:uav_readdata -> perf_counter_control_slave_agent:m0_readdata
	wire         perf_counter_control_slave_agent_m0_waitrequest;                           // perf_counter_control_slave_translator:uav_waitrequest -> perf_counter_control_slave_agent:m0_waitrequest
	wire         perf_counter_control_slave_agent_m0_debugaccess;                           // perf_counter_control_slave_agent:m0_debugaccess -> perf_counter_control_slave_translator:uav_debugaccess
	wire  [17:0] perf_counter_control_slave_agent_m0_address;                               // perf_counter_control_slave_agent:m0_address -> perf_counter_control_slave_translator:uav_address
	wire   [3:0] perf_counter_control_slave_agent_m0_byteenable;                            // perf_counter_control_slave_agent:m0_byteenable -> perf_counter_control_slave_translator:uav_byteenable
	wire         perf_counter_control_slave_agent_m0_read;                                  // perf_counter_control_slave_agent:m0_read -> perf_counter_control_slave_translator:uav_read
	wire         perf_counter_control_slave_agent_m0_readdatavalid;                         // perf_counter_control_slave_translator:uav_readdatavalid -> perf_counter_control_slave_agent:m0_readdatavalid
	wire         perf_counter_control_slave_agent_m0_lock;                                  // perf_counter_control_slave_agent:m0_lock -> perf_counter_control_slave_translator:uav_lock
	wire  [31:0] perf_counter_control_slave_agent_m0_writedata;                             // perf_counter_control_slave_agent:m0_writedata -> perf_counter_control_slave_translator:uav_writedata
	wire         perf_counter_control_slave_agent_m0_write;                                 // perf_counter_control_slave_agent:m0_write -> perf_counter_control_slave_translator:uav_write
	wire   [2:0] perf_counter_control_slave_agent_m0_burstcount;                            // perf_counter_control_slave_agent:m0_burstcount -> perf_counter_control_slave_translator:uav_burstcount
	wire         perf_counter_control_slave_agent_rf_source_valid;                          // perf_counter_control_slave_agent:rf_source_valid -> perf_counter_control_slave_agent_rsp_fifo:in_valid
	wire  [94:0] perf_counter_control_slave_agent_rf_source_data;                           // perf_counter_control_slave_agent:rf_source_data -> perf_counter_control_slave_agent_rsp_fifo:in_data
	wire         perf_counter_control_slave_agent_rf_source_ready;                          // perf_counter_control_slave_agent_rsp_fifo:in_ready -> perf_counter_control_slave_agent:rf_source_ready
	wire         perf_counter_control_slave_agent_rf_source_startofpacket;                  // perf_counter_control_slave_agent:rf_source_startofpacket -> perf_counter_control_slave_agent_rsp_fifo:in_startofpacket
	wire         perf_counter_control_slave_agent_rf_source_endofpacket;                    // perf_counter_control_slave_agent:rf_source_endofpacket -> perf_counter_control_slave_agent_rsp_fifo:in_endofpacket
	wire         perf_counter_control_slave_agent_rsp_fifo_out_valid;                       // perf_counter_control_slave_agent_rsp_fifo:out_valid -> perf_counter_control_slave_agent:rf_sink_valid
	wire  [94:0] perf_counter_control_slave_agent_rsp_fifo_out_data;                        // perf_counter_control_slave_agent_rsp_fifo:out_data -> perf_counter_control_slave_agent:rf_sink_data
	wire         perf_counter_control_slave_agent_rsp_fifo_out_ready;                       // perf_counter_control_slave_agent:rf_sink_ready -> perf_counter_control_slave_agent_rsp_fifo:out_ready
	wire         perf_counter_control_slave_agent_rsp_fifo_out_startofpacket;               // perf_counter_control_slave_agent_rsp_fifo:out_startofpacket -> perf_counter_control_slave_agent:rf_sink_startofpacket
	wire         perf_counter_control_slave_agent_rsp_fifo_out_endofpacket;                 // perf_counter_control_slave_agent_rsp_fifo:out_endofpacket -> perf_counter_control_slave_agent:rf_sink_endofpacket
	wire         cmd_mux_001_src_valid;                                                     // cmd_mux_001:src_valid -> perf_counter_control_slave_agent:cp_valid
	wire  [93:0] cmd_mux_001_src_data;                                                      // cmd_mux_001:src_data -> perf_counter_control_slave_agent:cp_data
	wire         cmd_mux_001_src_ready;                                                     // perf_counter_control_slave_agent:cp_ready -> cmd_mux_001:src_ready
	wire   [7:0] cmd_mux_001_src_channel;                                                   // cmd_mux_001:src_channel -> perf_counter_control_slave_agent:cp_channel
	wire         cmd_mux_001_src_startofpacket;                                             // cmd_mux_001:src_startofpacket -> perf_counter_control_slave_agent:cp_startofpacket
	wire         cmd_mux_001_src_endofpacket;                                               // cmd_mux_001:src_endofpacket -> perf_counter_control_slave_agent:cp_endofpacket
	wire  [31:0] sem_ctl_slave_agent_m0_readdata;                                           // sem_ctl_slave_translator:uav_readdata -> sem_ctl_slave_agent:m0_readdata
	wire         sem_ctl_slave_agent_m0_waitrequest;                                        // sem_ctl_slave_translator:uav_waitrequest -> sem_ctl_slave_agent:m0_waitrequest
	wire         sem_ctl_slave_agent_m0_debugaccess;                                        // sem_ctl_slave_agent:m0_debugaccess -> sem_ctl_slave_translator:uav_debugaccess
	wire  [17:0] sem_ctl_slave_agent_m0_address;                                            // sem_ctl_slave_agent:m0_address -> sem_ctl_slave_translator:uav_address
	wire   [3:0] sem_ctl_slave_agent_m0_byteenable;                                         // sem_ctl_slave_agent:m0_byteenable -> sem_ctl_slave_translator:uav_byteenable
	wire         sem_ctl_slave_agent_m0_read;                                               // sem_ctl_slave_agent:m0_read -> sem_ctl_slave_translator:uav_read
	wire         sem_ctl_slave_agent_m0_readdatavalid;                                      // sem_ctl_slave_translator:uav_readdatavalid -> sem_ctl_slave_agent:m0_readdatavalid
	wire         sem_ctl_slave_agent_m0_lock;                                               // sem_ctl_slave_agent:m0_lock -> sem_ctl_slave_translator:uav_lock
	wire  [31:0] sem_ctl_slave_agent_m0_writedata;                                          // sem_ctl_slave_agent:m0_writedata -> sem_ctl_slave_translator:uav_writedata
	wire         sem_ctl_slave_agent_m0_write;                                              // sem_ctl_slave_agent:m0_write -> sem_ctl_slave_translator:uav_write
	wire   [2:0] sem_ctl_slave_agent_m0_burstcount;                                         // sem_ctl_slave_agent:m0_burstcount -> sem_ctl_slave_translator:uav_burstcount
	wire         sem_ctl_slave_agent_rf_source_valid;                                       // sem_ctl_slave_agent:rf_source_valid -> sem_ctl_slave_agent_rsp_fifo:in_valid
	wire  [94:0] sem_ctl_slave_agent_rf_source_data;                                        // sem_ctl_slave_agent:rf_source_data -> sem_ctl_slave_agent_rsp_fifo:in_data
	wire         sem_ctl_slave_agent_rf_source_ready;                                       // sem_ctl_slave_agent_rsp_fifo:in_ready -> sem_ctl_slave_agent:rf_source_ready
	wire         sem_ctl_slave_agent_rf_source_startofpacket;                               // sem_ctl_slave_agent:rf_source_startofpacket -> sem_ctl_slave_agent_rsp_fifo:in_startofpacket
	wire         sem_ctl_slave_agent_rf_source_endofpacket;                                 // sem_ctl_slave_agent:rf_source_endofpacket -> sem_ctl_slave_agent_rsp_fifo:in_endofpacket
	wire         sem_ctl_slave_agent_rsp_fifo_out_valid;                                    // sem_ctl_slave_agent_rsp_fifo:out_valid -> sem_ctl_slave_agent:rf_sink_valid
	wire  [94:0] sem_ctl_slave_agent_rsp_fifo_out_data;                                     // sem_ctl_slave_agent_rsp_fifo:out_data -> sem_ctl_slave_agent:rf_sink_data
	wire         sem_ctl_slave_agent_rsp_fifo_out_ready;                                    // sem_ctl_slave_agent:rf_sink_ready -> sem_ctl_slave_agent_rsp_fifo:out_ready
	wire         sem_ctl_slave_agent_rsp_fifo_out_startofpacket;                            // sem_ctl_slave_agent_rsp_fifo:out_startofpacket -> sem_ctl_slave_agent:rf_sink_startofpacket
	wire         sem_ctl_slave_agent_rsp_fifo_out_endofpacket;                              // sem_ctl_slave_agent_rsp_fifo:out_endofpacket -> sem_ctl_slave_agent:rf_sink_endofpacket
	wire         cmd_mux_002_src_valid;                                                     // cmd_mux_002:src_valid -> sem_ctl_slave_agent:cp_valid
	wire  [93:0] cmd_mux_002_src_data;                                                      // cmd_mux_002:src_data -> sem_ctl_slave_agent:cp_data
	wire         cmd_mux_002_src_ready;                                                     // sem_ctl_slave_agent:cp_ready -> cmd_mux_002:src_ready
	wire   [7:0] cmd_mux_002_src_channel;                                                   // cmd_mux_002:src_channel -> sem_ctl_slave_agent:cp_channel
	wire         cmd_mux_002_src_startofpacket;                                             // cmd_mux_002:src_startofpacket -> sem_ctl_slave_agent:cp_startofpacket
	wire         cmd_mux_002_src_endofpacket;                                               // cmd_mux_002:src_endofpacket -> sem_ctl_slave_agent:cp_endofpacket
	wire  [31:0] cpu_debug_mem_slave_agent_m0_readdata;                                     // cpu_debug_mem_slave_translator:uav_readdata -> cpu_debug_mem_slave_agent:m0_readdata
	wire         cpu_debug_mem_slave_agent_m0_waitrequest;                                  // cpu_debug_mem_slave_translator:uav_waitrequest -> cpu_debug_mem_slave_agent:m0_waitrequest
	wire         cpu_debug_mem_slave_agent_m0_debugaccess;                                  // cpu_debug_mem_slave_agent:m0_debugaccess -> cpu_debug_mem_slave_translator:uav_debugaccess
	wire  [17:0] cpu_debug_mem_slave_agent_m0_address;                                      // cpu_debug_mem_slave_agent:m0_address -> cpu_debug_mem_slave_translator:uav_address
	wire   [3:0] cpu_debug_mem_slave_agent_m0_byteenable;                                   // cpu_debug_mem_slave_agent:m0_byteenable -> cpu_debug_mem_slave_translator:uav_byteenable
	wire         cpu_debug_mem_slave_agent_m0_read;                                         // cpu_debug_mem_slave_agent:m0_read -> cpu_debug_mem_slave_translator:uav_read
	wire         cpu_debug_mem_slave_agent_m0_readdatavalid;                                // cpu_debug_mem_slave_translator:uav_readdatavalid -> cpu_debug_mem_slave_agent:m0_readdatavalid
	wire         cpu_debug_mem_slave_agent_m0_lock;                                         // cpu_debug_mem_slave_agent:m0_lock -> cpu_debug_mem_slave_translator:uav_lock
	wire  [31:0] cpu_debug_mem_slave_agent_m0_writedata;                                    // cpu_debug_mem_slave_agent:m0_writedata -> cpu_debug_mem_slave_translator:uav_writedata
	wire         cpu_debug_mem_slave_agent_m0_write;                                        // cpu_debug_mem_slave_agent:m0_write -> cpu_debug_mem_slave_translator:uav_write
	wire   [2:0] cpu_debug_mem_slave_agent_m0_burstcount;                                   // cpu_debug_mem_slave_agent:m0_burstcount -> cpu_debug_mem_slave_translator:uav_burstcount
	wire         cpu_debug_mem_slave_agent_rf_source_valid;                                 // cpu_debug_mem_slave_agent:rf_source_valid -> cpu_debug_mem_slave_agent_rsp_fifo:in_valid
	wire  [94:0] cpu_debug_mem_slave_agent_rf_source_data;                                  // cpu_debug_mem_slave_agent:rf_source_data -> cpu_debug_mem_slave_agent_rsp_fifo:in_data
	wire         cpu_debug_mem_slave_agent_rf_source_ready;                                 // cpu_debug_mem_slave_agent_rsp_fifo:in_ready -> cpu_debug_mem_slave_agent:rf_source_ready
	wire         cpu_debug_mem_slave_agent_rf_source_startofpacket;                         // cpu_debug_mem_slave_agent:rf_source_startofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_startofpacket
	wire         cpu_debug_mem_slave_agent_rf_source_endofpacket;                           // cpu_debug_mem_slave_agent:rf_source_endofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_endofpacket
	wire         cpu_debug_mem_slave_agent_rsp_fifo_out_valid;                              // cpu_debug_mem_slave_agent_rsp_fifo:out_valid -> cpu_debug_mem_slave_agent:rf_sink_valid
	wire  [94:0] cpu_debug_mem_slave_agent_rsp_fifo_out_data;                               // cpu_debug_mem_slave_agent_rsp_fifo:out_data -> cpu_debug_mem_slave_agent:rf_sink_data
	wire         cpu_debug_mem_slave_agent_rsp_fifo_out_ready;                              // cpu_debug_mem_slave_agent:rf_sink_ready -> cpu_debug_mem_slave_agent_rsp_fifo:out_ready
	wire         cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket;                      // cpu_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> cpu_debug_mem_slave_agent:rf_sink_startofpacket
	wire         cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket;                        // cpu_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> cpu_debug_mem_slave_agent:rf_sink_endofpacket
	wire         cmd_mux_003_src_valid;                                                     // cmd_mux_003:src_valid -> cpu_debug_mem_slave_agent:cp_valid
	wire  [93:0] cmd_mux_003_src_data;                                                      // cmd_mux_003:src_data -> cpu_debug_mem_slave_agent:cp_data
	wire         cmd_mux_003_src_ready;                                                     // cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_003:src_ready
	wire   [7:0] cmd_mux_003_src_channel;                                                   // cmd_mux_003:src_channel -> cpu_debug_mem_slave_agent:cp_channel
	wire         cmd_mux_003_src_startofpacket;                                             // cmd_mux_003:src_startofpacket -> cpu_debug_mem_slave_agent:cp_startofpacket
	wire         cmd_mux_003_src_endofpacket;                                               // cmd_mux_003:src_endofpacket -> cpu_debug_mem_slave_agent:cp_endofpacket
	wire  [31:0] sem_ram_slave_agent_m0_readdata;                                           // sem_ram_slave_translator:uav_readdata -> sem_ram_slave_agent:m0_readdata
	wire         sem_ram_slave_agent_m0_waitrequest;                                        // sem_ram_slave_translator:uav_waitrequest -> sem_ram_slave_agent:m0_waitrequest
	wire         sem_ram_slave_agent_m0_debugaccess;                                        // sem_ram_slave_agent:m0_debugaccess -> sem_ram_slave_translator:uav_debugaccess
	wire  [17:0] sem_ram_slave_agent_m0_address;                                            // sem_ram_slave_agent:m0_address -> sem_ram_slave_translator:uav_address
	wire   [3:0] sem_ram_slave_agent_m0_byteenable;                                         // sem_ram_slave_agent:m0_byteenable -> sem_ram_slave_translator:uav_byteenable
	wire         sem_ram_slave_agent_m0_read;                                               // sem_ram_slave_agent:m0_read -> sem_ram_slave_translator:uav_read
	wire         sem_ram_slave_agent_m0_readdatavalid;                                      // sem_ram_slave_translator:uav_readdatavalid -> sem_ram_slave_agent:m0_readdatavalid
	wire         sem_ram_slave_agent_m0_lock;                                               // sem_ram_slave_agent:m0_lock -> sem_ram_slave_translator:uav_lock
	wire  [31:0] sem_ram_slave_agent_m0_writedata;                                          // sem_ram_slave_agent:m0_writedata -> sem_ram_slave_translator:uav_writedata
	wire         sem_ram_slave_agent_m0_write;                                              // sem_ram_slave_agent:m0_write -> sem_ram_slave_translator:uav_write
	wire   [2:0] sem_ram_slave_agent_m0_burstcount;                                         // sem_ram_slave_agent:m0_burstcount -> sem_ram_slave_translator:uav_burstcount
	wire         sem_ram_slave_agent_rf_source_valid;                                       // sem_ram_slave_agent:rf_source_valid -> sem_ram_slave_agent_rsp_fifo:in_valid
	wire  [94:0] sem_ram_slave_agent_rf_source_data;                                        // sem_ram_slave_agent:rf_source_data -> sem_ram_slave_agent_rsp_fifo:in_data
	wire         sem_ram_slave_agent_rf_source_ready;                                       // sem_ram_slave_agent_rsp_fifo:in_ready -> sem_ram_slave_agent:rf_source_ready
	wire         sem_ram_slave_agent_rf_source_startofpacket;                               // sem_ram_slave_agent:rf_source_startofpacket -> sem_ram_slave_agent_rsp_fifo:in_startofpacket
	wire         sem_ram_slave_agent_rf_source_endofpacket;                                 // sem_ram_slave_agent:rf_source_endofpacket -> sem_ram_slave_agent_rsp_fifo:in_endofpacket
	wire         sem_ram_slave_agent_rsp_fifo_out_valid;                                    // sem_ram_slave_agent_rsp_fifo:out_valid -> sem_ram_slave_agent:rf_sink_valid
	wire  [94:0] sem_ram_slave_agent_rsp_fifo_out_data;                                     // sem_ram_slave_agent_rsp_fifo:out_data -> sem_ram_slave_agent:rf_sink_data
	wire         sem_ram_slave_agent_rsp_fifo_out_ready;                                    // sem_ram_slave_agent:rf_sink_ready -> sem_ram_slave_agent_rsp_fifo:out_ready
	wire         sem_ram_slave_agent_rsp_fifo_out_startofpacket;                            // sem_ram_slave_agent_rsp_fifo:out_startofpacket -> sem_ram_slave_agent:rf_sink_startofpacket
	wire         sem_ram_slave_agent_rsp_fifo_out_endofpacket;                              // sem_ram_slave_agent_rsp_fifo:out_endofpacket -> sem_ram_slave_agent:rf_sink_endofpacket
	wire         cmd_mux_004_src_valid;                                                     // cmd_mux_004:src_valid -> sem_ram_slave_agent:cp_valid
	wire  [93:0] cmd_mux_004_src_data;                                                      // cmd_mux_004:src_data -> sem_ram_slave_agent:cp_data
	wire         cmd_mux_004_src_ready;                                                     // sem_ram_slave_agent:cp_ready -> cmd_mux_004:src_ready
	wire   [7:0] cmd_mux_004_src_channel;                                                   // cmd_mux_004:src_channel -> sem_ram_slave_agent:cp_channel
	wire         cmd_mux_004_src_startofpacket;                                             // cmd_mux_004:src_startofpacket -> sem_ram_slave_agent:cp_startofpacket
	wire         cmd_mux_004_src_endofpacket;                                               // cmd_mux_004:src_endofpacket -> sem_ram_slave_agent:cp_endofpacket
	wire  [31:0] sys_clk_timer_s1_agent_m0_readdata;                                        // sys_clk_timer_s1_translator:uav_readdata -> sys_clk_timer_s1_agent:m0_readdata
	wire         sys_clk_timer_s1_agent_m0_waitrequest;                                     // sys_clk_timer_s1_translator:uav_waitrequest -> sys_clk_timer_s1_agent:m0_waitrequest
	wire         sys_clk_timer_s1_agent_m0_debugaccess;                                     // sys_clk_timer_s1_agent:m0_debugaccess -> sys_clk_timer_s1_translator:uav_debugaccess
	wire  [17:0] sys_clk_timer_s1_agent_m0_address;                                         // sys_clk_timer_s1_agent:m0_address -> sys_clk_timer_s1_translator:uav_address
	wire   [3:0] sys_clk_timer_s1_agent_m0_byteenable;                                      // sys_clk_timer_s1_agent:m0_byteenable -> sys_clk_timer_s1_translator:uav_byteenable
	wire         sys_clk_timer_s1_agent_m0_read;                                            // sys_clk_timer_s1_agent:m0_read -> sys_clk_timer_s1_translator:uav_read
	wire         sys_clk_timer_s1_agent_m0_readdatavalid;                                   // sys_clk_timer_s1_translator:uav_readdatavalid -> sys_clk_timer_s1_agent:m0_readdatavalid
	wire         sys_clk_timer_s1_agent_m0_lock;                                            // sys_clk_timer_s1_agent:m0_lock -> sys_clk_timer_s1_translator:uav_lock
	wire  [31:0] sys_clk_timer_s1_agent_m0_writedata;                                       // sys_clk_timer_s1_agent:m0_writedata -> sys_clk_timer_s1_translator:uav_writedata
	wire         sys_clk_timer_s1_agent_m0_write;                                           // sys_clk_timer_s1_agent:m0_write -> sys_clk_timer_s1_translator:uav_write
	wire   [2:0] sys_clk_timer_s1_agent_m0_burstcount;                                      // sys_clk_timer_s1_agent:m0_burstcount -> sys_clk_timer_s1_translator:uav_burstcount
	wire         sys_clk_timer_s1_agent_rf_source_valid;                                    // sys_clk_timer_s1_agent:rf_source_valid -> sys_clk_timer_s1_agent_rsp_fifo:in_valid
	wire  [94:0] sys_clk_timer_s1_agent_rf_source_data;                                     // sys_clk_timer_s1_agent:rf_source_data -> sys_clk_timer_s1_agent_rsp_fifo:in_data
	wire         sys_clk_timer_s1_agent_rf_source_ready;                                    // sys_clk_timer_s1_agent_rsp_fifo:in_ready -> sys_clk_timer_s1_agent:rf_source_ready
	wire         sys_clk_timer_s1_agent_rf_source_startofpacket;                            // sys_clk_timer_s1_agent:rf_source_startofpacket -> sys_clk_timer_s1_agent_rsp_fifo:in_startofpacket
	wire         sys_clk_timer_s1_agent_rf_source_endofpacket;                              // sys_clk_timer_s1_agent:rf_source_endofpacket -> sys_clk_timer_s1_agent_rsp_fifo:in_endofpacket
	wire         sys_clk_timer_s1_agent_rsp_fifo_out_valid;                                 // sys_clk_timer_s1_agent_rsp_fifo:out_valid -> sys_clk_timer_s1_agent:rf_sink_valid
	wire  [94:0] sys_clk_timer_s1_agent_rsp_fifo_out_data;                                  // sys_clk_timer_s1_agent_rsp_fifo:out_data -> sys_clk_timer_s1_agent:rf_sink_data
	wire         sys_clk_timer_s1_agent_rsp_fifo_out_ready;                                 // sys_clk_timer_s1_agent:rf_sink_ready -> sys_clk_timer_s1_agent_rsp_fifo:out_ready
	wire         sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket;                         // sys_clk_timer_s1_agent_rsp_fifo:out_startofpacket -> sys_clk_timer_s1_agent:rf_sink_startofpacket
	wire         sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket;                           // sys_clk_timer_s1_agent_rsp_fifo:out_endofpacket -> sys_clk_timer_s1_agent:rf_sink_endofpacket
	wire         cmd_mux_005_src_valid;                                                     // cmd_mux_005:src_valid -> sys_clk_timer_s1_agent:cp_valid
	wire  [93:0] cmd_mux_005_src_data;                                                      // cmd_mux_005:src_data -> sys_clk_timer_s1_agent:cp_data
	wire         cmd_mux_005_src_ready;                                                     // sys_clk_timer_s1_agent:cp_ready -> cmd_mux_005:src_ready
	wire   [7:0] cmd_mux_005_src_channel;                                                   // cmd_mux_005:src_channel -> sys_clk_timer_s1_agent:cp_channel
	wire         cmd_mux_005_src_startofpacket;                                             // cmd_mux_005:src_startofpacket -> sys_clk_timer_s1_agent:cp_startofpacket
	wire         cmd_mux_005_src_endofpacket;                                               // cmd_mux_005:src_endofpacket -> sys_clk_timer_s1_agent:cp_endofpacket
	wire  [31:0] mem_s2_agent_m0_readdata;                                                  // mem_s2_translator:uav_readdata -> mem_s2_agent:m0_readdata
	wire         mem_s2_agent_m0_waitrequest;                                               // mem_s2_translator:uav_waitrequest -> mem_s2_agent:m0_waitrequest
	wire         mem_s2_agent_m0_debugaccess;                                               // mem_s2_agent:m0_debugaccess -> mem_s2_translator:uav_debugaccess
	wire  [17:0] mem_s2_agent_m0_address;                                                   // mem_s2_agent:m0_address -> mem_s2_translator:uav_address
	wire   [3:0] mem_s2_agent_m0_byteenable;                                                // mem_s2_agent:m0_byteenable -> mem_s2_translator:uav_byteenable
	wire         mem_s2_agent_m0_read;                                                      // mem_s2_agent:m0_read -> mem_s2_translator:uav_read
	wire         mem_s2_agent_m0_readdatavalid;                                             // mem_s2_translator:uav_readdatavalid -> mem_s2_agent:m0_readdatavalid
	wire         mem_s2_agent_m0_lock;                                                      // mem_s2_agent:m0_lock -> mem_s2_translator:uav_lock
	wire  [31:0] mem_s2_agent_m0_writedata;                                                 // mem_s2_agent:m0_writedata -> mem_s2_translator:uav_writedata
	wire         mem_s2_agent_m0_write;                                                     // mem_s2_agent:m0_write -> mem_s2_translator:uav_write
	wire   [2:0] mem_s2_agent_m0_burstcount;                                                // mem_s2_agent:m0_burstcount -> mem_s2_translator:uav_burstcount
	wire         mem_s2_agent_rf_source_valid;                                              // mem_s2_agent:rf_source_valid -> mem_s2_agent_rsp_fifo:in_valid
	wire  [94:0] mem_s2_agent_rf_source_data;                                               // mem_s2_agent:rf_source_data -> mem_s2_agent_rsp_fifo:in_data
	wire         mem_s2_agent_rf_source_ready;                                              // mem_s2_agent_rsp_fifo:in_ready -> mem_s2_agent:rf_source_ready
	wire         mem_s2_agent_rf_source_startofpacket;                                      // mem_s2_agent:rf_source_startofpacket -> mem_s2_agent_rsp_fifo:in_startofpacket
	wire         mem_s2_agent_rf_source_endofpacket;                                        // mem_s2_agent:rf_source_endofpacket -> mem_s2_agent_rsp_fifo:in_endofpacket
	wire         mem_s2_agent_rsp_fifo_out_valid;                                           // mem_s2_agent_rsp_fifo:out_valid -> mem_s2_agent:rf_sink_valid
	wire  [94:0] mem_s2_agent_rsp_fifo_out_data;                                            // mem_s2_agent_rsp_fifo:out_data -> mem_s2_agent:rf_sink_data
	wire         mem_s2_agent_rsp_fifo_out_ready;                                           // mem_s2_agent:rf_sink_ready -> mem_s2_agent_rsp_fifo:out_ready
	wire         mem_s2_agent_rsp_fifo_out_startofpacket;                                   // mem_s2_agent_rsp_fifo:out_startofpacket -> mem_s2_agent:rf_sink_startofpacket
	wire         mem_s2_agent_rsp_fifo_out_endofpacket;                                     // mem_s2_agent_rsp_fifo:out_endofpacket -> mem_s2_agent:rf_sink_endofpacket
	wire         cmd_mux_006_src_valid;                                                     // cmd_mux_006:src_valid -> mem_s2_agent:cp_valid
	wire  [93:0] cmd_mux_006_src_data;                                                      // cmd_mux_006:src_data -> mem_s2_agent:cp_data
	wire         cmd_mux_006_src_ready;                                                     // mem_s2_agent:cp_ready -> cmd_mux_006:src_ready
	wire   [7:0] cmd_mux_006_src_channel;                                                   // cmd_mux_006:src_channel -> mem_s2_agent:cp_channel
	wire         cmd_mux_006_src_startofpacket;                                             // cmd_mux_006:src_startofpacket -> mem_s2_agent:cp_startofpacket
	wire         cmd_mux_006_src_endofpacket;                                               // cmd_mux_006:src_endofpacket -> mem_s2_agent:cp_endofpacket
	wire  [31:0] mem_s1_agent_m0_readdata;                                                  // mem_s1_translator:uav_readdata -> mem_s1_agent:m0_readdata
	wire         mem_s1_agent_m0_waitrequest;                                               // mem_s1_translator:uav_waitrequest -> mem_s1_agent:m0_waitrequest
	wire         mem_s1_agent_m0_debugaccess;                                               // mem_s1_agent:m0_debugaccess -> mem_s1_translator:uav_debugaccess
	wire  [17:0] mem_s1_agent_m0_address;                                                   // mem_s1_agent:m0_address -> mem_s1_translator:uav_address
	wire   [3:0] mem_s1_agent_m0_byteenable;                                                // mem_s1_agent:m0_byteenable -> mem_s1_translator:uav_byteenable
	wire         mem_s1_agent_m0_read;                                                      // mem_s1_agent:m0_read -> mem_s1_translator:uav_read
	wire         mem_s1_agent_m0_readdatavalid;                                             // mem_s1_translator:uav_readdatavalid -> mem_s1_agent:m0_readdatavalid
	wire         mem_s1_agent_m0_lock;                                                      // mem_s1_agent:m0_lock -> mem_s1_translator:uav_lock
	wire  [31:0] mem_s1_agent_m0_writedata;                                                 // mem_s1_agent:m0_writedata -> mem_s1_translator:uav_writedata
	wire         mem_s1_agent_m0_write;                                                     // mem_s1_agent:m0_write -> mem_s1_translator:uav_write
	wire   [2:0] mem_s1_agent_m0_burstcount;                                                // mem_s1_agent:m0_burstcount -> mem_s1_translator:uav_burstcount
	wire         mem_s1_agent_rf_source_valid;                                              // mem_s1_agent:rf_source_valid -> mem_s1_agent_rsp_fifo:in_valid
	wire  [94:0] mem_s1_agent_rf_source_data;                                               // mem_s1_agent:rf_source_data -> mem_s1_agent_rsp_fifo:in_data
	wire         mem_s1_agent_rf_source_ready;                                              // mem_s1_agent_rsp_fifo:in_ready -> mem_s1_agent:rf_source_ready
	wire         mem_s1_agent_rf_source_startofpacket;                                      // mem_s1_agent:rf_source_startofpacket -> mem_s1_agent_rsp_fifo:in_startofpacket
	wire         mem_s1_agent_rf_source_endofpacket;                                        // mem_s1_agent:rf_source_endofpacket -> mem_s1_agent_rsp_fifo:in_endofpacket
	wire         mem_s1_agent_rsp_fifo_out_valid;                                           // mem_s1_agent_rsp_fifo:out_valid -> mem_s1_agent:rf_sink_valid
	wire  [94:0] mem_s1_agent_rsp_fifo_out_data;                                            // mem_s1_agent_rsp_fifo:out_data -> mem_s1_agent:rf_sink_data
	wire         mem_s1_agent_rsp_fifo_out_ready;                                           // mem_s1_agent:rf_sink_ready -> mem_s1_agent_rsp_fifo:out_ready
	wire         mem_s1_agent_rsp_fifo_out_startofpacket;                                   // mem_s1_agent_rsp_fifo:out_startofpacket -> mem_s1_agent:rf_sink_startofpacket
	wire         mem_s1_agent_rsp_fifo_out_endofpacket;                                     // mem_s1_agent_rsp_fifo:out_endofpacket -> mem_s1_agent:rf_sink_endofpacket
	wire         cmd_mux_007_src_valid;                                                     // cmd_mux_007:src_valid -> mem_s1_agent:cp_valid
	wire  [93:0] cmd_mux_007_src_data;                                                      // cmd_mux_007:src_data -> mem_s1_agent:cp_data
	wire         cmd_mux_007_src_ready;                                                     // mem_s1_agent:cp_ready -> cmd_mux_007:src_ready
	wire   [7:0] cmd_mux_007_src_channel;                                                   // cmd_mux_007:src_channel -> mem_s1_agent:cp_channel
	wire         cmd_mux_007_src_startofpacket;                                             // cmd_mux_007:src_startofpacket -> mem_s1_agent:cp_startofpacket
	wire         cmd_mux_007_src_endofpacket;                                               // cmd_mux_007:src_endofpacket -> mem_s1_agent:cp_endofpacket
	wire         cpu_data_master_agent_cp_valid;                                            // cpu_data_master_agent:cp_valid -> router:sink_valid
	wire  [93:0] cpu_data_master_agent_cp_data;                                             // cpu_data_master_agent:cp_data -> router:sink_data
	wire         cpu_data_master_agent_cp_ready;                                            // router:sink_ready -> cpu_data_master_agent:cp_ready
	wire         cpu_data_master_agent_cp_startofpacket;                                    // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire         cpu_data_master_agent_cp_endofpacket;                                      // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire         router_src_valid;                                                          // router:src_valid -> cmd_demux:sink_valid
	wire  [93:0] router_src_data;                                                           // router:src_data -> cmd_demux:sink_data
	wire         router_src_ready;                                                          // cmd_demux:sink_ready -> router:src_ready
	wire   [7:0] router_src_channel;                                                        // router:src_channel -> cmd_demux:sink_channel
	wire         router_src_startofpacket;                                                  // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire         router_src_endofpacket;                                                    // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire         cpu_instruction_master_agent_cp_valid;                                     // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
	wire  [93:0] cpu_instruction_master_agent_cp_data;                                      // cpu_instruction_master_agent:cp_data -> router_001:sink_data
	wire         cpu_instruction_master_agent_cp_ready;                                     // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
	wire         cpu_instruction_master_agent_cp_startofpacket;                             // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire         cpu_instruction_master_agent_cp_endofpacket;                               // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire         router_001_src_valid;                                                      // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [93:0] router_001_src_data;                                                       // router_001:src_data -> cmd_demux_001:sink_data
	wire         router_001_src_ready;                                                      // cmd_demux_001:sink_ready -> router_001:src_ready
	wire   [7:0] router_001_src_channel;                                                    // router_001:src_channel -> cmd_demux_001:sink_channel
	wire         router_001_src_startofpacket;                                              // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire         router_001_src_endofpacket;                                                // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rp_valid;                                // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
	wire  [93:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                                 // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
	wire         jtag_uart_avalon_jtag_slave_agent_rp_ready;                                // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
	wire         jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                        // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                          // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire         router_002_src_valid;                                                      // router_002:src_valid -> rsp_demux:sink_valid
	wire  [93:0] router_002_src_data;                                                       // router_002:src_data -> rsp_demux:sink_data
	wire         router_002_src_ready;                                                      // rsp_demux:sink_ready -> router_002:src_ready
	wire   [7:0] router_002_src_channel;                                                    // router_002:src_channel -> rsp_demux:sink_channel
	wire         router_002_src_startofpacket;                                              // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire         router_002_src_endofpacket;                                                // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire         perf_counter_control_slave_agent_rp_valid;                                 // perf_counter_control_slave_agent:rp_valid -> router_003:sink_valid
	wire  [93:0] perf_counter_control_slave_agent_rp_data;                                  // perf_counter_control_slave_agent:rp_data -> router_003:sink_data
	wire         perf_counter_control_slave_agent_rp_ready;                                 // router_003:sink_ready -> perf_counter_control_slave_agent:rp_ready
	wire         perf_counter_control_slave_agent_rp_startofpacket;                         // perf_counter_control_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire         perf_counter_control_slave_agent_rp_endofpacket;                           // perf_counter_control_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire         router_003_src_valid;                                                      // router_003:src_valid -> rsp_demux_001:sink_valid
	wire  [93:0] router_003_src_data;                                                       // router_003:src_data -> rsp_demux_001:sink_data
	wire         router_003_src_ready;                                                      // rsp_demux_001:sink_ready -> router_003:src_ready
	wire   [7:0] router_003_src_channel;                                                    // router_003:src_channel -> rsp_demux_001:sink_channel
	wire         router_003_src_startofpacket;                                              // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire         router_003_src_endofpacket;                                                // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire         sem_ctl_slave_agent_rp_valid;                                              // sem_ctl_slave_agent:rp_valid -> router_004:sink_valid
	wire  [93:0] sem_ctl_slave_agent_rp_data;                                               // sem_ctl_slave_agent:rp_data -> router_004:sink_data
	wire         sem_ctl_slave_agent_rp_ready;                                              // router_004:sink_ready -> sem_ctl_slave_agent:rp_ready
	wire         sem_ctl_slave_agent_rp_startofpacket;                                      // sem_ctl_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire         sem_ctl_slave_agent_rp_endofpacket;                                        // sem_ctl_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire         router_004_src_valid;                                                      // router_004:src_valid -> rsp_demux_002:sink_valid
	wire  [93:0] router_004_src_data;                                                       // router_004:src_data -> rsp_demux_002:sink_data
	wire         router_004_src_ready;                                                      // rsp_demux_002:sink_ready -> router_004:src_ready
	wire   [7:0] router_004_src_channel;                                                    // router_004:src_channel -> rsp_demux_002:sink_channel
	wire         router_004_src_startofpacket;                                              // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire         router_004_src_endofpacket;                                                // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire         cpu_debug_mem_slave_agent_rp_valid;                                        // cpu_debug_mem_slave_agent:rp_valid -> router_005:sink_valid
	wire  [93:0] cpu_debug_mem_slave_agent_rp_data;                                         // cpu_debug_mem_slave_agent:rp_data -> router_005:sink_data
	wire         cpu_debug_mem_slave_agent_rp_ready;                                        // router_005:sink_ready -> cpu_debug_mem_slave_agent:rp_ready
	wire         cpu_debug_mem_slave_agent_rp_startofpacket;                                // cpu_debug_mem_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire         cpu_debug_mem_slave_agent_rp_endofpacket;                                  // cpu_debug_mem_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire         router_005_src_valid;                                                      // router_005:src_valid -> rsp_demux_003:sink_valid
	wire  [93:0] router_005_src_data;                                                       // router_005:src_data -> rsp_demux_003:sink_data
	wire         router_005_src_ready;                                                      // rsp_demux_003:sink_ready -> router_005:src_ready
	wire   [7:0] router_005_src_channel;                                                    // router_005:src_channel -> rsp_demux_003:sink_channel
	wire         router_005_src_startofpacket;                                              // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire         router_005_src_endofpacket;                                                // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire         sem_ram_slave_agent_rp_valid;                                              // sem_ram_slave_agent:rp_valid -> router_006:sink_valid
	wire  [93:0] sem_ram_slave_agent_rp_data;                                               // sem_ram_slave_agent:rp_data -> router_006:sink_data
	wire         sem_ram_slave_agent_rp_ready;                                              // router_006:sink_ready -> sem_ram_slave_agent:rp_ready
	wire         sem_ram_slave_agent_rp_startofpacket;                                      // sem_ram_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire         sem_ram_slave_agent_rp_endofpacket;                                        // sem_ram_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire         router_006_src_valid;                                                      // router_006:src_valid -> rsp_demux_004:sink_valid
	wire  [93:0] router_006_src_data;                                                       // router_006:src_data -> rsp_demux_004:sink_data
	wire         router_006_src_ready;                                                      // rsp_demux_004:sink_ready -> router_006:src_ready
	wire   [7:0] router_006_src_channel;                                                    // router_006:src_channel -> rsp_demux_004:sink_channel
	wire         router_006_src_startofpacket;                                              // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire         router_006_src_endofpacket;                                                // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire         sys_clk_timer_s1_agent_rp_valid;                                           // sys_clk_timer_s1_agent:rp_valid -> router_007:sink_valid
	wire  [93:0] sys_clk_timer_s1_agent_rp_data;                                            // sys_clk_timer_s1_agent:rp_data -> router_007:sink_data
	wire         sys_clk_timer_s1_agent_rp_ready;                                           // router_007:sink_ready -> sys_clk_timer_s1_agent:rp_ready
	wire         sys_clk_timer_s1_agent_rp_startofpacket;                                   // sys_clk_timer_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire         sys_clk_timer_s1_agent_rp_endofpacket;                                     // sys_clk_timer_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire         router_007_src_valid;                                                      // router_007:src_valid -> rsp_demux_005:sink_valid
	wire  [93:0] router_007_src_data;                                                       // router_007:src_data -> rsp_demux_005:sink_data
	wire         router_007_src_ready;                                                      // rsp_demux_005:sink_ready -> router_007:src_ready
	wire   [7:0] router_007_src_channel;                                                    // router_007:src_channel -> rsp_demux_005:sink_channel
	wire         router_007_src_startofpacket;                                              // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire         router_007_src_endofpacket;                                                // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire         mem_s2_agent_rp_valid;                                                     // mem_s2_agent:rp_valid -> router_008:sink_valid
	wire  [93:0] mem_s2_agent_rp_data;                                                      // mem_s2_agent:rp_data -> router_008:sink_data
	wire         mem_s2_agent_rp_ready;                                                     // router_008:sink_ready -> mem_s2_agent:rp_ready
	wire         mem_s2_agent_rp_startofpacket;                                             // mem_s2_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire         mem_s2_agent_rp_endofpacket;                                               // mem_s2_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire         router_008_src_valid;                                                      // router_008:src_valid -> rsp_demux_006:sink_valid
	wire  [93:0] router_008_src_data;                                                       // router_008:src_data -> rsp_demux_006:sink_data
	wire         router_008_src_ready;                                                      // rsp_demux_006:sink_ready -> router_008:src_ready
	wire   [7:0] router_008_src_channel;                                                    // router_008:src_channel -> rsp_demux_006:sink_channel
	wire         router_008_src_startofpacket;                                              // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
	wire         router_008_src_endofpacket;                                                // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
	wire         mem_s1_agent_rp_valid;                                                     // mem_s1_agent:rp_valid -> router_009:sink_valid
	wire  [93:0] mem_s1_agent_rp_data;                                                      // mem_s1_agent:rp_data -> router_009:sink_data
	wire         mem_s1_agent_rp_ready;                                                     // router_009:sink_ready -> mem_s1_agent:rp_ready
	wire         mem_s1_agent_rp_startofpacket;                                             // mem_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire         mem_s1_agent_rp_endofpacket;                                               // mem_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire         router_009_src_valid;                                                      // router_009:src_valid -> rsp_demux_007:sink_valid
	wire  [93:0] router_009_src_data;                                                       // router_009:src_data -> rsp_demux_007:sink_data
	wire         router_009_src_ready;                                                      // rsp_demux_007:sink_ready -> router_009:src_ready
	wire   [7:0] router_009_src_channel;                                                    // router_009:src_channel -> rsp_demux_007:sink_channel
	wire         router_009_src_startofpacket;                                              // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
	wire         router_009_src_endofpacket;                                                // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
	wire         cmd_demux_src0_valid;                                                      // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [93:0] cmd_demux_src0_data;                                                       // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire         cmd_demux_src0_ready;                                                      // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire   [7:0] cmd_demux_src0_channel;                                                    // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire         cmd_demux_src0_startofpacket;                                              // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire         cmd_demux_src0_endofpacket;                                                // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire         cmd_demux_src1_valid;                                                      // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [93:0] cmd_demux_src1_data;                                                       // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire         cmd_demux_src1_ready;                                                      // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire   [7:0] cmd_demux_src1_channel;                                                    // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire         cmd_demux_src1_startofpacket;                                              // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire         cmd_demux_src1_endofpacket;                                                // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire         cmd_demux_src2_valid;                                                      // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [93:0] cmd_demux_src2_data;                                                       // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire         cmd_demux_src2_ready;                                                      // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire   [7:0] cmd_demux_src2_channel;                                                    // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire         cmd_demux_src2_startofpacket;                                              // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire         cmd_demux_src2_endofpacket;                                                // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire         cmd_demux_src3_valid;                                                      // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [93:0] cmd_demux_src3_data;                                                       // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire         cmd_demux_src3_ready;                                                      // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire   [7:0] cmd_demux_src3_channel;                                                    // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire         cmd_demux_src3_startofpacket;                                              // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire         cmd_demux_src3_endofpacket;                                                // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire         cmd_demux_src4_valid;                                                      // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire  [93:0] cmd_demux_src4_data;                                                       // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire         cmd_demux_src4_ready;                                                      // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire   [7:0] cmd_demux_src4_channel;                                                    // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire         cmd_demux_src4_startofpacket;                                              // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire         cmd_demux_src4_endofpacket;                                                // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire         cmd_demux_src5_valid;                                                      // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	wire  [93:0] cmd_demux_src5_data;                                                       // cmd_demux:src5_data -> cmd_mux_005:sink0_data
	wire         cmd_demux_src5_ready;                                                      // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	wire   [7:0] cmd_demux_src5_channel;                                                    // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	wire         cmd_demux_src5_startofpacket;                                              // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire         cmd_demux_src5_endofpacket;                                                // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire         cmd_demux_src6_valid;                                                      // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
	wire  [93:0] cmd_demux_src6_data;                                                       // cmd_demux:src6_data -> cmd_mux_006:sink0_data
	wire         cmd_demux_src6_ready;                                                      // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
	wire   [7:0] cmd_demux_src6_channel;                                                    // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
	wire         cmd_demux_src6_startofpacket;                                              // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	wire         cmd_demux_src6_endofpacket;                                                // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	wire         cmd_demux_001_src0_valid;                                                  // cmd_demux_001:src0_valid -> cmd_mux_003:sink1_valid
	wire  [93:0] cmd_demux_001_src0_data;                                                   // cmd_demux_001:src0_data -> cmd_mux_003:sink1_data
	wire         cmd_demux_001_src0_ready;                                                  // cmd_mux_003:sink1_ready -> cmd_demux_001:src0_ready
	wire   [7:0] cmd_demux_001_src0_channel;                                                // cmd_demux_001:src0_channel -> cmd_mux_003:sink1_channel
	wire         cmd_demux_001_src0_startofpacket;                                          // cmd_demux_001:src0_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire         cmd_demux_001_src0_endofpacket;                                            // cmd_demux_001:src0_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire         cmd_demux_001_src1_valid;                                                  // cmd_demux_001:src1_valid -> cmd_mux_007:sink0_valid
	wire  [93:0] cmd_demux_001_src1_data;                                                   // cmd_demux_001:src1_data -> cmd_mux_007:sink0_data
	wire         cmd_demux_001_src1_ready;                                                  // cmd_mux_007:sink0_ready -> cmd_demux_001:src1_ready
	wire   [7:0] cmd_demux_001_src1_channel;                                                // cmd_demux_001:src1_channel -> cmd_mux_007:sink0_channel
	wire         cmd_demux_001_src1_startofpacket;                                          // cmd_demux_001:src1_startofpacket -> cmd_mux_007:sink0_startofpacket
	wire         cmd_demux_001_src1_endofpacket;                                            // cmd_demux_001:src1_endofpacket -> cmd_mux_007:sink0_endofpacket
	wire         rsp_demux_src0_valid;                                                      // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [93:0] rsp_demux_src0_data;                                                       // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire         rsp_demux_src0_ready;                                                      // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire   [7:0] rsp_demux_src0_channel;                                                    // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire         rsp_demux_src0_startofpacket;                                              // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire         rsp_demux_src0_endofpacket;                                                // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire         rsp_demux_001_src0_valid;                                                  // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [93:0] rsp_demux_001_src0_data;                                                   // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire         rsp_demux_001_src0_ready;                                                  // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire   [7:0] rsp_demux_001_src0_channel;                                                // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire         rsp_demux_001_src0_startofpacket;                                          // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire         rsp_demux_001_src0_endofpacket;                                            // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire         rsp_demux_002_src0_valid;                                                  // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [93:0] rsp_demux_002_src0_data;                                                   // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire         rsp_demux_002_src0_ready;                                                  // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire   [7:0] rsp_demux_002_src0_channel;                                                // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire         rsp_demux_002_src0_startofpacket;                                          // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire         rsp_demux_002_src0_endofpacket;                                            // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire         rsp_demux_003_src0_valid;                                                  // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [93:0] rsp_demux_003_src0_data;                                                   // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire         rsp_demux_003_src0_ready;                                                  // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire   [7:0] rsp_demux_003_src0_channel;                                                // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire         rsp_demux_003_src0_startofpacket;                                          // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire         rsp_demux_003_src0_endofpacket;                                            // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire         rsp_demux_003_src1_valid;                                                  // rsp_demux_003:src1_valid -> rsp_mux_001:sink0_valid
	wire  [93:0] rsp_demux_003_src1_data;                                                   // rsp_demux_003:src1_data -> rsp_mux_001:sink0_data
	wire         rsp_demux_003_src1_ready;                                                  // rsp_mux_001:sink0_ready -> rsp_demux_003:src1_ready
	wire   [7:0] rsp_demux_003_src1_channel;                                                // rsp_demux_003:src1_channel -> rsp_mux_001:sink0_channel
	wire         rsp_demux_003_src1_startofpacket;                                          // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire         rsp_demux_003_src1_endofpacket;                                            // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire         rsp_demux_004_src0_valid;                                                  // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire  [93:0] rsp_demux_004_src0_data;                                                   // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire         rsp_demux_004_src0_ready;                                                  // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire   [7:0] rsp_demux_004_src0_channel;                                                // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire         rsp_demux_004_src0_startofpacket;                                          // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire         rsp_demux_004_src0_endofpacket;                                            // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire         rsp_demux_005_src0_valid;                                                  // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	wire  [93:0] rsp_demux_005_src0_data;                                                   // rsp_demux_005:src0_data -> rsp_mux:sink5_data
	wire         rsp_demux_005_src0_ready;                                                  // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	wire   [7:0] rsp_demux_005_src0_channel;                                                // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	wire         rsp_demux_005_src0_startofpacket;                                          // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	wire         rsp_demux_005_src0_endofpacket;                                            // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	wire         rsp_demux_006_src0_valid;                                                  // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
	wire  [93:0] rsp_demux_006_src0_data;                                                   // rsp_demux_006:src0_data -> rsp_mux:sink6_data
	wire         rsp_demux_006_src0_ready;                                                  // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
	wire   [7:0] rsp_demux_006_src0_channel;                                                // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
	wire         rsp_demux_006_src0_startofpacket;                                          // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
	wire         rsp_demux_006_src0_endofpacket;                                            // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
	wire         rsp_demux_007_src0_valid;                                                  // rsp_demux_007:src0_valid -> rsp_mux_001:sink1_valid
	wire  [93:0] rsp_demux_007_src0_data;                                                   // rsp_demux_007:src0_data -> rsp_mux_001:sink1_data
	wire         rsp_demux_007_src0_ready;                                                  // rsp_mux_001:sink1_ready -> rsp_demux_007:src0_ready
	wire   [7:0] rsp_demux_007_src0_channel;                                                // rsp_demux_007:src0_channel -> rsp_mux_001:sink1_channel
	wire         rsp_demux_007_src0_startofpacket;                                          // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire         rsp_demux_007_src0_endofpacket;                                            // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire         jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;                    // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire  [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                     // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire         jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;                    // avalon_st_adapter:in_0_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_out_0_valid;                                             // avalon_st_adapter:out_0_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_out_0_data;                                              // avalon_st_adapter:out_0_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_out_0_ready;                                             // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire   [0:0] avalon_st_adapter_out_0_error;                                             // avalon_st_adapter:out_0_error -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error
	wire         perf_counter_control_slave_agent_rdata_fifo_src_valid;                     // perf_counter_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	wire  [33:0] perf_counter_control_slave_agent_rdata_fifo_src_data;                      // perf_counter_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	wire         perf_counter_control_slave_agent_rdata_fifo_src_ready;                     // avalon_st_adapter_001:in_0_ready -> perf_counter_control_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_001_out_0_valid;                                         // avalon_st_adapter_001:out_0_valid -> perf_counter_control_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_001_out_0_data;                                          // avalon_st_adapter_001:out_0_data -> perf_counter_control_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_001_out_0_ready;                                         // perf_counter_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire   [0:0] avalon_st_adapter_001_out_0_error;                                         // avalon_st_adapter_001:out_0_error -> perf_counter_control_slave_agent:rdata_fifo_sink_error
	wire         sem_ctl_slave_agent_rdata_fifo_src_valid;                                  // sem_ctl_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
	wire  [33:0] sem_ctl_slave_agent_rdata_fifo_src_data;                                   // sem_ctl_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
	wire         sem_ctl_slave_agent_rdata_fifo_src_ready;                                  // avalon_st_adapter_002:in_0_ready -> sem_ctl_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_002_out_0_valid;                                         // avalon_st_adapter_002:out_0_valid -> sem_ctl_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_002_out_0_data;                                          // avalon_st_adapter_002:out_0_data -> sem_ctl_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_002_out_0_ready;                                         // sem_ctl_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire   [0:0] avalon_st_adapter_002_out_0_error;                                         // avalon_st_adapter_002:out_0_error -> sem_ctl_slave_agent:rdata_fifo_sink_error
	wire         cpu_debug_mem_slave_agent_rdata_fifo_src_valid;                            // cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
	wire  [33:0] cpu_debug_mem_slave_agent_rdata_fifo_src_data;                             // cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
	wire         cpu_debug_mem_slave_agent_rdata_fifo_src_ready;                            // avalon_st_adapter_003:in_0_ready -> cpu_debug_mem_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_003_out_0_valid;                                         // avalon_st_adapter_003:out_0_valid -> cpu_debug_mem_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_003_out_0_data;                                          // avalon_st_adapter_003:out_0_data -> cpu_debug_mem_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_003_out_0_ready;                                         // cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire   [0:0] avalon_st_adapter_003_out_0_error;                                         // avalon_st_adapter_003:out_0_error -> cpu_debug_mem_slave_agent:rdata_fifo_sink_error
	wire         sem_ram_slave_agent_rdata_fifo_src_valid;                                  // sem_ram_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
	wire  [33:0] sem_ram_slave_agent_rdata_fifo_src_data;                                   // sem_ram_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
	wire         sem_ram_slave_agent_rdata_fifo_src_ready;                                  // avalon_st_adapter_004:in_0_ready -> sem_ram_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_004_out_0_valid;                                         // avalon_st_adapter_004:out_0_valid -> sem_ram_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_004_out_0_data;                                          // avalon_st_adapter_004:out_0_data -> sem_ram_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_004_out_0_ready;                                         // sem_ram_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
	wire   [0:0] avalon_st_adapter_004_out_0_error;                                         // avalon_st_adapter_004:out_0_error -> sem_ram_slave_agent:rdata_fifo_sink_error
	wire         sys_clk_timer_s1_agent_rdata_fifo_src_valid;                               // sys_clk_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
	wire  [33:0] sys_clk_timer_s1_agent_rdata_fifo_src_data;                                // sys_clk_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
	wire         sys_clk_timer_s1_agent_rdata_fifo_src_ready;                               // avalon_st_adapter_005:in_0_ready -> sys_clk_timer_s1_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_005_out_0_valid;                                         // avalon_st_adapter_005:out_0_valid -> sys_clk_timer_s1_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_005_out_0_data;                                          // avalon_st_adapter_005:out_0_data -> sys_clk_timer_s1_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_005_out_0_ready;                                         // sys_clk_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
	wire   [0:0] avalon_st_adapter_005_out_0_error;                                         // avalon_st_adapter_005:out_0_error -> sys_clk_timer_s1_agent:rdata_fifo_sink_error
	wire         mem_s2_agent_rdata_fifo_src_valid;                                         // mem_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
	wire  [33:0] mem_s2_agent_rdata_fifo_src_data;                                          // mem_s2_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
	wire         mem_s2_agent_rdata_fifo_src_ready;                                         // avalon_st_adapter_006:in_0_ready -> mem_s2_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_006_out_0_valid;                                         // avalon_st_adapter_006:out_0_valid -> mem_s2_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_006_out_0_data;                                          // avalon_st_adapter_006:out_0_data -> mem_s2_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_006_out_0_ready;                                         // mem_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
	wire   [0:0] avalon_st_adapter_006_out_0_error;                                         // avalon_st_adapter_006:out_0_error -> mem_s2_agent:rdata_fifo_sink_error
	wire         mem_s1_agent_rdata_fifo_src_valid;                                         // mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
	wire  [33:0] mem_s1_agent_rdata_fifo_src_data;                                          // mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
	wire         mem_s1_agent_rdata_fifo_src_ready;                                         // avalon_st_adapter_007:in_0_ready -> mem_s1_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_007_out_0_valid;                                         // avalon_st_adapter_007:out_0_valid -> mem_s1_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_007_out_0_data;                                          // avalon_st_adapter_007:out_0_data -> mem_s1_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_007_out_0_ready;                                         // mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
	wire   [0:0] avalon_st_adapter_007_out_0_error;                                         // avalon_st_adapter_007:out_0_error -> mem_s1_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (18),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (18),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) cpu_data_master_translator (
		.clk                    (clk_clk_clk),                                                        //                       clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                              //                     reset.reset
		.uav_address            (cpu_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (cpu_data_master_byteenable),                                         //                          .byteenable
		.av_read                (cpu_data_master_read),                                               //                          .read
		.av_readdata            (cpu_data_master_readdata),                                           //                          .readdata
		.av_write               (cpu_data_master_write),                                              //                          .write
		.av_writedata           (cpu_data_master_writedata),                                          //                          .writedata
		.av_debugaccess         (cpu_data_master_debugaccess),                                        //                          .debugaccess
		.av_burstcount          (1'b1),                                                               //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                               //               (terminated)
		.av_begintransfer       (1'b0),                                                               //               (terminated)
		.av_chipselect          (1'b0),                                                               //               (terminated)
		.av_readdatavalid       (),                                                                   //               (terminated)
		.av_lock                (1'b0),                                                               //               (terminated)
		.uav_clken              (),                                                                   //               (terminated)
		.av_clken               (1'b1),                                                               //               (terminated)
		.uav_response           (2'b00),                                                              //               (terminated)
		.av_response            (),                                                                   //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                               //               (terminated)
		.av_writeresponsevalid  ()                                                                    //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (18),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (18),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_instruction_master_translator (
		.clk                    (clk_clk_clk),                                                               //                       clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                     //                     reset.reset
		.uav_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read                (cpu_instruction_master_read),                                               //                          .read
		.av_readdata            (cpu_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount          (1'b1),                                                                      //               (terminated)
		.av_byteenable          (4'b1111),                                                                   //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                      //               (terminated)
		.av_begintransfer       (1'b0),                                                                      //               (terminated)
		.av_chipselect          (1'b0),                                                                      //               (terminated)
		.av_readdatavalid       (),                                                                          //               (terminated)
		.av_write               (1'b0),                                                                      //               (terminated)
		.av_writedata           (32'b00000000000000000000000000000000),                                      //               (terminated)
		.av_lock                (1'b0),                                                                      //               (terminated)
		.av_debugaccess         (1'b0),                                                                      //               (terminated)
		.uav_clken              (),                                                                          //               (terminated)
		.av_clken               (1'b1),                                                                      //               (terminated)
		.uav_response           (2'b00),                                                                     //               (terminated)
		.av_response            (),                                                                          //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                      //               (terminated)
		.av_writeresponsevalid  ()                                                                           //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                    (clk_clk_clk),                                        //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),              //                    reset.reset
		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),          //                         .read
		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (jtag_uart_avalon_jtag_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (jtag_uart_avalon_jtag_slave_write),                  //                         .write
		.av_read                (jtag_uart_avalon_jtag_slave_read),                   //                         .read
		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),               //                         .readdata
		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),              //                         .writedata
		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),            //                         .waitrequest
		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                   //              (terminated)
		.av_beginbursttransfer  (),                                                   //              (terminated)
		.av_burstcount          (),                                                   //              (terminated)
		.av_byteenable          (),                                                   //              (terminated)
		.av_readdatavalid       (1'b0),                                               //              (terminated)
		.av_writebyteenable     (),                                                   //              (terminated)
		.av_lock                (),                                                   //              (terminated)
		.av_clken               (),                                                   //              (terminated)
		.uav_clken              (1'b0),                                               //              (terminated)
		.av_debugaccess         (),                                                   //              (terminated)
		.av_outputenable        (),                                                   //              (terminated)
		.uav_response           (),                                                   //              (terminated)
		.av_response            (2'b00),                                              //              (terminated)
		.uav_writeresponsevalid (),                                                   //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (4),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) perf_counter_control_slave_translator (
		.clk                    (clk_clk_clk),                                       //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),             //                    reset.reset
		.uav_address            (perf_counter_control_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (perf_counter_control_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (perf_counter_control_slave_agent_m0_read),          //                         .read
		.uav_write              (perf_counter_control_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (perf_counter_control_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (perf_counter_control_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (perf_counter_control_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (perf_counter_control_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (perf_counter_control_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (perf_counter_control_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (perf_counter_control_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (perf_counter_control_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (perf_counter_control_slave_write),                  //                         .write
		.av_readdata            (perf_counter_control_slave_readdata),               //                         .readdata
		.av_writedata           (perf_counter_control_slave_writedata),              //                         .writedata
		.av_begintransfer       (perf_counter_control_slave_begintransfer),          //                         .begintransfer
		.av_read                (),                                                  //              (terminated)
		.av_beginbursttransfer  (),                                                  //              (terminated)
		.av_burstcount          (),                                                  //              (terminated)
		.av_byteenable          (),                                                  //              (terminated)
		.av_readdatavalid       (1'b0),                                              //              (terminated)
		.av_waitrequest         (1'b0),                                              //              (terminated)
		.av_writebyteenable     (),                                                  //              (terminated)
		.av_lock                (),                                                  //              (terminated)
		.av_chipselect          (),                                                  //              (terminated)
		.av_clken               (),                                                  //              (terminated)
		.uav_clken              (1'b0),                                              //              (terminated)
		.av_debugaccess         (),                                                  //              (terminated)
		.av_outputenable        (),                                                  //              (terminated)
		.uav_response           (),                                                  //              (terminated)
		.av_response            (2'b00),                                             //              (terminated)
		.uav_writeresponsevalid (),                                                  //              (terminated)
		.av_writeresponsevalid  (1'b0)                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sem_ctl_slave_translator (
		.clk                    (clk_clk_clk),                           //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sem_ctl_slave_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (sem_ctl_slave_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (sem_ctl_slave_agent_m0_read),           //                         .read
		.uav_write              (sem_ctl_slave_agent_m0_write),          //                         .write
		.uav_waitrequest        (sem_ctl_slave_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (sem_ctl_slave_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (sem_ctl_slave_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (sem_ctl_slave_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (sem_ctl_slave_agent_m0_writedata),      //                         .writedata
		.uav_lock               (sem_ctl_slave_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (sem_ctl_slave_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (sem_ctl_slave_address),                 //      avalon_anti_slave_0.address
		.av_write               (sem_ctl_slave_write),                   //                         .write
		.av_read                (sem_ctl_slave_read),                    //                         .read
		.av_readdata            (sem_ctl_slave_readdata),                //                         .readdata
		.av_writedata           (sem_ctl_slave_writedata),               //                         .writedata
		.av_begintransfer       (),                                      //              (terminated)
		.av_beginbursttransfer  (),                                      //              (terminated)
		.av_burstcount          (),                                      //              (terminated)
		.av_byteenable          (),                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                  //              (terminated)
		.av_waitrequest         (1'b0),                                  //              (terminated)
		.av_writebyteenable     (),                                      //              (terminated)
		.av_lock                (),                                      //              (terminated)
		.av_chipselect          (),                                      //              (terminated)
		.av_clken               (),                                      //              (terminated)
		.uav_clken              (1'b0),                                  //              (terminated)
		.av_debugaccess         (),                                      //              (terminated)
		.av_outputenable        (),                                      //              (terminated)
		.uav_response           (),                                      //              (terminated)
		.av_response            (2'b00),                                 //              (terminated)
		.uav_writeresponsevalid (),                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) cpu_debug_mem_slave_translator (
		.clk                    (clk_clk_clk),                                //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),      //                    reset.reset
		.uav_address            (cpu_debug_mem_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (cpu_debug_mem_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (cpu_debug_mem_slave_agent_m0_read),          //                         .read
		.uav_write              (cpu_debug_mem_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (cpu_debug_mem_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (cpu_debug_mem_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (cpu_debug_mem_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (cpu_debug_mem_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (cpu_debug_mem_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (cpu_debug_mem_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (cpu_debug_mem_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (cpu_debug_mem_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (cpu_debug_mem_slave_write),                  //                         .write
		.av_read                (cpu_debug_mem_slave_read),                   //                         .read
		.av_readdata            (cpu_debug_mem_slave_readdata),               //                         .readdata
		.av_writedata           (cpu_debug_mem_slave_writedata),              //                         .writedata
		.av_byteenable          (cpu_debug_mem_slave_byteenable),             //                         .byteenable
		.av_waitrequest         (cpu_debug_mem_slave_waitrequest),            //                         .waitrequest
		.av_debugaccess         (cpu_debug_mem_slave_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                           //              (terminated)
		.av_beginbursttransfer  (),                                           //              (terminated)
		.av_burstcount          (),                                           //              (terminated)
		.av_readdatavalid       (1'b0),                                       //              (terminated)
		.av_writebyteenable     (),                                           //              (terminated)
		.av_lock                (),                                           //              (terminated)
		.av_chipselect          (),                                           //              (terminated)
		.av_clken               (),                                           //              (terminated)
		.uav_clken              (1'b0),                                       //              (terminated)
		.av_outputenable        (),                                           //              (terminated)
		.uav_response           (),                                           //              (terminated)
		.av_response            (2'b00),                                      //              (terminated)
		.uav_writeresponsevalid (),                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (4),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sem_ram_slave_translator (
		.clk                    (clk_clk_clk),                           //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sem_ram_slave_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (sem_ram_slave_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (sem_ram_slave_agent_m0_read),           //                         .read
		.uav_write              (sem_ram_slave_agent_m0_write),          //                         .write
		.uav_waitrequest        (sem_ram_slave_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (sem_ram_slave_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (sem_ram_slave_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (sem_ram_slave_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (sem_ram_slave_agent_m0_writedata),      //                         .writedata
		.uav_lock               (sem_ram_slave_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (sem_ram_slave_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (sem_ram_slave_address),                 //      avalon_anti_slave_0.address
		.av_write               (sem_ram_slave_write),                   //                         .write
		.av_writedata           (sem_ram_slave_writedata),               //                         .writedata
		.av_read                (),                                      //              (terminated)
		.av_readdata            (32'b11011110101011011101111010101101),  //              (terminated)
		.av_begintransfer       (),                                      //              (terminated)
		.av_beginbursttransfer  (),                                      //              (terminated)
		.av_burstcount          (),                                      //              (terminated)
		.av_byteenable          (),                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                  //              (terminated)
		.av_waitrequest         (1'b0),                                  //              (terminated)
		.av_writebyteenable     (),                                      //              (terminated)
		.av_lock                (),                                      //              (terminated)
		.av_chipselect          (),                                      //              (terminated)
		.av_clken               (),                                      //              (terminated)
		.uav_clken              (1'b0),                                  //              (terminated)
		.av_debugaccess         (),                                      //              (terminated)
		.av_outputenable        (),                                      //              (terminated)
		.uav_response           (),                                      //              (terminated)
		.av_response            (2'b00),                                 //              (terminated)
		.uav_writeresponsevalid (),                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sys_clk_timer_s1_translator (
		.clk                    (clk_clk_clk),                             //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset),   //                    reset.reset
		.uav_address            (sys_clk_timer_s1_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (sys_clk_timer_s1_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (sys_clk_timer_s1_agent_m0_read),          //                         .read
		.uav_write              (sys_clk_timer_s1_agent_m0_write),         //                         .write
		.uav_waitrequest        (sys_clk_timer_s1_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (sys_clk_timer_s1_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (sys_clk_timer_s1_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (sys_clk_timer_s1_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (sys_clk_timer_s1_agent_m0_writedata),     //                         .writedata
		.uav_lock               (sys_clk_timer_s1_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (sys_clk_timer_s1_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (sys_clk_timer_s1_address),                //      avalon_anti_slave_0.address
		.av_write               (sys_clk_timer_s1_write),                  //                         .write
		.av_readdata            (sys_clk_timer_s1_readdata),               //                         .readdata
		.av_writedata           (sys_clk_timer_s1_writedata),              //                         .writedata
		.av_chipselect          (sys_clk_timer_s1_chipselect),             //                         .chipselect
		.av_read                (),                                        //              (terminated)
		.av_begintransfer       (),                                        //              (terminated)
		.av_beginbursttransfer  (),                                        //              (terminated)
		.av_burstcount          (),                                        //              (terminated)
		.av_byteenable          (),                                        //              (terminated)
		.av_readdatavalid       (1'b0),                                    //              (terminated)
		.av_waitrequest         (1'b0),                                    //              (terminated)
		.av_writebyteenable     (),                                        //              (terminated)
		.av_lock                (),                                        //              (terminated)
		.av_clken               (),                                        //              (terminated)
		.uav_clken              (1'b0),                                    //              (terminated)
		.av_debugaccess         (),                                        //              (terminated)
		.av_outputenable        (),                                        //              (terminated)
		.uav_response           (),                                        //              (terminated)
		.av_response            (2'b00),                                   //              (terminated)
		.uav_writeresponsevalid (),                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (15),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) mem_s2_translator (
		.clk                    (clk_clk_clk),                           //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (mem_s2_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (mem_s2_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (mem_s2_agent_m0_read),                  //                         .read
		.uav_write              (mem_s2_agent_m0_write),                 //                         .write
		.uav_waitrequest        (mem_s2_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (mem_s2_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (mem_s2_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (mem_s2_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (mem_s2_agent_m0_writedata),             //                         .writedata
		.uav_lock               (mem_s2_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (mem_s2_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (mem_s2_address),                        //      avalon_anti_slave_0.address
		.av_write               (mem_s2_write),                          //                         .write
		.av_readdata            (mem_s2_readdata),                       //                         .readdata
		.av_writedata           (mem_s2_writedata),                      //                         .writedata
		.av_byteenable          (mem_s2_byteenable),                     //                         .byteenable
		.av_chipselect          (mem_s2_chipselect),                     //                         .chipselect
		.av_clken               (mem_s2_clken),                          //                         .clken
		.av_read                (),                                      //              (terminated)
		.av_begintransfer       (),                                      //              (terminated)
		.av_beginbursttransfer  (),                                      //              (terminated)
		.av_burstcount          (),                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                  //              (terminated)
		.av_waitrequest         (1'b0),                                  //              (terminated)
		.av_writebyteenable     (),                                      //              (terminated)
		.av_lock                (),                                      //              (terminated)
		.uav_clken              (1'b0),                                  //              (terminated)
		.av_debugaccess         (),                                      //              (terminated)
		.av_outputenable        (),                                      //              (terminated)
		.uav_response           (),                                      //              (terminated)
		.av_response            (2'b00),                                 //              (terminated)
		.uav_writeresponsevalid (),                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (15),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (18),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) mem_s1_translator (
		.clk                    (clk_clk_clk),                           //                      clk.clk
		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (mem_s1_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (mem_s1_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (mem_s1_agent_m0_read),                  //                         .read
		.uav_write              (mem_s1_agent_m0_write),                 //                         .write
		.uav_waitrequest        (mem_s1_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (mem_s1_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (mem_s1_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (mem_s1_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (mem_s1_agent_m0_writedata),             //                         .writedata
		.uav_lock               (mem_s1_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (mem_s1_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (mem_s1_address),                        //      avalon_anti_slave_0.address
		.av_write               (mem_s1_write),                          //                         .write
		.av_readdata            (mem_s1_readdata),                       //                         .readdata
		.av_writedata           (mem_s1_writedata),                      //                         .writedata
		.av_byteenable          (mem_s1_byteenable),                     //                         .byteenable
		.av_chipselect          (mem_s1_chipselect),                     //                         .chipselect
		.av_clken               (mem_s1_clken),                          //                         .clken
		.av_read                (),                                      //              (terminated)
		.av_begintransfer       (),                                      //              (terminated)
		.av_beginbursttransfer  (),                                      //              (terminated)
		.av_burstcount          (),                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                  //              (terminated)
		.av_waitrequest         (1'b0),                                  //              (terminated)
		.av_writebyteenable     (),                                      //              (terminated)
		.av_lock                (),                                      //              (terminated)
		.uav_clken              (1'b0),                                  //              (terminated)
		.av_debugaccess         (),                                      //              (terminated)
		.av_outputenable        (),                                      //              (terminated)
		.uav_response           (),                                      //              (terminated)
		.av_response            (2'b00),                                 //              (terminated)
		.uav_writeresponsevalid (),                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_QOS_H                 (74),
		.PKT_QOS_L                 (74),
		.PKT_DATA_SIDEBAND_H       (72),
		.PKT_DATA_SIDEBAND_L       (72),
		.PKT_ADDR_SIDEBAND_H       (71),
		.PKT_ADDR_SIDEBAND_L       (71),
		.PKT_BURST_TYPE_H          (70),
		.PKT_BURST_TYPE_L          (69),
		.PKT_CACHE_H               (88),
		.PKT_CACHE_L               (85),
		.PKT_THREAD_ID_H           (81),
		.PKT_THREAD_ID_L           (81),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_EXCLUSIVE       (59),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.ST_DATA_W                 (94),
		.ST_CHANNEL_W              (8),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_data_master_agent (
		.clk                   (clk_clk_clk),                                                        //       clk.clk
		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                              // clk_reset.reset
		.av_address            (cpu_data_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_data_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_data_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_data_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_data_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_data_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                  //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                   //          .data
		.rp_channel            (rsp_mux_src_channel),                                                //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                          //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                            //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                  //          .ready
		.av_response           (),                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                    // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_QOS_H                 (74),
		.PKT_QOS_L                 (74),
		.PKT_DATA_SIDEBAND_H       (72),
		.PKT_DATA_SIDEBAND_L       (72),
		.PKT_ADDR_SIDEBAND_H       (71),
		.PKT_ADDR_SIDEBAND_L       (71),
		.PKT_BURST_TYPE_H          (70),
		.PKT_BURST_TYPE_L          (69),
		.PKT_CACHE_H               (88),
		.PKT_CACHE_L               (85),
		.PKT_THREAD_ID_H           (81),
		.PKT_THREAD_ID_L           (81),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_EXCLUSIVE       (59),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.ST_DATA_W                 (94),
		.ST_CHANNEL_W              (8),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_instruction_master_agent (
		.clk                   (clk_clk_clk),                                                               //       clk.clk
		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                     // clk_reset.reset
		.av_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_instruction_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_instruction_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_instruction_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                     //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                      //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                                   //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                             //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                               //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                     //          .ready
		.av_response           (),                                                                          // (terminated)
		.av_writeresponsevalid ()                                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) jtag_uart_avalon_jtag_slave_agent (
		.clk                     (clk_clk_clk),                                                  //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                        //       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                            //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                            //                .valid
		.cp_data                 (cmd_mux_src_data),                                             //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                          //                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                 //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                //                .error
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                        //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                                  //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),                        // clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated)
		.csr_read          (1'b0),                                                         // (terminated)
		.csr_write         (1'b0),                                                         // (terminated)
		.csr_readdata      (),                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
		.almost_full_data  (),                                                             // (terminated)
		.almost_empty_data (),                                                             // (terminated)
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.in_error          (1'b0),                                                         // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_channel        (1'b0),                                                         // (terminated)
		.out_channel       ()                                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) perf_counter_control_slave_agent (
		.clk                     (clk_clk_clk),                                                 //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                       //       clk_reset.reset
		.m0_address              (perf_counter_control_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (perf_counter_control_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (perf_counter_control_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (perf_counter_control_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (perf_counter_control_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (perf_counter_control_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (perf_counter_control_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (perf_counter_control_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (perf_counter_control_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (perf_counter_control_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (perf_counter_control_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (perf_counter_control_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (perf_counter_control_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (perf_counter_control_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (perf_counter_control_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (perf_counter_control_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                       //              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                       //                .valid
		.cp_data                 (cmd_mux_001_src_data),                                        //                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                               //                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                                 //                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                     //                .channel
		.rf_sink_ready           (perf_counter_control_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (perf_counter_control_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (perf_counter_control_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (perf_counter_control_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (perf_counter_control_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (perf_counter_control_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (perf_counter_control_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (perf_counter_control_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (perf_counter_control_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (perf_counter_control_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                           // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                           //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                            //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                           //                .error
		.rdata_fifo_src_ready    (perf_counter_control_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (perf_counter_control_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (perf_counter_control_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                       //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                         //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) perf_counter_control_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                                 //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),                       // clk_reset.reset
		.in_data           (perf_counter_control_slave_agent_rf_source_data),             //        in.data
		.in_valid          (perf_counter_control_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (perf_counter_control_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (perf_counter_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (perf_counter_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (perf_counter_control_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (perf_counter_control_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (perf_counter_control_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (perf_counter_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (perf_counter_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                       // (terminated)
		.csr_read          (1'b0),                                                        // (terminated)
		.csr_write         (1'b0),                                                        // (terminated)
		.csr_readdata      (),                                                            // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                        // (terminated)
		.almost_full_data  (),                                                            // (terminated)
		.almost_empty_data (),                                                            // (terminated)
		.in_empty          (1'b0),                                                        // (terminated)
		.out_empty         (),                                                            // (terminated)
		.in_error          (1'b0),                                                        // (terminated)
		.out_error         (),                                                            // (terminated)
		.in_channel        (1'b0),                                                        // (terminated)
		.out_channel       ()                                                             // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sem_ctl_slave_agent (
		.clk                     (clk_clk_clk),                                    //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
		.m0_address              (sem_ctl_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sem_ctl_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sem_ctl_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sem_ctl_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sem_ctl_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (sem_ctl_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sem_ctl_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sem_ctl_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (sem_ctl_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sem_ctl_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (sem_ctl_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (sem_ctl_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sem_ctl_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (sem_ctl_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (sem_ctl_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (sem_ctl_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_002_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                        //                .channel
		.rf_sink_ready           (sem_ctl_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sem_ctl_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sem_ctl_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sem_ctl_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sem_ctl_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sem_ctl_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sem_ctl_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sem_ctl_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sem_ctl_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sem_ctl_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),              //                .error
		.rdata_fifo_src_ready    (sem_ctl_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sem_ctl_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sem_ctl_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sem_ctl_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                    //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
		.in_data           (sem_ctl_slave_agent_rf_source_data),             //        in.data
		.in_valid          (sem_ctl_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (sem_ctl_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sem_ctl_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sem_ctl_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sem_ctl_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sem_ctl_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sem_ctl_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sem_ctl_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sem_ctl_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) cpu_debug_mem_slave_agent (
		.clk                     (clk_clk_clk),                                          //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                //       clk_reset.reset
		.m0_address              (cpu_debug_mem_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (cpu_debug_mem_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (cpu_debug_mem_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (cpu_debug_mem_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (cpu_debug_mem_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (cpu_debug_mem_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (cpu_debug_mem_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (cpu_debug_mem_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (cpu_debug_mem_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (cpu_debug_mem_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (cpu_debug_mem_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (cpu_debug_mem_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (cpu_debug_mem_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (cpu_debug_mem_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (cpu_debug_mem_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (cpu_debug_mem_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                //              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                //                .valid
		.cp_data                 (cmd_mux_003_src_data),                                 //                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                          //                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                              //                .channel
		.rf_sink_ready           (cpu_debug_mem_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (cpu_debug_mem_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (cpu_debug_mem_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (cpu_debug_mem_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (cpu_debug_mem_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (cpu_debug_mem_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (cpu_debug_mem_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (cpu_debug_mem_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                    //                .error
		.rdata_fifo_src_ready    (cpu_debug_mem_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (cpu_debug_mem_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (cpu_debug_mem_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) cpu_debug_mem_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                          //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_data           (cpu_debug_mem_slave_agent_rf_source_data),             //        in.data
		.in_valid          (cpu_debug_mem_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (cpu_debug_mem_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (cpu_debug_mem_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (cpu_debug_mem_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (cpu_debug_mem_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (cpu_debug_mem_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (cpu_debug_mem_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sem_ram_slave_agent (
		.clk                     (clk_clk_clk),                                    //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
		.m0_address              (sem_ram_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sem_ram_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sem_ram_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sem_ram_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sem_ram_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (sem_ram_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sem_ram_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sem_ram_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (sem_ram_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sem_ram_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (sem_ram_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (sem_ram_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sem_ram_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (sem_ram_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (sem_ram_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (sem_ram_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_004_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_004_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_004_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_004_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_004_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_004_src_channel),                        //                .channel
		.rf_sink_ready           (sem_ram_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sem_ram_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sem_ram_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sem_ram_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sem_ram_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sem_ram_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sem_ram_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sem_ram_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sem_ram_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sem_ram_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_004_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_004_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_004_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_004_out_0_error),              //                .error
		.rdata_fifo_src_ready    (sem_ram_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sem_ram_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sem_ram_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sem_ram_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                    //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
		.in_data           (sem_ram_slave_agent_rf_source_data),             //        in.data
		.in_valid          (sem_ram_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (sem_ram_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sem_ram_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sem_ram_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sem_ram_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sem_ram_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sem_ram_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sem_ram_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sem_ram_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sys_clk_timer_s1_agent (
		.clk                     (clk_clk_clk),                                       //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),             //       clk_reset.reset
		.m0_address              (sys_clk_timer_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sys_clk_timer_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sys_clk_timer_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sys_clk_timer_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sys_clk_timer_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (sys_clk_timer_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sys_clk_timer_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sys_clk_timer_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (sys_clk_timer_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sys_clk_timer_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (sys_clk_timer_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (sys_clk_timer_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sys_clk_timer_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (sys_clk_timer_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (sys_clk_timer_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (sys_clk_timer_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_005_src_ready),                             //              cp.ready
		.cp_valid                (cmd_mux_005_src_valid),                             //                .valid
		.cp_data                 (cmd_mux_005_src_data),                              //                .data
		.cp_startofpacket        (cmd_mux_005_src_startofpacket),                     //                .startofpacket
		.cp_endofpacket          (cmd_mux_005_src_endofpacket),                       //                .endofpacket
		.cp_channel              (cmd_mux_005_src_channel),                           //                .channel
		.rf_sink_ready           (sys_clk_timer_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sys_clk_timer_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sys_clk_timer_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sys_clk_timer_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sys_clk_timer_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sys_clk_timer_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sys_clk_timer_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sys_clk_timer_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_005_out_0_ready),                 // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_005_out_0_valid),                 //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_005_out_0_data),                  //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_005_out_0_error),                 //                .error
		.rdata_fifo_src_ready    (sys_clk_timer_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sys_clk_timer_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sys_clk_timer_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                             //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                               //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sys_clk_timer_s1_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                       //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),             // clk_reset.reset
		.in_data           (sys_clk_timer_s1_agent_rf_source_data),             //        in.data
		.in_valid          (sys_clk_timer_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (sys_clk_timer_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sys_clk_timer_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sys_clk_timer_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sys_clk_timer_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sys_clk_timer_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sys_clk_timer_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                             // (terminated)
		.csr_read          (1'b0),                                              // (terminated)
		.csr_write         (1'b0),                                              // (terminated)
		.csr_readdata      (),                                                  // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated)
		.almost_full_data  (),                                                  // (terminated)
		.almost_empty_data (),                                                  // (terminated)
		.in_empty          (1'b0),                                              // (terminated)
		.out_empty         (),                                                  // (terminated)
		.in_error          (1'b0),                                              // (terminated)
		.out_error         (),                                                  // (terminated)
		.in_channel        (1'b0),                                              // (terminated)
		.out_channel       ()                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) mem_s2_agent (
		.clk                     (clk_clk_clk),                             //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),   //       clk_reset.reset
		.m0_address              (mem_s2_agent_m0_address),                 //              m0.address
		.m0_burstcount           (mem_s2_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (mem_s2_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (mem_s2_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (mem_s2_agent_m0_lock),                    //                .lock
		.m0_readdata             (mem_s2_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (mem_s2_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (mem_s2_agent_m0_read),                    //                .read
		.m0_waitrequest          (mem_s2_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (mem_s2_agent_m0_writedata),               //                .writedata
		.m0_write                (mem_s2_agent_m0_write),                   //                .write
		.rp_endofpacket          (mem_s2_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (mem_s2_agent_rp_ready),                   //                .ready
		.rp_valid                (mem_s2_agent_rp_valid),                   //                .valid
		.rp_data                 (mem_s2_agent_rp_data),                    //                .data
		.rp_startofpacket        (mem_s2_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_006_src_ready),                   //              cp.ready
		.cp_valid                (cmd_mux_006_src_valid),                   //                .valid
		.cp_data                 (cmd_mux_006_src_data),                    //                .data
		.cp_startofpacket        (cmd_mux_006_src_startofpacket),           //                .startofpacket
		.cp_endofpacket          (cmd_mux_006_src_endofpacket),             //                .endofpacket
		.cp_channel              (cmd_mux_006_src_channel),                 //                .channel
		.rf_sink_ready           (mem_s2_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (mem_s2_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (mem_s2_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (mem_s2_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (mem_s2_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (mem_s2_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (mem_s2_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (mem_s2_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (mem_s2_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (mem_s2_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_006_out_0_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_006_out_0_valid),       //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_006_out_0_data),        //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_006_out_0_error),       //                .error
		.rdata_fifo_src_ready    (mem_s2_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mem_s2_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (mem_s2_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                   //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                     //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mem_s2_agent_rsp_fifo (
		.clk               (clk_clk_clk),                             //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.in_data           (mem_s2_agent_rf_source_data),             //        in.data
		.in_valid          (mem_s2_agent_rf_source_valid),            //          .valid
		.in_ready          (mem_s2_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (mem_s2_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (mem_s2_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (mem_s2_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (mem_s2_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (mem_s2_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (mem_s2_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (mem_s2_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                   // (terminated)
		.csr_read          (1'b0),                                    // (terminated)
		.csr_write         (1'b0),                                    // (terminated)
		.csr_readdata      (),                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),    // (terminated)
		.almost_full_data  (),                                        // (terminated)
		.almost_empty_data (),                                        // (terminated)
		.in_empty          (1'b0),                                    // (terminated)
		.out_empty         (),                                        // (terminated)
		.in_error          (1'b0),                                    // (terminated)
		.out_error         (),                                        // (terminated)
		.in_channel        (1'b0),                                    // (terminated)
		.out_channel       ()                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (93),
		.PKT_ORI_BURST_SIZE_L      (91),
		.PKT_RESPONSE_STATUS_H     (90),
		.PKT_RESPONSE_STATUS_L     (89),
		.PKT_BURST_SIZE_H          (68),
		.PKT_BURST_SIZE_L          (66),
		.PKT_TRANS_LOCK            (58),
		.PKT_BEGIN_BURST           (73),
		.PKT_PROTECTION_H          (84),
		.PKT_PROTECTION_L          (82),
		.PKT_BURSTWRAP_H           (65),
		.PKT_BURSTWRAP_L           (63),
		.PKT_BYTE_CNT_H            (62),
		.PKT_BYTE_CNT_L            (60),
		.PKT_ADDR_H                (53),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (54),
		.PKT_TRANS_POSTED          (55),
		.PKT_TRANS_WRITE           (56),
		.PKT_TRANS_READ            (57),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (75),
		.PKT_DEST_ID_H             (80),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (8),
		.ST_DATA_W                 (94),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) mem_s1_agent (
		.clk                     (clk_clk_clk),                             //             clk.clk
		.reset                   (cpu_reset_reset_bridge_in_reset_reset),   //       clk_reset.reset
		.m0_address              (mem_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (mem_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (mem_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (mem_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (mem_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (mem_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (mem_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (mem_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (mem_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (mem_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (mem_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (mem_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (mem_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (mem_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (mem_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (mem_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_007_src_ready),                   //              cp.ready
		.cp_valid                (cmd_mux_007_src_valid),                   //                .valid
		.cp_data                 (cmd_mux_007_src_data),                    //                .data
		.cp_startofpacket        (cmd_mux_007_src_startofpacket),           //                .startofpacket
		.cp_endofpacket          (cmd_mux_007_src_endofpacket),             //                .endofpacket
		.cp_channel              (cmd_mux_007_src_channel),                 //                .channel
		.rf_sink_ready           (mem_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (mem_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (mem_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (mem_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (mem_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (mem_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (mem_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (mem_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (mem_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (mem_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_007_out_0_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_007_out_0_valid),       //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_007_out_0_data),        //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_007_out_0_error),       //                .error
		.rdata_fifo_src_ready    (mem_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mem_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (mem_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                   //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                     //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (95),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mem_s1_agent_rsp_fifo (
		.clk               (clk_clk_clk),                             //       clk.clk
		.reset             (cpu_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.in_data           (mem_s1_agent_rf_source_data),             //        in.data
		.in_valid          (mem_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (mem_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (mem_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (mem_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (mem_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (mem_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (mem_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (mem_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (mem_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                   // (terminated)
		.csr_read          (1'b0),                                    // (terminated)
		.csr_write         (1'b0),                                    // (terminated)
		.csr_readdata      (),                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),    // (terminated)
		.almost_full_data  (),                                        // (terminated)
		.almost_empty_data (),                                        // (terminated)
		.in_empty          (1'b0),                                    // (terminated)
		.out_empty         (),                                        // (terminated)
		.in_error          (1'b0),                                    // (terminated)
		.out_error         (),                                        // (terminated)
		.in_channel        (1'b0),                                    // (terminated)
		.out_channel       ()                                         // (terminated)
	);

	niosII_mm_interconnect_0_router router (
		.sink_ready         (cpu_data_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_data_master_agent_cp_valid),         //          .valid
		.sink_data          (cpu_data_master_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_data_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                            //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.src_ready          (router_src_ready),                       //       src.ready
		.src_valid          (router_src_valid),                       //          .valid
		.src_data           (router_src_data),                        //          .data
		.src_channel        (router_src_channel),                     //          .channel
		.src_startofpacket  (router_src_startofpacket),               //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                  //          .endofpacket
	);

	niosII_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (cpu_instruction_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_instruction_master_agent_cp_valid),         //          .valid
		.sink_data          (cpu_instruction_master_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_instruction_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                   //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
		.src_ready          (router_001_src_ready),                          //       src.ready
		.src_valid          (router_001_src_valid),                          //          .valid
		.src_data           (router_001_src_data),                           //          .data
		.src_channel        (router_001_src_channel),                        //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                  //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                     //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),         //          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),          //          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                        //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.src_ready          (router_002_src_ready),                               //       src.ready
		.src_valid          (router_002_src_valid),                               //          .valid
		.src_data           (router_002_src_data),                                //          .data
		.src_channel        (router_002_src_channel),                             //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                       //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                          //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_003 (
		.sink_ready         (perf_counter_control_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (perf_counter_control_slave_agent_rp_valid),         //          .valid
		.sink_data          (perf_counter_control_slave_agent_rp_data),          //          .data
		.sink_startofpacket (perf_counter_control_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (perf_counter_control_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                       //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),             // clk_reset.reset
		.src_ready          (router_003_src_ready),                              //       src.ready
		.src_valid          (router_003_src_valid),                              //          .valid
		.src_data           (router_003_src_data),                               //          .data
		.src_channel        (router_003_src_channel),                            //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                      //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                         //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_004 (
		.sink_ready         (sem_ctl_slave_agent_rp_ready),          //      sink.ready
		.sink_valid         (sem_ctl_slave_agent_rp_valid),          //          .valid
		.sink_data          (sem_ctl_slave_agent_rp_data),           //          .data
		.sink_startofpacket (sem_ctl_slave_agent_rp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (sem_ctl_slave_agent_rp_endofpacket),    //          .endofpacket
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                  //       src.ready
		.src_valid          (router_004_src_valid),                  //          .valid
		.src_data           (router_004_src_data),                   //          .data
		.src_channel        (router_004_src_channel),                //          .channel
		.src_startofpacket  (router_004_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_router_005 router_005 (
		.sink_ready         (cpu_debug_mem_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (cpu_debug_mem_slave_agent_rp_valid),         //          .valid
		.sink_data          (cpu_debug_mem_slave_agent_rp_data),          //          .data
		.sink_startofpacket (cpu_debug_mem_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_debug_mem_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
		.src_ready          (router_005_src_ready),                       //       src.ready
		.src_valid          (router_005_src_valid),                       //          .valid
		.src_data           (router_005_src_data),                        //          .data
		.src_channel        (router_005_src_channel),                     //          .channel
		.src_startofpacket  (router_005_src_startofpacket),               //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                  //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_006 (
		.sink_ready         (sem_ram_slave_agent_rp_ready),          //      sink.ready
		.sink_valid         (sem_ram_slave_agent_rp_valid),          //          .valid
		.sink_data          (sem_ram_slave_agent_rp_data),           //          .data
		.sink_startofpacket (sem_ram_slave_agent_rp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (sem_ram_slave_agent_rp_endofpacket),    //          .endofpacket
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                  //       src.ready
		.src_valid          (router_006_src_valid),                  //          .valid
		.src_data           (router_006_src_data),                   //          .data
		.src_channel        (router_006_src_channel),                //          .channel
		.src_startofpacket  (router_006_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_007 (
		.sink_ready         (sys_clk_timer_s1_agent_rp_ready),         //      sink.ready
		.sink_valid         (sys_clk_timer_s1_agent_rp_valid),         //          .valid
		.sink_data          (sys_clk_timer_s1_agent_rp_data),          //          .data
		.sink_startofpacket (sys_clk_timer_s1_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sys_clk_timer_s1_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.src_ready          (router_007_src_ready),                    //       src.ready
		.src_valid          (router_007_src_valid),                    //          .valid
		.src_data           (router_007_src_data),                     //          .data
		.src_channel        (router_007_src_channel),                  //          .channel
		.src_startofpacket  (router_007_src_startofpacket),            //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)               //          .endofpacket
	);

	niosII_mm_interconnect_0_router_002 router_008 (
		.sink_ready         (mem_s2_agent_rp_ready),                 //      sink.ready
		.sink_valid         (mem_s2_agent_rp_valid),                 //          .valid
		.sink_data          (mem_s2_agent_rp_data),                  //          .data
		.sink_startofpacket (mem_s2_agent_rp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (mem_s2_agent_rp_endofpacket),           //          .endofpacket
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_008_src_ready),                  //       src.ready
		.src_valid          (router_008_src_valid),                  //          .valid
		.src_data           (router_008_src_data),                   //          .data
		.src_channel        (router_008_src_channel),                //          .channel
		.src_startofpacket  (router_008_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_router_009 router_009 (
		.sink_ready         (mem_s1_agent_rp_ready),                 //      sink.ready
		.sink_valid         (mem_s1_agent_rp_valid),                 //          .valid
		.sink_data          (mem_s1_agent_rp_data),                  //          .data
		.sink_startofpacket (mem_s1_agent_rp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (mem_s1_agent_rp_endofpacket),           //          .endofpacket
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_009_src_ready),                  //       src.ready
		.src_valid          (router_009_src_valid),                  //          .valid
		.src_data           (router_009_src_data),                   //          .data
		.src_channel        (router_009_src_channel),                //          .channel
		.src_startofpacket  (router_009_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (router_009_src_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                      //      sink.ready
		.sink_channel       (router_src_channel),                    //          .channel
		.sink_data          (router_src_data),                       //          .data
		.sink_startofpacket (router_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                //          .endofpacket
		.sink_valid         (router_src_valid),                      //          .valid
		.src0_ready         (cmd_demux_src0_ready),                  //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                  //          .valid
		.src0_data          (cmd_demux_src0_data),                   //          .data
		.src0_channel       (cmd_demux_src0_channel),                //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),          //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),            //          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                  //      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                  //          .valid
		.src1_data          (cmd_demux_src1_data),                   //          .data
		.src1_channel       (cmd_demux_src1_channel),                //          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),          //          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),            //          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                  //      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                  //          .valid
		.src2_data          (cmd_demux_src2_data),                   //          .data
		.src2_channel       (cmd_demux_src2_channel),                //          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),          //          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),            //          .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                  //      src3.ready
		.src3_valid         (cmd_demux_src3_valid),                  //          .valid
		.src3_data          (cmd_demux_src3_data),                   //          .data
		.src3_channel       (cmd_demux_src3_channel),                //          .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),          //          .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket),            //          .endofpacket
		.src4_ready         (cmd_demux_src4_ready),                  //      src4.ready
		.src4_valid         (cmd_demux_src4_valid),                  //          .valid
		.src4_data          (cmd_demux_src4_data),                   //          .data
		.src4_channel       (cmd_demux_src4_channel),                //          .channel
		.src4_startofpacket (cmd_demux_src4_startofpacket),          //          .startofpacket
		.src4_endofpacket   (cmd_demux_src4_endofpacket),            //          .endofpacket
		.src5_ready         (cmd_demux_src5_ready),                  //      src5.ready
		.src5_valid         (cmd_demux_src5_valid),                  //          .valid
		.src5_data          (cmd_demux_src5_data),                   //          .data
		.src5_channel       (cmd_demux_src5_channel),                //          .channel
		.src5_startofpacket (cmd_demux_src5_startofpacket),          //          .startofpacket
		.src5_endofpacket   (cmd_demux_src5_endofpacket),            //          .endofpacket
		.src6_ready         (cmd_demux_src6_ready),                  //      src6.ready
		.src6_valid         (cmd_demux_src6_valid),                  //          .valid
		.src6_data          (cmd_demux_src6_data),                   //          .data
		.src6_channel       (cmd_demux_src6_channel),                //          .channel
		.src6_startofpacket (cmd_demux_src6_startofpacket),          //          .startofpacket
		.src6_endofpacket   (cmd_demux_src6_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                  //      sink.ready
		.sink_channel       (router_001_src_channel),                //          .channel
		.sink_data          (router_001_src_data),                   //          .data
		.sink_startofpacket (router_001_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_001_src_valid),                  //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),              //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),              //          .valid
		.src0_data          (cmd_demux_001_src0_data),               //          .data
		.src0_channel       (cmd_demux_001_src0_channel),            //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),        //          .endofpacket
		.src1_ready         (cmd_demux_001_src1_ready),              //      src1.ready
		.src1_valid         (cmd_demux_001_src1_valid),              //          .valid
		.src1_data          (cmd_demux_001_src1_data),               //          .data
		.src1_channel       (cmd_demux_001_src1_channel),            //          .channel
		.src1_startofpacket (cmd_demux_001_src1_startofpacket),      //          .startofpacket
		.src1_endofpacket   (cmd_demux_001_src1_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                     //       src.ready
		.src_valid           (cmd_mux_src_valid),                     //          .valid
		.src_data            (cmd_mux_src_data),                      //          .data
		.src_channel         (cmd_mux_src_channel),                   //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),             //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),               //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                //          .channel
		.sink0_data          (cmd_demux_src0_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_001 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                 //          .valid
		.src_data            (cmd_mux_001_src_data),                  //          .data
		.src_channel         (cmd_mux_001_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                //          .channel
		.sink0_data          (cmd_demux_src1_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_002 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                 //          .valid
		.src_data            (cmd_mux_002_src_data),                  //          .data
		.src_channel         (cmd_mux_002_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src2_channel),                //          .channel
		.sink0_data          (cmd_demux_src2_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                 //          .valid
		.src_data            (cmd_mux_003_src_data),                  //          .data
		.src_channel         (cmd_mux_003_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src3_channel),                //          .channel
		.sink0_data          (cmd_demux_src3_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket),            //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),              //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),              //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),            //          .channel
		.sink1_data          (cmd_demux_001_src0_data),               //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),      //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_004 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_004_src_valid),                 //          .valid
		.src_data            (cmd_mux_004_src_data),                  //          .data
		.src_channel         (cmd_mux_004_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src4_channel),                //          .channel
		.sink0_data          (cmd_demux_src4_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_005 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_005_src_valid),                 //          .valid
		.src_data            (cmd_mux_005_src_data),                  //          .data
		.src_channel         (cmd_mux_005_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src5_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src5_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src5_channel),                //          .channel
		.sink0_data          (cmd_demux_src5_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src5_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src5_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_006 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_006_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_006_src_valid),                 //          .valid
		.src_data            (cmd_mux_006_src_data),                  //          .data
		.src_channel         (cmd_mux_006_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_006_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_006_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_src6_ready),                  //     sink0.ready
		.sink0_valid         (cmd_demux_src6_valid),                  //          .valid
		.sink0_channel       (cmd_demux_src6_channel),                //          .channel
		.sink0_data          (cmd_demux_src6_data),                   //          .data
		.sink0_startofpacket (cmd_demux_src6_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src6_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_mux cmd_mux_007 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_007_src_ready),                 //       src.ready
		.src_valid           (cmd_mux_007_src_valid),                 //          .valid
		.src_data            (cmd_mux_007_src_data),                  //          .data
		.src_channel         (cmd_mux_007_src_channel),               //          .channel
		.src_startofpacket   (cmd_mux_007_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_mux_007_src_endofpacket),           //          .endofpacket
		.sink0_ready         (cmd_demux_001_src1_ready),              //     sink0.ready
		.sink0_valid         (cmd_demux_001_src1_valid),              //          .valid
		.sink0_channel       (cmd_demux_001_src1_channel),            //          .channel
		.sink0_data          (cmd_demux_001_src1_data),               //          .data
		.sink0_startofpacket (cmd_demux_001_src1_startofpacket),      //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src1_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                  //      sink.ready
		.sink_channel       (router_002_src_channel),                //          .channel
		.sink_data          (router_002_src_data),                   //          .data
		.sink_startofpacket (router_002_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_002_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_src0_ready),                  //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                  //          .valid
		.src0_data          (rsp_demux_src0_data),                   //          .data
		.src0_channel       (rsp_demux_src0_channel),                //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),          //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)             //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_001 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                  //      sink.ready
		.sink_channel       (router_003_src_channel),                //          .channel
		.sink_data          (router_003_src_data),                   //          .data
		.sink_startofpacket (router_003_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_003_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),              //          .valid
		.src0_data          (rsp_demux_001_src0_data),               //          .data
		.src0_channel       (rsp_demux_001_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_002 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                  //      sink.ready
		.sink_channel       (router_004_src_channel),                //          .channel
		.sink_data          (router_004_src_data),                   //          .data
		.sink_startofpacket (router_004_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_004_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),              //          .valid
		.src0_data          (rsp_demux_002_src0_data),               //          .data
		.src0_channel       (rsp_demux_002_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_cmd_demux_001 rsp_demux_003 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                  //      sink.ready
		.sink_channel       (router_005_src_channel),                //          .channel
		.sink_data          (router_005_src_data),                   //          .data
		.sink_startofpacket (router_005_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_005_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),              //          .valid
		.src0_data          (rsp_demux_003_src0_data),               //          .data
		.src0_channel       (rsp_demux_003_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),        //          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),              //      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),              //          .valid
		.src1_data          (rsp_demux_003_src1_data),               //          .data
		.src1_channel       (rsp_demux_003_src1_channel),            //          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),      //          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_004 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                  //      sink.ready
		.sink_channel       (router_006_src_channel),                //          .channel
		.sink_data          (router_006_src_data),                   //          .data
		.sink_startofpacket (router_006_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_006_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_004_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),              //          .valid
		.src0_data          (rsp_demux_004_src0_data),               //          .data
		.src0_channel       (rsp_demux_004_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_005 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                  //      sink.ready
		.sink_channel       (router_007_src_channel),                //          .channel
		.sink_data          (router_007_src_data),                   //          .data
		.sink_startofpacket (router_007_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_007_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_005_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),              //          .valid
		.src0_data          (rsp_demux_005_src0_data),               //          .data
		.src0_channel       (rsp_demux_005_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_006 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_008_src_ready),                  //      sink.ready
		.sink_channel       (router_008_src_channel),                //          .channel
		.sink_data          (router_008_src_data),                   //          .data
		.sink_startofpacket (router_008_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_008_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_006_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_006_src0_valid),              //          .valid
		.src0_data          (rsp_demux_006_src0_data),               //          .data
		.src0_channel       (rsp_demux_006_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_006_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_006_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_demux rsp_demux_007 (
		.clk                (clk_clk_clk),                           //       clk.clk
		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_009_src_ready),                  //      sink.ready
		.sink_channel       (router_009_src_channel),                //          .channel
		.sink_data          (router_009_src_data),                   //          .data
		.sink_startofpacket (router_009_src_startofpacket),          //          .startofpacket
		.sink_endofpacket   (router_009_src_endofpacket),            //          .endofpacket
		.sink_valid         (router_009_src_valid),                  //          .valid
		.src0_ready         (rsp_demux_007_src0_ready),              //      src0.ready
		.src0_valid         (rsp_demux_007_src0_valid),              //          .valid
		.src0_data          (rsp_demux_007_src0_data),               //          .data
		.src0_channel       (rsp_demux_007_src0_channel),            //          .channel
		.src0_startofpacket (rsp_demux_007_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (rsp_demux_007_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                     //       src.ready
		.src_valid           (rsp_mux_src_valid),                     //          .valid
		.src_data            (rsp_mux_src_data),                      //          .data
		.src_channel         (rsp_mux_src_channel),                   //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),             //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),               //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                  //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                  //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                //          .channel
		.sink0_data          (rsp_demux_src0_data),                   //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),            //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),              //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),              //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),            //          .channel
		.sink1_data          (rsp_demux_001_src0_data),               //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),      //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),        //          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),              //     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),              //          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),            //          .channel
		.sink2_data          (rsp_demux_002_src0_data),               //          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),      //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),        //          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),              //     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),              //          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),            //          .channel
		.sink3_data          (rsp_demux_003_src0_data),               //          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),      //          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket),        //          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),              //     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),              //          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),            //          .channel
		.sink4_data          (rsp_demux_004_src0_data),               //          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),      //          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),        //          .endofpacket
		.sink5_ready         (rsp_demux_005_src0_ready),              //     sink5.ready
		.sink5_valid         (rsp_demux_005_src0_valid),              //          .valid
		.sink5_channel       (rsp_demux_005_src0_channel),            //          .channel
		.sink5_data          (rsp_demux_005_src0_data),               //          .data
		.sink5_startofpacket (rsp_demux_005_src0_startofpacket),      //          .startofpacket
		.sink5_endofpacket   (rsp_demux_005_src0_endofpacket),        //          .endofpacket
		.sink6_ready         (rsp_demux_006_src0_ready),              //     sink6.ready
		.sink6_valid         (rsp_demux_006_src0_valid),              //          .valid
		.sink6_channel       (rsp_demux_006_src0_channel),            //          .channel
		.sink6_data          (rsp_demux_006_src0_data),               //          .data
		.sink6_startofpacket (rsp_demux_006_src0_startofpacket),      //          .startofpacket
		.sink6_endofpacket   (rsp_demux_006_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
		.clk                 (clk_clk_clk),                           //       clk.clk
		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                 //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                 //          .valid
		.src_data            (rsp_mux_001_src_data),                  //          .data
		.src_channel         (rsp_mux_001_src_channel),               //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),           //          .endofpacket
		.sink0_ready         (rsp_demux_003_src1_ready),              //     sink0.ready
		.sink0_valid         (rsp_demux_003_src1_valid),              //          .valid
		.sink0_channel       (rsp_demux_003_src1_channel),            //          .channel
		.sink0_data          (rsp_demux_003_src1_data),               //          .data
		.sink0_startofpacket (rsp_demux_003_src1_startofpacket),      //          .startofpacket
		.sink0_endofpacket   (rsp_demux_003_src1_endofpacket),        //          .endofpacket
		.sink1_ready         (rsp_demux_007_src0_ready),              //     sink1.ready
		.sink1_valid         (rsp_demux_007_src0_valid),              //          .valid
		.sink1_channel       (rsp_demux_007_src0_channel),            //          .channel
		.sink1_data          (rsp_demux_007_src0_data),               //          .data
		.sink1_startofpacket (rsp_demux_007_src0_startofpacket),      //          .startofpacket
		.sink1_endofpacket   (rsp_demux_007_src0_endofpacket)         //          .endofpacket
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (clk_clk_clk),                                            // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),                  // in_rst_0.reset
		.in_0_data      (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                           //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                          //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                          //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                           //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (clk_clk_clk),                                           // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),                 // in_rst_0.reset
		.in_0_data      (perf_counter_control_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (perf_counter_control_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (perf_counter_control_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                      //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                     //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                     //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                      //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_002 (
		.in_clk_0_clk   (clk_clk_clk),                              // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
		.in_0_data      (sem_ctl_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (sem_ctl_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (sem_ctl_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_002_out_0_data),         //    out_0.data
		.out_0_valid    (avalon_st_adapter_002_out_0_valid),        //         .valid
		.out_0_ready    (avalon_st_adapter_002_out_0_ready),        //         .ready
		.out_0_error    (avalon_st_adapter_002_out_0_error)         //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_003 (
		.in_clk_0_clk   (clk_clk_clk),                                    // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),          // in_rst_0.reset
		.in_0_data      (cpu_debug_mem_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_003_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_003_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_003_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_003_out_0_error)               //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_004 (
		.in_clk_0_clk   (clk_clk_clk),                              // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
		.in_0_data      (sem_ram_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (sem_ram_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (sem_ram_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_004_out_0_data),         //    out_0.data
		.out_0_valid    (avalon_st_adapter_004_out_0_valid),        //         .valid
		.out_0_ready    (avalon_st_adapter_004_out_0_ready),        //         .ready
		.out_0_error    (avalon_st_adapter_004_out_0_error)         //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_005 (
		.in_clk_0_clk   (clk_clk_clk),                                 // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),       // in_rst_0.reset
		.in_0_data      (sys_clk_timer_s1_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (sys_clk_timer_s1_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (sys_clk_timer_s1_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_005_out_0_data),            //    out_0.data
		.out_0_valid    (avalon_st_adapter_005_out_0_valid),           //         .valid
		.out_0_ready    (avalon_st_adapter_005_out_0_ready),           //         .ready
		.out_0_error    (avalon_st_adapter_005_out_0_error)            //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_006 (
		.in_clk_0_clk   (clk_clk_clk),                           // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (mem_s2_agent_rdata_fifo_src_data),      //     in_0.data
		.in_0_valid     (mem_s2_agent_rdata_fifo_src_valid),     //         .valid
		.in_0_ready     (mem_s2_agent_rdata_fifo_src_ready),     //         .ready
		.out_0_data     (avalon_st_adapter_006_out_0_data),      //    out_0.data
		.out_0_valid    (avalon_st_adapter_006_out_0_valid),     //         .valid
		.out_0_ready    (avalon_st_adapter_006_out_0_ready),     //         .ready
		.out_0_error    (avalon_st_adapter_006_out_0_error)      //         .error
	);

	niosII_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_007 (
		.in_clk_0_clk   (clk_clk_clk),                           // in_clk_0.clk
		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (mem_s1_agent_rdata_fifo_src_data),      //     in_0.data
		.in_0_valid     (mem_s1_agent_rdata_fifo_src_valid),     //         .valid
		.in_0_ready     (mem_s1_agent_rdata_fifo_src_ready),     //         .ready
		.out_0_data     (avalon_st_adapter_007_out_0_data),      //    out_0.data
		.out_0_valid    (avalon_st_adapter_007_out_0_valid),     //         .valid
		.out_0_ready    (avalon_st_adapter_007_out_0_ready),     //         .ready
		.out_0_error    (avalon_st_adapter_007_out_0_error)      //         .error
	);

endmodule